rtx reg, insn, pattern;
rtx increment, tem;
enum rtx_code code;
- rtx insert_before;
+ rtx insert_before, seq;
bl = reg_biv_class[REGNO (v->src_reg)];
|| REGNO (XEXP (SET_SRC (pattern), 0)) != bl->regno)
abort ();
+ start_sequence ();
tem = expand_binop (GET_MODE (tem), sub_optab, tem,
XEXP (SET_SRC (pattern), 1), 0, 0,
OPTAB_LIB_WIDEN);
+ seq = gen_sequence ();
+ end_sequence ();
+ emit_insn_before (seq, insert_before);
}
}