PR target/53110

	* config/i386/i386.md (and<mode>3): For andq $0xffffffff, reg
	instead expand it as zero extension.

git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@186839 138bc75d-0d04-0410-961f-82ee72b054a4

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 820ba1b..a93d3cd 100644 (file)
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,9 @@
+2012-04-25  Jakub Jelinek  <jakub@redhat.com>
+
+       PR target/53110
+       * config/i386/i386.md (and<mode>3): For andq $0xffffffff, reg
+       instead expand it as zero extension.
+
 2012-04-25  H.J. Lu  <hongjiu.lu@intel.com>
 
        PR debug/52857

diff --git a/gcc/config/i386/i386.md b/gcc/config/i386/i386.md
index 0b2fe55..60439f9 100644 (file)
--- a/gcc/config/i386/i386.md
+++ b/gcc/config/i386/i386.md
@@ -7694,7 +7694,17 @@
        (and:SWIM (match_operand:SWIM 1 "nonimmediate_operand")
                  (match_operand:SWIM 2 "<general_szext_operand>")))]
   ""
-  "ix86_expand_binary_operator (AND, <MODE>mode, operands); DONE;")
+{
+  if (<MODE>mode == DImode
+      && GET_CODE (operands[2]) == CONST_INT
+      && INTVAL (operands[2]) == (HOST_WIDE_INT) 0xffffffff
+      && REG_P (operands[1]))
+    emit_insn (gen_zero_extendsidi2 (operands[0],
+                                    gen_lowpart (SImode, operands[1])));
+  else
+    ix86_expand_binary_operator (AND, <MODE>mode, operands);
+  DONE;
+})
 
 (define_insn "*anddi_1"
   [(set (match_operand:DI 0 "nonimmediate_operand" "=r,rm,r,r")