ARM: dts: stm32: remove timer5 duplicate unit-address on stm32f7 series

Remove the following warnings seen when building with W=1.
Warning (unique_unit_address): /soc/timer@40000c00: duplicate unit-address
(also used in node /soc/timers@40000c00)
This approach is based on some discussions[1], to restructure the dtsi
and dts files.

Timer5 is enabled by default on stm32f7 series, to act as clockevent. In
order to get rid of the W=1 warning, and be compliant with dt-schemas
(e.g. dtbs_check):
- In stm32f746.dtsi:
  . Keep the more complete timers5 description
  . Remove the most simple timer5 node that is duplicate
- In each board:
  . adopt "st,stm32-timer" compatible for timers5, also add the interrupt
  . use /delete-property/ and /delete-node/ so the it matches the
    clockevent bindings

Note: all this is done in one shot (e.g. not split) to keep clockevent
functionality.

[1] https://lore.kernel.org/linux-arm-kernel/Yaf4jiZIp8+ndaXs@robh.at.kernel.org/

Signed-off-by: Fabrice Gasnier <fabrice.gasnier@foss.st.com>
Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>

diff --git a/arch/arm/boot/dts/stm32746g-eval.dts b/arch/arm/boot/dts/stm32746g-eval.dts
index 327613fd9666c1b4a050b10cc3f5f80e3e168b86..a293e65141c6c7f34b4307d50655e992f7b2ba73 100644 (file)
--- a/arch/arm/boot/dts/stm32746g-eval.dts
+++ b/arch/arm/boot/dts/stm32746g-eval.dts
@@ -194,6 +194,18 @@
        bus-width = <4>;
 };
 
+&timers5 {
+       /* Override timer5 to act as clockevent */
+       compatible = "st,stm32-timer";
+       interrupts = <50>;
+       status = "okay";
+       /delete-property/#address-cells;
+       /delete-property/#size-cells;
+       /delete-property/clock-names;
+       /delete-node/pwm;
+       /delete-node/timer@4;
+};
+
 &usart1 {
        pinctrl-0 = <&usart1_pins_a>;
        pinctrl-names = "default";

diff --git a/arch/arm/boot/dts/stm32f746-disco.dts b/arch/arm/boot/dts/stm32f746-disco.dts
index 569d23cc61e52eea83f7db2ce83988b6de7d77b6..c11616ed5fc685394d7f473b7312682a9b25864c 100644 (file)
--- a/arch/arm/boot/dts/stm32f746-disco.dts
+++ b/arch/arm/boot/dts/stm32f746-disco.dts
@@ -109,6 +109,18 @@
        bus-width = <4>;
 };
 
+&timers5 {
+       /* Override timer5 to act as clockevent */
+       compatible = "st,stm32-timer";
+       interrupts = <50>;
+       status = "okay";
+       /delete-property/#address-cells;
+       /delete-property/#size-cells;
+       /delete-property/clock-names;
+       /delete-node/pwm;
+       /delete-node/timer@4;
+};
+
 &usart1 {
        pinctrl-0 = <&usart1_pins_b>;
        pinctrl-names = "default";

diff --git a/arch/arm/boot/dts/stm32f746.dtsi b/arch/arm/boot/dts/stm32f746.dtsi
index a4f5c6a66e08af3546bef6bc9da4901a586f904f..dc868e6da40e0fae8e98cfca3f3674efa61210d7 100644 (file)
--- a/arch/arm/boot/dts/stm32f746.dtsi
+++ b/arch/arm/boot/dts/stm32f746.dtsi
@@ -141,13 +141,6 @@
                        };
                };
 
-               timer5: timer@40000c00 {
-                       compatible = "st,stm32-timer";
-                       reg = <0x40000c00 0x400>;
-                       interrupts = <50>;
-                       clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM5)>;
-               };
-
                timers5: timers@40000c00 {
                        #address-cells = <1>;
                        #size-cells = <0>;

diff --git a/arch/arm/boot/dts/stm32f769-disco.dts b/arch/arm/boot/dts/stm32f769-disco.dts
index be943b701980638d8a401716c6fe238e51487f65..b038d0ed39e8c91488fe6e5fa1a0dc49899a5d23 100644 (file)
--- a/arch/arm/boot/dts/stm32f769-disco.dts
+++ b/arch/arm/boot/dts/stm32f769-disco.dts
@@ -137,6 +137,18 @@
        bus-width = <4>;
 };
 
+&timers5 {
+       /* Override timer5 to act as clockevent */
+       compatible = "st,stm32-timer";
+       interrupts = <50>;
+       status = "okay";
+       /delete-property/#address-cells;
+       /delete-property/#size-cells;
+       /delete-property/clock-names;
+       /delete-node/pwm;
+       /delete-node/timer@4;
+};
+
 &usart1 {
        pinctrl-0 = <&usart1_pins_a>;
        pinctrl-names = "default";