drivers/watchdog: ASPEED reference dev tree properties for config

Reference the system device tree when configuring the watchdog
engines. If property 'aspeed,reset_type' is present then set
reset behavior based on the specified value.  This can be one of
three different mutually exclusive values
  * cpu - Reset CPU only on watchdog timeout
  * soc - Reset System on Chip
  * system - Full system reset

No reset can also be specified by indicating:
  * none - No reset, assumes another watchdog is responsible for
           this.

Add optional property 'aspeed,external-signal'. If present then
configure to generate external signal on watchdog timeout.

Signed-off-by: Christopher Bostic <cbostic@linux.vnet.ibm.com>
Reviewed-by: Guenter Roeck <linux@roeck-us.net>
Signed-off-by: Guenter Roeck <linux@roeck-us.net>
Signed-off-by: Wim Van Sebroeck <wim@iguana.be>

diff --git a/drivers/watchdog/aspeed_wdt.c b/drivers/watchdog/aspeed_wdt.c
index 1c65258..c707ab6 100644 (file)
--- a/drivers/watchdog/aspeed_wdt.c
+++ b/drivers/watchdog/aspeed_wdt.c
@@ -36,6 +36,7 @@ MODULE_DEVICE_TABLE(of, aspeed_wdt_of_table);
 #define WDT_CTRL               0x0C
 #define   WDT_CTRL_RESET_MODE_SOC      (0x00 << 5)
 #define   WDT_CTRL_RESET_MODE_FULL_CHIP        (0x01 << 5)
+#define   WDT_CTRL_RESET_MODE_ARM_CPU  (0x10 << 5)
 #define   WDT_CTRL_1MHZ_CLK            BIT(4)
 #define   WDT_CTRL_WDT_EXT             BIT(3)
 #define   WDT_CTRL_WDT_INTR            BIT(2)
@@ -140,6 +141,8 @@ static int aspeed_wdt_probe(struct platform_device *pdev)
 {
        struct aspeed_wdt *wdt;
        struct resource *res;
+       struct device_node *np;
+       const char *reset_type;
        int ret;
 
        wdt = devm_kzalloc(&pdev->dev, sizeof(*wdt), GFP_KERNEL);
@@ -164,14 +167,30 @@ static int aspeed_wdt_probe(struct platform_device *pdev)
        wdt->wdd.timeout = WDT_DEFAULT_TIMEOUT;
        watchdog_init_timeout(&wdt->wdd, 0, &pdev->dev);
 
+       wdt->ctrl = WDT_CTRL_1MHZ_CLK;
+
        /*
         * Control reset on a per-device basis to ensure the
-        * host is not affected by a BMC reboot, so only reset
-        * the SOC and not the full chip
+        * host is not affected by a BMC reboot
         */
-       wdt->ctrl = WDT_CTRL_RESET_MODE_SOC |
-               WDT_CTRL_1MHZ_CLK |
-               WDT_CTRL_RESET_SYSTEM;
+       np = pdev->dev.of_node;
+       ret = of_property_read_string(np, "aspeed,reset-type", &reset_type);
+       if (ret) {
+               wdt->ctrl |= WDT_CTRL_RESET_MODE_SOC | WDT_CTRL_RESET_SYSTEM;
+       } else {
+               if (!strcmp(reset_type, "cpu"))
+                       wdt->ctrl |= WDT_CTRL_RESET_MODE_ARM_CPU;
+               else if (!strcmp(reset_type, "soc"))
+                       wdt->ctrl |= WDT_CTRL_RESET_MODE_SOC;
+               else if (!strcmp(reset_type, "system"))
+                       wdt->ctrl |= WDT_CTRL_RESET_SYSTEM;
+               else if (strcmp(reset_type, "none"))
+                       return -EINVAL;
+       }
+       if (of_property_read_bool(np, "aspeed,external-signal"))
+               wdt->ctrl |= WDT_CTRL_WDT_EXT;
+
+       writel(wdt->ctrl, wdt->base + WDT_CTRL);
 
        if (readl(wdt->base + WDT_CTRL) & WDT_CTRL_ENABLE)  {
                aspeed_wdt_start(&wdt->wdd);