display.v_active = mode->vdisplay;
display.v_total = mode->vtotal;
- display.v_sync_start = mode->vsync_start;
- display.v_sync_end = mode->vsync_end;
+
+ if (crtc_state->encoder_type == DRM_MODE_ENCODER_DSI){
+ display.v_sync_start = mode->vsync_start + 1;
+ display.v_sync_end = mode->vsync_end - 1;
+ }else{
+ display.v_sync_start = mode->vsync_start;
+ display.v_sync_end = mode->vsync_end;
+ }
+
if (mode->flags & DRM_MODE_FLAG_PVSYNC)
display.v_sync_polarity = true;
else
else
dc_set_clear(hw, DC_DISPLAY_PANEL_START, 0, BIT(1) | BIT(2));
-#ifdef CONFIG_STARFIVE_DSI
- dc_write(hw, DC_DISPLAY_H + offset, hw->display[id].h_active |
- (hw->display[id].h_total << 16));
-
- dc_write(hw, DC_DISPLAY_H_SYNC + offset,
- hw->display[id].h_sync_start |
- (hw->display[id].h_sync_end << 15) |
- BIT(31) |
- BIT(30));
-
- dc_write(hw, DC_DISPLAY_V + offset, hw->display[id].v_active |
- (hw->display[id].v_total << 16));
-
- dc_write(hw, DC_DISPLAY_V_SYNC + offset,
- hw->display[id].v_sync_start |
- (hw->display[id].v_sync_end << 15) |
- (hw->display[id].v_sync_polarity ? 0 : BIT(31)) |
- BIT(30));
-
-#else
dc_write(hw, DC_DISPLAY_H + offset, hw->display[id].h_active |
(hw->display[id].h_total << 16));
dc_write(hw, DC_DISPLAY_H_SYNC + offset,
(hw->display[id].v_sync_end << 15) |
(hw->display[id].v_sync_polarity ? 0 : BIT(31)) |
BIT(30));
-#endif
if (hw->info->pipe_sync) {
switch (display->sync_mode) {