[Hexagon] Account for <def,read-undef> when validating moves for predication

llvm-svn: 286009

diff --git a/llvm/lib/Target/Hexagon/HexagonExpandCondsets.cpp b/llvm/lib/Target/Hexagon/HexagonExpandCondsets.cpp
index edbd61d5eb40cbebe1a1341eb6b353e18195db1e..ba4a9a1832b524e1d2a5de8be85b104b3ff9789c 100644 (file)
--- a/llvm/lib/Target/Hexagon/HexagonExpandCondsets.cpp
+++ b/llvm/lib/Target/Hexagon/HexagonExpandCondsets.cpp
@@ -948,6 +948,13 @@ bool HexagonExpandCondsets::predicate(MachineInstr &TfrI, bool Cond,
         return false;
 
       ReferenceMap &Map = Op.isDef() ? Defs : Uses;
+      if (Op.isDef() && Op.isUndef()) {
+        assert(RR.Sub && "Expecting a subregister on <def,read-undef>");
+        // If this is a <def,read-undef>, then it invalidates the non-written
+        // part of the register. For the purpose of checking the validity of
+        // the move, assume that it modifies the whole register.
+        RR.Sub = 0;
+      }
       addRefToMap(RR, Map, Exec);
     }
   }

diff --git a/llvm/test/CodeGen/Hexagon/expand-condsets-def-undef.mir b/llvm/test/CodeGen/Hexagon/expand-condsets-def-undef.mir
new file mode 100644 (file)
index 0000000..6704b70
--- /dev/null
+++ b/llvm/test/CodeGen/Hexagon/expand-condsets-def-undef.mir
@@ -0,0 +1,41 @@
+# RUN: llc -march=hexagon -run-pass expand-condsets -o - %s -verify-machineinstrs | FileCheck %s
+
+# CHECK-LABEL: name: fred
+
+# Make sure that <def,read-undef> is accounted for when validating moves
+# during predication. In the code below, %2.subreg_hireg is invalidated
+# by the C2_mux instruction, and so predicating the A2_addi as an argument
+# to the C2_muxir should not happen.
+
+--- |
+  define void @fred() { ret void }
+
+...
+---
+
+name: fred
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: predregs }
+  - { id: 1, class: intregs }
+  - { id: 2, class: doubleregs }
+  - { id: 3, class: intregs }
+liveins:
+  - { reg: '%p0', virtual-reg: '%0' }
+  - { reg: '%r0', virtual-reg: '%1' }
+  - { reg: '%d0', virtual-reg: '%2' }
+
+body: |
+  bb.0:
+    liveins: %r0, %d0, %p0
+    %0 = COPY %p0
+    %1 = COPY %r0
+    %2 = COPY %d0
+    ; Check that this instruction is unchanged (remains unpredicated)
+    ; CHECK: %3 = A2_addi %2.subreg_hireg, 1
+    %3 = A2_addi %2.subreg_hireg, 1
+    undef %2.subreg_loreg = C2_mux %0, %2.subreg_loreg, %1
+    %2.subreg_hireg = C2_muxir %0, %3, 0
+
+...
+