freedreno/ir3: Fix pre-a6xx ldgb/stib parsing

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8175>

diff --git a/src/freedreno/ir3/instr-a3xx.h b/src/freedreno/ir3/instr-a3xx.h
index 138d721..2eaf73a 100644 (file)
--- a/src/freedreno/ir3/instr-a3xx.h
+++ b/src/freedreno/ir3/instr-a3xx.h
@@ -1014,13 +1014,15 @@ static inline bool is_cat6_legacy(instr_t *instr, unsigned gpu_id)
 {
        instr_cat6_a6xx_t *cat6 = &instr->cat6_a6xx;
 
+       if (gpu_id < 600)
+               return true;
+
        /* At least one of these two bits is pad in all the possible
         * "legacy" cat6 encodings, and a analysis of all the pre-a6xx
         * cmdstream traces I have indicates that the pad bit is zero
         * in all cases.  So we can use this to detect new encoding:
         */
        if ((cat6->pad3 & 0x4) && (cat6->pad5 & 0x2)) {
-               ir3_assert(gpu_id >= 600);
                ir3_assert(instr->cat6.opc == 0);
                return false;
        }

diff --git a/src/freedreno/ir3/tests/disasm.c b/src/freedreno/ir3/tests/disasm.c
index 4c53d58..aea38a3 100644 (file)
--- a/src/freedreno/ir3/tests/disasm.c
+++ b/src/freedreno/ir3/tests/disasm.c
@@ -137,6 +137,9 @@ static const struct test {
 
        /* cat6 */
 
+       INSTR_5XX(c6e60000_00010600, "ldgb.untyped.4d.u32.1 r0.x, g[0], r1.x, r0.x"),
+       INSTR_5XX(d7660204_02000a01, "(sy)stib.typed.2d.u32.1 g[1], r0.x, r0.z, r1.x", .parse_fail=true),
+
        INSTR_6XX(c0c00000_00000000, "stg.f16 g[hr0.x], hr0.x, hr0.x", .parse_fail=true),
        /* dEQP-GLES31.functional.tessellation.invariance.outer_edge_symmetry.isolines_equal_spacing_ccw */
        INSTR_6XX(c0d20906_02800004, "stg.f32 g[r1.x+r1.z], r0.z, 2"), /* stg.a.f32 g[r1.x+(r1.z<<2)], r0.z, 2 */