clk: ingenic: jz4740: Fix gating of UDC clock
authorPaul Cercueil <paul@crapouillou.net>
Fri, 25 Jan 2019 15:34:36 +0000 (12:34 -0300)
committerStephen Boyd <sboyd@kernel.org>
Tue, 5 Feb 2019 21:32:26 +0000 (13:32 -0800)
The UDC clock is gated when the bit is cleared, not when it is set.

Signed-off-by: Paul Cercueil <paul@crapouillou.net>
Tested-by: Artur Rojek <contact@artur-rojek.eu>
Fixes: 2b555a4b9cae ("clk: ingenic: Add missing flag for UDC clock")
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
drivers/clk/ingenic/jz4740-cgu.c

index 4479c102e8994bdb414038d117adc9544c971e6c..b86edd3282493388590e979eea386cd8b8cdbef9 100644 (file)
@@ -165,7 +165,7 @@ static const struct ingenic_cgu_clk_info jz4740_cgu_clocks[] = {
                .parents = { JZ4740_CLK_EXT, JZ4740_CLK_PLL_HALF, -1, -1 },
                .mux = { CGU_REG_CPCCR, 29, 1 },
                .div = { CGU_REG_CPCCR, 23, 1, 6, -1, -1, -1 },
-               .gate = { CGU_REG_SCR, 6 },
+               .gate = { CGU_REG_SCR, 6, true },
        },
 
        /* Gate-only clocks */