drm/i915: move dbuf under display sub-struct

Move display dbuf related members under drm_i915_private display
sub-struct.

Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/3363a516c12bd8bfb240131e9eb9fc3a0f3057a3.1661779055.git.jani.nikula@intel.com

diff --git a/drivers/gpu/drm/i915/display/intel_display_core.h b/drivers/gpu/drm/i915/display/intel_display_core.h
index 3d2e1b1..b061deb 100644 (file)
--- a/drivers/gpu/drm/i915/display/intel_display_core.h
+++ b/drivers/gpu/drm/i915/display/intel_display_core.h
@@ -300,6 +300,13 @@ struct intel_display {
        } cdclk;
 
        struct {
+               /* The current hardware dbuf configuration */
+               u8 enabled_slices;
+
+               struct intel_global_obj obj;
+       } dbuf;
+
+       struct {
                /* VLV/CHV/BXT/GLK DSI MMIO register base address */
                u32 mmio_base;
        } dsi;

diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c
index b64aec6..1af1705 100644 (file)
--- a/drivers/gpu/drm/i915/display/intel_display_power.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power.c
@@ -1061,14 +1061,14 @@ void gen9_dbuf_slices_update(struct drm_i915_private *dev_priv,
        for_each_dbuf_slice(dev_priv, slice)
                gen9_dbuf_slice_set(dev_priv, slice, req_slices & BIT(slice));
 
-       dev_priv->dbuf.enabled_slices = req_slices;
+       dev_priv->display.dbuf.enabled_slices = req_slices;
 
        mutex_unlock(&power_domains->lock);
 }
 
 static void gen9_dbuf_enable(struct drm_i915_private *dev_priv)
 {
-       dev_priv->dbuf.enabled_slices =
+       dev_priv->display.dbuf.enabled_slices =
                intel_enabled_dbuf_slices_mask(dev_priv);
 
        /*
@@ -1076,7 +1076,7 @@ static void gen9_dbuf_enable(struct drm_i915_private *dev_priv)
         * figure out later which slices we have and what we need.
         */
        gen9_dbuf_slices_update(dev_priv, BIT(DBUF_S1) |
-                               dev_priv->dbuf.enabled_slices);
+                               dev_priv->display.dbuf.enabled_slices);
 }
 
 static void gen9_dbuf_disable(struct drm_i915_private *dev_priv)

diff --git a/drivers/gpu/drm/i915/display/intel_display_power_well.c b/drivers/gpu/drm/i915/display/intel_display_power_well.c
index a358ce9..c8b741d 100644 (file)
--- a/drivers/gpu/drm/i915/display/intel_display_power_well.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power_well.c
@@ -946,7 +946,7 @@ static bool gen9_dc_off_power_well_enabled(struct drm_i915_private *dev_priv,
 static void gen9_assert_dbuf_enabled(struct drm_i915_private *dev_priv)
 {
        u8 hw_enabled_dbuf_slices = intel_enabled_dbuf_slices_mask(dev_priv);
-       u8 enabled_dbuf_slices = dev_priv->dbuf.enabled_slices;
+       u8 enabled_dbuf_slices = dev_priv->display.dbuf.enabled_slices;
 
        drm_WARN(&dev_priv->drm,
                 hw_enabled_dbuf_slices != enabled_dbuf_slices,

diff --git a/drivers/gpu/drm/i915/display/intel_modeset_setup.c b/drivers/gpu/drm/i915/display/intel_modeset_setup.c
index def7827..aed386d 100644 (file)
--- a/drivers/gpu/drm/i915/display/intel_modeset_setup.c
+++ b/drivers/gpu/drm/i915/display/intel_modeset_setup.c
@@ -34,7 +34,7 @@ static void intel_crtc_disable_noatomic(struct intel_crtc *crtc,
        struct intel_cdclk_state *cdclk_state =
                to_intel_cdclk_state(i915->display.cdclk.obj.state);
        struct intel_dbuf_state *dbuf_state =
-               to_intel_dbuf_state(i915->dbuf.obj.state);
+               to_intel_dbuf_state(i915->display.dbuf.obj.state);
        struct intel_crtc_state *crtc_state =
                to_intel_crtc_state(crtc->base.state);
        struct intel_plane *plane;
@@ -417,7 +417,7 @@ static void intel_modeset_readout_hw_state(struct drm_i915_private *i915)
        struct intel_cdclk_state *cdclk_state =
                to_intel_cdclk_state(i915->display.cdclk.obj.state);
        struct intel_dbuf_state *dbuf_state =
-               to_intel_dbuf_state(i915->dbuf.obj.state);
+               to_intel_dbuf_state(i915->display.dbuf.obj.state);
        enum pipe pipe;
        struct intel_crtc *crtc;
        struct intel_encoder *encoder;

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index c950867..1a49493 100644 (file)
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -281,13 +281,6 @@ struct drm_i915_private {
        unsigned int hpll_freq;
        unsigned int czclk_freq;
 
-       struct {
-               /* The current hardware dbuf configuration */
-               u8 enabled_slices;
-
-               struct intel_global_obj obj;
-       } dbuf;
-
        /**
         * wq - Driver workqueue for GEM.
         *

diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index cd89a94..76d1c5f 100644 (file)
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -6569,7 +6569,7 @@ static void skl_pipe_wm_get_hw_state(struct intel_crtc *crtc,
 void skl_wm_get_hw_state(struct drm_i915_private *dev_priv)
 {
        struct intel_dbuf_state *dbuf_state =
-               to_intel_dbuf_state(dev_priv->dbuf.obj.state);
+               to_intel_dbuf_state(dev_priv->display.dbuf.obj.state);
        struct intel_crtc *crtc;
 
        if (HAS_MBUS_JOINING(dev_priv))
@@ -6631,13 +6631,13 @@ void skl_wm_get_hw_state(struct drm_i915_private *dev_priv)
                            str_yes_no(dbuf_state->joined_mbus));
        }
 
-       dbuf_state->enabled_slices = dev_priv->dbuf.enabled_slices;
+       dbuf_state->enabled_slices = dev_priv->display.dbuf.enabled_slices;
 }
 
 static bool skl_dbuf_is_misconfigured(struct drm_i915_private *i915)
 {
        const struct intel_dbuf_state *dbuf_state =
-               to_intel_dbuf_state(i915->dbuf.obj.state);
+               to_intel_dbuf_state(i915->display.dbuf.obj.state);
        struct skl_ddb_entry entries[I915_MAX_PIPES] = {};
        struct intel_crtc *crtc;
 
@@ -7223,10 +7223,10 @@ void intel_wm_state_verify(struct intel_crtc *crtc,
        hw_enabled_slices = intel_enabled_dbuf_slices_mask(dev_priv);
 
        if (DISPLAY_VER(dev_priv) >= 11 &&
-           hw_enabled_slices != dev_priv->dbuf.enabled_slices)
+           hw_enabled_slices != dev_priv->display.dbuf.enabled_slices)
                drm_err(&dev_priv->drm,
                        "mismatch in DBUF Slices (expected 0x%x, got 0x%x)\n",
-                       dev_priv->dbuf.enabled_slices,
+                       dev_priv->display.dbuf.enabled_slices,
                        hw_enabled_slices);
 
        for_each_intel_plane_on_crtc(&dev_priv->drm, crtc, plane) {
@@ -8343,7 +8343,7 @@ intel_atomic_get_dbuf_state(struct intel_atomic_state *state)
        struct drm_i915_private *dev_priv = to_i915(state->base.dev);
        struct intel_global_state *dbuf_state;
 
-       dbuf_state = intel_atomic_get_global_obj_state(state, &dev_priv->dbuf.obj);
+       dbuf_state = intel_atomic_get_global_obj_state(state, &dev_priv->display.dbuf.obj);
        if (IS_ERR(dbuf_state))
                return ERR_CAST(dbuf_state);
 
@@ -8358,7 +8358,7 @@ int intel_dbuf_init(struct drm_i915_private *dev_priv)
        if (!dbuf_state)
                return -ENOMEM;
 
-       intel_atomic_global_obj_init(dev_priv, &dev_priv->dbuf.obj,
+       intel_atomic_global_obj_init(dev_priv, &dev_priv->display.dbuf.obj,
                                     &dbuf_state->base, &intel_dbuf_funcs);
 
        return 0;

diff --git a/drivers/gpu/drm/i915/intel_pm.h b/drivers/gpu/drm/i915/intel_pm.h
index 945503a..3ee7183 100644 (file)
--- a/drivers/gpu/drm/i915/intel_pm.h
+++ b/drivers/gpu/drm/i915/intel_pm.h
@@ -77,9 +77,9 @@ intel_atomic_get_dbuf_state(struct intel_atomic_state *state);
 
 #define to_intel_dbuf_state(x) container_of((x), struct intel_dbuf_state, base)
 #define intel_atomic_get_old_dbuf_state(state) \
-       to_intel_dbuf_state(intel_atomic_get_old_global_obj_state(state, &to_i915(state->base.dev)->dbuf.obj))
+       to_intel_dbuf_state(intel_atomic_get_old_global_obj_state(state, &to_i915(state->base.dev)->display.dbuf.obj))
 #define intel_atomic_get_new_dbuf_state(state) \
-       to_intel_dbuf_state(intel_atomic_get_new_global_obj_state(state, &to_i915(state->base.dev)->dbuf.obj))
+       to_intel_dbuf_state(intel_atomic_get_new_global_obj_state(state, &to_i915(state->base.dev)->display.dbuf.obj))
 
 int intel_dbuf_init(struct drm_i915_private *dev_priv);
 void intel_dbuf_pre_plane_update(struct intel_atomic_state *state);