* gas/config/tc-arm.c (insns): Add DCPS instruction.

	* gas/testsuite/gas/arm/armv8-a.d: Update.
	* gas/testsuite/gas/arm/armv8-a.s: Likewise.
	* opcodes/arm-dis.c (thumb32_opcodes): Add DCPS instruction.

diff --git a/gas/ChangeLog b/gas/ChangeLog
index 785bf08..34beb86 100644 (file)
--- a/gas/ChangeLog
+++ b/gas/ChangeLog
@@ -1,5 +1,9 @@
 2012-08-24  Matthew Gretton-Dann  <matthew.gretton-dann@arm.com>
 
+       * config/tc-arm.c (insns): Add DCPS instruction.
+
+2012-08-24  Matthew Gretton-Dann  <matthew.gretton-dann@arm.com>
+
        * config/tc-arm.c (T16_32_TAB): Add _sevl.
        (insns): Add SEVL.
 

diff --git a/gas/config/tc-arm.c b/gas/config/tc-arm.c
index cfcdecb..1c5eb31 100644 (file)
--- a/gas/config/tc-arm.c
+++ b/gas/config/tc-arm.c
@@ -17975,6 +17975,12 @@ static const struct asm_opcode insns[] =
 
  tCE("sevl",   320f005, _sevl,    0, (),               noargs, t_hint),
 
+#undef ARM_VARIANT
+#define ARM_VARIANT  NULL
+ TUF("dcps1",  0,       f78f8001, 0, (),       noargs, noargs),
+ TUF("dcps2",  0,       f78f8002, 0, (),       noargs, noargs),
+ TUF("dcps3",  0,       f78f8003, 0, (),       noargs, noargs),
+
 #undef  ARM_VARIANT
 #define ARM_VARIANT  & fpu_fpa_ext_v1  /* Core FPA instruction set (V1).  */
 #undef  THUMB_VARIANT

diff --git a/gas/testsuite/ChangeLog b/gas/testsuite/ChangeLog
index a890b80..1fb915b 100644 (file)
--- a/gas/testsuite/ChangeLog
+++ b/gas/testsuite/ChangeLog
@@ -1,5 +1,10 @@
 2012-08-24  Matthew Gretton-Dann  <matthew.gretton-dann@arm.com>
 
+       * gas/arm/armv8-a.d: Update.
+       * gas/arm/armv8-a.s: Likewise.
+
+2012-08-24  Matthew Gretton-Dann  <matthew.gretton-dann@arm.com>
+
        * gas/arm/armv8-a.s: New testcase.
        * gas/arm/armv8-a.d: Likewise.
 

diff --git a/gas/testsuite/gas/arm/armv8-a.d b/gas/testsuite/gas/arm/armv8-a.d
index f558910..52fcf71 100644 (file)
--- a/gas/testsuite/gas/arm/armv8-a.d
+++ b/gas/testsuite/gas/arm/armv8-a.d
@@ -8,3 +8,6 @@ Disassembly of section .text:
 0[0-9a-f]+ <[^>]+> bf50        sevl
 0[0-9a-f]+ <[^>]+> bf50        sevl
 0[0-9a-f]+ <[^>]+> f3af 8005   sevl.w
+0[0-9a-f]+ <[^>]+> f78f 8001   dcps1
+0[0-9a-f]+ <[^>]+> f78f 8002   dcps2
+0[0-9a-f]+ <[^>]+> f78f 8003   dcps3

diff --git a/gas/testsuite/gas/arm/armv8-a.s b/gas/testsuite/gas/arm/armv8-a.s
index 000a5a7..4e097b1 100644 (file)
--- a/gas/testsuite/gas/arm/armv8-a.s
+++ b/gas/testsuite/gas/arm/armv8-a.s
@@ -12,3 +12,6 @@ bar:
        sevl
        sevl.n
        sevl.w
+       dcps1
+       dcps2
+       dcps3

diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index b60b6af..ac0e891 100644 (file)
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -1,5 +1,9 @@
 2012-08-24  Matthew Gretton-Dann  <matthew.gretton-dann@arm.com>
 
+       * arm-dis.c (thumb32_opcodes): Add DCPS instruction.
+
+2012-08-24  Matthew Gretton-Dann  <matthew.gretton-dann@arm.com>
+
        * arm-dis.c (arm_opcodes): Add SEVL.
        (thumb_opcodes): Likewise.
        (thumb32_opcodes): Likewise.

diff --git a/opcodes/arm-dis.c b/opcodes/arm-dis.c
index 5a450d7..6ee016f 100644 (file)
--- a/opcodes/arm-dis.c
+++ b/opcodes/arm-dis.c
@@ -1421,6 +1421,7 @@ static const struct opcode32 thumb32_opcodes[] =
 {
   /* V8 instructions.  */
   {ARM_EXT_V8, 0xf3af8005, 0xffffffff, "sevl%c.w"},
+  {ARM_EXT_V8, 0xf78f8000, 0xfffffffc, "dcps%0-1d"},
 
   /* V7 instructions.  */
   {ARM_EXT_V7, 0xf910f000, 0xff70f000, "pli%c\t%a"},