#include "qemu-timer.h"
#include "sysemu.h"
#include "ppc_mac.h"
+#include "sh.h"
/* debug IDE devices */
//#define DEBUG_IDE
PCIBus *pci_apb_init(target_phys_addr_t special_base, target_phys_addr_t mem_base,
qemu_irq *pic);
+/* sh_pci.c */
+PCIBus *sh_pci_register_bus(pci_set_irq_fn set_irq, pci_map_irq_fn map_irq,
+ qemu_irq *pic, int devfn_min, int nirq);
+
#endif
/* initialization which should be done by firmware */
uint32_t bcr1 = 1 << 3; /* cs3 SDRAM */
uint16_t bcr2 = 3 << (3 * 2); /* cs3 32-bit */
- cpu_physical_memory_write(SH7750_BCR1_A7, &bcr1, 4);
- cpu_physical_memory_write(SH7750_BCR2_A7, &bcr2, 2);
+ cpu_physical_memory_write(SH7750_BCR1_A7, (uint8_t *)&bcr1, 4);
+ cpu_physical_memory_write(SH7750_BCR2_A7, (uint8_t *)&bcr2, 2);
kernel_size = load_image(kernel_filename, phys_ram_base);
}
}
-void sh_intc_set_irq (void *opaque, int n, int level)
+static void sh_intc_set_irq (void *opaque, int n, int level)
{
struct intc_desc *desc = opaque;
struct intc_source *source = &(desc->sources[n]);
#include "hw.h"
#include "pc.h"
#include "console.h"
+#include "devices.h"
/*
* Status: 2008/11/02
static TCGv cpu_gregs[24];
static TCGv cpu_pc, cpu_sr, cpu_ssr, cpu_spc, cpu_gbr;
static TCGv cpu_vbr, cpu_sgr, cpu_dbr, cpu_mach, cpu_macl;
-static TCGv cpu_pr, cpu_fpscr, cpu_fpul, cpu_flags;
+static TCGv cpu_pr, cpu_fpscr, cpu_fpul;
static TCGv cpu_fregs[32];
/* internal register indexes */
}
}
-void cpu_sh4_reset(CPUSH4State * env)
+static void cpu_sh4_reset(CPUSH4State * env)
{
#if defined(CONFIG_USER_ONLY)
env->sr = SR_FD; /* FD - kernel does lazy fpu context switch */