#define DSD_CFG_MUX_TE_UNMASK_GLOBAL BIT(13)
#define WINDOWS_NR 5
-#define PRIMARY_WIN 2
-#define CURSON_WIN 4
#define MIN_FB_WIDTH_FOR_16WORD_BURST 128
ret = exynos_drm_crtc_init(&ctx->crtc, drm_dev);
if (ret)
return ret;
- ctx->crtc.base.primary = &ctx->planes[PRIMARY_WIN].base;
decon_clear_channels(&ctx->crtc);
decon_ctx_remove(ctx);
return ret;
}
- ctx->crtc.base.primary = &ctx->planes[DEFAULT_WIN].base;
if (ctx->encoder)
exynos_dpi_bind(drm_dev, ctx->encoder);
struct drm_device *drm_dev)
{
struct drm_crtc *crtc = &exynos_crtc->base;
+ struct drm_plane *primary = NULL, *plane;
+
+ drm_for_each_plane(plane, drm_dev) {
+ if (plane->possible_crtcs != BIT(drm_dev->mode_config.num_crtc))
+ continue;
+ if (!primary && plane->type == DRM_PLANE_TYPE_PRIMARY)
+ primary = plane;
+ }
drm_crtc_helper_add(crtc, &exynos_crtc_helper_funcs);
- return drm_crtc_init_with_planes(drm_dev, crtc, NULL, NULL,
+ return drm_crtc_init_with_planes(drm_dev, crtc, primary, NULL,
&exynos_crtc_funcs, NULL);
}
#define MAX_PLANE 5
#define MAX_FB_BUFFER 4
-#define DEFAULT_WIN 0
-
#define to_exynos_crtc(x) container_of(x, struct exynos_drm_crtc, base)
#define to_exynos_plane(x) container_of(x, struct exynos_drm_plane, base)
ret = exynos_drm_crtc_init(&ctx->crtc, drm_dev);
if (ret)
return ret;
- ctx->crtc.base.primary = &ctx->planes[DEFAULT_WIN].base;
if (ctx->driver_data->has_dp_clk) {
ctx->dp_clk.enable = fimd_dp_clock_enable;
DRM_ERROR("failed to create crtc.\n");
return ret;
}
- ctx->crtc.base.primary = &ctx->planes[DEFAULT_WIN].base;
drm_encoder_init(drm_dev, encoder, &exynos_vidi_encoder_funcs,
DRM_MODE_ENCODER_TMDS, NULL);
mixer_ctx_remove(ctx);
goto free_ctx;
}
- ctx->crtc.base.primary = &ctx->planes[DEFAULT_WIN].base;
return 0;