oxygen_set_bits8(chip, OXYGEN_FUNCTION,
OXYGEN_FUNCTION_RESET_CODEC |
chip->model->function_flags);
+ oxygen_write8_masked(chip, OXYGEN_FUNCTION,
+ OXYGEN_FUNCTION_SPI,
+ OXYGEN_FUNCTION_2WIRE_SPI_MASK);
+ oxygen_write8(chip, OXYGEN_DMA_STATUS, 0);
+ oxygen_write8(chip, OXYGEN_DMA_PAUSE, 0);
+ oxygen_write8(chip, OXYGEN_PLAY_CHANNELS,
+ OXYGEN_PLAY_CHANNELS_2 |
+ OXYGEN_DMA_A_BURST_8 |
+ OXYGEN_DMA_MULTICH_BURST_8);
+ oxygen_write16(chip, OXYGEN_INTERRUPT_MASK, 0);
+ oxygen_write8_masked(chip, OXYGEN_MISC, 0,
+ OXYGEN_MISC_WRITE_PCI_SUBID |
+ OXYGEN_MISC_REC_C_FROM_SPDIF |
+ OXYGEN_MISC_REC_B_FROM_AC97 |
+ OXYGEN_MISC_REC_A_FROM_MULTICH);
+ oxygen_write8(chip, OXYGEN_REC_FORMAT,
+ (OXYGEN_FORMAT_16 << OXYGEN_REC_FORMAT_A_SHIFT) |
+ (OXYGEN_FORMAT_16 << OXYGEN_REC_FORMAT_B_SHIFT) |
+ (OXYGEN_FORMAT_16 << OXYGEN_REC_FORMAT_C_SHIFT));
+ oxygen_write8(chip, OXYGEN_PLAY_FORMAT,
+ (OXYGEN_FORMAT_16 << OXYGEN_SPDIF_FORMAT_SHIFT) |
+ (OXYGEN_FORMAT_16 << OXYGEN_MULTICH_FORMAT_SHIFT));
+ oxygen_write8(chip, OXYGEN_REC_CHANNELS, OXYGEN_REC_CHANNELS_2_2_2);
oxygen_write16(chip, OXYGEN_I2S_MULTICH_FORMAT,
OXYGEN_RATE_48000 | OXYGEN_I2S_FORMAT_LJUST |
OXYGEN_I2S_MCLK_128 | OXYGEN_I2S_BITS_16 |
OXYGEN_SPDIF_LOCK_PAR |
OXYGEN_SPDIF_IN_CLOCK_MASK);
oxygen_write32(chip, OXYGEN_SPDIF_OUTPUT_BITS, chip->spdif_bits);
+ oxygen_clear_bits8(chip, OXYGEN_MPU401_CONTROL, OXYGEN_MPU401_LOOPBACK);
+ oxygen_write8(chip, OXYGEN_GPI_INTERRUPT_MASK, 0);
+ oxygen_write16(chip, OXYGEN_GPIO_INTERRUPT_MASK, 0);
oxygen_write16(chip, OXYGEN_PLAY_ROUTING,
- OXYGEN_PLAY_MULTICH_I2S_DAC | OXYGEN_PLAY_SPDIF_SPDIF |
+ OXYGEN_PLAY_MULTICH_I2S_DAC |
+ OXYGEN_PLAY_SPDIF_SPDIF |
(0 << OXYGEN_PLAY_DAC0_SOURCE_SHIFT) |
(1 << OXYGEN_PLAY_DAC1_SOURCE_SHIFT) |
(2 << OXYGEN_PLAY_DAC2_SOURCE_SHIFT) |
(3 << OXYGEN_PLAY_DAC3_SOURCE_SHIFT));
oxygen_write8(chip, OXYGEN_REC_ROUTING,
OXYGEN_REC_A_ROUTE_I2S_ADC_1 |
- OXYGEN_REC_B_ROUTE_AC97_1 |
+ OXYGEN_REC_B_ROUTE_I2S_ADC_2 |
OXYGEN_REC_C_ROUTE_SPDIF);
oxygen_write8(chip, OXYGEN_ADC_MONITOR, 0);
oxygen_write8(chip, OXYGEN_A_MONITOR_ROUTING,
(2 << OXYGEN_A_MONITOR_ROUTE_2_SHIFT) |
(3 << OXYGEN_A_MONITOR_ROUTE_3_SHIFT));
- oxygen_write16(chip, OXYGEN_INTERRUPT_MASK, 0);
- oxygen_write16(chip, OXYGEN_DMA_STATUS, 0);
-
oxygen_write8(chip, OXYGEN_AC97_INTERRUPT_MASK, 0);
- if (chip->has_ac97_0) {
- oxygen_clear_bits16(chip, OXYGEN_AC97_OUT_CONFIG,
- OXYGEN_AC97_CODEC0_FRONTL |
- OXYGEN_AC97_CODEC0_FRONTR |
- OXYGEN_AC97_CODEC0_SIDEL |
- OXYGEN_AC97_CODEC0_SIDER |
- OXYGEN_AC97_CODEC0_CENTER |
- OXYGEN_AC97_CODEC0_BASE |
- OXYGEN_AC97_CODEC0_REARL |
- OXYGEN_AC97_CODEC0_REARR);
- oxygen_set_bits16(chip, OXYGEN_AC97_IN_CONFIG,
- OXYGEN_AC97_CODEC0_LINEL |
- OXYGEN_AC97_CODEC0_LINER);
+ oxygen_write32(chip, OXYGEN_AC97_OUT_CONFIG, 0);
+ oxygen_write32(chip, OXYGEN_AC97_IN_CONFIG, 0);
+ if (!(chip->has_ac97_0 | chip->has_ac97_1))
+ oxygen_set_bits16(chip, OXYGEN_AC97_CONTROL,
+ OXYGEN_AC97_CLOCK_DISABLE);
+ if (!chip->has_ac97_0) {
+ oxygen_set_bits16(chip, OXYGEN_AC97_CONTROL,
+ OXYGEN_AC97_NO_CODEC_0);
+ } else {
oxygen_write_ac97(chip, 0, AC97_RESET, 0);
msleep(1);
oxygen_ac97_set_bits(chip, 0, CM9780_GPIO_SETUP,
oxygen_ac97_set_bits(chip, 0, AC97_EXTENDED_STATUS,
AC97_EA_PRI | AC97_EA_PRJ | AC97_EA_PRK);
}
+ if (chip->has_ac97_1) {
+ oxygen_set_bits32(chip, OXYGEN_AC97_OUT_CONFIG,
+ OXYGEN_AC97_CODEC1_SLOT3 |
+ OXYGEN_AC97_CODEC1_SLOT4);
+ oxygen_write_ac97(chip, 1, AC97_RESET, 0);
+ msleep(1);
+ oxygen_write_ac97(chip, 1, AC97_MASTER, 0x0000);
+ oxygen_write_ac97(chip, 1, AC97_HEADPHONE, 0x8000);
+ oxygen_write_ac97(chip, 1, AC97_PC_BEEP, 0x8000);
+ oxygen_write_ac97(chip, 1, AC97_MIC, 0x8808);
+ oxygen_write_ac97(chip, 1, AC97_LINE, 0x8808);
+ oxygen_write_ac97(chip, 1, AC97_CD, 0x8808);
+ oxygen_write_ac97(chip, 1, AC97_VIDEO, 0x8808);
+ oxygen_write_ac97(chip, 1, AC97_AUX, 0x8808);
+ oxygen_write_ac97(chip, 1, AC97_PCM, 0x0808);
+ oxygen_write_ac97(chip, 1, AC97_REC_SEL, 0x0000);
+ oxygen_write_ac97(chip, 1, AC97_REC_GAIN, 0x8000);
+ oxygen_ac97_clear_bits(chip, 1, AC97_REC_GAIN, 0x1c00);
+ oxygen_ac97_set_bits(chip, 1, 0x6a, 0x0040);
+ }
}
static void oxygen_card_free(struct snd_card *card)
static unsigned int oxygen_i2s_mclk(struct snd_pcm_hw_params *hw_params)
{
- return params_rate(hw_params) <= 96000
- ? OXYGEN_I2S_MCLK_256 : OXYGEN_I2S_MCLK_128;
+ if (params_rate(hw_params) <= 96000)
+ return OXYGEN_I2S_MCLK_256;
+ else
+ return OXYGEN_I2S_MCLK_128;
}
static unsigned int oxygen_i2s_bits(struct snd_pcm_hw_params *hw_params)
OXYGEN_I2S_FORMAT_MASK |
OXYGEN_I2S_MCLK_MASK |
OXYGEN_I2S_BITS_MASK);
- oxygen_write8_masked(chip, OXYGEN_REC_ROUTING,
- OXYGEN_REC_A_ROUTE_I2S_ADC_1,
- OXYGEN_REC_A_ROUTE_MASK);
spin_unlock_irq(&chip->reg_lock);
mutex_lock(&chip->mutex);
OXYGEN_I2S_FORMAT_MASK |
OXYGEN_I2S_MCLK_MASK |
OXYGEN_I2S_BITS_MASK);
- oxygen_write8_masked(chip, OXYGEN_REC_ROUTING,
- OXYGEN_REC_B_ROUTE_I2S_ADC_2,
- OXYGEN_REC_B_ROUTE_MASK);
spin_unlock_irq(&chip->reg_lock);
mutex_lock(&chip->mutex);
oxygen_write8_masked(chip, OXYGEN_REC_FORMAT,
oxygen_format(hw_params) << OXYGEN_REC_FORMAT_C_SHIFT,
OXYGEN_REC_FORMAT_C_MASK);
- oxygen_write8_masked(chip, OXYGEN_REC_ROUTING,
- OXYGEN_REC_C_ROUTE_SPDIF,
- OXYGEN_REC_C_ROUTE_MASK);
spin_unlock_irq(&chip->reg_lock);
return 0;
}
OXYGEN_I2S_RATE_MASK |
OXYGEN_I2S_FORMAT_MASK |
OXYGEN_I2S_BITS_MASK);
- oxygen_write16_masked(chip, OXYGEN_PLAY_ROUTING,
- OXYGEN_PLAY_MULTICH_I2S_DAC,
- OXYGEN_PLAY_MUTE01 | OXYGEN_PLAY_MUTE23 |
- OXYGEN_PLAY_MUTE45 | OXYGEN_PLAY_MUTE67 |
- OXYGEN_PLAY_MULTICH_MASK);
oxygen_update_dac_routing(chip);
oxygen_update_spdif_source(chip);
spin_unlock_irq(&chip->reg_lock);