imx: mx6: Fix incorrect clear mmdc_ch0 handshake mask
authorYe Li <ye.li@nxp.com>
Wed, 9 Mar 2016 08:13:48 +0000 (16:13 +0800)
committerStefano Babic <sbabic@denx.de>
Fri, 25 Mar 2016 12:55:54 +0000 (13:55 +0100)
Since the MX6UL/SL/SX only has one DDR channel, in CCM_CCDR register
the bit[17] for mmdc_ch0 is reserved and its proper state should be 1.
When clear this bit, the periph_clk_sel cannot be set and that
CDHIPR[periph_clk_sel_busy] handshake never clears.

Signed-off-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <van.freenix@gmail.com>
Acked-by: Stefano Babic <sbabic@denx.de>
arch/arm/cpu/armv7/mx6/soc.c

index 91a3deb..bdd41b0 100644 (file)
@@ -278,7 +278,10 @@ static void clear_mmdc_ch_mask(void)
        reg = readl(&mxc_ccm->ccdr);
 
        /* Clear MMDC channel mask */
-       reg &= ~(MXC_CCM_CCDR_MMDC_CH1_HS_MASK | MXC_CCM_CCDR_MMDC_CH0_HS_MASK);
+       if (is_cpu_type(MXC_CPU_MX6SX) || is_cpu_type(MXC_CPU_MX6UL) || is_cpu_type(MXC_CPU_MX6SL))
+               reg &= ~(MXC_CCM_CCDR_MMDC_CH1_HS_MASK);
+       else
+               reg &= ~(MXC_CCM_CCDR_MMDC_CH1_HS_MASK | MXC_CCM_CCDR_MMDC_CH0_HS_MASK);
        writel(reg, &mxc_ccm->ccdr);
 }