+++ /dev/null
-/*
- * STM32F2XX ADC
- *
- * Copyright (c) 2014 Alistair Francis <alistair@alistair23.me>
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
- * furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
- * THE SOFTWARE.
- */
-
-#ifndef HW_STM32F2XX_ADC_H
-#define HW_STM32F2XX_ADC_H
-
-#include "hw/sysbus.h"
-#include "qom/object.h"
-
-#define ADC_SR 0x00
-#define ADC_CR1 0x04
-#define ADC_CR2 0x08
-#define ADC_SMPR1 0x0C
-#define ADC_SMPR2 0x10
-#define ADC_JOFR1 0x14
-#define ADC_JOFR2 0x18
-#define ADC_JOFR3 0x1C
-#define ADC_JOFR4 0x20
-#define ADC_HTR 0x24
-#define ADC_LTR 0x28
-#define ADC_SQR1 0x2C
-#define ADC_SQR2 0x30
-#define ADC_SQR3 0x34
-#define ADC_JSQR 0x38
-#define ADC_JDR1 0x3C
-#define ADC_JDR2 0x40
-#define ADC_JDR3 0x44
-#define ADC_JDR4 0x48
-#define ADC_DR 0x4C
-
-#define ADC_CR2_ADON 0x01
-#define ADC_CR2_CONT 0x02
-#define ADC_CR2_ALIGN 0x800
-#define ADC_CR2_SWSTART 0x40000000
-
-#define ADC_CR1_RES 0x3000000
-
-#define ADC_COMMON_ADDRESS 0x100
-
-#define TYPE_STM32F2XX_ADC "stm32f2xx-adc"
-OBJECT_DECLARE_SIMPLE_TYPE(STM32F2XXADCState, STM32F2XX_ADC)
-
-struct STM32F2XXADCState {
- /* <private> */
- SysBusDevice parent_obj;
-
- /* <public> */
- MemoryRegion mmio;
-
- uint32_t adc_sr;
- uint32_t adc_cr1;
- uint32_t adc_cr2;
- uint32_t adc_smpr1;
- uint32_t adc_smpr2;
- uint32_t adc_jofr[4];
- uint32_t adc_htr;
- uint32_t adc_ltr;
- uint32_t adc_sqr1;
- uint32_t adc_sqr2;
- uint32_t adc_sqr3;
- uint32_t adc_jsqr;
- uint32_t adc_jdr[4];
- uint32_t adc_dr;
-
- qemu_irq irq;
-};
-
-#endif /* HW_STM32F2XX_ADC_H */
+++ /dev/null
-#ifndef HW_ARM_ALLWINNER_A10_H
-#define HW_ARM_ALLWINNER_A10_H
-
-#include "qemu/error-report.h"
-#include "hw/char/serial.h"
-#include "hw/arm/boot.h"
-#include "hw/timer/allwinner-a10-pit.h"
-#include "hw/intc/allwinner-a10-pic.h"
-#include "hw/net/allwinner_emac.h"
-#include "hw/sd/allwinner-sdhost.h"
-#include "hw/ide/ahci.h"
-#include "hw/usb/hcd-ohci.h"
-#include "hw/usb/hcd-ehci.h"
-#include "hw/rtc/allwinner-rtc.h"
-
-#include "target/arm/cpu.h"
-#include "qom/object.h"
-
-
-#define AW_A10_SDRAM_BASE 0x40000000
-
-#define AW_A10_NUM_USB 2
-
-#define TYPE_AW_A10 "allwinner-a10"
-OBJECT_DECLARE_SIMPLE_TYPE(AwA10State, AW_A10)
-
-struct AwA10State {
- /*< private >*/
- DeviceState parent_obj;
- /*< public >*/
-
- ARMCPU cpu;
- AwA10PITState timer;
- AwA10PICState intc;
- AwEmacState emac;
- AllwinnerAHCIState sata;
- AwSdHostState mmc0;
- AwRtcState rtc;
- MemoryRegion sram_a;
- EHCISysBusState ehci[AW_A10_NUM_USB];
- OHCISysBusState ohci[AW_A10_NUM_USB];
-};
-
-#endif
+++ /dev/null
-/*
- * Allwinner H3 System on Chip emulation
- *
- * Copyright (C) 2019 Niek Linnenbank <nieklinnenbank@gmail.com>
- *
- * This program is free software: you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation, either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program. If not, see <http://www.gnu.org/licenses/>.
- */
-
-/*
- * The Allwinner H3 is a System on Chip containing four ARM Cortex A7
- * processor cores. Features and specifications include DDR2/DDR3 memory,
- * SD/MMC storage cards, 10/100/1000Mbit Ethernet, USB 2.0, HDMI and
- * various I/O modules.
- *
- * This implementation is based on the following datasheet:
- *
- * https://linux-sunxi.org/File:Allwinner_H3_Datasheet_V1.2.pdf
- *
- * The latest datasheet and more info can be found on the Linux Sunxi wiki:
- *
- * https://linux-sunxi.org/H3
- */
-
-#ifndef HW_ARM_ALLWINNER_H3_H
-#define HW_ARM_ALLWINNER_H3_H
-
-#include "qom/object.h"
-#include "hw/arm/boot.h"
-#include "hw/timer/allwinner-a10-pit.h"
-#include "hw/intc/arm_gic.h"
-#include "hw/misc/allwinner-h3-ccu.h"
-#include "hw/misc/allwinner-cpucfg.h"
-#include "hw/misc/allwinner-h3-dramc.h"
-#include "hw/misc/allwinner-h3-sysctrl.h"
-#include "hw/misc/allwinner-sid.h"
-#include "hw/sd/allwinner-sdhost.h"
-#include "hw/net/allwinner-sun8i-emac.h"
-#include "hw/rtc/allwinner-rtc.h"
-#include "target/arm/cpu.h"
-#include "sysemu/block-backend.h"
-
-/**
- * Allwinner H3 device list
- *
- * This enumeration is can be used refer to a particular device in the
- * Allwinner H3 SoC. For example, the physical memory base address for
- * each device can be found in the AwH3State object in the memmap member
- * using the device enum value as index.
- *
- * @see AwH3State
- */
-enum {
- AW_H3_DEV_SRAM_A1,
- AW_H3_DEV_SRAM_A2,
- AW_H3_DEV_SRAM_C,
- AW_H3_DEV_SYSCTRL,
- AW_H3_DEV_MMC0,
- AW_H3_DEV_SID,
- AW_H3_DEV_EHCI0,
- AW_H3_DEV_OHCI0,
- AW_H3_DEV_EHCI1,
- AW_H3_DEV_OHCI1,
- AW_H3_DEV_EHCI2,
- AW_H3_DEV_OHCI2,
- AW_H3_DEV_EHCI3,
- AW_H3_DEV_OHCI3,
- AW_H3_DEV_CCU,
- AW_H3_DEV_PIT,
- AW_H3_DEV_UART0,
- AW_H3_DEV_UART1,
- AW_H3_DEV_UART2,
- AW_H3_DEV_UART3,
- AW_H3_DEV_EMAC,
- AW_H3_DEV_DRAMCOM,
- AW_H3_DEV_DRAMCTL,
- AW_H3_DEV_DRAMPHY,
- AW_H3_DEV_GIC_DIST,
- AW_H3_DEV_GIC_CPU,
- AW_H3_DEV_GIC_HYP,
- AW_H3_DEV_GIC_VCPU,
- AW_H3_DEV_RTC,
- AW_H3_DEV_CPUCFG,
- AW_H3_DEV_SDRAM
-};
-
-/** Total number of CPU cores in the H3 SoC */
-#define AW_H3_NUM_CPUS (4)
-
-/**
- * Allwinner H3 object model
- * @{
- */
-
-/** Object type for the Allwinner H3 SoC */
-#define TYPE_AW_H3 "allwinner-h3"
-
-/** Convert input object to Allwinner H3 state object */
-OBJECT_DECLARE_SIMPLE_TYPE(AwH3State, AW_H3)
-
-/** @} */
-
-/**
- * Allwinner H3 object
- *
- * This struct contains the state of all the devices
- * which are currently emulated by the H3 SoC code.
- */
-struct AwH3State {
- /*< private >*/
- DeviceState parent_obj;
- /*< public >*/
-
- ARMCPU cpus[AW_H3_NUM_CPUS];
- const hwaddr *memmap;
- AwA10PITState timer;
- AwH3ClockCtlState ccu;
- AwCpuCfgState cpucfg;
- AwH3DramCtlState dramc;
- AwH3SysCtrlState sysctrl;
- AwSidState sid;
- AwSdHostState mmc0;
- AwSun8iEmacState emac;
- AwRtcState rtc;
- GICState gic;
- MemoryRegion sram_a1;
- MemoryRegion sram_a2;
- MemoryRegion sram_c;
-};
-
-/**
- * Emulate Boot ROM firmware setup functionality.
- *
- * A real Allwinner H3 SoC contains a Boot ROM
- * which is the first code that runs right after
- * the SoC is powered on. The Boot ROM is responsible
- * for loading user code (e.g. a bootloader) from any
- * of the supported external devices and writing the
- * downloaded code to internal SRAM. After loading the SoC
- * begins executing the code written to SRAM.
- *
- * This function emulates the Boot ROM by copying 32 KiB
- * of data from the given block device and writes it to
- * the start of the first internal SRAM memory.
- *
- * @s: Allwinner H3 state object pointer
- * @blk: Block backend device object pointer
- */
-void allwinner_h3_bootrom_setup(AwH3State *s, BlockBackend *blk);
-
-#endif /* HW_ARM_ALLWINNER_H3_H */
+++ /dev/null
-/*
- * ARM SSE (Subsystems for Embedded): IoTKit, SSE-200
- *
- * Copyright (c) 2018 Linaro Limited
- * Written by Peter Maydell
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 or
- * (at your option) any later version.
- */
-
-/*
- * This is a model of the Arm "Subsystems for Embedded" family of
- * hardware, which include the IoT Kit and the SSE-050, SSE-100 and
- * SSE-200. Currently we model:
- * - the Arm IoT Kit which is documented in
- * http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ecm0601256/index.html
- * - the SSE-200 which is documented in
- * http://infocenter.arm.com/help/topic/com.arm.doc.101104_0100_00_en/corelink_sse200_subsystem_for_embedded_technical_reference_manual_101104_0100_00_en.pdf
- *
- * The IoTKit contains:
- * a Cortex-M33
- * the IDAU
- * some timers and watchdogs
- * two peripheral protection controllers
- * a memory protection controller
- * a security controller
- * a bus fabric which arranges that some parts of the address
- * space are secure and non-secure aliases of each other
- * The SSE-200 additionally contains:
- * a second Cortex-M33
- * two Message Handling Units (MHUs)
- * an optional CryptoCell (which we do not model)
- * more SRAM banks with associated MPCs
- * multiple Power Policy Units (PPUs)
- * a control interface for an icache for each CPU
- * per-CPU identity and control register blocks
- *
- * QEMU interface:
- * + QOM property "memory" is a MemoryRegion containing the devices provided
- * by the board model.
- * + QOM property "MAINCLK" is the frequency of the main system clock
- * + QOM property "EXP_NUMIRQ" sets the number of expansion interrupts.
- * (In hardware, the SSE-200 permits the number of expansion interrupts
- * for the two CPUs to be configured separately, but we restrict it to
- * being the same for both, to avoid having to have separate Property
- * lists for different variants. This restriction can be relaxed later
- * if necessary.)
- * + QOM property "SRAM_ADDR_WIDTH" sets the number of bits used for the
- * address of each SRAM bank (and thus the total amount of internal SRAM)
- * + QOM property "init-svtor" sets the initial value of the CPU SVTOR register
- * (where it expects to load the PC and SP from the vector table on reset)
- * + QOM properties "CPU0_FPU", "CPU0_DSP", "CPU1_FPU" and "CPU1_DSP" which
- * set whether the CPUs have the FPU and DSP features present. The default
- * (matching the hardware) is that for CPU0 in an IoTKit and CPU1 in an
- * SSE-200 both are present; CPU0 in an SSE-200 has neither.
- * Since the IoTKit has only one CPU, it does not have the CPU1_* properties.
- * + Named GPIO inputs "EXP_IRQ" 0..n are the expansion interrupts for CPU 0,
- * which are wired to its NVIC lines 32 .. n+32
- * + Named GPIO inputs "EXP_CPU1_IRQ" 0..n are the expansion interrupts for
- * CPU 1, which are wired to its NVIC lines 32 .. n+32
- * + sysbus MMIO region 0 is the "AHB Slave Expansion" which allows
- * bus master devices in the board model to make transactions into
- * all the devices and memory areas in the IoTKit
- * Controlling up to 4 AHB expansion PPBs which a system using the IoTKit
- * might provide:
- * + named GPIO outputs apb_ppcexp{0,1,2,3}_nonsec[0..15]
- * + named GPIO outputs apb_ppcexp{0,1,2,3}_ap[0..15]
- * + named GPIO outputs apb_ppcexp{0,1,2,3}_irq_enable
- * + named GPIO outputs apb_ppcexp{0,1,2,3}_irq_clear
- * + named GPIO inputs apb_ppcexp{0,1,2,3}_irq_status
- * Controlling each of the 4 expansion AHB PPCs which a system using the IoTKit
- * might provide:
- * + named GPIO outputs ahb_ppcexp{0,1,2,3}_nonsec[0..15]
- * + named GPIO outputs ahb_ppcexp{0,1,2,3}_ap[0..15]
- * + named GPIO outputs ahb_ppcexp{0,1,2,3}_irq_enable
- * + named GPIO outputs ahb_ppcexp{0,1,2,3}_irq_clear
- * + named GPIO inputs ahb_ppcexp{0,1,2,3}_irq_status
- * Controlling each of the 16 expansion MPCs which a system using the IoTKit
- * might provide:
- * + named GPIO inputs mpcexp_status[0..15]
- * Controlling each of the 16 expansion MSCs which a system using the IoTKit
- * might provide:
- * + named GPIO inputs mscexp_status[0..15]
- * + named GPIO outputs mscexp_clear[0..15]
- * + named GPIO outputs mscexp_ns[0..15]
- */
-
-#ifndef ARMSSE_H
-#define ARMSSE_H
-
-#include "hw/sysbus.h"
-#include "hw/arm/armv7m.h"
-#include "hw/misc/iotkit-secctl.h"
-#include "hw/misc/tz-ppc.h"
-#include "hw/misc/tz-mpc.h"
-#include "hw/timer/cmsdk-apb-timer.h"
-#include "hw/timer/cmsdk-apb-dualtimer.h"
-#include "hw/watchdog/cmsdk-apb-watchdog.h"
-#include "hw/misc/iotkit-sysctl.h"
-#include "hw/misc/iotkit-sysinfo.h"
-#include "hw/misc/armsse-cpuid.h"
-#include "hw/misc/armsse-mhu.h"
-#include "hw/misc/unimp.h"
-#include "hw/or-irq.h"
-#include "hw/core/split-irq.h"
-#include "hw/cpu/cluster.h"
-#include "qom/object.h"
-
-#define TYPE_ARM_SSE "arm-sse"
-OBJECT_DECLARE_TYPE(ARMSSE, ARMSSEClass,
- ARM_SSE)
-
-/*
- * These type names are for specific IoTKit subsystems; other than
- * instantiating them, code using these devices should always handle
- * them via the ARMSSE base class, so they have no IOTKIT() etc macros.
- */
-#define TYPE_IOTKIT "iotkit"
-#define TYPE_SSE200 "sse-200"
-
-/* We have an IRQ splitter and an OR gate input for each external PPC
- * and the 2 internal PPCs
- */
-#define NUM_EXTERNAL_PPCS (IOTS_NUM_AHB_EXP_PPC + IOTS_NUM_APB_EXP_PPC)
-#define NUM_PPCS (NUM_EXTERNAL_PPCS + 2)
-
-#define MAX_SRAM_BANKS 4
-#if MAX_SRAM_BANKS > IOTS_NUM_MPC
-#error Too many SRAM banks
-#endif
-
-#define SSE_MAX_CPUS 2
-
-/* These define what each PPU in the ppu[] index is for */
-#define CPU0CORE_PPU 0
-#define CPU1CORE_PPU 1
-#define DBG_PPU 2
-#define RAM0_PPU 3
-#define RAM1_PPU 4
-#define RAM2_PPU 5
-#define RAM3_PPU 6
-#define NUM_PPUS 7
-
-struct ARMSSE {
- /*< private >*/
- SysBusDevice parent_obj;
-
- /*< public >*/
- ARMv7MState armv7m[SSE_MAX_CPUS];
- CPUClusterState cluster[SSE_MAX_CPUS];
- IoTKitSecCtl secctl;
- TZPPC apb_ppc0;
- TZPPC apb_ppc1;
- TZMPC mpc[IOTS_NUM_MPC];
- CMSDKAPBTIMER timer0;
- CMSDKAPBTIMER timer1;
- CMSDKAPBTIMER s32ktimer;
- qemu_or_irq ppc_irq_orgate;
- SplitIRQ sec_resp_splitter;
- SplitIRQ ppc_irq_splitter[NUM_PPCS];
- SplitIRQ mpc_irq_splitter[IOTS_NUM_EXP_MPC + IOTS_NUM_MPC];
- qemu_or_irq mpc_irq_orgate;
- qemu_or_irq nmi_orgate;
-
- SplitIRQ cpu_irq_splitter[32];
-
- CMSDKAPBDualTimer dualtimer;
-
- CMSDKAPBWatchdog s32kwatchdog;
- CMSDKAPBWatchdog nswatchdog;
- CMSDKAPBWatchdog swatchdog;
-
- IoTKitSysCtl sysctl;
- IoTKitSysCtl sysinfo;
-
- ARMSSEMHU mhu[2];
- UnimplementedDeviceState ppu[NUM_PPUS];
- UnimplementedDeviceState cachectrl[SSE_MAX_CPUS];
- UnimplementedDeviceState cpusecctrl[SSE_MAX_CPUS];
-
- ARMSSECPUID cpuid[SSE_MAX_CPUS];
-
- /*
- * 'container' holds all devices seen by all CPUs.
- * 'cpu_container[i]' is the view that CPU i has: this has the
- * per-CPU devices of that CPU, plus as the background 'container'
- * (or an alias of it, since we can only use it directly once).
- * container_alias[i] is the alias of 'container' used by CPU i+1;
- * CPU 0 can use 'container' directly.
- */
- MemoryRegion container;
- MemoryRegion container_alias[SSE_MAX_CPUS - 1];
- MemoryRegion cpu_container[SSE_MAX_CPUS];
- MemoryRegion alias1;
- MemoryRegion alias2;
- MemoryRegion alias3[SSE_MAX_CPUS];
- MemoryRegion sram[MAX_SRAM_BANKS];
-
- qemu_irq *exp_irqs[SSE_MAX_CPUS];
- qemu_irq ppc0_irq;
- qemu_irq ppc1_irq;
- qemu_irq sec_resp_cfg;
- qemu_irq sec_resp_cfg_in;
- qemu_irq nsc_cfg_in;
-
- qemu_irq irq_status_in[NUM_EXTERNAL_PPCS];
- qemu_irq mpcexp_status_in[IOTS_NUM_EXP_MPC];
-
- uint32_t nsccfg;
-
- /* Properties */
- MemoryRegion *board_memory;
- uint32_t exp_numirq;
- uint32_t mainclk_frq;
- uint32_t sram_addr_width;
- uint32_t init_svtor;
- bool cpu_fpu[SSE_MAX_CPUS];
- bool cpu_dsp[SSE_MAX_CPUS];
-};
-
-typedef struct ARMSSEInfo ARMSSEInfo;
-
-struct ARMSSEClass {
- SysBusDeviceClass parent_class;
- const ARMSSEInfo *info;
-};
-
-
-#endif
+++ /dev/null
-/*
- * ARMv7M CPU object
- *
- * Copyright (c) 2017 Linaro Ltd
- * Written by Peter Maydell <peter.maydell@linaro.org>
- *
- * This code is licensed under the GPL version 2 or later.
- */
-
-#ifndef HW_ARM_ARMV7M_H
-#define HW_ARM_ARMV7M_H
-
-#include "hw/sysbus.h"
-#include "hw/intc/armv7m_nvic.h"
-#include "target/arm/idau.h"
-#include "qom/object.h"
-
-#define TYPE_BITBAND "ARM,bitband-memory"
-OBJECT_DECLARE_SIMPLE_TYPE(BitBandState, BITBAND)
-
-struct BitBandState {
- /*< private >*/
- SysBusDevice parent_obj;
- /*< public >*/
-
- AddressSpace source_as;
- MemoryRegion iomem;
- uint32_t base;
- MemoryRegion *source_memory;
-};
-
-#define TYPE_ARMV7M "armv7m"
-OBJECT_DECLARE_SIMPLE_TYPE(ARMv7MState, ARMV7M)
-
-#define ARMV7M_NUM_BITBANDS 2
-
-/* ARMv7M container object.
- * + Unnamed GPIO input lines: external IRQ lines for the NVIC
- * + Named GPIO output SYSRESETREQ: signalled for guest AIRCR.SYSRESETREQ.
- * If this GPIO is not wired up then the NVIC will default to performing
- * a qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET).
- * + Property "cpu-type": CPU type to instantiate
- * + Property "num-irq": number of external IRQ lines
- * + Property "memory": MemoryRegion defining the physical address space
- * that CPU accesses see. (The NVIC, bitbanding and other CPU-internal
- * devices will be automatically layered on top of this view.)
- * + Property "idau": IDAU interface (forwarded to CPU object)
- * + Property "init-svtor": secure VTOR reset value (forwarded to CPU object)
- * + Property "vfp": enable VFP (forwarded to CPU object)
- * + Property "dsp": enable DSP (forwarded to CPU object)
- * + Property "enable-bitband": expose bitbanded IO
- */
-struct ARMv7MState {
- /*< private >*/
- SysBusDevice parent_obj;
- /*< public >*/
- NVICState nvic;
- BitBandState bitband[ARMV7M_NUM_BITBANDS];
- ARMCPU *cpu;
-
- /* MemoryRegion we pass to the CPU, with our devices layered on
- * top of the ones the board provides in board_memory.
- */
- MemoryRegion container;
-
- /* Properties */
- char *cpu_type;
- /* MemoryRegion the board provides to us (with its devices, RAM, etc) */
- MemoryRegion *board_memory;
- Object *idau;
- uint32_t init_svtor;
- bool enable_bitband;
- bool start_powered_off;
- bool vfp;
- bool dsp;
-};
-
-#endif
+++ /dev/null
-/*
- * Aspeed Machines
- *
- * Copyright 2018 IBM Corp.
- *
- * This code is licensed under the GPL version 2 or later. See
- * the COPYING file in the top-level directory.
- */
-#ifndef ARM_ASPEED_H
-#define ARM_ASPEED_H
-
-#include "hw/boards.h"
-#include "qom/object.h"
-
-typedef struct AspeedMachineState AspeedMachineState;
-
-#define TYPE_ASPEED_MACHINE MACHINE_TYPE_NAME("aspeed")
-typedef struct AspeedMachineClass AspeedMachineClass;
-DECLARE_OBJ_CHECKERS(AspeedMachineState, AspeedMachineClass,
- ASPEED_MACHINE, TYPE_ASPEED_MACHINE)
-
-#define ASPEED_MAC0_ON (1 << 0)
-#define ASPEED_MAC1_ON (1 << 1)
-#define ASPEED_MAC2_ON (1 << 2)
-#define ASPEED_MAC3_ON (1 << 3)
-
-
-struct AspeedMachineClass {
- MachineClass parent_obj;
-
- const char *name;
- const char *desc;
- const char *soc_name;
- uint32_t hw_strap1;
- uint32_t hw_strap2;
- const char *fmc_model;
- const char *spi_model;
- uint32_t num_cs;
- uint32_t macs_mask;
- void (*i2c_init)(AspeedMachineState *bmc);
-};
-
-
-#endif
+++ /dev/null
-/*
- * ASPEED SoC family
- *
- * Andrew Jeffery <andrew@aj.id.au>
- *
- * Copyright 2016 IBM Corp.
- *
- * This code is licensed under the GPL version 2 or later. See
- * the COPYING file in the top-level directory.
- */
-
-#ifndef ASPEED_SOC_H
-#define ASPEED_SOC_H
-
-#include "hw/cpu/a15mpcore.h"
-#include "hw/intc/aspeed_vic.h"
-#include "hw/misc/aspeed_scu.h"
-#include "hw/misc/aspeed_sdmc.h"
-#include "hw/misc/aspeed_xdma.h"
-#include "hw/timer/aspeed_timer.h"
-#include "hw/rtc/aspeed_rtc.h"
-#include "hw/i2c/aspeed_i2c.h"
-#include "hw/ssi/aspeed_smc.h"
-#include "hw/watchdog/wdt_aspeed.h"
-#include "hw/net/ftgmac100.h"
-#include "target/arm/cpu.h"
-#include "hw/gpio/aspeed_gpio.h"
-#include "hw/sd/aspeed_sdhci.h"
-#include "hw/usb/hcd-ehci.h"
-#include "qom/object.h"
-
-#define ASPEED_SPIS_NUM 2
-#define ASPEED_EHCIS_NUM 2
-#define ASPEED_WDTS_NUM 4
-#define ASPEED_CPUS_NUM 2
-#define ASPEED_MACS_NUM 4
-
-struct AspeedSoCState {
- /*< private >*/
- DeviceState parent;
-
- /*< public >*/
- ARMCPU cpu[ASPEED_CPUS_NUM];
- A15MPPrivState a7mpcore;
- MemoryRegion *dram_mr;
- MemoryRegion sram;
- AspeedVICState vic;
- AspeedRtcState rtc;
- AspeedTimerCtrlState timerctrl;
- AspeedI2CState i2c;
- AspeedSCUState scu;
- AspeedXDMAState xdma;
- AspeedSMCState fmc;
- AspeedSMCState spi[ASPEED_SPIS_NUM];
- EHCISysBusState ehci[ASPEED_EHCIS_NUM];
- AspeedSDMCState sdmc;
- AspeedWDTState wdt[ASPEED_WDTS_NUM];
- FTGMAC100State ftgmac100[ASPEED_MACS_NUM];
- AspeedMiiState mii[ASPEED_MACS_NUM];
- AspeedGPIOState gpio;
- AspeedGPIOState gpio_1_8v;
- AspeedSDHCIState sdhci;
- AspeedSDHCIState emmc;
-};
-
-#define TYPE_ASPEED_SOC "aspeed-soc"
-OBJECT_DECLARE_TYPE(AspeedSoCState, AspeedSoCClass, ASPEED_SOC)
-
-struct AspeedSoCClass {
- DeviceClass parent_class;
-
- const char *name;
- const char *cpu_type;
- uint32_t silicon_rev;
- uint64_t sram_size;
- int spis_num;
- int ehcis_num;
- int wdts_num;
- int macs_num;
- const int *irqmap;
- const hwaddr *memmap;
- uint32_t num_cpus;
-};
-
-
-enum {
- ASPEED_DEV_IOMEM,
- ASPEED_DEV_UART1,
- ASPEED_DEV_UART2,
- ASPEED_DEV_UART3,
- ASPEED_DEV_UART4,
- ASPEED_DEV_UART5,
- ASPEED_DEV_VUART,
- ASPEED_DEV_FMC,
- ASPEED_DEV_SPI1,
- ASPEED_DEV_SPI2,
- ASPEED_DEV_EHCI1,
- ASPEED_DEV_EHCI2,
- ASPEED_DEV_VIC,
- ASPEED_DEV_SDMC,
- ASPEED_DEV_SCU,
- ASPEED_DEV_ADC,
- ASPEED_DEV_VIDEO,
- ASPEED_DEV_SRAM,
- ASPEED_DEV_SDHCI,
- ASPEED_DEV_GPIO,
- ASPEED_DEV_GPIO_1_8V,
- ASPEED_DEV_RTC,
- ASPEED_DEV_TIMER1,
- ASPEED_DEV_TIMER2,
- ASPEED_DEV_TIMER3,
- ASPEED_DEV_TIMER4,
- ASPEED_DEV_TIMER5,
- ASPEED_DEV_TIMER6,
- ASPEED_DEV_TIMER7,
- ASPEED_DEV_TIMER8,
- ASPEED_DEV_WDT,
- ASPEED_DEV_PWM,
- ASPEED_DEV_LPC,
- ASPEED_DEV_IBT,
- ASPEED_DEV_I2C,
- ASPEED_DEV_ETH1,
- ASPEED_DEV_ETH2,
- ASPEED_DEV_ETH3,
- ASPEED_DEV_ETH4,
- ASPEED_DEV_MII1,
- ASPEED_DEV_MII2,
- ASPEED_DEV_MII3,
- ASPEED_DEV_MII4,
- ASPEED_DEV_SDRAM,
- ASPEED_DEV_XDMA,
- ASPEED_DEV_EMMC,
-};
-
-#endif /* ASPEED_SOC_H */
+++ /dev/null
-/*
- * Raspberry Pi emulation (c) 2012 Gregory Estrade
- * Upstreaming code cleanup [including bcm2835_*] (c) 2013 Jan Petrous
- *
- * Rasperry Pi 2 emulation and refactoring Copyright (c) 2015, Microsoft
- * Written by Andrew Baumann
- *
- * This work is licensed under the terms of the GNU GPL, version 2 or later.
- * See the COPYING file in the top-level directory.
- */
-
-#ifndef BCM2835_PERIPHERALS_H
-#define BCM2835_PERIPHERALS_H
-
-#include "hw/sysbus.h"
-#include "hw/char/pl011.h"
-#include "hw/char/bcm2835_aux.h"
-#include "hw/display/bcm2835_fb.h"
-#include "hw/dma/bcm2835_dma.h"
-#include "hw/intc/bcm2835_ic.h"
-#include "hw/misc/bcm2835_property.h"
-#include "hw/misc/bcm2835_rng.h"
-#include "hw/misc/bcm2835_mbox.h"
-#include "hw/misc/bcm2835_mphi.h"
-#include "hw/misc/bcm2835_thermal.h"
-#include "hw/misc/bcm2835_cprman.h"
-#include "hw/sd/sdhci.h"
-#include "hw/sd/bcm2835_sdhost.h"
-#include "hw/gpio/bcm2835_gpio.h"
-#include "hw/timer/bcm2835_systmr.h"
-#include "hw/usb/hcd-dwc2.h"
-#include "hw/misc/unimp.h"
-#include "qom/object.h"
-
-#define TYPE_BCM2835_PERIPHERALS "bcm2835-peripherals"
-OBJECT_DECLARE_SIMPLE_TYPE(BCM2835PeripheralState, BCM2835_PERIPHERALS)
-
-struct BCM2835PeripheralState {
- /*< private >*/
- SysBusDevice parent_obj;
- /*< public >*/
-
- MemoryRegion peri_mr, peri_mr_alias, gpu_bus_mr, mbox_mr;
- MemoryRegion ram_alias[4];
- qemu_irq irq, fiq;
-
- BCM2835SystemTimerState systmr;
- BCM2835MphiState mphi;
- UnimplementedDeviceState txp;
- UnimplementedDeviceState armtmr;
- UnimplementedDeviceState powermgt;
- BCM2835CprmanState cprman;
- PL011State uart0;
- BCM2835AuxState aux;
- BCM2835FBState fb;
- BCM2835DMAState dma;
- BCM2835ICState ic;
- BCM2835PropertyState property;
- BCM2835RngState rng;
- BCM2835MboxState mboxes;
- SDHCIState sdhci;
- BCM2835SDHostState sdhost;
- BCM2835GpioState gpio;
- Bcm2835ThermalState thermal;
- UnimplementedDeviceState i2s;
- UnimplementedDeviceState spi[1];
- UnimplementedDeviceState i2c[3];
- UnimplementedDeviceState otp;
- UnimplementedDeviceState dbus;
- UnimplementedDeviceState ave0;
- UnimplementedDeviceState v3d;
- UnimplementedDeviceState bscsl;
- UnimplementedDeviceState smi;
- DWC2State dwc2;
- UnimplementedDeviceState sdramc;
-};
-
-#endif /* BCM2835_PERIPHERALS_H */
+++ /dev/null
-/*
- * Raspberry Pi emulation (c) 2012 Gregory Estrade
- * Upstreaming code cleanup [including bcm2835_*] (c) 2013 Jan Petrous
- *
- * Rasperry Pi 2 emulation and refactoring Copyright (c) 2015, Microsoft
- * Written by Andrew Baumann
- *
- * This work is licensed under the terms of the GNU GPL, version 2 or later.
- * See the COPYING file in the top-level directory.
- */
-
-#ifndef BCM2836_H
-#define BCM2836_H
-
-#include "hw/arm/bcm2835_peripherals.h"
-#include "hw/intc/bcm2836_control.h"
-#include "target/arm/cpu.h"
-#include "qom/object.h"
-
-#define TYPE_BCM283X "bcm283x"
-OBJECT_DECLARE_TYPE(BCM283XState, BCM283XClass, BCM283X)
-
-#define BCM283X_NCPUS 4
-
-/* These type names are for specific SoCs; other than instantiating
- * them, code using these devices should always handle them via the
- * BCM283x base class, so they have no BCM2836(obj) etc macros.
- */
-#define TYPE_BCM2835 "bcm2835"
-#define TYPE_BCM2836 "bcm2836"
-#define TYPE_BCM2837 "bcm2837"
-
-struct BCM283XState {
- /*< private >*/
- DeviceState parent_obj;
- /*< public >*/
-
- uint32_t enabled_cpus;
-
- struct {
- ARMCPU core;
- } cpu[BCM283X_NCPUS];
- BCM2836ControlState control;
- BCM2835PeripheralState peripherals;
-};
-
-#endif /* BCM2836_H */
+++ /dev/null
-/*
- * ARM kernel loader.
- *
- * Copyright (c) 2006 CodeSourcery.
- * Written by Paul Brook
- *
- * This code is licensed under the LGPL.
- *
- */
-
-#ifndef HW_ARM_BOOT_H
-#define HW_ARM_BOOT_H
-
-#include "target/arm/cpu-qom.h"
-#include "qemu/notify.h"
-
-typedef enum {
- ARM_ENDIANNESS_UNKNOWN = 0,
- ARM_ENDIANNESS_LE,
- ARM_ENDIANNESS_BE8,
- ARM_ENDIANNESS_BE32,
-} arm_endianness;
-
-/**
- * armv7m_load_kernel:
- * @cpu: CPU
- * @kernel_filename: file to load
- * @mem_size: mem_size: maximum image size to load
- *
- * Load the guest image for an ARMv7M system. This must be called by
- * any ARMv7M board. (This is necessary to ensure that the CPU resets
- * correctly on system reset, as well as for kernel loading.)
- */
-void armv7m_load_kernel(ARMCPU *cpu, const char *kernel_filename, int mem_size);
-
-/* arm_boot.c */
-struct arm_boot_info {
- uint64_t ram_size;
- const char *kernel_filename;
- const char *kernel_cmdline;
- const char *initrd_filename;
- const char *dtb_filename;
- hwaddr loader_start;
- hwaddr dtb_start;
- hwaddr dtb_limit;
- /* If set to True, arm_load_kernel() will not load DTB.
- * It allows board to load DTB manually later.
- * (default: False)
- */
- bool skip_dtb_autoload;
- /* multicore boards that use the default secondary core boot functions
- * need to put the address of the secondary boot code, the boot reg,
- * and the GIC address in the next 3 values, respectively. boards that
- * have their own boot functions can use these values as they want.
- */
- hwaddr smp_loader_start;
- hwaddr smp_bootreg_addr;
- hwaddr gic_cpu_if_addr;
- int nb_cpus;
- int board_id;
- /* ARM machines that support the ARM Security Extensions use this field to
- * control whether Linux is booted as secure(true) or non-secure(false).
- */
- bool secure_boot;
- int (*atag_board)(const struct arm_boot_info *info, void *p);
- /* multicore boards that use the default secondary core boot functions
- * can ignore these two function calls. If the default functions won't
- * work, then write_secondary_boot() should write a suitable blob of
- * code mimicking the secondary CPU startup process used by the board's
- * boot loader/boot ROM code, and secondary_cpu_reset_hook() should
- * perform any necessary CPU reset handling and set the PC for the
- * secondary CPUs to point at this boot blob.
- */
- void (*write_secondary_boot)(ARMCPU *cpu,
- const struct arm_boot_info *info);
- void (*secondary_cpu_reset_hook)(ARMCPU *cpu,
- const struct arm_boot_info *info);
- /* if a board is able to create a dtb without a dtb file then it
- * sets get_dtb. This will only be used if no dtb file is provided
- * by the user. On success, sets *size to the length of the created
- * dtb, and returns a pointer to it. (The caller must free this memory
- * with g_free() when it has finished with it.) On failure, returns NULL.
- */
- void *(*get_dtb)(const struct arm_boot_info *info, int *size);
- /* if a board needs to be able to modify a device tree provided by
- * the user it should implement this hook.
- */
- void (*modify_dtb)(const struct arm_boot_info *info, void *fdt);
- /* Used internally by arm_boot.c */
- int is_linux;
- hwaddr initrd_start;
- hwaddr initrd_size;
- hwaddr entry;
-
- /* Boot firmware has been loaded, typically at address 0, with -bios or
- * -pflash. It also implies that fw_cfg_find() will succeed.
- */
- bool firmware_loaded;
-
- /* Address at which board specific loader/setup code exists. If enabled,
- * this code-blob will run before anything else. It must return to the
- * caller via the link register. There is no stack set up. Enabled by
- * defining write_board_setup, which is responsible for loading the blob
- * to the specified address.
- */
- hwaddr board_setup_addr;
- void (*write_board_setup)(ARMCPU *cpu,
- const struct arm_boot_info *info);
-
- /*
- * If set, the board specific loader/setup blob will be run from secure
- * mode, regardless of secure_boot. The blob becomes responsible for
- * changing to non-secure state if implementing a non-secure boot,
- * including setting up EL3/Secure registers such as the NSACR as
- * required by the Linux booting ABI before the switch to non-secure.
- */
- bool secure_board_setup;
-
- arm_endianness endianness;
-};
-
-/**
- * arm_load_kernel - Loads memory with everything needed to boot
- *
- * @cpu: handle to the first CPU object
- * @info: handle to the boot info struct
- * Registers a machine init done notifier that copies to memory
- * everything needed to boot, depending on machine and user options:
- * kernel image, boot loaders, initrd, dtb. Also registers the CPU
- * reset handler.
- *
- * In case the machine file supports the platform bus device and its
- * dynamically instantiable sysbus devices, this function must be called
- * before sysbus-fdt arm_register_platform_bus_fdt_creator. Indeed the
- * machine init done notifiers are called in registration reverse order.
- */
-void arm_load_kernel(ARMCPU *cpu, MachineState *ms, struct arm_boot_info *info);
-
-AddressSpace *arm_boot_address_space(ARMCPU *cpu,
- const struct arm_boot_info *info);
-
-/**
- * arm_load_dtb() - load a device tree binary image into memory
- * @addr: the address to load the image at
- * @binfo: struct describing the boot environment
- * @addr_limit: upper limit of the available memory area at @addr
- * @as: address space to load image to
- *
- * Load a device tree supplied by the machine or by the user with the
- * '-dtb' command line option, and put it at offset @addr in target
- * memory.
- *
- * If @addr_limit contains a meaningful value (i.e., it is strictly greater
- * than @addr), the device tree is only loaded if its size does not exceed
- * the limit.
- *
- * Returns: the size of the device tree image on success,
- * 0 if the image size exceeds the limit,
- * -1 on errors.
- *
- * Note: Must not be called unless have_dtb(binfo) is true.
- */
-int arm_load_dtb(hwaddr addr, const struct arm_boot_info *binfo,
- hwaddr addr_limit, AddressSpace *as, MachineState *ms);
-
-/* Write a secure board setup routine with a dummy handler for SMCs */
-void arm_write_secure_board_setup_dummy_smc(ARMCPU *cpu,
- const struct arm_boot_info *info,
- hwaddr mvbar_addr);
-
-#endif /* HW_ARM_BOOT_H */
+++ /dev/null
-/*
- * Misc Canon DIGIC declarations.
- *
- * Copyright (C) 2013 Antony Pavlov <antonynpavlov@gmail.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- */
-
-#ifndef HW_ARM_DIGIC_H
-#define HW_ARM_DIGIC_H
-
-#include "cpu.h"
-#include "hw/timer/digic-timer.h"
-#include "hw/char/digic-uart.h"
-#include "qom/object.h"
-
-#define TYPE_DIGIC "digic"
-
-OBJECT_DECLARE_SIMPLE_TYPE(DigicState, DIGIC)
-
-#define DIGIC4_NB_TIMERS 3
-
-struct DigicState {
- /*< private >*/
- DeviceState parent_obj;
- /*< public >*/
-
- ARMCPU cpu;
-
- DigicTimerState timer[DIGIC4_NB_TIMERS];
- DigicUartState uart;
-};
-
-#endif /* HW_ARM_DIGIC_H */
+++ /dev/null
-/*
- * Samsung exynos4210 SoC emulation
- *
- * Copyright (c) 2011 Samsung Electronics Co., Ltd. All rights reserved.
- * Maksim Kozlov <m.kozlov@samsung.com>
- * Evgeny Voevodin <e.voevodin@samsung.com>
- * Igor Mitsyanko <i.mitsyanko@samsung.com>
- *
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License as published by the
- * Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
- * for more details.
- *
- * You should have received a copy of the GNU General Public License along
- * with this program; if not, see <http://www.gnu.org/licenses/>.
- */
-
-#ifndef EXYNOS4210_H
-#define EXYNOS4210_H
-
-#include "hw/or-irq.h"
-#include "hw/sysbus.h"
-#include "target/arm/cpu-qom.h"
-#include "qom/object.h"
-
-#define EXYNOS4210_NCPUS 2
-
-#define EXYNOS4210_DRAM0_BASE_ADDR 0x40000000
-#define EXYNOS4210_DRAM1_BASE_ADDR 0xa0000000
-#define EXYNOS4210_DRAM_MAX_SIZE 0x60000000 /* 1.5 GB */
-
-#define EXYNOS4210_IROM_BASE_ADDR 0x00000000
-#define EXYNOS4210_IROM_SIZE 0x00010000 /* 64 KB */
-#define EXYNOS4210_IROM_MIRROR_BASE_ADDR 0x02000000
-#define EXYNOS4210_IROM_MIRROR_SIZE 0x00010000 /* 64 KB */
-
-#define EXYNOS4210_IRAM_BASE_ADDR 0x02020000
-#define EXYNOS4210_IRAM_SIZE 0x00020000 /* 128 KB */
-
-/* Secondary CPU startup code is in IROM memory */
-#define EXYNOS4210_SMP_BOOT_ADDR EXYNOS4210_IROM_BASE_ADDR
-#define EXYNOS4210_SMP_BOOT_SIZE 0x1000
-#define EXYNOS4210_BASE_BOOT_ADDR EXYNOS4210_DRAM0_BASE_ADDR
-/* Secondary CPU polling address to get loader start from */
-#define EXYNOS4210_SECOND_CPU_BOOTREG 0x10020814
-
-#define EXYNOS4210_SMP_PRIVATE_BASE_ADDR 0x10500000
-#define EXYNOS4210_L2X0_BASE_ADDR 0x10502000
-
-/*
- * exynos4210 IRQ subsystem stub definitions.
- */
-#define EXYNOS4210_IRQ_GATE_NINPUTS 2 /* Internal and External GIC */
-
-#define EXYNOS4210_MAX_INT_COMBINER_OUT_IRQ 64
-#define EXYNOS4210_MAX_EXT_COMBINER_OUT_IRQ 16
-#define EXYNOS4210_MAX_INT_COMBINER_IN_IRQ \
- (EXYNOS4210_MAX_INT_COMBINER_OUT_IRQ * 8)
-#define EXYNOS4210_MAX_EXT_COMBINER_IN_IRQ \
- (EXYNOS4210_MAX_EXT_COMBINER_OUT_IRQ * 8)
-
-#define EXYNOS4210_COMBINER_GET_IRQ_NUM(grp, bit) ((grp)*8 + (bit))
-#define EXYNOS4210_COMBINER_GET_GRP_NUM(irq) ((irq) / 8)
-#define EXYNOS4210_COMBINER_GET_BIT_NUM(irq) \
- ((irq) - 8 * EXYNOS4210_COMBINER_GET_GRP_NUM(irq))
-
-/* IRQs number for external and internal GIC */
-#define EXYNOS4210_EXT_GIC_NIRQ (160-32)
-#define EXYNOS4210_INT_GIC_NIRQ 64
-
-#define EXYNOS4210_I2C_NUMBER 9
-
-#define EXYNOS4210_NUM_DMA 3
-
-typedef struct Exynos4210Irq {
- qemu_irq int_combiner_irq[EXYNOS4210_MAX_INT_COMBINER_IN_IRQ];
- qemu_irq ext_combiner_irq[EXYNOS4210_MAX_EXT_COMBINER_IN_IRQ];
- qemu_irq int_gic_irq[EXYNOS4210_INT_GIC_NIRQ];
- qemu_irq ext_gic_irq[EXYNOS4210_EXT_GIC_NIRQ];
- qemu_irq board_irqs[EXYNOS4210_MAX_INT_COMBINER_IN_IRQ];
-} Exynos4210Irq;
-
-struct Exynos4210State {
- /*< private >*/
- SysBusDevice parent_obj;
- /*< public >*/
- ARMCPU *cpu[EXYNOS4210_NCPUS];
- Exynos4210Irq irqs;
- qemu_irq *irq_table;
-
- MemoryRegion chipid_mem;
- MemoryRegion iram_mem;
- MemoryRegion irom_mem;
- MemoryRegion irom_alias_mem;
- MemoryRegion boot_secondary;
- MemoryRegion bootreg_mem;
- I2CBus *i2c_if[EXYNOS4210_I2C_NUMBER];
- qemu_or_irq pl330_irq_orgate[EXYNOS4210_NUM_DMA];
-};
-
-#define TYPE_EXYNOS4210_SOC "exynos4210"
-OBJECT_DECLARE_SIMPLE_TYPE(Exynos4210State, EXYNOS4210_SOC)
-
-void exynos4210_write_secondary(ARMCPU *cpu,
- const struct arm_boot_info *info);
-
-/* Initialize exynos4210 IRQ subsystem stub */
-qemu_irq *exynos4210_init_irq(Exynos4210Irq *env);
-
-/* Initialize board IRQs.
- * These IRQs contain splitted Int/External Combiner and External Gic IRQs */
-void exynos4210_init_board_irqs(Exynos4210Irq *s);
-
-/* Get IRQ number from exynos4210 IRQ subsystem stub.
- * To identify IRQ source use internal combiner group and bit number
- * grp - group number
- * bit - bit number inside group */
-uint32_t exynos4210_get_irq(uint32_t grp, uint32_t bit);
-
-/*
- * Get Combiner input GPIO into irqs structure
- */
-void exynos4210_combiner_get_gpioin(Exynos4210Irq *irqs, DeviceState *dev,
- int ext);
-
-/*
- * exynos4210 UART
- */
-DeviceState *exynos4210_uart_create(hwaddr addr,
- int fifo_size,
- int channel,
- Chardev *chr,
- qemu_irq irq);
-
-#endif /* EXYNOS4210_H */
+++ /dev/null
-/*
- *
- * Copyright (c) 2015 Linaro Limited
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms and conditions of the GNU General Public License,
- * version 2 or later, as published by the Free Software Foundation.
- *
- * This program is distributed in the hope it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License along with
- * this program. If not, see <http://www.gnu.org/licenses/>.
- *
- * Define macros useful when building ARM device tree nodes
- */
-
-#ifndef QEMU_ARM_FDT_H
-#define QEMU_ARM_FDT_H
-
-#define GIC_FDT_IRQ_TYPE_SPI 0
-#define GIC_FDT_IRQ_TYPE_PPI 1
-
-#define GIC_FDT_IRQ_FLAGS_EDGE_LO_HI 1
-#define GIC_FDT_IRQ_FLAGS_EDGE_HI_LO 2
-#define GIC_FDT_IRQ_FLAGS_LEVEL_HI 4
-#define GIC_FDT_IRQ_FLAGS_LEVEL_LO 8
-
-#define GIC_FDT_IRQ_PPI_CPU_START 8
-#define GIC_FDT_IRQ_PPI_CPU_WIDTH 8
-
-#endif
+++ /dev/null
-/*
- * Freescale i.MX25 SoC emulation
- *
- * Copyright (C) 2015 Jean-Christophe Dubois <jcd@tribudubois.net>
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License as published by the
- * Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
- * for more details.
- */
-
-#ifndef FSL_IMX25_H
-#define FSL_IMX25_H
-
-#include "hw/arm/boot.h"
-#include "hw/intc/imx_avic.h"
-#include "hw/misc/imx25_ccm.h"
-#include "hw/char/imx_serial.h"
-#include "hw/timer/imx_gpt.h"
-#include "hw/timer/imx_epit.h"
-#include "hw/net/imx_fec.h"
-#include "hw/misc/imx_rngc.h"
-#include "hw/i2c/imx_i2c.h"
-#include "hw/gpio/imx_gpio.h"
-#include "hw/sd/sdhci.h"
-#include "hw/usb/chipidea.h"
-#include "hw/watchdog/wdt_imx2.h"
-#include "exec/memory.h"
-#include "target/arm/cpu.h"
-#include "qom/object.h"
-
-#define TYPE_FSL_IMX25 "fsl,imx25"
-OBJECT_DECLARE_SIMPLE_TYPE(FslIMX25State, FSL_IMX25)
-
-#define FSL_IMX25_NUM_UARTS 5
-#define FSL_IMX25_NUM_GPTS 4
-#define FSL_IMX25_NUM_EPITS 2
-#define FSL_IMX25_NUM_I2CS 3
-#define FSL_IMX25_NUM_GPIOS 4
-#define FSL_IMX25_NUM_ESDHCS 2
-#define FSL_IMX25_NUM_USBS 2
-
-struct FslIMX25State {
- /*< private >*/
- DeviceState parent_obj;
-
- /*< public >*/
- ARMCPU cpu;
- IMXAVICState avic;
- IMX25CCMState ccm;
- IMXSerialState uart[FSL_IMX25_NUM_UARTS];
- IMXGPTState gpt[FSL_IMX25_NUM_GPTS];
- IMXEPITState epit[FSL_IMX25_NUM_EPITS];
- IMXFECState fec;
- IMXRNGCState rngc;
- IMXI2CState i2c[FSL_IMX25_NUM_I2CS];
- IMXGPIOState gpio[FSL_IMX25_NUM_GPIOS];
- SDHCIState esdhc[FSL_IMX25_NUM_ESDHCS];
- ChipideaState usb[FSL_IMX25_NUM_USBS];
- IMX2WdtState wdt;
- MemoryRegion rom[2];
- MemoryRegion iram;
- MemoryRegion iram_alias;
- uint32_t phy_num;
-};
-
-/**
- * i.MX25 memory map
- ****************************************************************
- * 0x0000_0000 0x0000_3FFF 16 Kbytes ROM (36 Kbytes)
- * 0x0000_4000 0x0040_3FFF 4 Mbytes Reserved
- * 0x0040_4000 0x0040_8FFF 20 Kbytes ROM (36 Kbytes)
- * 0x0040_9000 0x0FFF_FFFF 252 Mbytes (minus 36 Kbytes) Reserved
- * 0x1000_0000 0x1FFF_FFFF 256 Mbytes Reserved
- * 0x2000_0000 0x2FFF_FFFF 256 Mbytes Reserved
- * 0x3000_0000 0x3FFF_FFFF 256 Mbytes Reserved
- * 0x4000_0000 0x43EF_FFFF 63 Mbytes Reserved
- * 0x43F0_0000 0x43F0_3FFF 16 Kbytes AIPS A control registers
- * 0x43F0_4000 0x43F0_7FFF 16 Kbytes ARM926 platform MAX
- * 0x43F0_8000 0x43F0_BFFF 16 Kbytes ARM926 platform CLKCTL
- * 0x43F0_C000 0x43F0_FFFF 16 Kbytes ARM926 platform ETB registers
- * 0x43F1_0000 0x43F1_3FFF 16 Kbytes ARM926 platform ETB memory
- * 0x43F1_4000 0x43F1_7FFF 16 Kbytes ARM926 platform AAPE registers
- * 0x43F1_8000 0x43F7_FFFF 416 Kbytes Reserved
- * 0x43F8_0000 0x43F8_3FFF 16 Kbytes I2C-1
- * 0x43F8_4000 0x43F8_7FFF 16 Kbytes I2C-3
- * 0x43F8_8000 0x43F8_BFFF 16 Kbytes CAN-1
- * 0x43F8_C000 0x43F8_FFFF 16 Kbytes CAN-2
- * 0x43F9_0000 0x43F9_3FFF 16 Kbytes UART-1
- * 0x43F9_4000 0x43F9_7FFF 16 Kbytes UART-2
- * 0x43F9_8000 0x43F9_BFFF 16 Kbytes I2C-2
- * 0x43F9_C000 0x43F9_FFFF 16 Kbytes 1-Wire
- * 0x43FA_0000 0x43FA_3FFF 16 Kbytes ATA (CPU side)
- * 0x43FA_4000 0x43FA_7FFF 16 Kbytes CSPI-1
- * 0x43FA_8000 0x43FA_BFFF 16 Kbytes KPP
- * 0x43FA_C000 0x43FA_FFFF 16 Kbytes IOMUXC
- * 0x43FB_0000 0x43FB_3FFF 16 Kbytes AUDMUX
- * 0x43FB_4000 0x43FB_7FFF 16 Kbytes Reserved
- * 0x43FB_8000 0x43FB_BFFF 16 Kbytes ECT (IP BUS A)
- * 0x43FB_C000 0x43FB_FFFF 16 Kbytes ECT (IP BUS B)
- * 0x43FC_0000 0x43FF_FFFF 256 Kbytes Reserved AIPS A off-platform slots
- * 0x4400_0000 0x4FFF_FFFF 192 Mbytes Reserved
- * 0x5000_0000 0x5000_3FFF 16 Kbytes SPBA base address
- * 0x5000_4000 0x5000_7FFF 16 Kbytes CSPI-3
- * 0x5000_8000 0x5000_BFFF 16 Kbytes UART-4
- * 0x5000_C000 0x5000_FFFF 16 Kbytes UART-3
- * 0x5001_0000 0x5001_3FFF 16 Kbytes CSPI-2
- * 0x5001_4000 0x5001_7FFF 16 Kbytes SSI-2
- * 0x5001_C000 0x5001_FFFF 16 Kbytes Reserved
- * 0x5002_0000 0x5002_3FFF 16 Kbytes ATA
- * 0x5002_4000 0x5002_7FFF 16 Kbytes SIM-1
- * 0x5002_8000 0x5002_BFFF 16 Kbytes SIM-2
- * 0x5002_C000 0x5002_FFFF 16 Kbytes UART-5
- * 0x5003_0000 0x5003_3FFF 16 Kbytes TSC
- * 0x5003_4000 0x5003_7FFF 16 Kbytes SSI-1
- * 0x5003_8000 0x5003_BFFF 16 Kbytes FEC
- * 0x5003_C000 0x5003_FFFF 16 Kbytes SPBA registers
- * 0x5004_0000 0x51FF_FFFF 32 Mbytes (minus 256 Kbytes)
- * 0x5200_0000 0x53EF_FFFF 31 Mbytes Reserved
- * 0x53F0_0000 0x53F0_3FFF 16 Kbytes AIPS B control registers
- * 0x53F0_4000 0x53F7_FFFF 496 Kbytes Reserved
- * 0x53F8_0000 0x53F8_3FFF 16 Kbytes CCM
- * 0x53F8_4000 0x53F8_7FFF 16 Kbytes GPT-4
- * 0x53F8_8000 0x53F8_BFFF 16 Kbytes GPT-3
- * 0x53F8_C000 0x53F8_FFFF 16 Kbytes GPT-2
- * 0x53F9_0000 0x53F9_3FFF 16 Kbytes GPT-1
- * 0x53F9_4000 0x53F9_7FFF 16 Kbytes EPIT-1
- * 0x53F9_8000 0x53F9_BFFF 16 Kbytes EPIT-2
- * 0x53F9_C000 0x53F9_FFFF 16 Kbytes GPIO-4
- * 0x53FA_0000 0x53FA_3FFF 16 Kbytes PWM-2
- * 0x53FA_4000 0x53FA_7FFF 16 Kbytes GPIO-3
- * 0x53FA_8000 0x53FA_BFFF 16 Kbytes PWM-3
- * 0x53FA_C000 0x53FA_FFFF 16 Kbytes SCC
- * 0x53FB_0000 0x53FB_3FFF 16 Kbytes RNGB
- * 0x53FB_4000 0x53FB_7FFF 16 Kbytes eSDHC-1
- * 0x53FB_8000 0x53FB_BFFF 16 Kbytes eSDHC-2
- * 0x53FB_C000 0x53FB_FFFF 16 Kbytes LCDC
- * 0x53FC_0000 0x53FC_3FFF 16 Kbytes SLCDC
- * 0x53FC_4000 0x53FC_7FFF 16 Kbytes Reserved
- * 0x53FC_8000 0x53FC_BFFF 16 Kbytes PWM-4
- * 0x53FC_C000 0x53FC_FFFF 16 Kbytes GPIO-1
- * 0x53FD_0000 0x53FD_3FFF 16 Kbytes GPIO-2
- * 0x53FD_4000 0x53FD_7FFF 16 Kbytes SDMA
- * 0x53FD_8000 0x53FD_BFFF 16 Kbytes Reserved
- * 0x53FD_C000 0x53FD_FFFF 16 Kbytes WDOG
- * 0x53FE_0000 0x53FE_3FFF 16 Kbytes PWM-1
- * 0x53FE_4000 0x53FE_7FFF 16 Kbytes Reserved
- * 0x53FE_8000 0x53FE_BFFF 16 Kbytes Reserved
- * 0x53FE_C000 0x53FE_FFFF 16 Kbytes RTICv3
- * 0x53FF_0000 0x53FF_3FFF 16 Kbytes IIM
- * 0x53FF_4000 0x53FF_7FFF 16 Kbytes USB
- * 0x53FF_8000 0x53FF_BFFF 16 Kbytes CSI
- * 0x53FF_C000 0x53FF_FFFF 16 Kbytes DryIce
- * 0x5400_0000 0x5FFF_FFFF 192 Mbytes Reserved (aliased AIPS B slots)
- * 0x6000_0000 0x67FF_FFFF 128 Mbytes ARM926 platform ROMPATCH
- * 0x6800_0000 0x6FFF_FFFF 128 Mbytes ARM926 platform ASIC
- * 0x7000_0000 0x77FF_FFFF 128 Mbytes Reserved
- * 0x7800_0000 0x7801_FFFF 128 Kbytes RAM
- * 0x7802_0000 0x7FFF_FFFF 128 Mbytes (minus 128 Kbytes)
- * 0x8000_0000 0x8FFF_FFFF 256 Mbytes SDRAM bank 0
- * 0x9000_0000 0x9FFF_FFFF 256 Mbytes SDRAM bank 1
- * 0xA000_0000 0xA7FF_FFFF 128 Mbytes WEIM CS0 (flash 128) 1
- * 0xA800_0000 0xAFFF_FFFF 128 Mbytes WEIM CS1 (flash 64) 1
- * 0xB000_0000 0xB1FF_FFFF 32 Mbytes WEIM CS2 (SRAM)
- * 0xB200_0000 0xB3FF_FFFF 32 Mbytes WEIM CS3 (SRAM)
- * 0xB400_0000 0xB5FF_FFFF 32 Mbytes WEIM CS4
- * 0xB600_0000 0xB7FF_FFFF 32 Mbytes Reserved
- * 0xB800_0000 0xB800_0FFF 4 Kbytes Reserved
- * 0xB800_1000 0xB800_1FFF 4 Kbytes SDRAM control registers
- * 0xB800_2000 0xB800_2FFF 4 Kbytes WEIM control registers
- * 0xB800_3000 0xB800_3FFF 4 Kbytes M3IF control registers
- * 0xB800_4000 0xB800_4FFF 4 Kbytes EMI control registers
- * 0xB800_5000 0xBAFF_FFFF 32 Mbytes (minus 20 Kbytes)
- * 0xBB00_0000 0xBB00_0FFF 4 Kbytes NAND flash main area buffer
- * 0xBB00_1000 0xBB00_11FF 512 B NAND flash spare area buffer
- * 0xBB00_1200 0xBB00_1DFF 3 Kbytes Reserved
- * 0xBB00_1E00 0xBB00_1FFF 512 B NAND flash control registers
- * 0xBB01_2000 0xBFFF_FFFF 96 Mbytes (minus 8 Kbytes) Reserved
- * 0xC000_0000 0xFFFF_FFFF 1024 Mbytes Reserved
- */
-
-#define FSL_IMX25_ROM0_ADDR 0x00000000
-#define FSL_IMX25_ROM0_SIZE 0x4000
-#define FSL_IMX25_ROM1_ADDR 0x00404000
-#define FSL_IMX25_ROM1_SIZE 0x4000
-#define FSL_IMX25_I2C1_ADDR 0x43F80000
-#define FSL_IMX25_I2C1_SIZE 0x4000
-#define FSL_IMX25_I2C3_ADDR 0x43F84000
-#define FSL_IMX25_I2C3_SIZE 0x4000
-#define FSL_IMX25_UART1_ADDR 0x43F90000
-#define FSL_IMX25_UART1_SIZE 0x4000
-#define FSL_IMX25_UART2_ADDR 0x43F94000
-#define FSL_IMX25_UART2_SIZE 0x4000
-#define FSL_IMX25_I2C2_ADDR 0x43F98000
-#define FSL_IMX25_I2C2_SIZE 0x4000
-#define FSL_IMX25_UART4_ADDR 0x50008000
-#define FSL_IMX25_UART4_SIZE 0x4000
-#define FSL_IMX25_UART3_ADDR 0x5000C000
-#define FSL_IMX25_UART3_SIZE 0x4000
-#define FSL_IMX25_UART5_ADDR 0x5002C000
-#define FSL_IMX25_UART5_SIZE 0x4000
-#define FSL_IMX25_FEC_ADDR 0x50038000
-#define FSL_IMX25_CCM_ADDR 0x53F80000
-#define FSL_IMX25_CCM_SIZE 0x4000
-#define FSL_IMX25_GPT4_ADDR 0x53F84000
-#define FSL_IMX25_GPT4_SIZE 0x4000
-#define FSL_IMX25_GPT3_ADDR 0x53F88000
-#define FSL_IMX25_GPT3_SIZE 0x4000
-#define FSL_IMX25_GPT2_ADDR 0x53F8C000
-#define FSL_IMX25_GPT2_SIZE 0x4000
-#define FSL_IMX25_GPT1_ADDR 0x53F90000
-#define FSL_IMX25_GPT1_SIZE 0x4000
-#define FSL_IMX25_EPIT1_ADDR 0x53F94000
-#define FSL_IMX25_EPIT1_SIZE 0x4000
-#define FSL_IMX25_EPIT2_ADDR 0x53F98000
-#define FSL_IMX25_EPIT2_SIZE 0x4000
-#define FSL_IMX25_GPIO4_ADDR 0x53F9C000
-#define FSL_IMX25_GPIO4_SIZE 0x4000
-#define FSL_IMX25_GPIO3_ADDR 0x53FA4000
-#define FSL_IMX25_GPIO3_SIZE 0x4000
-#define FSL_IMX25_RNGC_ADDR 0x53FB0000
-#define FSL_IMX25_RNGC_SIZE 0x4000
-#define FSL_IMX25_ESDHC1_ADDR 0x53FB4000
-#define FSL_IMX25_ESDHC1_SIZE 0x4000
-#define FSL_IMX25_ESDHC2_ADDR 0x53FB8000
-#define FSL_IMX25_ESDHC2_SIZE 0x4000
-#define FSL_IMX25_GPIO1_ADDR 0x53FCC000
-#define FSL_IMX25_GPIO1_SIZE 0x4000
-#define FSL_IMX25_GPIO2_ADDR 0x53FD0000
-#define FSL_IMX25_GPIO2_SIZE 0x4000
-#define FSL_IMX25_WDT_ADDR 0x53FDC000
-#define FSL_IMX25_WDT_SIZE 0x4000
-#define FSL_IMX25_USB1_ADDR 0x53FF4000
-#define FSL_IMX25_USB1_SIZE 0x0200
-#define FSL_IMX25_USB2_ADDR 0x53FF4400
-#define FSL_IMX25_USB2_SIZE 0x0200
-#define FSL_IMX25_AVIC_ADDR 0x68000000
-#define FSL_IMX25_AVIC_SIZE 0x4000
-#define FSL_IMX25_IRAM_ADDR 0x78000000
-#define FSL_IMX25_IRAM_SIZE 0x20000
-#define FSL_IMX25_IRAM_ALIAS_ADDR 0x78020000
-#define FSL_IMX25_IRAM_ALIAS_SIZE 0x7FE0000
-#define FSL_IMX25_SDRAM0_ADDR 0x80000000
-#define FSL_IMX25_SDRAM0_SIZE 0x10000000
-#define FSL_IMX25_SDRAM1_ADDR 0x90000000
-#define FSL_IMX25_SDRAM1_SIZE 0x10000000
-
-#define FSL_IMX25_UART1_IRQ 45
-#define FSL_IMX25_UART2_IRQ 32
-#define FSL_IMX25_UART3_IRQ 18
-#define FSL_IMX25_UART4_IRQ 5
-#define FSL_IMX25_UART5_IRQ 40
-#define FSL_IMX25_GPT1_IRQ 54
-#define FSL_IMX25_GPT2_IRQ 53
-#define FSL_IMX25_GPT3_IRQ 29
-#define FSL_IMX25_GPT4_IRQ 1
-#define FSL_IMX25_EPIT1_IRQ 28
-#define FSL_IMX25_EPIT2_IRQ 27
-#define FSL_IMX25_FEC_IRQ 57
-#define FSL_IMX25_RNGC_IRQ 22
-#define FSL_IMX25_I2C1_IRQ 3
-#define FSL_IMX25_I2C2_IRQ 4
-#define FSL_IMX25_I2C3_IRQ 10
-#define FSL_IMX25_GPIO1_IRQ 52
-#define FSL_IMX25_GPIO2_IRQ 51
-#define FSL_IMX25_GPIO3_IRQ 16
-#define FSL_IMX25_GPIO4_IRQ 23
-#define FSL_IMX25_ESDHC1_IRQ 9
-#define FSL_IMX25_ESDHC2_IRQ 8
-#define FSL_IMX25_USB1_IRQ 37
-#define FSL_IMX25_USB2_IRQ 35
-#define FSL_IMX25_WDT_IRQ 55
-
-#endif /* FSL_IMX25_H */
+++ /dev/null
-/*
- * Freescale i.MX31 SoC emulation
- *
- * Copyright (C) 2015 Jean-Christophe Dubois <jcd@tribudubois.net>
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License as published by the
- * Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
- * for more details.
- */
-
-#ifndef FSL_IMX31_H
-#define FSL_IMX31_H
-
-#include "hw/arm/boot.h"
-#include "hw/intc/imx_avic.h"
-#include "hw/misc/imx31_ccm.h"
-#include "hw/char/imx_serial.h"
-#include "hw/timer/imx_gpt.h"
-#include "hw/timer/imx_epit.h"
-#include "hw/i2c/imx_i2c.h"
-#include "hw/gpio/imx_gpio.h"
-#include "hw/watchdog/wdt_imx2.h"
-#include "exec/memory.h"
-#include "target/arm/cpu.h"
-#include "qom/object.h"
-
-#define TYPE_FSL_IMX31 "fsl,imx31"
-OBJECT_DECLARE_SIMPLE_TYPE(FslIMX31State, FSL_IMX31)
-
-#define FSL_IMX31_NUM_UARTS 2
-#define FSL_IMX31_NUM_EPITS 2
-#define FSL_IMX31_NUM_I2CS 3
-#define FSL_IMX31_NUM_GPIOS 3
-
-struct FslIMX31State {
- /*< private >*/
- DeviceState parent_obj;
-
- /*< public >*/
- ARMCPU cpu;
- IMXAVICState avic;
- IMX31CCMState ccm;
- IMXSerialState uart[FSL_IMX31_NUM_UARTS];
- IMXGPTState gpt;
- IMXEPITState epit[FSL_IMX31_NUM_EPITS];
- IMXI2CState i2c[FSL_IMX31_NUM_I2CS];
- IMXGPIOState gpio[FSL_IMX31_NUM_GPIOS];
- IMX2WdtState wdt;
- MemoryRegion secure_rom;
- MemoryRegion rom;
- MemoryRegion iram;
- MemoryRegion iram_alias;
-};
-
-#define FSL_IMX31_SECURE_ROM_ADDR 0x00000000
-#define FSL_IMX31_SECURE_ROM_SIZE 0x4000
-#define FSL_IMX31_ROM_ADDR 0x00404000
-#define FSL_IMX31_ROM_SIZE 0x4000
-#define FSL_IMX31_IRAM_ALIAS_ADDR 0x10000000
-#define FSL_IMX31_IRAM_ALIAS_SIZE 0xFFC0000
-#define FSL_IMX31_IRAM_ADDR 0x1FFFC000
-#define FSL_IMX31_IRAM_SIZE 0x4000
-#define FSL_IMX31_I2C1_ADDR 0x43F80000
-#define FSL_IMX31_I2C1_SIZE 0x4000
-#define FSL_IMX31_I2C3_ADDR 0x43F84000
-#define FSL_IMX31_I2C3_SIZE 0x4000
-#define FSL_IMX31_UART1_ADDR 0x43F90000
-#define FSL_IMX31_UART1_SIZE 0x4000
-#define FSL_IMX31_UART2_ADDR 0x43F94000
-#define FSL_IMX31_UART2_SIZE 0x4000
-#define FSL_IMX31_I2C2_ADDR 0x43F98000
-#define FSL_IMX31_I2C2_SIZE 0x4000
-#define FSL_IMX31_CCM_ADDR 0x53F80000
-#define FSL_IMX31_CCM_SIZE 0x4000
-#define FSL_IMX31_GPT_ADDR 0x53F90000
-#define FSL_IMX31_GPT_SIZE 0x4000
-#define FSL_IMX31_EPIT1_ADDR 0x53F94000
-#define FSL_IMX31_EPIT1_SIZE 0x4000
-#define FSL_IMX31_EPIT2_ADDR 0x53F98000
-#define FSL_IMX31_EPIT2_SIZE 0x4000
-#define FSL_IMX31_GPIO3_ADDR 0x53FA4000
-#define FSL_IMX31_GPIO3_SIZE 0x4000
-#define FSL_IMX31_GPIO1_ADDR 0x53FCC000
-#define FSL_IMX31_GPIO1_SIZE 0x4000
-#define FSL_IMX31_GPIO2_ADDR 0x53FD0000
-#define FSL_IMX31_GPIO2_SIZE 0x4000
-#define FSL_IMX31_WDT_ADDR 0x53FDC000
-#define FSL_IMX31_WDT_SIZE 0x4000
-#define FSL_IMX31_AVIC_ADDR 0x68000000
-#define FSL_IMX31_AVIC_SIZE 0x100
-#define FSL_IMX31_SDRAM0_ADDR 0x80000000
-#define FSL_IMX31_SDRAM0_SIZE 0x10000000
-#define FSL_IMX31_SDRAM1_ADDR 0x90000000
-#define FSL_IMX31_SDRAM1_SIZE 0x10000000
-#define FSL_IMX31_FLASH0_ADDR 0xA0000000
-#define FSL_IMX31_FLASH0_SIZE 0x8000000
-#define FSL_IMX31_FLASH1_ADDR 0xA8000000
-#define FSL_IMX31_FLASH1_SIZE 0x8000000
-#define FSL_IMX31_CS2_ADDR 0xB0000000
-#define FSL_IMX31_CS2_SIZE 0x2000000
-#define FSL_IMX31_CS3_ADDR 0xB2000000
-#define FSL_IMX31_CS3_SIZE 0x2000000
-#define FSL_IMX31_CS4_ADDR 0xB4000000
-#define FSL_IMX31_CS4_SIZE 0x2000000
-#define FSL_IMX31_CS5_ADDR 0xB6000000
-#define FSL_IMX31_CS5_SIZE 0x2000000
-#define FSL_IMX31_NAND_ADDR 0xB8000000
-#define FSL_IMX31_NAND_SIZE 0x1000
-
-#define FSL_IMX31_EPIT2_IRQ 27
-#define FSL_IMX31_EPIT1_IRQ 28
-#define FSL_IMX31_GPT_IRQ 29
-#define FSL_IMX31_UART2_IRQ 32
-#define FSL_IMX31_UART1_IRQ 45
-#define FSL_IMX31_I2C1_IRQ 10
-#define FSL_IMX31_I2C2_IRQ 4
-#define FSL_IMX31_I2C3_IRQ 3
-#define FSL_IMX31_GPIO1_IRQ 52
-#define FSL_IMX31_GPIO2_IRQ 51
-#define FSL_IMX31_GPIO3_IRQ 56
-
-#endif /* FSL_IMX31_H */
+++ /dev/null
-/*
- * Freescale i.MX31 SoC emulation
- *
- * Copyright (C) 2015 Jean-Christophe Dubois <jcd@tribudubois.net>
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License as published by the
- * Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
- * for more details.
- */
-
-#ifndef FSL_IMX6_H
-#define FSL_IMX6_H
-
-#include "hw/arm/boot.h"
-#include "hw/cpu/a9mpcore.h"
-#include "hw/misc/imx6_ccm.h"
-#include "hw/misc/imx6_src.h"
-#include "hw/watchdog/wdt_imx2.h"
-#include "hw/char/imx_serial.h"
-#include "hw/timer/imx_gpt.h"
-#include "hw/timer/imx_epit.h"
-#include "hw/i2c/imx_i2c.h"
-#include "hw/gpio/imx_gpio.h"
-#include "hw/sd/sdhci.h"
-#include "hw/ssi/imx_spi.h"
-#include "hw/net/imx_fec.h"
-#include "hw/usb/chipidea.h"
-#include "hw/usb/imx-usb-phy.h"
-#include "exec/memory.h"
-#include "cpu.h"
-#include "qom/object.h"
-
-#define TYPE_FSL_IMX6 "fsl,imx6"
-OBJECT_DECLARE_SIMPLE_TYPE(FslIMX6State, FSL_IMX6)
-
-#define FSL_IMX6_NUM_CPUS 4
-#define FSL_IMX6_NUM_UARTS 5
-#define FSL_IMX6_NUM_EPITS 2
-#define FSL_IMX6_NUM_I2CS 3
-#define FSL_IMX6_NUM_GPIOS 7
-#define FSL_IMX6_NUM_ESDHCS 4
-#define FSL_IMX6_NUM_ECSPIS 5
-#define FSL_IMX6_NUM_WDTS 2
-#define FSL_IMX6_NUM_USB_PHYS 2
-#define FSL_IMX6_NUM_USBS 4
-
-struct FslIMX6State {
- /*< private >*/
- DeviceState parent_obj;
-
- /*< public >*/
- ARMCPU cpu[FSL_IMX6_NUM_CPUS];
- A9MPPrivState a9mpcore;
- IMX6CCMState ccm;
- IMX6SRCState src;
- IMXSerialState uart[FSL_IMX6_NUM_UARTS];
- IMXGPTState gpt;
- IMXEPITState epit[FSL_IMX6_NUM_EPITS];
- IMXI2CState i2c[FSL_IMX6_NUM_I2CS];
- IMXGPIOState gpio[FSL_IMX6_NUM_GPIOS];
- SDHCIState esdhc[FSL_IMX6_NUM_ESDHCS];
- IMXSPIState spi[FSL_IMX6_NUM_ECSPIS];
- IMX2WdtState wdt[FSL_IMX6_NUM_WDTS];
- IMXUSBPHYState usbphy[FSL_IMX6_NUM_USB_PHYS];
- ChipideaState usb[FSL_IMX6_NUM_USBS];
- IMXFECState eth;
- MemoryRegion rom;
- MemoryRegion caam;
- MemoryRegion ocram;
- MemoryRegion ocram_alias;
- uint32_t phy_num;
-};
-
-
-#define FSL_IMX6_MMDC_ADDR 0x10000000
-#define FSL_IMX6_MMDC_SIZE 0xF0000000
-#define FSL_IMX6_EIM_MEM_ADDR 0x08000000
-#define FSL_IMX6_EIM_MEM_SIZE 0x8000000
-#define FSL_IMX6_IPU_2_ADDR 0x02800000
-#define FSL_IMX6_IPU_2_SIZE 0x400000
-#define FSL_IMX6_IPU_1_ADDR 0x02400000
-#define FSL_IMX6_IPU_1_SIZE 0x400000
-#define FSL_IMX6_MIPI_HSI_ADDR 0x02208000
-#define FSL_IMX6_MIPI_HSI_SIZE 0x4000
-#define FSL_IMX6_OPENVG_ADDR 0x02204000
-#define FSL_IMX6_OPENVG_SIZE 0x4000
-#define FSL_IMX6_SATA_ADDR 0x02200000
-#define FSL_IMX6_SATA_SIZE 0x4000
-#define FSL_IMX6_AIPS_2_ADDR 0x02100000
-#define FSL_IMX6_AIPS_2_SIZE 0x100000
-/* AIPS2 */
-#define FSL_IMX6_UART5_ADDR 0x021F4000
-#define FSL_IMX6_UART5_SIZE 0x4000
-#define FSL_IMX6_UART4_ADDR 0x021F0000
-#define FSL_IMX6_UART4_SIZE 0x4000
-#define FSL_IMX6_UART3_ADDR 0x021EC000
-#define FSL_IMX6_UART3_SIZE 0x4000
-#define FSL_IMX6_UART2_ADDR 0x021E8000
-#define FSL_IMX6_UART2_SIZE 0x4000
-#define FSL_IMX6_VDOA_ADDR 0x021E4000
-#define FSL_IMX6_VDOA_SIZE 0x4000
-#define FSL_IMX6_MIPI_DSI_ADDR 0x021E0000
-#define FSL_IMX6_MIPI_DSI_SIZE 0x4000
-#define FSL_IMX6_MIPI_CSI_ADDR 0x021DC000
-#define FSL_IMX6_MIPI_CSI_SIZE 0x4000
-#define FSL_IMX6_AUDMUX_ADDR 0x021D8000
-#define FSL_IMX6_AUDMUX_SIZE 0x4000
-#define FSL_IMX6_TZASC2_ADDR 0x021D4000
-#define FSL_IMX6_TZASC2_SIZE 0x4000
-#define FSL_IMX6_TZASC1_ADDR 0x021D0000
-#define FSL_IMX6_TZASC1_SIZE 0x4000
-#define FSL_IMX6_CSU_ADDR 0x021C0000
-#define FSL_IMX6_CSU_SIZE 0x4000
-#define FSL_IMX6_OCOTPCTRL_ADDR 0x021BC000
-#define FSL_IMX6_OCOTPCTRL_SIZE 0x4000
-#define FSL_IMX6_EIM_ADDR 0x021B8000
-#define FSL_IMX6_EIM_SIZE 0x4000
-#define FSL_IMX6_MMDC1_ADDR 0x021B4000
-#define FSL_IMX6_MMDC1_SIZE 0x4000
-#define FSL_IMX6_MMDC0_ADDR 0x021B0000
-#define FSL_IMX6_MMDC0_SIZE 0x4000
-#define FSL_IMX6_ROMCP_ADDR 0x021AC000
-#define FSL_IMX6_ROMCP_SIZE 0x4000
-#define FSL_IMX6_I2C3_ADDR 0x021A8000
-#define FSL_IMX6_I2C3_SIZE 0x4000
-#define FSL_IMX6_I2C2_ADDR 0x021A4000
-#define FSL_IMX6_I2C2_SIZE 0x4000
-#define FSL_IMX6_I2C1_ADDR 0x021A0000
-#define FSL_IMX6_I2C1_SIZE 0x4000
-#define FSL_IMX6_uSDHC4_ADDR 0x0219C000
-#define FSL_IMX6_uSDHC4_SIZE 0x4000
-#define FSL_IMX6_uSDHC3_ADDR 0x02198000
-#define FSL_IMX6_uSDHC3_SIZE 0x4000
-#define FSL_IMX6_uSDHC2_ADDR 0x02194000
-#define FSL_IMX6_uSDHC2_SIZE 0x4000
-#define FSL_IMX6_uSDHC1_ADDR 0x02190000
-#define FSL_IMX6_uSDHC1_SIZE 0x4000
-#define FSL_IMX6_MLB150_ADDR 0x0218C000
-#define FSL_IMX6_MLB150_SIZE 0x4000
-#define FSL_IMX6_ENET_ADDR 0x02188000
-#define FSL_IMX6_ENET_SIZE 0x4000
-#define FSL_IMX6_USBOH3_USB_ADDR 0x02184000
-#define FSL_IMX6_USBOH3_USB_SIZE 0x4000
-#define FSL_IMX6_AIPS2_CFG_ADDR 0x0217C000
-#define FSL_IMX6_AIPS2_CFG_SIZE 0x4000
-/* DAP */
-#define FSL_IMX6_PTF_CTRL_ADDR 0x02160000
-#define FSL_IMX6_PTF_CTRL_SIZE 0x1000
-#define FSL_IMX6_PTM3_ADDR 0x0215F000
-#define FSL_IMX6_PTM3_SIZE 0x1000
-#define FSL_IMX6_PTM2_ADDR 0x0215E000
-#define FSL_IMX6_PTM2_SIZE 0x1000
-#define FSL_IMX6_PTM1_ADDR 0x0215D000
-#define FSL_IMX6_PTM1_SIZE 0x1000
-#define FSL_IMX6_PTM0_ADDR 0x0215C000
-#define FSL_IMX6_PTM0_SIZE 0x1000
-#define FSL_IMX6_CTI3_ADDR 0x0215B000
-#define FSL_IMX6_CTI3_SIZE 0x1000
-#define FSL_IMX6_CTI2_ADDR 0x0215A000
-#define FSL_IMX6_CTI2_SIZE 0x1000
-#define FSL_IMX6_CTI1_ADDR 0x02159000
-#define FSL_IMX6_CTI1_SIZE 0x1000
-#define FSL_IMX6_CTI0_ADDR 0x02158000
-#define FSL_IMX6_CTI0_SIZE 0x1000
-#define FSL_IMX6_CPU3_PMU_ADDR 0x02157000
-#define FSL_IMX6_CPU3_PMU_SIZE 0x1000
-#define FSL_IMX6_CPU3_DEBUG_IF_ADDR 0x02156000
-#define FSL_IMX6_CPU3_DEBUG_IF_SIZE 0x1000
-#define FSL_IMX6_CPU2_PMU_ADDR 0x02155000
-#define FSL_IMX6_CPU2_PMU_SIZE 0x1000
-#define FSL_IMX6_CPU2_DEBUG_IF_ADDR 0x02154000
-#define FSL_IMX6_CPU2_DEBUG_IF_SIZE 0x1000
-#define FSL_IMX6_CPU1_PMU_ADDR 0x02153000
-#define FSL_IMX6_CPU1_PMU_SIZE 0x1000
-#define FSL_IMX6_CPU1_DEBUG_IF_ADDR 0x02152000
-#define FSL_IMX6_CPU1_DEBUG_IF_SIZE 0x1000
-#define FSL_IMX6_CPU0_PMU_ADDR 0x02151000
-#define FSL_IMX6_CPU0_PMU_SIZE 0x1000
-#define FSL_IMX6_CPU0_DEBUG_IF_ADDR 0x02150000
-#define FSL_IMX6_CPU0_DEBUG_IF_SIZE 0x1000
-#define FSL_IMX6_CA9_INTEG_ADDR 0x0214F000
-#define FSL_IMX6_CA9_INTEG_SIZE 0x1000
-#define FSL_IMX6_FUNNEL_ADDR 0x02144000
-#define FSL_IMX6_FUNNEL_SIZE 0x1000
-#define FSL_IMX6_TPIU_ADDR 0x02143000
-#define FSL_IMX6_TPIU_SIZE 0x1000
-#define FSL_IMX6_EXT_CTI_ADDR 0x02142000
-#define FSL_IMX6_EXT_CTI_SIZE 0x1000
-#define FSL_IMX6_ETB_ADDR 0x02141000
-#define FSL_IMX6_ETB_SIZE 0x1000
-#define FSL_IMX6_DAP_ROM_TABLE_ADDR 0x02140000
-#define FSL_IMX6_DAP_ROM_TABLE_SIZE 0x1000
-/* DAP end */
-#define FSL_IMX6_CAAM_ADDR 0x02100000
-#define FSL_IMX6_CAAM_SIZE 0x10000
-/* AIPS2 end */
-#define FSL_IMX6_AIPS_1_ADDR 0x02000000
-#define FSL_IMX6_AIPS_1_SIZE 0x100000
-/* AIPS1 */
-#define FSL_IMX6_SDMA_ADDR 0x020EC000
-#define FSL_IMX6_SDMA_SIZE 0x4000
-#define FSL_IMX6_DCIC2_ADDR 0x020E8000
-#define FSL_IMX6_DCIC2_SIZE 0x4000
-#define FSL_IMX6_DCIC1_ADDR 0x020E4000
-#define FSL_IMX6_DCIC1_SIZE 0x4000
-#define FSL_IMX6_IOMUXC_ADDR 0x020E0000
-#define FSL_IMX6_IOMUXC_SIZE 0x4000
-#define FSL_IMX6_PGCARM_ADDR 0x020DCA00
-#define FSL_IMX6_PGCARM_SIZE 0x20
-#define FSL_IMX6_PGCPU_ADDR 0x020DC260
-#define FSL_IMX6_PGCPU_SIZE 0x20
-#define FSL_IMX6_GPC_ADDR 0x020DC000
-#define FSL_IMX6_GPC_SIZE 0x4000
-#define FSL_IMX6_SRC_ADDR 0x020D8000
-#define FSL_IMX6_SRC_SIZE 0x4000
-#define FSL_IMX6_EPIT2_ADDR 0x020D4000
-#define FSL_IMX6_EPIT2_SIZE 0x4000
-#define FSL_IMX6_EPIT1_ADDR 0x020D0000
-#define FSL_IMX6_EPIT1_SIZE 0x4000
-#define FSL_IMX6_SNVSHP_ADDR 0x020CC000
-#define FSL_IMX6_SNVSHP_SIZE 0x4000
-#define FSL_IMX6_USBPHY2_ADDR 0x020CA000
-#define FSL_IMX6_USBPHY2_SIZE 0x1000
-#define FSL_IMX6_USBPHY1_ADDR 0x020C9000
-#define FSL_IMX6_USBPHY1_SIZE 0x1000
-#define FSL_IMX6_ANALOG_ADDR 0x020C8000
-#define FSL_IMX6_ANALOG_SIZE 0x1000
-#define FSL_IMX6_CCM_ADDR 0x020C4000
-#define FSL_IMX6_CCM_SIZE 0x4000
-#define FSL_IMX6_WDOG2_ADDR 0x020C0000
-#define FSL_IMX6_WDOG2_SIZE 0x4000
-#define FSL_IMX6_WDOG1_ADDR 0x020BC000
-#define FSL_IMX6_WDOG1_SIZE 0x4000
-#define FSL_IMX6_KPP_ADDR 0x020B8000
-#define FSL_IMX6_KPP_SIZE 0x4000
-#define FSL_IMX6_GPIO7_ADDR 0x020B4000
-#define FSL_IMX6_GPIO7_SIZE 0x4000
-#define FSL_IMX6_GPIO6_ADDR 0x020B0000
-#define FSL_IMX6_GPIO6_SIZE 0x4000
-#define FSL_IMX6_GPIO5_ADDR 0x020AC000
-#define FSL_IMX6_GPIO5_SIZE 0x4000
-#define FSL_IMX6_GPIO4_ADDR 0x020A8000
-#define FSL_IMX6_GPIO4_SIZE 0x4000
-#define FSL_IMX6_GPIO3_ADDR 0x020A4000
-#define FSL_IMX6_GPIO3_SIZE 0x4000
-#define FSL_IMX6_GPIO2_ADDR 0x020A0000
-#define FSL_IMX6_GPIO2_SIZE 0x4000
-#define FSL_IMX6_GPIO1_ADDR 0x0209C000
-#define FSL_IMX6_GPIO1_SIZE 0x4000
-#define FSL_IMX6_GPT_ADDR 0x02098000
-#define FSL_IMX6_GPT_SIZE 0x4000
-#define FSL_IMX6_CAN2_ADDR 0x02094000
-#define FSL_IMX6_CAN2_SIZE 0x4000
-#define FSL_IMX6_CAN1_ADDR 0x02090000
-#define FSL_IMX6_CAN1_SIZE 0x4000
-#define FSL_IMX6_PWM4_ADDR 0x0208C000
-#define FSL_IMX6_PWM4_SIZE 0x4000
-#define FSL_IMX6_PWM3_ADDR 0x02088000
-#define FSL_IMX6_PWM3_SIZE 0x4000
-#define FSL_IMX6_PWM2_ADDR 0x02084000
-#define FSL_IMX6_PWM2_SIZE 0x4000
-#define FSL_IMX6_PWM1_ADDR 0x02080000
-#define FSL_IMX6_PWM1_SIZE 0x4000
-#define FSL_IMX6_AIPS1_CFG_ADDR 0x0207C000
-#define FSL_IMX6_AIPS1_CFG_SIZE 0x4000
-#define FSL_IMX6_VPU_ADDR 0x02040000
-#define FSL_IMX6_VPU_SIZE 0x3C000
-#define FSL_IMX6_AIPS1_SPBA_ADDR 0x0203C000
-#define FSL_IMX6_AIPS1_SPBA_SIZE 0x4000
-#define FSL_IMX6_ASRC_ADDR 0x02034000
-#define FSL_IMX6_ASRC_SIZE 0x4000
-#define FSL_IMX6_SSI3_ADDR 0x02030000
-#define FSL_IMX6_SSI3_SIZE 0x4000
-#define FSL_IMX6_SSI2_ADDR 0x0202C000
-#define FSL_IMX6_SSI2_SIZE 0x4000
-#define FSL_IMX6_SSI1_ADDR 0x02028000
-#define FSL_IMX6_SSI1_SIZE 0x4000
-#define FSL_IMX6_ESAI_ADDR 0x02024000
-#define FSL_IMX6_ESAI_SIZE 0x4000
-#define FSL_IMX6_UART1_ADDR 0x02020000
-#define FSL_IMX6_UART1_SIZE 0x4000
-#define FSL_IMX6_eCSPI5_ADDR 0x02018000
-#define FSL_IMX6_eCSPI5_SIZE 0x4000
-#define FSL_IMX6_eCSPI4_ADDR 0x02014000
-#define FSL_IMX6_eCSPI4_SIZE 0x4000
-#define FSL_IMX6_eCSPI3_ADDR 0x02010000
-#define FSL_IMX6_eCSPI3_SIZE 0x4000
-#define FSL_IMX6_eCSPI2_ADDR 0x0200C000
-#define FSL_IMX6_eCSPI2_SIZE 0x4000
-#define FSL_IMX6_eCSPI1_ADDR 0x02008000
-#define FSL_IMX6_eCSPI1_SIZE 0x4000
-#define FSL_IMX6_SPDIF_ADDR 0x02004000
-#define FSL_IMX6_SPDIF_SIZE 0x4000
-/* AIPS1 end */
-#define FSL_IMX6_PCIe_REG_ADDR 0x01FFC000
-#define FSL_IMX6_PCIe_REG_SIZE 0x4000
-#define FSL_IMX6_PCIe_ADDR 0x01000000
-#define FSL_IMX6_PCIe_SIZE 0xFFC000
-#define FSL_IMX6_GPV_1_PL301_CFG_ADDR 0x00C00000
-#define FSL_IMX6_GPV_1_PL301_CFG_SIZE 0x100000
-#define FSL_IMX6_GPV_0_PL301_CFG_ADDR 0x00B00000
-#define FSL_IMX6_GPV_0_PL301_CFG_SIZE 0x100000
-#define FSL_IMX6_PL310_ADDR 0x00A02000
-#define FSL_IMX6_PL310_SIZE 0x1000
-#define FSL_IMX6_A9MPCORE_ADDR 0x00A00000
-#define FSL_IMX6_A9MPCORE_SIZE 0x2000
-#define FSL_IMX6_OCRAM_ALIAS_ADDR 0x00940000
-#define FSL_IMX6_OCRAM_ALIAS_SIZE 0xC0000
-#define FSL_IMX6_OCRAM_ADDR 0x00900000
-#define FSL_IMX6_OCRAM_SIZE 0x40000
-#define FSL_IMX6_GPV_4_PL301_CFG_ADDR 0x00800000
-#define FSL_IMX6_GPV_4_PL301_CFG_SIZE 0x100000
-#define FSL_IMX6_GPV_3_PL301_CFG_ADDR 0x00300000
-#define FSL_IMX6_GPV_3_PL301_CFG_SIZE 0x100000
-#define FSL_IMX6_GPV_2_PL301_CFG_ADDR 0x00200000
-#define FSL_IMX6_GPV_2_PL301_CFG_SIZE 0x100000
-#define FSL_IMX6_DTCP_ADDR 0x00138000
-#define FSL_IMX6_DTCP_SIZE 0x4000
-#define FSL_IMX6_GPU_2D_ADDR 0x00134000
-#define FSL_IMX6_GPU_2D_SIZE 0x4000
-#define FSL_IMX6_GPU_3D_ADDR 0x00130000
-#define FSL_IMX6_GPU_3D_SIZE 0x4000
-#define FSL_IMX6_HDMI_ADDR 0x00120000
-#define FSL_IMX6_HDMI_SIZE 0x9000
-#define FSL_IMX6_BCH_ADDR 0x00114000
-#define FSL_IMX6_BCH_SIZE 0x4000
-#define FSL_IMX6_GPMI_ADDR 0x00112000
-#define FSL_IMX6_GPMI_SIZE 0x2000
-#define FSL_IMX6_APBH_BRIDGE_DMA_ADDR 0x00110000
-#define FSL_IMX6_APBH_BRIDGE_DMA_SIZE 0x2000
-#define FSL_IMX6_CAAM_MEM_ADDR 0x00100000
-#define FSL_IMX6_CAAM_MEM_SIZE 0x4000
-#define FSL_IMX6_ROM_ADDR 0x00000000
-#define FSL_IMX6_ROM_SIZE 0x18000
-
-#define FSL_IMX6_IOMUXC_IRQ 0
-#define FSL_IMX6_DAP_IRQ 1
-#define FSL_IMX6_SDMA_IRQ 2
-#define FSL_IMX6_VPU_JPEG_IRQ 3
-#define FSL_IMX6_SNVS_PMIC_IRQ 4
-#define FSL_IMX6_IPU1_ERROR_IRQ 5
-#define FSL_IMX6_IPU1_SYNC_IRQ 6
-#define FSL_IMX6_IPU2_ERROR_IRQ 7
-#define FSL_IMX6_IPU2_SYNC_IRQ 8
-#define FSL_IMX6_GPU3D_IRQ 9
-#define FSL_IMX6_R2D_IRQ 10
-#define FSL_IMX6_V2D_IRQ 11
-#define FSL_IMX6_VPU_IRQ 12
-#define FSL_IMX6_APBH_BRIDGE_DMA_IRQ 13
-#define FSL_IMX6_EIM_IRQ 14
-#define FSL_IMX6_BCH_IRQ 15
-#define FSL_IMX6_GPMI_IRQ 16
-#define FSL_IMX6_DTCP_IRQ 17
-#define FSL_IMX6_VDOA_IRQ 18
-#define FSL_IMX6_SNVS_CONS_IRQ 19
-#define FSL_IMX6_SNVS_SEC_IRQ 20
-#define FSL_IMX6_CSU_IRQ 21
-#define FSL_IMX6_uSDHC1_IRQ 22
-#define FSL_IMX6_uSDHC2_IRQ 23
-#define FSL_IMX6_uSDHC3_IRQ 24
-#define FSL_IMX6_uSDHC4_IRQ 25
-#define FSL_IMX6_UART1_IRQ 26
-#define FSL_IMX6_UART2_IRQ 27
-#define FSL_IMX6_UART3_IRQ 28
-#define FSL_IMX6_UART4_IRQ 29
-#define FSL_IMX6_UART5_IRQ 30
-#define FSL_IMX6_ECSPI1_IRQ 31
-#define FSL_IMX6_ECSPI2_IRQ 32
-#define FSL_IMX6_ECSPI3_IRQ 33
-#define FSL_IMX6_ECSPI4_IRQ 34
-#define FSL_IMX6_ECSPI5_IRQ 35
-#define FSL_IMX6_I2C1_IRQ 36
-#define FSL_IMX6_I2C2_IRQ 37
-#define FSL_IMX6_I2C3_IRQ 38
-#define FSL_IMX6_SATA_IRQ 39
-#define FSL_IMX6_USB_HOST1_IRQ 40
-#define FSL_IMX6_USB_HOST2_IRQ 41
-#define FSL_IMX6_USB_HOST3_IRQ 42
-#define FSL_IMX6_USB_OTG_IRQ 43
-#define FSL_IMX6_USB_PHY_UTMI0_IRQ 44
-#define FSL_IMX6_USB_PHY_UTMI1_IRQ 45
-#define FSL_IMX6_SSI1_IRQ 46
-#define FSL_IMX6_SSI2_IRQ 47
-#define FSL_IMX6_SSI3_IRQ 48
-#define FSL_IMX6_TEMP_IRQ 49
-#define FSL_IMX6_ASRC_IRQ 50
-#define FSL_IMX6_ESAI_IRQ 51
-#define FSL_IMX6_SPDIF_IRQ 52
-#define FSL_IMX6_MLB150_IRQ 53
-#define FSL_IMX6_PMU1_IRQ 54
-#define FSL_IMX6_GPT_IRQ 55
-#define FSL_IMX6_EPIT1_IRQ 56
-#define FSL_IMX6_EPIT2_IRQ 57
-#define FSL_IMX6_GPIO1_INT7_IRQ 58
-#define FSL_IMX6_GPIO1_INT6_IRQ 59
-#define FSL_IMX6_GPIO1_INT5_IRQ 60
-#define FSL_IMX6_GPIO1_INT4_IRQ 61
-#define FSL_IMX6_GPIO1_INT3_IRQ 62
-#define FSL_IMX6_GPIO1_INT2_IRQ 63
-#define FSL_IMX6_GPIO1_INT1_IRQ 64
-#define FSL_IMX6_GPIO1_INT0_IRQ 65
-#define FSL_IMX6_GPIO1_LOW_IRQ 66
-#define FSL_IMX6_GPIO1_HIGH_IRQ 67
-#define FSL_IMX6_GPIO2_LOW_IRQ 68
-#define FSL_IMX6_GPIO2_HIGH_IRQ 69
-#define FSL_IMX6_GPIO3_LOW_IRQ 70
-#define FSL_IMX6_GPIO3_HIGH_IRQ 71
-#define FSL_IMX6_GPIO4_LOW_IRQ 72
-#define FSL_IMX6_GPIO4_HIGH_IRQ 73
-#define FSL_IMX6_GPIO5_LOW_IRQ 74
-#define FSL_IMX6_GPIO5_HIGH_IRQ 75
-#define FSL_IMX6_GPIO6_LOW_IRQ 76
-#define FSL_IMX6_GPIO6_HIGH_IRQ 77
-#define FSL_IMX6_GPIO7_LOW_IRQ 78
-#define FSL_IMX6_GPIO7_HIGH_IRQ 79
-#define FSL_IMX6_WDOG1_IRQ 80
-#define FSL_IMX6_WDOG2_IRQ 81
-#define FSL_IMX6_KPP_IRQ 82
-#define FSL_IMX6_PWM1_IRQ 83
-#define FSL_IMX6_PWM2_IRQ 84
-#define FSL_IMX6_PWM3_IRQ 85
-#define FSL_IMX6_PWM4_IRQ 86
-#define FSL_IMX6_CCM1_IRQ 87
-#define FSL_IMX6_CCM2_IRQ 88
-#define FSL_IMX6_GPC_IRQ 89
-#define FSL_IMX6_SRC_IRQ 91
-#define FSL_IMX6_CPU_L2_IRQ 92
-#define FSL_IMX6_CPU_PARITY_IRQ 93
-#define FSL_IMX6_CPU_PERF_IRQ 94
-#define FSL_IMX6_CPU_CTI_IRQ 95
-#define FSL_IMX6_SRC_COMB_IRQ 96
-#define FSL_IMX6_MIPI_CSI1_IRQ 100
-#define FSL_IMX6_MIPI_CSI2_IRQ 101
-#define FSL_IMX6_MIPI_DSI_IRQ 102
-#define FSL_IMX6_MIPI_HSI_IRQ 103
-#define FSL_IMX6_SJC_IRQ 104
-#define FSL_IMX6_CAAM0_IRQ 105
-#define FSL_IMX6_CAAM1_IRQ 106
-#define FSL_IMX6_ASC1_IRQ 108
-#define FSL_IMX6_ASC2_IRQ 109
-#define FSL_IMX6_FLEXCAN1_IRQ 110
-#define FSL_IMX6_FLEXCAN2_IRQ 111
-#define FSL_IMX6_HDMI_MASTER_IRQ 115
-#define FSL_IMX6_HDMI_CEC_IRQ 116
-#define FSL_IMX6_MLB150_LOW_IRQ 117
-#define FSL_IMX6_ENET_MAC_IRQ 118
-#define FSL_IMX6_ENET_MAC_1588_IRQ 119
-#define FSL_IMX6_PCIE1_IRQ 120
-#define FSL_IMX6_PCIE2_IRQ 121
-#define FSL_IMX6_PCIE3_IRQ 122
-#define FSL_IMX6_PCIE4_IRQ 123
-#define FSL_IMX6_DCIC1_IRQ 124
-#define FSL_IMX6_DCIC2_IRQ 125
-#define FSL_IMX6_MLB150_HIGH_IRQ 126
-#define FSL_IMX6_PMU2_IRQ 127
-#define FSL_IMX6_MAX_IRQ 128
-
-#endif /* FSL_IMX6_H */
+++ /dev/null
-/*
- * Copyright (c) 2018 Jean-Christophe Dubois <jcd@tribudubois.net>
- *
- * i.MX6ul SoC definitions
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#ifndef FSL_IMX6UL_H
-#define FSL_IMX6UL_H
-
-#include "hw/arm/boot.h"
-#include "hw/cpu/a15mpcore.h"
-#include "hw/misc/imx6ul_ccm.h"
-#include "hw/misc/imx6_src.h"
-#include "hw/misc/imx7_snvs.h"
-#include "hw/misc/imx7_gpr.h"
-#include "hw/intc/imx_gpcv2.h"
-#include "hw/watchdog/wdt_imx2.h"
-#include "hw/gpio/imx_gpio.h"
-#include "hw/char/imx_serial.h"
-#include "hw/timer/imx_gpt.h"
-#include "hw/timer/imx_epit.h"
-#include "hw/i2c/imx_i2c.h"
-#include "hw/gpio/imx_gpio.h"
-#include "hw/sd/sdhci.h"
-#include "hw/ssi/imx_spi.h"
-#include "hw/net/imx_fec.h"
-#include "hw/usb/chipidea.h"
-#include "hw/usb/imx-usb-phy.h"
-#include "exec/memory.h"
-#include "cpu.h"
-#include "qom/object.h"
-
-#define TYPE_FSL_IMX6UL "fsl,imx6ul"
-OBJECT_DECLARE_SIMPLE_TYPE(FslIMX6ULState, FSL_IMX6UL)
-
-enum FslIMX6ULConfiguration {
- FSL_IMX6UL_NUM_CPUS = 1,
- FSL_IMX6UL_NUM_UARTS = 8,
- FSL_IMX6UL_NUM_ETHS = 2,
- FSL_IMX6UL_ETH_NUM_TX_RINGS = 2,
- FSL_IMX6UL_NUM_USDHCS = 2,
- FSL_IMX6UL_NUM_WDTS = 3,
- FSL_IMX6UL_NUM_GPTS = 2,
- FSL_IMX6UL_NUM_EPITS = 2,
- FSL_IMX6UL_NUM_IOMUXCS = 2,
- FSL_IMX6UL_NUM_GPIOS = 5,
- FSL_IMX6UL_NUM_I2CS = 4,
- FSL_IMX6UL_NUM_ECSPIS = 4,
- FSL_IMX6UL_NUM_ADCS = 2,
- FSL_IMX6UL_NUM_USB_PHYS = 2,
- FSL_IMX6UL_NUM_USBS = 2,
-};
-
-struct FslIMX6ULState {
- /*< private >*/
- DeviceState parent_obj;
-
- /*< public >*/
- ARMCPU cpu;
- A15MPPrivState a7mpcore;
- IMXGPTState gpt[FSL_IMX6UL_NUM_GPTS];
- IMXEPITState epit[FSL_IMX6UL_NUM_EPITS];
- IMXGPIOState gpio[FSL_IMX6UL_NUM_GPIOS];
- IMX6ULCCMState ccm;
- IMX6SRCState src;
- IMX7SNVSState snvs;
- IMXGPCv2State gpcv2;
- IMX7GPRState gpr;
- IMXSPIState spi[FSL_IMX6UL_NUM_ECSPIS];
- IMXI2CState i2c[FSL_IMX6UL_NUM_I2CS];
- IMXSerialState uart[FSL_IMX6UL_NUM_UARTS];
- IMXFECState eth[FSL_IMX6UL_NUM_ETHS];
- SDHCIState usdhc[FSL_IMX6UL_NUM_USDHCS];
- IMX2WdtState wdt[FSL_IMX6UL_NUM_WDTS];
- IMXUSBPHYState usbphy[FSL_IMX6UL_NUM_USB_PHYS];
- ChipideaState usb[FSL_IMX6UL_NUM_USBS];
- MemoryRegion rom;
- MemoryRegion caam;
- MemoryRegion ocram;
- MemoryRegion ocram_alias;
-
- uint32_t phy_num[FSL_IMX6UL_NUM_ETHS];
-};
-
-enum FslIMX6ULMemoryMap {
- FSL_IMX6UL_MMDC_ADDR = 0x80000000,
- FSL_IMX6UL_MMDC_SIZE = 2 * 1024 * 1024 * 1024UL,
-
- FSL_IMX6UL_QSPI1_MEM_ADDR = 0x60000000,
- FSL_IMX6UL_EIM_ALIAS_ADDR = 0x58000000,
- FSL_IMX6UL_EIM_CS_ADDR = 0x50000000,
- FSL_IMX6UL_AES_ENCRYPT_ADDR = 0x10000000,
- FSL_IMX6UL_QSPI1_RX_ADDR = 0x0C000000,
-
- /* AIPS-2 */
- FSL_IMX6UL_UART6_ADDR = 0x021FC000,
- FSL_IMX6UL_I2C4_ADDR = 0x021F8000,
- FSL_IMX6UL_UART5_ADDR = 0x021F4000,
- FSL_IMX6UL_UART4_ADDR = 0x021F0000,
- FSL_IMX6UL_UART3_ADDR = 0x021EC000,
- FSL_IMX6UL_UART2_ADDR = 0x021E8000,
- FSL_IMX6UL_WDOG3_ADDR = 0x021E4000,
- FSL_IMX6UL_QSPI_ADDR = 0x021E0000,
- FSL_IMX6UL_SYS_CNT_CTRL_ADDR = 0x021DC000,
- FSL_IMX6UL_SYS_CNT_CMP_ADDR = 0x021D8000,
- FSL_IMX6UL_SYS_CNT_RD_ADDR = 0x021D4000,
- FSL_IMX6UL_TZASC_ADDR = 0x021D0000,
- FSL_IMX6UL_PXP_ADDR = 0x021CC000,
- FSL_IMX6UL_LCDIF_ADDR = 0x021C8000,
- FSL_IMX6UL_CSI_ADDR = 0x021C4000,
- FSL_IMX6UL_CSU_ADDR = 0x021C0000,
- FSL_IMX6UL_OCOTP_CTRL_ADDR = 0x021BC000,
- FSL_IMX6UL_EIM_ADDR = 0x021B8000,
- FSL_IMX6UL_SIM2_ADDR = 0x021B4000,
- FSL_IMX6UL_MMDC_CFG_ADDR = 0x021B0000,
- FSL_IMX6UL_ROMCP_ADDR = 0x021AC000,
- FSL_IMX6UL_I2C3_ADDR = 0x021A8000,
- FSL_IMX6UL_I2C2_ADDR = 0x021A4000,
- FSL_IMX6UL_I2C1_ADDR = 0x021A0000,
- FSL_IMX6UL_ADC2_ADDR = 0x0219C000,
- FSL_IMX6UL_ADC1_ADDR = 0x02198000,
- FSL_IMX6UL_USDHC2_ADDR = 0x02194000,
- FSL_IMX6UL_USDHC1_ADDR = 0x02190000,
- FSL_IMX6UL_SIM1_ADDR = 0x0218C000,
- FSL_IMX6UL_ENET1_ADDR = 0x02188000,
- FSL_IMX6UL_USBO2_USBMISC_ADDR = 0x02184800,
- FSL_IMX6UL_USBO2_USB_ADDR = 0x02184000,
- FSL_IMX6UL_USBO2_PL301_ADDR = 0x02180000,
- FSL_IMX6UL_AIPS2_CFG_ADDR = 0x0217C000,
- FSL_IMX6UL_CAAM_ADDR = 0x02140000,
- FSL_IMX6UL_A7MPCORE_DAP_ADDR = 0x02100000,
-
- /* AIPS-1 */
- FSL_IMX6UL_PWM8_ADDR = 0x020FC000,
- FSL_IMX6UL_PWM7_ADDR = 0x020F8000,
- FSL_IMX6UL_PWM6_ADDR = 0x020F4000,
- FSL_IMX6UL_PWM5_ADDR = 0x020F0000,
- FSL_IMX6UL_SDMA_ADDR = 0x020EC000,
- FSL_IMX6UL_GPT2_ADDR = 0x020E8000,
- FSL_IMX6UL_IOMUXC_GPR_ADDR = 0x020E4000,
- FSL_IMX6UL_IOMUXC_ADDR = 0x020E0000,
- FSL_IMX6UL_GPC_ADDR = 0x020DC000,
- FSL_IMX6UL_SRC_ADDR = 0x020D8000,
- FSL_IMX6UL_EPIT2_ADDR = 0x020D4000,
- FSL_IMX6UL_EPIT1_ADDR = 0x020D0000,
- FSL_IMX6UL_SNVS_HP_ADDR = 0x020CC000,
- FSL_IMX6UL_USBPHY2_ADDR = 0x020CA000,
- FSL_IMX6UL_USBPHY2_SIZE = (4 * 1024),
- FSL_IMX6UL_USBPHY1_ADDR = 0x020C9000,
- FSL_IMX6UL_USBPHY1_SIZE = (4 * 1024),
- FSL_IMX6UL_ANALOG_ADDR = 0x020C8000,
- FSL_IMX6UL_CCM_ADDR = 0x020C4000,
- FSL_IMX6UL_WDOG2_ADDR = 0x020C0000,
- FSL_IMX6UL_WDOG1_ADDR = 0x020BC000,
- FSL_IMX6UL_KPP_ADDR = 0x020B8000,
- FSL_IMX6UL_ENET2_ADDR = 0x020B4000,
- FSL_IMX6UL_SNVS_LP_ADDR = 0x020B0000,
- FSL_IMX6UL_GPIO5_ADDR = 0x020AC000,
- FSL_IMX6UL_GPIO4_ADDR = 0x020A8000,
- FSL_IMX6UL_GPIO3_ADDR = 0x020A4000,
- FSL_IMX6UL_GPIO2_ADDR = 0x020A0000,
- FSL_IMX6UL_GPIO1_ADDR = 0x0209C000,
- FSL_IMX6UL_GPT1_ADDR = 0x02098000,
- FSL_IMX6UL_CAN2_ADDR = 0x02094000,
- FSL_IMX6UL_CAN1_ADDR = 0x02090000,
- FSL_IMX6UL_PWM4_ADDR = 0x0208C000,
- FSL_IMX6UL_PWM3_ADDR = 0x02088000,
- FSL_IMX6UL_PWM2_ADDR = 0x02084000,
- FSL_IMX6UL_PWM1_ADDR = 0x02080000,
- FSL_IMX6UL_AIPS1_CFG_ADDR = 0x0207C000,
- FSL_IMX6UL_BEE_ADDR = 0x02044000,
- FSL_IMX6UL_TOUCH_CTRL_ADDR = 0x02040000,
- FSL_IMX6UL_SPBA_ADDR = 0x0203C000,
- FSL_IMX6UL_ASRC_ADDR = 0x02034000,
- FSL_IMX6UL_SAI3_ADDR = 0x02030000,
- FSL_IMX6UL_SAI2_ADDR = 0x0202C000,
- FSL_IMX6UL_SAI1_ADDR = 0x02028000,
- FSL_IMX6UL_UART8_ADDR = 0x02024000,
- FSL_IMX6UL_UART1_ADDR = 0x02020000,
- FSL_IMX6UL_UART7_ADDR = 0x02018000,
- FSL_IMX6UL_ECSPI4_ADDR = 0x02014000,
- FSL_IMX6UL_ECSPI3_ADDR = 0x02010000,
- FSL_IMX6UL_ECSPI2_ADDR = 0x0200C000,
- FSL_IMX6UL_ECSPI1_ADDR = 0x02008000,
- FSL_IMX6UL_SPDIF_ADDR = 0x02004000,
-
- FSL_IMX6UL_APBH_DMA_ADDR = 0x01804000,
- FSL_IMX6UL_APBH_DMA_SIZE = (32 * 1024),
-
- FSL_IMX6UL_A7MPCORE_ADDR = 0x00A00000,
-
- FSL_IMX6UL_OCRAM_ALIAS_ADDR = 0x00920000,
- FSL_IMX6UL_OCRAM_ALIAS_SIZE = 0x00060000,
- FSL_IMX6UL_OCRAM_MEM_ADDR = 0x00900000,
- FSL_IMX6UL_OCRAM_MEM_SIZE = 0x00020000,
- FSL_IMX6UL_CAAM_MEM_ADDR = 0x00100000,
- FSL_IMX6UL_CAAM_MEM_SIZE = 0x00008000,
- FSL_IMX6UL_ROM_ADDR = 0x00000000,
- FSL_IMX6UL_ROM_SIZE = 0x00018000,
-};
-
-enum FslIMX6ULIRQs {
- FSL_IMX6UL_IOMUXC_IRQ = 0,
- FSL_IMX6UL_DAP_IRQ = 1,
- FSL_IMX6UL_SDMA_IRQ = 2,
- FSL_IMX6UL_TSC_IRQ = 3,
- FSL_IMX6UL_SNVS_IRQ = 4,
- FSL_IMX6UL_LCDIF_IRQ = 5,
- FSL_IMX6UL_BEE_IRQ = 6,
- FSL_IMX6UL_CSI_IRQ = 7,
- FSL_IMX6UL_PXP_IRQ = 8,
- FSL_IMX6UL_SCTR1_IRQ = 9,
- FSL_IMX6UL_SCTR2_IRQ = 10,
- FSL_IMX6UL_WDOG3_IRQ = 11,
- FSL_IMX6UL_APBH_DMA_IRQ = 13,
- FSL_IMX6UL_WEIM_IRQ = 14,
- FSL_IMX6UL_RAWNAND1_IRQ = 15,
- FSL_IMX6UL_RAWNAND2_IRQ = 16,
- FSL_IMX6UL_UART6_IRQ = 17,
- FSL_IMX6UL_SRTC_IRQ = 19,
- FSL_IMX6UL_SRTC_SEC_IRQ = 20,
- FSL_IMX6UL_CSU_IRQ = 21,
- FSL_IMX6UL_USDHC1_IRQ = 22,
- FSL_IMX6UL_USDHC2_IRQ = 23,
- FSL_IMX6UL_SAI3_IRQ = 24,
- FSL_IMX6UL_SAI32_IRQ = 25,
-
- FSL_IMX6UL_UART1_IRQ = 26,
- FSL_IMX6UL_UART2_IRQ = 27,
- FSL_IMX6UL_UART3_IRQ = 28,
- FSL_IMX6UL_UART4_IRQ = 29,
- FSL_IMX6UL_UART5_IRQ = 30,
-
- FSL_IMX6UL_ECSPI1_IRQ = 31,
- FSL_IMX6UL_ECSPI2_IRQ = 32,
- FSL_IMX6UL_ECSPI3_IRQ = 33,
- FSL_IMX6UL_ECSPI4_IRQ = 34,
-
- FSL_IMX6UL_I2C4_IRQ = 35,
- FSL_IMX6UL_I2C1_IRQ = 36,
- FSL_IMX6UL_I2C2_IRQ = 37,
- FSL_IMX6UL_I2C3_IRQ = 38,
-
- FSL_IMX6UL_UART7_IRQ = 39,
- FSL_IMX6UL_UART8_IRQ = 40,
-
- FSL_IMX6UL_USB1_IRQ = 43,
- FSL_IMX6UL_USB2_IRQ = 42,
- FSL_IMX6UL_USB_PHY1_IRQ = 44,
- FSL_IMX6UL_USB_PHY2_IRQ = 45,
-
- FSL_IMX6UL_CAAM_JQ2_IRQ = 46,
- FSL_IMX6UL_CAAM_ERR_IRQ = 47,
- FSL_IMX6UL_CAAM_RTIC_IRQ = 48,
- FSL_IMX6UL_TEMP_IRQ = 49,
- FSL_IMX6UL_ASRC_IRQ = 50,
- FSL_IMX6UL_SPDIF_IRQ = 52,
- FSL_IMX6UL_PMU_REG_IRQ = 54,
- FSL_IMX6UL_GPT1_IRQ = 55,
-
- FSL_IMX6UL_EPIT1_IRQ = 56,
- FSL_IMX6UL_EPIT2_IRQ = 57,
-
- FSL_IMX6UL_GPIO1_INT7_IRQ = 58,
- FSL_IMX6UL_GPIO1_INT6_IRQ = 59,
- FSL_IMX6UL_GPIO1_INT5_IRQ = 60,
- FSL_IMX6UL_GPIO1_INT4_IRQ = 61,
- FSL_IMX6UL_GPIO1_INT3_IRQ = 62,
- FSL_IMX6UL_GPIO1_INT2_IRQ = 63,
- FSL_IMX6UL_GPIO1_INT1_IRQ = 64,
- FSL_IMX6UL_GPIO1_INT0_IRQ = 65,
- FSL_IMX6UL_GPIO1_LOW_IRQ = 66,
- FSL_IMX6UL_GPIO1_HIGH_IRQ = 67,
- FSL_IMX6UL_GPIO2_LOW_IRQ = 68,
- FSL_IMX6UL_GPIO2_HIGH_IRQ = 69,
- FSL_IMX6UL_GPIO3_LOW_IRQ = 70,
- FSL_IMX6UL_GPIO3_HIGH_IRQ = 71,
- FSL_IMX6UL_GPIO4_LOW_IRQ = 72,
- FSL_IMX6UL_GPIO4_HIGH_IRQ = 73,
- FSL_IMX6UL_GPIO5_LOW_IRQ = 74,
- FSL_IMX6UL_GPIO5_HIGH_IRQ = 75,
-
- FSL_IMX6UL_WDOG1_IRQ = 80,
- FSL_IMX6UL_WDOG2_IRQ = 81,
-
- FSL_IMX6UL_KPP_IRQ = 82,
-
- FSL_IMX6UL_PWM1_IRQ = 83,
- FSL_IMX6UL_PWM2_IRQ = 84,
- FSL_IMX6UL_PWM3_IRQ = 85,
- FSL_IMX6UL_PWM4_IRQ = 86,
-
- FSL_IMX6UL_CCM1_IRQ = 87,
- FSL_IMX6UL_CCM2_IRQ = 88,
-
- FSL_IMX6UL_GPC_IRQ = 89,
-
- FSL_IMX6UL_SRC_IRQ = 91,
-
- FSL_IMX6UL_CPU_PERF_IRQ = 94,
- FSL_IMX6UL_CPU_CTI_IRQ = 95,
-
- FSL_IMX6UL_SRC_WDOG_IRQ = 96,
-
- FSL_IMX6UL_SAI1_IRQ = 97,
- FSL_IMX6UL_SAI2_IRQ = 98,
-
- FSL_IMX6UL_ADC1_IRQ = 100,
- FSL_IMX6UL_ADC2_IRQ = 101,
-
- FSL_IMX6UL_SJC_IRQ = 104,
-
- FSL_IMX6UL_CAAM_RING0_IRQ = 105,
- FSL_IMX6UL_CAAM_RING1_IRQ = 106,
-
- FSL_IMX6UL_QSPI_IRQ = 107,
-
- FSL_IMX6UL_TZASC_IRQ = 108,
-
- FSL_IMX6UL_GPT2_IRQ = 109,
-
- FSL_IMX6UL_CAN1_IRQ = 110,
- FSL_IMX6UL_CAN2_IRQ = 111,
-
- FSL_IMX6UL_SIM1_IRQ = 112,
- FSL_IMX6UL_SIM2_IRQ = 113,
-
- FSL_IMX6UL_PWM5_IRQ = 114,
- FSL_IMX6UL_PWM6_IRQ = 115,
- FSL_IMX6UL_PWM7_IRQ = 116,
- FSL_IMX6UL_PWM8_IRQ = 117,
-
- FSL_IMX6UL_ENET1_IRQ = 118,
- FSL_IMX6UL_ENET1_TIMER_IRQ = 119,
- FSL_IMX6UL_ENET2_IRQ = 120,
- FSL_IMX6UL_ENET2_TIMER_IRQ = 121,
-
- FSL_IMX6UL_PMU_CORE_IRQ = 127,
- FSL_IMX6UL_MAX_IRQ = 128,
-};
-
-#endif /* FSL_IMX6UL_H */
+++ /dev/null
-/*
- * Copyright (c) 2018, Impinj, Inc.
- *
- * i.MX7 SoC definitions
- *
- * Author: Andrey Smirnov <andrew.smirnov@gmail.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#ifndef FSL_IMX7_H
-#define FSL_IMX7_H
-
-#include "hw/arm/boot.h"
-#include "hw/cpu/a15mpcore.h"
-#include "hw/intc/imx_gpcv2.h"
-#include "hw/misc/imx7_ccm.h"
-#include "hw/misc/imx7_snvs.h"
-#include "hw/misc/imx7_gpr.h"
-#include "hw/misc/imx6_src.h"
-#include "hw/watchdog/wdt_imx2.h"
-#include "hw/gpio/imx_gpio.h"
-#include "hw/char/imx_serial.h"
-#include "hw/timer/imx_gpt.h"
-#include "hw/timer/imx_epit.h"
-#include "hw/i2c/imx_i2c.h"
-#include "hw/gpio/imx_gpio.h"
-#include "hw/sd/sdhci.h"
-#include "hw/ssi/imx_spi.h"
-#include "hw/net/imx_fec.h"
-#include "hw/pci-host/designware.h"
-#include "hw/usb/chipidea.h"
-#include "cpu.h"
-#include "qom/object.h"
-
-#define TYPE_FSL_IMX7 "fsl,imx7"
-OBJECT_DECLARE_SIMPLE_TYPE(FslIMX7State, FSL_IMX7)
-
-enum FslIMX7Configuration {
- FSL_IMX7_NUM_CPUS = 2,
- FSL_IMX7_NUM_UARTS = 7,
- FSL_IMX7_NUM_ETHS = 2,
- FSL_IMX7_ETH_NUM_TX_RINGS = 3,
- FSL_IMX7_NUM_USDHCS = 3,
- FSL_IMX7_NUM_WDTS = 4,
- FSL_IMX7_NUM_GPTS = 4,
- FSL_IMX7_NUM_IOMUXCS = 2,
- FSL_IMX7_NUM_GPIOS = 7,
- FSL_IMX7_NUM_I2CS = 4,
- FSL_IMX7_NUM_ECSPIS = 4,
- FSL_IMX7_NUM_USBS = 3,
- FSL_IMX7_NUM_ADCS = 2,
-};
-
-struct FslIMX7State {
- /*< private >*/
- DeviceState parent_obj;
-
- /*< public >*/
- ARMCPU cpu[FSL_IMX7_NUM_CPUS];
- A15MPPrivState a7mpcore;
- IMXGPTState gpt[FSL_IMX7_NUM_GPTS];
- IMXGPIOState gpio[FSL_IMX7_NUM_GPIOS];
- IMX7CCMState ccm;
- IMX7AnalogState analog;
- IMX7SNVSState snvs;
- IMXGPCv2State gpcv2;
- IMXSPIState spi[FSL_IMX7_NUM_ECSPIS];
- IMXI2CState i2c[FSL_IMX7_NUM_I2CS];
- IMXSerialState uart[FSL_IMX7_NUM_UARTS];
- IMXFECState eth[FSL_IMX7_NUM_ETHS];
- SDHCIState usdhc[FSL_IMX7_NUM_USDHCS];
- IMX2WdtState wdt[FSL_IMX7_NUM_WDTS];
- IMX7GPRState gpr;
- ChipideaState usb[FSL_IMX7_NUM_USBS];
- DesignwarePCIEHost pcie;
- uint32_t phy_num[FSL_IMX7_NUM_ETHS];
-};
-
-enum FslIMX7MemoryMap {
- FSL_IMX7_MMDC_ADDR = 0x80000000,
- FSL_IMX7_MMDC_SIZE = 2 * 1024 * 1024 * 1024UL,
-
- FSL_IMX7_GPIO1_ADDR = 0x30200000,
- FSL_IMX7_GPIO2_ADDR = 0x30210000,
- FSL_IMX7_GPIO3_ADDR = 0x30220000,
- FSL_IMX7_GPIO4_ADDR = 0x30230000,
- FSL_IMX7_GPIO5_ADDR = 0x30240000,
- FSL_IMX7_GPIO6_ADDR = 0x30250000,
- FSL_IMX7_GPIO7_ADDR = 0x30260000,
-
- FSL_IMX7_IOMUXC_LPSR_GPR_ADDR = 0x30270000,
-
- FSL_IMX7_WDOG1_ADDR = 0x30280000,
- FSL_IMX7_WDOG2_ADDR = 0x30290000,
- FSL_IMX7_WDOG3_ADDR = 0x302A0000,
- FSL_IMX7_WDOG4_ADDR = 0x302B0000,
-
- FSL_IMX7_IOMUXC_LPSR_ADDR = 0x302C0000,
-
- FSL_IMX7_GPT1_ADDR = 0x302D0000,
- FSL_IMX7_GPT2_ADDR = 0x302E0000,
- FSL_IMX7_GPT3_ADDR = 0x302F0000,
- FSL_IMX7_GPT4_ADDR = 0x30300000,
-
- FSL_IMX7_IOMUXC_ADDR = 0x30330000,
- FSL_IMX7_IOMUXC_GPR_ADDR = 0x30340000,
- FSL_IMX7_IOMUXCn_SIZE = 0x1000,
-
- FSL_IMX7_OCOTP_ADDR = 0x30350000,
- FSL_IMX7_OCOTP_SIZE = 0x10000,
-
- FSL_IMX7_ANALOG_ADDR = 0x30360000,
- FSL_IMX7_SNVS_ADDR = 0x30370000,
- FSL_IMX7_CCM_ADDR = 0x30380000,
-
- FSL_IMX7_SRC_ADDR = 0x30390000,
- FSL_IMX7_SRC_SIZE = 0x1000,
-
- FSL_IMX7_ADC1_ADDR = 0x30610000,
- FSL_IMX7_ADC2_ADDR = 0x30620000,
- FSL_IMX7_ADCn_SIZE = 0x1000,
-
- FSL_IMX7_PWM1_ADDR = 0x30660000,
- FSL_IMX7_PWM2_ADDR = 0x30670000,
- FSL_IMX7_PWM3_ADDR = 0x30680000,
- FSL_IMX7_PWM4_ADDR = 0x30690000,
- FSL_IMX7_PWMn_SIZE = 0x10000,
-
- FSL_IMX7_PCIE_PHY_ADDR = 0x306D0000,
- FSL_IMX7_PCIE_PHY_SIZE = 0x10000,
-
- FSL_IMX7_GPC_ADDR = 0x303A0000,
-
- FSL_IMX7_CAAM_ADDR = 0x30900000,
- FSL_IMX7_CAAM_SIZE = 0x40000,
-
- FSL_IMX7_CAN1_ADDR = 0x30A00000,
- FSL_IMX7_CAN2_ADDR = 0x30A10000,
- FSL_IMX7_CANn_SIZE = 0x10000,
-
- FSL_IMX7_I2C1_ADDR = 0x30A20000,
- FSL_IMX7_I2C2_ADDR = 0x30A30000,
- FSL_IMX7_I2C3_ADDR = 0x30A40000,
- FSL_IMX7_I2C4_ADDR = 0x30A50000,
-
- FSL_IMX7_ECSPI1_ADDR = 0x30820000,
- FSL_IMX7_ECSPI2_ADDR = 0x30830000,
- FSL_IMX7_ECSPI3_ADDR = 0x30840000,
- FSL_IMX7_ECSPI4_ADDR = 0x30630000,
-
- FSL_IMX7_LCDIF_ADDR = 0x30730000,
- FSL_IMX7_LCDIF_SIZE = 0x1000,
-
- FSL_IMX7_UART1_ADDR = 0x30860000,
- /*
- * Some versions of the reference manual claim that UART2 is @
- * 0x30870000, but experiments with HW + DT files in upstream
- * Linux kernel show that not to be true and that block is
- * acutally located @ 0x30890000
- */
- FSL_IMX7_UART2_ADDR = 0x30890000,
- FSL_IMX7_UART3_ADDR = 0x30880000,
- FSL_IMX7_UART4_ADDR = 0x30A60000,
- FSL_IMX7_UART5_ADDR = 0x30A70000,
- FSL_IMX7_UART6_ADDR = 0x30A80000,
- FSL_IMX7_UART7_ADDR = 0x30A90000,
-
- FSL_IMX7_ENET1_ADDR = 0x30BE0000,
- FSL_IMX7_ENET2_ADDR = 0x30BF0000,
-
- FSL_IMX7_USB1_ADDR = 0x30B10000,
- FSL_IMX7_USBMISC1_ADDR = 0x30B10200,
- FSL_IMX7_USB2_ADDR = 0x30B20000,
- FSL_IMX7_USBMISC2_ADDR = 0x30B20200,
- FSL_IMX7_USB3_ADDR = 0x30B30000,
- FSL_IMX7_USBMISC3_ADDR = 0x30B30200,
- FSL_IMX7_USBMISCn_SIZE = 0x200,
-
- FSL_IMX7_USDHC1_ADDR = 0x30B40000,
- FSL_IMX7_USDHC2_ADDR = 0x30B50000,
- FSL_IMX7_USDHC3_ADDR = 0x30B60000,
-
- FSL_IMX7_SDMA_ADDR = 0x30BD0000,
- FSL_IMX7_SDMA_SIZE = 0x1000,
-
- FSL_IMX7_A7MPCORE_ADDR = 0x31000000,
- FSL_IMX7_A7MPCORE_DAP_ADDR = 0x30000000,
-
- FSL_IMX7_PCIE_REG_ADDR = 0x33800000,
- FSL_IMX7_PCIE_REG_SIZE = 16 * 1024,
-
- FSL_IMX7_GPR_ADDR = 0x30340000,
-
- FSL_IMX7_DMA_APBH_ADDR = 0x33000000,
- FSL_IMX7_DMA_APBH_SIZE = 0x2000,
-};
-
-enum FslIMX7IRQs {
- FSL_IMX7_USDHC1_IRQ = 22,
- FSL_IMX7_USDHC2_IRQ = 23,
- FSL_IMX7_USDHC3_IRQ = 24,
-
- FSL_IMX7_UART1_IRQ = 26,
- FSL_IMX7_UART2_IRQ = 27,
- FSL_IMX7_UART3_IRQ = 28,
- FSL_IMX7_UART4_IRQ = 29,
- FSL_IMX7_UART5_IRQ = 30,
- FSL_IMX7_UART6_IRQ = 16,
-
- FSL_IMX7_ECSPI1_IRQ = 31,
- FSL_IMX7_ECSPI2_IRQ = 32,
- FSL_IMX7_ECSPI3_IRQ = 33,
- FSL_IMX7_ECSPI4_IRQ = 34,
-
- FSL_IMX7_I2C1_IRQ = 35,
- FSL_IMX7_I2C2_IRQ = 36,
- FSL_IMX7_I2C3_IRQ = 37,
- FSL_IMX7_I2C4_IRQ = 38,
-
- FSL_IMX7_USB1_IRQ = 43,
- FSL_IMX7_USB2_IRQ = 42,
- FSL_IMX7_USB3_IRQ = 40,
-
- FSL_IMX7_WDOG1_IRQ = 78,
- FSL_IMX7_WDOG2_IRQ = 79,
- FSL_IMX7_WDOG3_IRQ = 10,
- FSL_IMX7_WDOG4_IRQ = 109,
-
- FSL_IMX7_PCI_INTA_IRQ = 125,
- FSL_IMX7_PCI_INTB_IRQ = 124,
- FSL_IMX7_PCI_INTC_IRQ = 123,
- FSL_IMX7_PCI_INTD_IRQ = 122,
-
- FSL_IMX7_UART7_IRQ = 126,
-
-#define FSL_IMX7_ENET_IRQ(i, n) ((n) + ((i) ? 100 : 118))
-
- FSL_IMX7_MAX_IRQ = 128,
-};
-
-#endif /* FSL_IMX7_H */
+++ /dev/null
-/*
- * hw/arm/linux-boot-if.h : interface for devices which need to behave
- * specially for direct boot of an ARM Linux kernel
- */
-
-#ifndef HW_ARM_LINUX_BOOT_IF_H
-#define HW_ARM_LINUX_BOOT_IF_H
-
-#include "qom/object.h"
-
-#define TYPE_ARM_LINUX_BOOT_IF "arm-linux-boot-if"
-typedef struct ARMLinuxBootIfClass ARMLinuxBootIfClass;
-DECLARE_CLASS_CHECKERS(ARMLinuxBootIfClass, ARM_LINUX_BOOT_IF,
- TYPE_ARM_LINUX_BOOT_IF)
-#define ARM_LINUX_BOOT_IF(obj) \
- INTERFACE_CHECK(ARMLinuxBootIf, (obj), TYPE_ARM_LINUX_BOOT_IF)
-
-typedef struct ARMLinuxBootIf ARMLinuxBootIf;
-
-struct ARMLinuxBootIfClass {
- /*< private >*/
- InterfaceClass parent_class;
-
- /*< public >*/
- /** arm_linux_init: configure the device for a direct boot
- * of an ARM Linux kernel (so that device reset puts it into
- * the state the kernel expects after firmware initialization,
- * rather than the true hardware reset state). This callback is
- * called once after machine construction is complete (before the
- * first system reset).
- *
- * @obj: the object implementing this interface
- * @secure_boot: true if we are booting Secure, false for NonSecure
- * (or for a CPU which doesn't support TrustZone)
- */
- void (*arm_linux_init)(ARMLinuxBootIf *obj, bool secure_boot);
-};
-
-#endif
+++ /dev/null
-/*
- * Microsemi Smartfusion2 SoC
- *
- * Copyright (c) 2017 Subbaraya Sundeep <sundeep.lkml@gmail.com>
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
- * furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
- * THE SOFTWARE.
- */
-
-#ifndef HW_ARM_MSF2_SOC_H
-#define HW_ARM_MSF2_SOC_H
-
-#include "hw/arm/armv7m.h"
-#include "hw/timer/mss-timer.h"
-#include "hw/misc/msf2-sysreg.h"
-#include "hw/ssi/mss-spi.h"
-#include "hw/net/msf2-emac.h"
-#include "qom/object.h"
-
-#define TYPE_MSF2_SOC "msf2-soc"
-OBJECT_DECLARE_SIMPLE_TYPE(MSF2State, MSF2_SOC)
-
-#define MSF2_NUM_SPIS 2
-#define MSF2_NUM_UARTS 2
-
-/*
- * System timer consists of two programmable 32-bit
- * decrementing counters that generate individual interrupts to
- * the Cortex-M3 processor
- */
-#define MSF2_NUM_TIMERS 2
-
-struct MSF2State {
- /*< private >*/
- SysBusDevice parent_obj;
- /*< public >*/
-
- ARMv7MState armv7m;
-
- char *cpu_type;
- char *part_name;
- uint64_t envm_size;
- uint64_t esram_size;
-
- uint32_t m3clk;
- uint8_t apb0div;
- uint8_t apb1div;
-
- MSF2SysregState sysreg;
- MSSTimerState timer;
- MSSSpiState spi[MSF2_NUM_SPIS];
- MSF2EmacState emac;
-};
-
-#endif
+++ /dev/null
-/*
- * Nuvoton NPCM7xx SoC family.
- *
- * Copyright 2020 Google LLC
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License as published by the
- * Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
- * for more details.
- */
-#ifndef NPCM7XX_H
-#define NPCM7XX_H
-
-#include "hw/boards.h"
-#include "hw/cpu/a9mpcore.h"
-#include "hw/gpio/npcm7xx_gpio.h"
-#include "hw/mem/npcm7xx_mc.h"
-#include "hw/misc/npcm7xx_clk.h"
-#include "hw/misc/npcm7xx_gcr.h"
-#include "hw/misc/npcm7xx_rng.h"
-#include "hw/nvram/npcm7xx_otp.h"
-#include "hw/timer/npcm7xx_timer.h"
-#include "hw/ssi/npcm7xx_fiu.h"
-#include "hw/usb/hcd-ehci.h"
-#include "hw/usb/hcd-ohci.h"
-#include "target/arm/cpu.h"
-
-#define NPCM7XX_MAX_NUM_CPUS (2)
-
-/* The first half of the address space is reserved for DDR4 DRAM. */
-#define NPCM7XX_DRAM_BA (0x00000000)
-#define NPCM7XX_DRAM_SZ (2 * GiB)
-
-/* Magic addresses for setting up direct kernel booting and SMP boot stubs. */
-#define NPCM7XX_LOADER_START (0x00000000) /* Start of SDRAM */
-#define NPCM7XX_SMP_LOADER_START (0xffff0000) /* Boot ROM */
-#define NPCM7XX_SMP_BOOTREG_ADDR (0xf080013c) /* GCR.SCRPAD */
-#define NPCM7XX_GIC_CPU_IF_ADDR (0xf03fe100) /* GIC within A9 */
-#define NPCM7XX_BOARD_SETUP_ADDR (0xffff1000) /* Boot ROM */
-
-typedef struct NPCM7xxMachine {
- MachineState parent;
-} NPCM7xxMachine;
-
-#define TYPE_NPCM7XX_MACHINE MACHINE_TYPE_NAME("npcm7xx")
-#define NPCM7XX_MACHINE(obj) \
- OBJECT_CHECK(NPCM7xxMachine, (obj), TYPE_NPCM7XX_MACHINE)
-
-typedef struct NPCM7xxMachineClass {
- MachineClass parent;
-
- const char *soc_type;
-} NPCM7xxMachineClass;
-
-#define NPCM7XX_MACHINE_CLASS(klass) \
- OBJECT_CLASS_CHECK(NPCM7xxMachineClass, (klass), TYPE_NPCM7XX_MACHINE)
-#define NPCM7XX_MACHINE_GET_CLASS(obj) \
- OBJECT_GET_CLASS(NPCM7xxMachineClass, (obj), TYPE_NPCM7XX_MACHINE)
-
-typedef struct NPCM7xxState {
- DeviceState parent;
-
- ARMCPU cpu[NPCM7XX_MAX_NUM_CPUS];
- A9MPPrivState a9mpcore;
-
- MemoryRegion sram;
- MemoryRegion irom;
- MemoryRegion ram3;
- MemoryRegion *dram;
-
- NPCM7xxGCRState gcr;
- NPCM7xxCLKState clk;
- NPCM7xxTimerCtrlState tim[3];
- NPCM7xxOTPState key_storage;
- NPCM7xxOTPState fuse_array;
- NPCM7xxMCState mc;
- NPCM7xxRNGState rng;
- NPCM7xxGPIOState gpio[8];
- EHCISysBusState ehci;
- OHCISysBusState ohci;
- NPCM7xxFIUState fiu[2];
-} NPCM7xxState;
-
-#define TYPE_NPCM7XX "npcm7xx"
-#define NPCM7XX(obj) OBJECT_CHECK(NPCM7xxState, (obj), TYPE_NPCM7XX)
-
-#define TYPE_NPCM730 "npcm730"
-#define TYPE_NPCM750 "npcm750"
-
-typedef struct NPCM7xxClass {
- DeviceClass parent;
-
- /* Bitmask of modules that are permanently disabled on this chip. */
- uint32_t disabled_modules;
- /* Number of CPU cores enabled in this SoC class (may be 1 or 2). */
- uint32_t num_cpus;
-} NPCM7xxClass;
-
-#define NPCM7XX_CLASS(klass) \
- OBJECT_CLASS_CHECK(NPCM7xxClass, (klass), TYPE_NPCM7XX)
-#define NPCM7XX_GET_CLASS(obj) \
- OBJECT_GET_CLASS(NPCM7xxClass, (obj), TYPE_NPCM7XX)
-
-/**
- * npcm7xx_load_kernel - Loads memory with everything needed to boot
- * @machine - The machine containing the SoC to be booted.
- * @soc - The SoC containing the CPU to be booted.
- *
- * This will set up the ARM boot info structure for the specific NPCM7xx
- * derivative and call arm_load_kernel() to set up loading of the kernel, etc.
- * into memory, if requested by the user.
- */
-void npcm7xx_load_kernel(MachineState *machine, NPCM7xxState *soc);
-
-#endif /* NPCM7XX_H */
+++ /dev/null
-/*
- * Nordic Semiconductor nRF51 Series SOC Common Defines
- *
- * This file hosts generic defines used in various nRF51 peripheral devices.
- *
- * Reference Manual: http://infocenter.nordicsemi.com/pdf/nRF51_RM_v3.0.pdf
- * Product Spec: http://infocenter.nordicsemi.com/pdf/nRF51822_PS_v3.1.pdf
- *
- * Copyright 2018 Steffen Görtz <contrib@steffen-goertz.de>
- *
- * This code is licensed under the GPL version 2 or later. See
- * the COPYING file in the top-level directory.
- */
-
-#ifndef NRF51_H
-#define NRF51_H
-
-#define NRF51_FLASH_BASE 0x00000000
-#define NRF51_FICR_BASE 0x10000000
-#define NRF51_FICR_SIZE 0x00000100
-#define NRF51_UICR_BASE 0x10001000
-#define NRF51_SRAM_BASE 0x20000000
-
-#define NRF51_IOMEM_BASE 0x40000000
-#define NRF51_IOMEM_SIZE 0x20000000
-
-#define NRF51_PERIPHERAL_SIZE 0x00001000
-#define NRF51_UART_BASE 0x40002000
-#define NRF51_TWI_BASE 0x40003000
-#define NRF51_TIMER_BASE 0x40008000
-#define NRF51_RNG_BASE 0x4000D000
-#define NRF51_NVMC_BASE 0x4001E000
-#define NRF51_GPIO_BASE 0x50000000
-
-#define NRF51_PRIVATE_BASE 0xF0000000
-#define NRF51_PRIVATE_SIZE 0x10000000
-
-#define NRF51_PAGE_SIZE 1024
-
-/* Trigger */
-#define NRF51_TRIGGER_TASK 0x01
-
-/* Events */
-#define NRF51_EVENT_CLEAR 0x00
-
-#endif
+++ /dev/null
-/*
- * Nordic Semiconductor nRF51 SoC
- *
- * Copyright 2018 Joel Stanley <joel@jms.id.au>
- *
- * This code is licensed under the GPL version 2 or later. See
- * the COPYING file in the top-level directory.
- */
-
-#ifndef NRF51_SOC_H
-#define NRF51_SOC_H
-
-#include "hw/sysbus.h"
-#include "hw/arm/armv7m.h"
-#include "hw/char/nrf51_uart.h"
-#include "hw/misc/nrf51_rng.h"
-#include "hw/gpio/nrf51_gpio.h"
-#include "hw/nvram/nrf51_nvm.h"
-#include "hw/timer/nrf51_timer.h"
-#include "qom/object.h"
-
-#define TYPE_NRF51_SOC "nrf51-soc"
-OBJECT_DECLARE_SIMPLE_TYPE(NRF51State, NRF51_SOC)
-
-#define NRF51_NUM_TIMERS 3
-
-struct NRF51State {
- /*< private >*/
- SysBusDevice parent_obj;
-
- /*< public >*/
- ARMv7MState cpu;
-
- NRF51UARTState uart;
- NRF51RNGState rng;
- NRF51NVMState nvm;
- NRF51GPIOState gpio;
- NRF51TimerState timer[NRF51_NUM_TIMERS];
-
- MemoryRegion iomem;
- MemoryRegion sram;
- MemoryRegion flash;
- MemoryRegion clock;
- MemoryRegion twi;
-
- uint32_t sram_size;
- uint32_t flash_size;
-
- MemoryRegion *board_memory;
-
- MemoryRegion container;
-
-};
-
-#endif
+++ /dev/null
-/*
- * Texas Instruments OMAP processors.
- *
- * Copyright (C) 2006-2008 Andrzej Zaborowski <balrog@zabor.org>
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 or
- * (at your option) version 3 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License along
- * with this program; if not, see <http://www.gnu.org/licenses/>.
- */
-
-#ifndef HW_ARM_OMAP_H
-#define HW_ARM_OMAP_H
-
-#include "exec/memory.h"
-#include "hw/input/tsc2xxx.h"
-#include "target/arm/cpu-qom.h"
-#include "qemu/log.h"
-#include "qom/object.h"
-
-# define OMAP_EMIFS_BASE 0x00000000
-# define OMAP2_Q0_BASE 0x00000000
-# define OMAP_CS0_BASE 0x00000000
-# define OMAP_CS1_BASE 0x04000000
-# define OMAP_CS2_BASE 0x08000000
-# define OMAP_CS3_BASE 0x0c000000
-# define OMAP_EMIFF_BASE 0x10000000
-# define OMAP_IMIF_BASE 0x20000000
-# define OMAP_LOCALBUS_BASE 0x30000000
-# define OMAP2_Q1_BASE 0x40000000
-# define OMAP2_L4_BASE 0x48000000
-# define OMAP2_SRAM_BASE 0x40200000
-# define OMAP2_L3_BASE 0x68000000
-# define OMAP2_Q2_BASE 0x80000000
-# define OMAP2_Q3_BASE 0xc0000000
-# define OMAP_MPUI_BASE 0xe1000000
-
-# define OMAP730_SRAM_SIZE 0x00032000
-# define OMAP15XX_SRAM_SIZE 0x00030000
-# define OMAP16XX_SRAM_SIZE 0x00004000
-# define OMAP1611_SRAM_SIZE 0x0003e800
-# define OMAP242X_SRAM_SIZE 0x000a0000
-# define OMAP243X_SRAM_SIZE 0x00010000
-# define OMAP_CS0_SIZE 0x04000000
-# define OMAP_CS1_SIZE 0x04000000
-# define OMAP_CS2_SIZE 0x04000000
-# define OMAP_CS3_SIZE 0x04000000
-
-/* omap_clk.c */
-struct omap_mpu_state_s;
-typedef struct clk *omap_clk;
-omap_clk omap_findclk(struct omap_mpu_state_s *mpu, const char *name);
-void omap_clk_init(struct omap_mpu_state_s *mpu);
-void omap_clk_adduser(struct clk *clk, qemu_irq user);
-void omap_clk_get(omap_clk clk);
-void omap_clk_put(omap_clk clk);
-void omap_clk_onoff(omap_clk clk, int on);
-void omap_clk_canidle(omap_clk clk, int can);
-void omap_clk_setrate(omap_clk clk, int divide, int multiply);
-int64_t omap_clk_getrate(omap_clk clk);
-void omap_clk_reparent(omap_clk clk, omap_clk parent);
-
-/* omap_intc.c */
-#define TYPE_OMAP_INTC "common-omap-intc"
-typedef struct omap_intr_handler_s omap_intr_handler;
-DECLARE_INSTANCE_CHECKER(omap_intr_handler, OMAP_INTC,
- TYPE_OMAP_INTC)
-
-
-/*
- * TODO: Ideally we should have a clock framework that
- * let us wire these clocks up with QOM properties or links.
- *
- * qdev should support a generic means of defining a 'port' with
- * an arbitrary interface for connecting two devices. Then we
- * could reframe the omap clock API in terms of clock ports,
- * and get some type safety. For now the best qdev provides is
- * passing an arbitrary pointer.
- * (It's not possible to pass in the string which is the clock
- * name, because this device does not have the necessary information
- * (ie the struct omap_mpu_state_s*) to do the clockname to pointer
- * translation.)
- */
-void omap_intc_set_iclk(omap_intr_handler *intc, omap_clk clk);
-void omap_intc_set_fclk(omap_intr_handler *intc, omap_clk clk);
-
-/* omap_i2c.c */
-#define TYPE_OMAP_I2C "omap_i2c"
-OBJECT_DECLARE_SIMPLE_TYPE(OMAPI2CState, OMAP_I2C)
-
-
-/* TODO: clock framework (see above) */
-void omap_i2c_set_iclk(OMAPI2CState *i2c, omap_clk clk);
-void omap_i2c_set_fclk(OMAPI2CState *i2c, omap_clk clk);
-
-/* omap_gpio.c */
-#define TYPE_OMAP1_GPIO "omap-gpio"
-DECLARE_INSTANCE_CHECKER(struct omap_gpif_s, OMAP1_GPIO,
- TYPE_OMAP1_GPIO)
-
-#define TYPE_OMAP2_GPIO "omap2-gpio"
-DECLARE_INSTANCE_CHECKER(struct omap2_gpif_s, OMAP2_GPIO,
- TYPE_OMAP2_GPIO)
-
-typedef struct omap_gpif_s omap_gpif;
-typedef struct omap2_gpif_s omap2_gpif;
-
-/* TODO: clock framework (see above) */
-void omap_gpio_set_clk(omap_gpif *gpio, omap_clk clk);
-
-void omap2_gpio_set_iclk(omap2_gpif *gpio, omap_clk clk);
-void omap2_gpio_set_fclk(omap2_gpif *gpio, uint8_t i, omap_clk clk);
-
-/* OMAP2 l4 Interconnect */
-struct omap_l4_s;
-struct omap_l4_region_s {
- hwaddr offset;
- size_t size;
- int access;
-};
-struct omap_l4_agent_info_s {
- int ta;
- int region;
- int regions;
- int ta_region;
-};
-struct omap_target_agent_s {
- MemoryRegion iomem;
- struct omap_l4_s *bus;
- int regions;
- const struct omap_l4_region_s *start;
- hwaddr base;
- uint32_t component;
- uint32_t control;
- uint32_t status;
-};
-struct omap_l4_s *omap_l4_init(MemoryRegion *address_space,
- hwaddr base, int ta_num);
-
-struct omap_target_agent_s;
-struct omap_target_agent_s *omap_l4ta_get(
- struct omap_l4_s *bus,
- const struct omap_l4_region_s *regions,
- const struct omap_l4_agent_info_s *agents,
- int cs);
-hwaddr omap_l4_attach(struct omap_target_agent_s *ta,
- int region, MemoryRegion *mr);
-hwaddr omap_l4_region_base(struct omap_target_agent_s *ta,
- int region);
-hwaddr omap_l4_region_size(struct omap_target_agent_s *ta,
- int region);
-
-/* OMAP2 SDRAM controller */
-struct omap_sdrc_s;
-struct omap_sdrc_s *omap_sdrc_init(MemoryRegion *sysmem,
- hwaddr base);
-void omap_sdrc_reset(struct omap_sdrc_s *s);
-
-/* OMAP2 general purpose memory controller */
-struct omap_gpmc_s;
-struct omap_gpmc_s *omap_gpmc_init(struct omap_mpu_state_s *mpu,
- hwaddr base,
- qemu_irq irq, qemu_irq drq);
-void omap_gpmc_reset(struct omap_gpmc_s *s);
-void omap_gpmc_attach(struct omap_gpmc_s *s, int cs, MemoryRegion *iomem);
-void omap_gpmc_attach_nand(struct omap_gpmc_s *s, int cs, DeviceState *nand);
-
-/*
- * Common IRQ numbers for level 1 interrupt handler
- * See /usr/include/asm-arm/arch-omap/irqs.h in Linux.
- */
-# define OMAP_INT_CAMERA 1
-# define OMAP_INT_FIQ 3
-# define OMAP_INT_RTDX 6
-# define OMAP_INT_DSP_MMU_ABORT 7
-# define OMAP_INT_HOST 8
-# define OMAP_INT_ABORT 9
-# define OMAP_INT_BRIDGE_PRIV 13
-# define OMAP_INT_GPIO_BANK1 14
-# define OMAP_INT_UART3 15
-# define OMAP_INT_TIMER3 16
-# define OMAP_INT_DMA_CH0_6 19
-# define OMAP_INT_DMA_CH1_7 20
-# define OMAP_INT_DMA_CH2_8 21
-# define OMAP_INT_DMA_CH3 22
-# define OMAP_INT_DMA_CH4 23
-# define OMAP_INT_DMA_CH5 24
-# define OMAP_INT_DMA_LCD 25
-# define OMAP_INT_TIMER1 26
-# define OMAP_INT_WD_TIMER 27
-# define OMAP_INT_BRIDGE_PUB 28
-# define OMAP_INT_TIMER2 30
-# define OMAP_INT_LCD_CTRL 31
-
-/*
- * Common OMAP-15xx IRQ numbers for level 1 interrupt handler
- */
-# define OMAP_INT_15XX_IH2_IRQ 0
-# define OMAP_INT_15XX_LB_MMU 17
-# define OMAP_INT_15XX_LOCAL_BUS 29
-
-/*
- * OMAP-1510 specific IRQ numbers for level 1 interrupt handler
- */
-# define OMAP_INT_1510_SPI_TX 4
-# define OMAP_INT_1510_SPI_RX 5
-# define OMAP_INT_1510_DSP_MAILBOX1 10
-# define OMAP_INT_1510_DSP_MAILBOX2 11
-
-/*
- * OMAP-310 specific IRQ numbers for level 1 interrupt handler
- */
-# define OMAP_INT_310_McBSP2_TX 4
-# define OMAP_INT_310_McBSP2_RX 5
-# define OMAP_INT_310_HSB_MAILBOX1 12
-# define OMAP_INT_310_HSAB_MMU 18
-
-/*
- * OMAP-1610 specific IRQ numbers for level 1 interrupt handler
- */
-# define OMAP_INT_1610_IH2_IRQ 0
-# define OMAP_INT_1610_IH2_FIQ 2
-# define OMAP_INT_1610_McBSP2_TX 4
-# define OMAP_INT_1610_McBSP2_RX 5
-# define OMAP_INT_1610_DSP_MAILBOX1 10
-# define OMAP_INT_1610_DSP_MAILBOX2 11
-# define OMAP_INT_1610_LCD_LINE 12
-# define OMAP_INT_1610_GPTIMER1 17
-# define OMAP_INT_1610_GPTIMER2 18
-# define OMAP_INT_1610_SSR_FIFO_0 29
-
-/*
- * OMAP-730 specific IRQ numbers for level 1 interrupt handler
- */
-# define OMAP_INT_730_IH2_FIQ 0
-# define OMAP_INT_730_IH2_IRQ 1
-# define OMAP_INT_730_USB_NON_ISO 2
-# define OMAP_INT_730_USB_ISO 3
-# define OMAP_INT_730_ICR 4
-# define OMAP_INT_730_EAC 5
-# define OMAP_INT_730_GPIO_BANK1 6
-# define OMAP_INT_730_GPIO_BANK2 7
-# define OMAP_INT_730_GPIO_BANK3 8
-# define OMAP_INT_730_McBSP2TX 10
-# define OMAP_INT_730_McBSP2RX 11
-# define OMAP_INT_730_McBSP2RX_OVF 12
-# define OMAP_INT_730_LCD_LINE 14
-# define OMAP_INT_730_GSM_PROTECT 15
-# define OMAP_INT_730_TIMER3 16
-# define OMAP_INT_730_GPIO_BANK5 17
-# define OMAP_INT_730_GPIO_BANK6 18
-# define OMAP_INT_730_SPGIO_WR 29
-
-/*
- * Common IRQ numbers for level 2 interrupt handler
- */
-# define OMAP_INT_KEYBOARD 1
-# define OMAP_INT_uWireTX 2
-# define OMAP_INT_uWireRX 3
-# define OMAP_INT_I2C 4
-# define OMAP_INT_MPUIO 5
-# define OMAP_INT_USB_HHC_1 6
-# define OMAP_INT_McBSP3TX 10
-# define OMAP_INT_McBSP3RX 11
-# define OMAP_INT_McBSP1TX 12
-# define OMAP_INT_McBSP1RX 13
-# define OMAP_INT_UART1 14
-# define OMAP_INT_UART2 15
-# define OMAP_INT_USB_W2FC 20
-# define OMAP_INT_1WIRE 21
-# define OMAP_INT_OS_TIMER 22
-# define OMAP_INT_OQN 23
-# define OMAP_INT_GAUGE_32K 24
-# define OMAP_INT_RTC_TIMER 25
-# define OMAP_INT_RTC_ALARM 26
-# define OMAP_INT_DSP_MMU 28
-
-/*
- * OMAP-1510 specific IRQ numbers for level 2 interrupt handler
- */
-# define OMAP_INT_1510_BT_MCSI1TX 16
-# define OMAP_INT_1510_BT_MCSI1RX 17
-# define OMAP_INT_1510_SoSSI_MATCH 19
-# define OMAP_INT_1510_MEM_STICK 27
-# define OMAP_INT_1510_COM_SPI_RO 31
-
-/*
- * OMAP-310 specific IRQ numbers for level 2 interrupt handler
- */
-# define OMAP_INT_310_FAC 0
-# define OMAP_INT_310_USB_HHC_2 7
-# define OMAP_INT_310_MCSI1_FE 16
-# define OMAP_INT_310_MCSI2_FE 17
-# define OMAP_INT_310_USB_W2FC_ISO 29
-# define OMAP_INT_310_USB_W2FC_NON_ISO 30
-# define OMAP_INT_310_McBSP2RX_OF 31
-
-/*
- * OMAP-1610 specific IRQ numbers for level 2 interrupt handler
- */
-# define OMAP_INT_1610_FAC 0
-# define OMAP_INT_1610_USB_HHC_2 7
-# define OMAP_INT_1610_USB_OTG 8
-# define OMAP_INT_1610_SoSSI 9
-# define OMAP_INT_1610_BT_MCSI1TX 16
-# define OMAP_INT_1610_BT_MCSI1RX 17
-# define OMAP_INT_1610_SoSSI_MATCH 19
-# define OMAP_INT_1610_MEM_STICK 27
-# define OMAP_INT_1610_McBSP2RX_OF 31
-# define OMAP_INT_1610_STI 32
-# define OMAP_INT_1610_STI_WAKEUP 33
-# define OMAP_INT_1610_GPTIMER3 34
-# define OMAP_INT_1610_GPTIMER4 35
-# define OMAP_INT_1610_GPTIMER5 36
-# define OMAP_INT_1610_GPTIMER6 37
-# define OMAP_INT_1610_GPTIMER7 38
-# define OMAP_INT_1610_GPTIMER8 39
-# define OMAP_INT_1610_GPIO_BANK2 40
-# define OMAP_INT_1610_GPIO_BANK3 41
-# define OMAP_INT_1610_MMC2 42
-# define OMAP_INT_1610_CF 43
-# define OMAP_INT_1610_WAKE_UP_REQ 46
-# define OMAP_INT_1610_GPIO_BANK4 48
-# define OMAP_INT_1610_SPI 49
-# define OMAP_INT_1610_DMA_CH6 53
-# define OMAP_INT_1610_DMA_CH7 54
-# define OMAP_INT_1610_DMA_CH8 55
-# define OMAP_INT_1610_DMA_CH9 56
-# define OMAP_INT_1610_DMA_CH10 57
-# define OMAP_INT_1610_DMA_CH11 58
-# define OMAP_INT_1610_DMA_CH12 59
-# define OMAP_INT_1610_DMA_CH13 60
-# define OMAP_INT_1610_DMA_CH14 61
-# define OMAP_INT_1610_DMA_CH15 62
-# define OMAP_INT_1610_NAND 63
-
-/*
- * OMAP-730 specific IRQ numbers for level 2 interrupt handler
- */
-# define OMAP_INT_730_HW_ERRORS 0
-# define OMAP_INT_730_NFIQ_PWR_FAIL 1
-# define OMAP_INT_730_CFCD 2
-# define OMAP_INT_730_CFIREQ 3
-# define OMAP_INT_730_I2C 4
-# define OMAP_INT_730_PCC 5
-# define OMAP_INT_730_MPU_EXT_NIRQ 6
-# define OMAP_INT_730_SPI_100K_1 7
-# define OMAP_INT_730_SYREN_SPI 8
-# define OMAP_INT_730_VLYNQ 9
-# define OMAP_INT_730_GPIO_BANK4 10
-# define OMAP_INT_730_McBSP1TX 11
-# define OMAP_INT_730_McBSP1RX 12
-# define OMAP_INT_730_McBSP1RX_OF 13
-# define OMAP_INT_730_UART_MODEM_IRDA_2 14
-# define OMAP_INT_730_UART_MODEM_1 15
-# define OMAP_INT_730_MCSI 16
-# define OMAP_INT_730_uWireTX 17
-# define OMAP_INT_730_uWireRX 18
-# define OMAP_INT_730_SMC_CD 19
-# define OMAP_INT_730_SMC_IREQ 20
-# define OMAP_INT_730_HDQ_1WIRE 21
-# define OMAP_INT_730_TIMER32K 22
-# define OMAP_INT_730_MMC_SDIO 23
-# define OMAP_INT_730_UPLD 24
-# define OMAP_INT_730_USB_HHC_1 27
-# define OMAP_INT_730_USB_HHC_2 28
-# define OMAP_INT_730_USB_GENI 29
-# define OMAP_INT_730_USB_OTG 30
-# define OMAP_INT_730_CAMERA_IF 31
-# define OMAP_INT_730_RNG 32
-# define OMAP_INT_730_DUAL_MODE_TIMER 33
-# define OMAP_INT_730_DBB_RF_EN 34
-# define OMAP_INT_730_MPUIO_KEYPAD 35
-# define OMAP_INT_730_SHA1_MD5 36
-# define OMAP_INT_730_SPI_100K_2 37
-# define OMAP_INT_730_RNG_IDLE 38
-# define OMAP_INT_730_MPUIO 39
-# define OMAP_INT_730_LLPC_LCD_CTRL_OFF 40
-# define OMAP_INT_730_LLPC_OE_FALLING 41
-# define OMAP_INT_730_LLPC_OE_RISING 42
-# define OMAP_INT_730_LLPC_VSYNC 43
-# define OMAP_INT_730_WAKE_UP_REQ 46
-# define OMAP_INT_730_DMA_CH6 53
-# define OMAP_INT_730_DMA_CH7 54
-# define OMAP_INT_730_DMA_CH8 55
-# define OMAP_INT_730_DMA_CH9 56
-# define OMAP_INT_730_DMA_CH10 57
-# define OMAP_INT_730_DMA_CH11 58
-# define OMAP_INT_730_DMA_CH12 59
-# define OMAP_INT_730_DMA_CH13 60
-# define OMAP_INT_730_DMA_CH14 61
-# define OMAP_INT_730_DMA_CH15 62
-# define OMAP_INT_730_NAND 63
-
-/*
- * OMAP-24xx common IRQ numbers
- */
-# define OMAP_INT_24XX_STI 4
-# define OMAP_INT_24XX_SYS_NIRQ 7
-# define OMAP_INT_24XX_L3_IRQ 10
-# define OMAP_INT_24XX_PRCM_MPU_IRQ 11
-# define OMAP_INT_24XX_SDMA_IRQ0 12
-# define OMAP_INT_24XX_SDMA_IRQ1 13
-# define OMAP_INT_24XX_SDMA_IRQ2 14
-# define OMAP_INT_24XX_SDMA_IRQ3 15
-# define OMAP_INT_243X_MCBSP2_IRQ 16
-# define OMAP_INT_243X_MCBSP3_IRQ 17
-# define OMAP_INT_243X_MCBSP4_IRQ 18
-# define OMAP_INT_243X_MCBSP5_IRQ 19
-# define OMAP_INT_24XX_GPMC_IRQ 20
-# define OMAP_INT_24XX_GUFFAW_IRQ 21
-# define OMAP_INT_24XX_IVA_IRQ 22
-# define OMAP_INT_24XX_EAC_IRQ 23
-# define OMAP_INT_24XX_CAM_IRQ 24
-# define OMAP_INT_24XX_DSS_IRQ 25
-# define OMAP_INT_24XX_MAIL_U0_MPU 26
-# define OMAP_INT_24XX_DSP_UMA 27
-# define OMAP_INT_24XX_DSP_MMU 28
-# define OMAP_INT_24XX_GPIO_BANK1 29
-# define OMAP_INT_24XX_GPIO_BANK2 30
-# define OMAP_INT_24XX_GPIO_BANK3 31
-# define OMAP_INT_24XX_GPIO_BANK4 32
-# define OMAP_INT_243X_GPIO_BANK5 33
-# define OMAP_INT_24XX_MAIL_U3_MPU 34
-# define OMAP_INT_24XX_WDT3 35
-# define OMAP_INT_24XX_WDT4 36
-# define OMAP_INT_24XX_GPTIMER1 37
-# define OMAP_INT_24XX_GPTIMER2 38
-# define OMAP_INT_24XX_GPTIMER3 39
-# define OMAP_INT_24XX_GPTIMER4 40
-# define OMAP_INT_24XX_GPTIMER5 41
-# define OMAP_INT_24XX_GPTIMER6 42
-# define OMAP_INT_24XX_GPTIMER7 43
-# define OMAP_INT_24XX_GPTIMER8 44
-# define OMAP_INT_24XX_GPTIMER9 45
-# define OMAP_INT_24XX_GPTIMER10 46
-# define OMAP_INT_24XX_GPTIMER11 47
-# define OMAP_INT_24XX_GPTIMER12 48
-# define OMAP_INT_24XX_PKA_IRQ 50
-# define OMAP_INT_24XX_SHA1MD5_IRQ 51
-# define OMAP_INT_24XX_RNG_IRQ 52
-# define OMAP_INT_24XX_MG_IRQ 53
-# define OMAP_INT_24XX_I2C1_IRQ 56
-# define OMAP_INT_24XX_I2C2_IRQ 57
-# define OMAP_INT_24XX_MCBSP1_IRQ_TX 59
-# define OMAP_INT_24XX_MCBSP1_IRQ_RX 60
-# define OMAP_INT_24XX_MCBSP2_IRQ_TX 62
-# define OMAP_INT_24XX_MCBSP2_IRQ_RX 63
-# define OMAP_INT_243X_MCBSP1_IRQ 64
-# define OMAP_INT_24XX_MCSPI1_IRQ 65
-# define OMAP_INT_24XX_MCSPI2_IRQ 66
-# define OMAP_INT_24XX_SSI1_IRQ0 67
-# define OMAP_INT_24XX_SSI1_IRQ1 68
-# define OMAP_INT_24XX_SSI2_IRQ0 69
-# define OMAP_INT_24XX_SSI2_IRQ1 70
-# define OMAP_INT_24XX_SSI_GDD_IRQ 71
-# define OMAP_INT_24XX_UART1_IRQ 72
-# define OMAP_INT_24XX_UART2_IRQ 73
-# define OMAP_INT_24XX_UART3_IRQ 74
-# define OMAP_INT_24XX_USB_IRQ_GEN 75
-# define OMAP_INT_24XX_USB_IRQ_NISO 76
-# define OMAP_INT_24XX_USB_IRQ_ISO 77
-# define OMAP_INT_24XX_USB_IRQ_HGEN 78
-# define OMAP_INT_24XX_USB_IRQ_HSOF 79
-# define OMAP_INT_24XX_USB_IRQ_OTG 80
-# define OMAP_INT_24XX_VLYNQ_IRQ 81
-# define OMAP_INT_24XX_MMC_IRQ 83
-# define OMAP_INT_24XX_MS_IRQ 84
-# define OMAP_INT_24XX_FAC_IRQ 85
-# define OMAP_INT_24XX_MCSPI3_IRQ 91
-# define OMAP_INT_243X_HS_USB_MC 92
-# define OMAP_INT_243X_HS_USB_DMA 93
-# define OMAP_INT_243X_CARKIT 94
-# define OMAP_INT_34XX_GPTIMER12 95
-
-/* omap_dma.c */
-enum omap_dma_model {
- omap_dma_3_0,
- omap_dma_3_1,
- omap_dma_3_2,
- omap_dma_4,
-};
-
-struct soc_dma_s;
-struct soc_dma_s *omap_dma_init(hwaddr base, qemu_irq *irqs,
- MemoryRegion *sysmem,
- qemu_irq lcd_irq, struct omap_mpu_state_s *mpu, omap_clk clk,
- enum omap_dma_model model);
-struct soc_dma_s *omap_dma4_init(hwaddr base, qemu_irq *irqs,
- MemoryRegion *sysmem,
- struct omap_mpu_state_s *mpu, int fifo,
- int chans, omap_clk iclk, omap_clk fclk);
-void omap_dma_reset(struct soc_dma_s *s);
-
-struct dma_irq_map {
- int ih;
- int intr;
-};
-
-/* Only used in OMAP DMA 3.x gigacells */
-enum omap_dma_port {
- emiff = 0,
- emifs,
- imif, /* omap16xx: ocp_t1 */
- tipb,
- local, /* omap16xx: ocp_t2 */
- tipb_mpui,
- __omap_dma_port_last,
-};
-
-typedef enum {
- constant = 0,
- post_incremented,
- single_index,
- double_index,
-} omap_dma_addressing_t;
-
-/* Only used in OMAP DMA 3.x gigacells */
-struct omap_dma_lcd_channel_s {
- enum omap_dma_port src;
- hwaddr src_f1_top;
- hwaddr src_f1_bottom;
- hwaddr src_f2_top;
- hwaddr src_f2_bottom;
-
- /* Used in OMAP DMA 3.2 gigacell */
- unsigned char brust_f1;
- unsigned char pack_f1;
- unsigned char data_type_f1;
- unsigned char brust_f2;
- unsigned char pack_f2;
- unsigned char data_type_f2;
- unsigned char end_prog;
- unsigned char repeat;
- unsigned char auto_init;
- unsigned char priority;
- unsigned char fs;
- unsigned char running;
- unsigned char bs;
- unsigned char omap_3_1_compatible_disable;
- unsigned char dst;
- unsigned char lch_type;
- int16_t element_index_f1;
- int16_t element_index_f2;
- int32_t frame_index_f1;
- int32_t frame_index_f2;
- uint16_t elements_f1;
- uint16_t frames_f1;
- uint16_t elements_f2;
- uint16_t frames_f2;
- omap_dma_addressing_t mode_f1;
- omap_dma_addressing_t mode_f2;
-
- /* Destination port is fixed. */
- int interrupts;
- int condition;
- int dual;
-
- int current_frame;
- hwaddr phys_framebuffer[2];
- qemu_irq irq;
- struct omap_mpu_state_s *mpu;
-} *omap_dma_get_lcdch(struct soc_dma_s *s);
-
-/*
- * DMA request numbers for OMAP1
- * See /usr/include/asm-arm/arch-omap/dma.h in Linux.
- */
-# define OMAP_DMA_NO_DEVICE 0
-# define OMAP_DMA_MCSI1_TX 1
-# define OMAP_DMA_MCSI1_RX 2
-# define OMAP_DMA_I2C_RX 3
-# define OMAP_DMA_I2C_TX 4
-# define OMAP_DMA_EXT_NDMA_REQ0 5
-# define OMAP_DMA_EXT_NDMA_REQ1 6
-# define OMAP_DMA_UWIRE_TX 7
-# define OMAP_DMA_MCBSP1_TX 8
-# define OMAP_DMA_MCBSP1_RX 9
-# define OMAP_DMA_MCBSP3_TX 10
-# define OMAP_DMA_MCBSP3_RX 11
-# define OMAP_DMA_UART1_TX 12
-# define OMAP_DMA_UART1_RX 13
-# define OMAP_DMA_UART2_TX 14
-# define OMAP_DMA_UART2_RX 15
-# define OMAP_DMA_MCBSP2_TX 16
-# define OMAP_DMA_MCBSP2_RX 17
-# define OMAP_DMA_UART3_TX 18
-# define OMAP_DMA_UART3_RX 19
-# define OMAP_DMA_CAMERA_IF_RX 20
-# define OMAP_DMA_MMC_TX 21
-# define OMAP_DMA_MMC_RX 22
-# define OMAP_DMA_NAND 23 /* Not in OMAP310 */
-# define OMAP_DMA_IRQ_LCD_LINE 24 /* Not in OMAP310 */
-# define OMAP_DMA_MEMORY_STICK 25 /* Not in OMAP310 */
-# define OMAP_DMA_USB_W2FC_RX0 26
-# define OMAP_DMA_USB_W2FC_RX1 27
-# define OMAP_DMA_USB_W2FC_RX2 28
-# define OMAP_DMA_USB_W2FC_TX0 29
-# define OMAP_DMA_USB_W2FC_TX1 30
-# define OMAP_DMA_USB_W2FC_TX2 31
-
-/* These are only for 1610 */
-# define OMAP_DMA_CRYPTO_DES_IN 32
-# define OMAP_DMA_SPI_TX 33
-# define OMAP_DMA_SPI_RX 34
-# define OMAP_DMA_CRYPTO_HASH 35
-# define OMAP_DMA_CCP_ATTN 36
-# define OMAP_DMA_CCP_FIFO_NOT_EMPTY 37
-# define OMAP_DMA_CMT_APE_TX_CHAN_0 38
-# define OMAP_DMA_CMT_APE_RV_CHAN_0 39
-# define OMAP_DMA_CMT_APE_TX_CHAN_1 40
-# define OMAP_DMA_CMT_APE_RV_CHAN_1 41
-# define OMAP_DMA_CMT_APE_TX_CHAN_2 42
-# define OMAP_DMA_CMT_APE_RV_CHAN_2 43
-# define OMAP_DMA_CMT_APE_TX_CHAN_3 44
-# define OMAP_DMA_CMT_APE_RV_CHAN_3 45
-# define OMAP_DMA_CMT_APE_TX_CHAN_4 46
-# define OMAP_DMA_CMT_APE_RV_CHAN_4 47
-# define OMAP_DMA_CMT_APE_TX_CHAN_5 48
-# define OMAP_DMA_CMT_APE_RV_CHAN_5 49
-# define OMAP_DMA_CMT_APE_TX_CHAN_6 50
-# define OMAP_DMA_CMT_APE_RV_CHAN_6 51
-# define OMAP_DMA_CMT_APE_TX_CHAN_7 52
-# define OMAP_DMA_CMT_APE_RV_CHAN_7 53
-# define OMAP_DMA_MMC2_TX 54
-# define OMAP_DMA_MMC2_RX 55
-# define OMAP_DMA_CRYPTO_DES_OUT 56
-
-/*
- * DMA request numbers for the OMAP2
- */
-# define OMAP24XX_DMA_NO_DEVICE 0
-# define OMAP24XX_DMA_XTI_DMA 1 /* Not in OMAP2420 */
-# define OMAP24XX_DMA_EXT_DMAREQ0 2
-# define OMAP24XX_DMA_EXT_DMAREQ1 3
-# define OMAP24XX_DMA_GPMC 4
-# define OMAP24XX_DMA_GFX 5 /* Not in OMAP2420 */
-# define OMAP24XX_DMA_DSS 6
-# define OMAP24XX_DMA_VLYNQ_TX 7 /* Not in OMAP2420 */
-# define OMAP24XX_DMA_CWT 8 /* Not in OMAP2420 */
-# define OMAP24XX_DMA_AES_TX 9 /* Not in OMAP2420 */
-# define OMAP24XX_DMA_AES_RX 10 /* Not in OMAP2420 */
-# define OMAP24XX_DMA_DES_TX 11 /* Not in OMAP2420 */
-# define OMAP24XX_DMA_DES_RX 12 /* Not in OMAP2420 */
-# define OMAP24XX_DMA_SHA1MD5_RX 13 /* Not in OMAP2420 */
-# define OMAP24XX_DMA_EXT_DMAREQ2 14
-# define OMAP24XX_DMA_EXT_DMAREQ3 15
-# define OMAP24XX_DMA_EXT_DMAREQ4 16
-# define OMAP24XX_DMA_EAC_AC_RD 17
-# define OMAP24XX_DMA_EAC_AC_WR 18
-# define OMAP24XX_DMA_EAC_MD_UL_RD 19
-# define OMAP24XX_DMA_EAC_MD_UL_WR 20
-# define OMAP24XX_DMA_EAC_MD_DL_RD 21
-# define OMAP24XX_DMA_EAC_MD_DL_WR 22
-# define OMAP24XX_DMA_EAC_BT_UL_RD 23
-# define OMAP24XX_DMA_EAC_BT_UL_WR 24
-# define OMAP24XX_DMA_EAC_BT_DL_RD 25
-# define OMAP24XX_DMA_EAC_BT_DL_WR 26
-# define OMAP24XX_DMA_I2C1_TX 27
-# define OMAP24XX_DMA_I2C1_RX 28
-# define OMAP24XX_DMA_I2C2_TX 29
-# define OMAP24XX_DMA_I2C2_RX 30
-# define OMAP24XX_DMA_MCBSP1_TX 31
-# define OMAP24XX_DMA_MCBSP1_RX 32
-# define OMAP24XX_DMA_MCBSP2_TX 33
-# define OMAP24XX_DMA_MCBSP2_RX 34
-# define OMAP24XX_DMA_SPI1_TX0 35
-# define OMAP24XX_DMA_SPI1_RX0 36
-# define OMAP24XX_DMA_SPI1_TX1 37
-# define OMAP24XX_DMA_SPI1_RX1 38
-# define OMAP24XX_DMA_SPI1_TX2 39
-# define OMAP24XX_DMA_SPI1_RX2 40
-# define OMAP24XX_DMA_SPI1_TX3 41
-# define OMAP24XX_DMA_SPI1_RX3 42
-# define OMAP24XX_DMA_SPI2_TX0 43
-# define OMAP24XX_DMA_SPI2_RX0 44
-# define OMAP24XX_DMA_SPI2_TX1 45
-# define OMAP24XX_DMA_SPI2_RX1 46
-
-# define OMAP24XX_DMA_UART1_TX 49
-# define OMAP24XX_DMA_UART1_RX 50
-# define OMAP24XX_DMA_UART2_TX 51
-# define OMAP24XX_DMA_UART2_RX 52
-# define OMAP24XX_DMA_UART3_TX 53
-# define OMAP24XX_DMA_UART3_RX 54
-# define OMAP24XX_DMA_USB_W2FC_TX0 55
-# define OMAP24XX_DMA_USB_W2FC_RX0 56
-# define OMAP24XX_DMA_USB_W2FC_TX1 57
-# define OMAP24XX_DMA_USB_W2FC_RX1 58
-# define OMAP24XX_DMA_USB_W2FC_TX2 59
-# define OMAP24XX_DMA_USB_W2FC_RX2 60
-# define OMAP24XX_DMA_MMC1_TX 61
-# define OMAP24XX_DMA_MMC1_RX 62
-# define OMAP24XX_DMA_MS 63 /* Not in OMAP2420 */
-# define OMAP24XX_DMA_EXT_DMAREQ5 64
-
-/* omap[123].c */
-/* OMAP2 gp timer */
-struct omap_gp_timer_s;
-struct omap_gp_timer_s *omap_gp_timer_init(struct omap_target_agent_s *ta,
- qemu_irq irq, omap_clk fclk, omap_clk iclk);
-void omap_gp_timer_reset(struct omap_gp_timer_s *s);
-
-/* OMAP2 sysctimer */
-struct omap_synctimer_s;
-struct omap_synctimer_s *omap_synctimer_init(struct omap_target_agent_s *ta,
- struct omap_mpu_state_s *mpu, omap_clk fclk, omap_clk iclk);
-void omap_synctimer_reset(struct omap_synctimer_s *s);
-
-struct omap_uart_s;
-struct omap_uart_s *omap_uart_init(hwaddr base,
- qemu_irq irq, omap_clk fclk, omap_clk iclk,
- qemu_irq txdma, qemu_irq rxdma,
- const char *label, Chardev *chr);
-struct omap_uart_s *omap2_uart_init(MemoryRegion *sysmem,
- struct omap_target_agent_s *ta,
- qemu_irq irq, omap_clk fclk, omap_clk iclk,
- qemu_irq txdma, qemu_irq rxdma,
- const char *label, Chardev *chr);
-void omap_uart_reset(struct omap_uart_s *s);
-void omap_uart_attach(struct omap_uart_s *s, Chardev *chr);
-
-struct omap_mpuio_s;
-qemu_irq *omap_mpuio_in_get(struct omap_mpuio_s *s);
-void omap_mpuio_out_set(struct omap_mpuio_s *s, int line, qemu_irq handler);
-void omap_mpuio_key(struct omap_mpuio_s *s, int row, int col, int down);
-
-struct omap_uwire_s;
-void omap_uwire_attach(struct omap_uwire_s *s,
- uWireSlave *slave, int chipselect);
-
-/* OMAP2 spi */
-struct omap_mcspi_s;
-struct omap_mcspi_s *omap_mcspi_init(struct omap_target_agent_s *ta, int chnum,
- qemu_irq irq, qemu_irq *drq, omap_clk fclk, omap_clk iclk);
-void omap_mcspi_attach(struct omap_mcspi_s *s,
- uint32_t (*txrx)(void *opaque, uint32_t, int), void *opaque,
- int chipselect);
-void omap_mcspi_reset(struct omap_mcspi_s *s);
-
-struct I2SCodec {
- void *opaque;
-
- /* The CPU can call this if it is generating the clock signal on the
- * i2s port. The CODEC can ignore it if it is set up as a clock
- * master and generates its own clock. */
- void (*set_rate)(void *opaque, int in, int out);
-
- void (*tx_swallow)(void *opaque);
- qemu_irq rx_swallow;
- qemu_irq tx_start;
-
- int tx_rate;
- int cts;
- int rx_rate;
- int rts;
-
- struct i2s_fifo_s {
- uint8_t *fifo;
- int len;
- int start;
- int size;
- } in, out;
-};
-struct omap_mcbsp_s;
-void omap_mcbsp_i2s_attach(struct omap_mcbsp_s *s, I2SCodec *slave);
-
-void omap_tap_init(struct omap_target_agent_s *ta,
- struct omap_mpu_state_s *mpu);
-
-/* omap_lcdc.c */
-struct omap_lcd_panel_s;
-void omap_lcdc_reset(struct omap_lcd_panel_s *s);
-struct omap_lcd_panel_s *omap_lcdc_init(MemoryRegion *sysmem,
- hwaddr base,
- qemu_irq irq,
- struct omap_dma_lcd_channel_s *dma,
- omap_clk clk);
-
-/* omap_dss.c */
-struct rfbi_chip_s {
- void *opaque;
- void (*write)(void *opaque, int dc, uint16_t value);
- void (*block)(void *opaque, int dc, void *buf, size_t len, int pitch);
- uint16_t (*read)(void *opaque, int dc);
-};
-struct omap_dss_s;
-void omap_dss_reset(struct omap_dss_s *s);
-struct omap_dss_s *omap_dss_init(struct omap_target_agent_s *ta,
- MemoryRegion *sysmem,
- hwaddr l3_base,
- qemu_irq irq, qemu_irq drq,
- omap_clk fck1, omap_clk fck2, omap_clk ck54m,
- omap_clk ick1, omap_clk ick2);
-void omap_rfbi_attach(struct omap_dss_s *s, int cs, struct rfbi_chip_s *chip);
-
-/* omap_mmc.c */
-struct omap_mmc_s;
-struct omap_mmc_s *omap_mmc_init(hwaddr base,
- MemoryRegion *sysmem,
- BlockBackend *blk,
- qemu_irq irq, qemu_irq dma[], omap_clk clk);
-struct omap_mmc_s *omap2_mmc_init(struct omap_target_agent_s *ta,
- BlockBackend *blk, qemu_irq irq, qemu_irq dma[],
- omap_clk fclk, omap_clk iclk);
-void omap_mmc_reset(struct omap_mmc_s *s);
-void omap_mmc_handlers(struct omap_mmc_s *s, qemu_irq ro, qemu_irq cover);
-void omap_mmc_enable(struct omap_mmc_s *s, int enable);
-
-/* omap_i2c.c */
-I2CBus *omap_i2c_bus(DeviceState *omap_i2c);
-
-# define cpu_is_omap310(cpu) (cpu->mpu_model == omap310)
-# define cpu_is_omap1510(cpu) (cpu->mpu_model == omap1510)
-# define cpu_is_omap1610(cpu) (cpu->mpu_model == omap1610)
-# define cpu_is_omap1710(cpu) (cpu->mpu_model == omap1710)
-# define cpu_is_omap2410(cpu) (cpu->mpu_model == omap2410)
-# define cpu_is_omap2420(cpu) (cpu->mpu_model == omap2420)
-# define cpu_is_omap2430(cpu) (cpu->mpu_model == omap2430)
-# define cpu_is_omap3430(cpu) (cpu->mpu_model == omap3430)
-# define cpu_is_omap3630(cpu) (cpu->mpu_model == omap3630)
-
-# define cpu_is_omap15xx(cpu) \
- (cpu_is_omap310(cpu) || cpu_is_omap1510(cpu))
-# define cpu_is_omap16xx(cpu) \
- (cpu_is_omap1610(cpu) || cpu_is_omap1710(cpu))
-# define cpu_is_omap24xx(cpu) \
- (cpu_is_omap2410(cpu) || cpu_is_omap2420(cpu) || cpu_is_omap2430(cpu))
-
-# define cpu_class_omap1(cpu) \
- (cpu_is_omap15xx(cpu) || cpu_is_omap16xx(cpu))
-# define cpu_class_omap2(cpu) cpu_is_omap24xx(cpu)
-# define cpu_class_omap3(cpu) \
- (cpu_is_omap3430(cpu) || cpu_is_omap3630(cpu))
-
-struct omap_mpu_state_s {
- enum omap_mpu_model {
- omap310,
- omap1510,
- omap1610,
- omap1710,
- omap2410,
- omap2420,
- omap2422,
- omap2423,
- omap2430,
- omap3430,
- omap3630,
- } mpu_model;
-
- ARMCPU *cpu;
-
- qemu_irq *drq;
-
- qemu_irq wakeup;
-
- MemoryRegion ulpd_pm_iomem;
- MemoryRegion pin_cfg_iomem;
- MemoryRegion id_iomem;
- MemoryRegion id_iomem_e18;
- MemoryRegion id_iomem_ed4;
- MemoryRegion id_iomem_e20;
- MemoryRegion mpui_iomem;
- MemoryRegion tcmi_iomem;
- MemoryRegion clkm_iomem;
- MemoryRegion clkdsp_iomem;
- MemoryRegion mpui_io_iomem;
- MemoryRegion tap_iomem;
- MemoryRegion imif_ram;
- MemoryRegion sram;
-
- struct omap_dma_port_if_s {
- uint32_t (*read[3])(struct omap_mpu_state_s *s,
- hwaddr offset);
- void (*write[3])(struct omap_mpu_state_s *s,
- hwaddr offset, uint32_t value);
- int (*addr_valid)(struct omap_mpu_state_s *s,
- hwaddr addr);
- } port[__omap_dma_port_last];
-
- uint64_t sdram_size;
- unsigned long sram_size;
-
- /* MPUI-TIPB peripherals */
- struct omap_uart_s *uart[3];
-
- DeviceState *gpio;
-
- struct omap_mcbsp_s *mcbsp1;
- struct omap_mcbsp_s *mcbsp3;
-
- /* MPU public TIPB peripherals */
- struct omap_32khz_timer_s *os_timer;
-
- struct omap_mmc_s *mmc;
-
- struct omap_mpuio_s *mpuio;
-
- struct omap_uwire_s *microwire;
-
- struct omap_pwl_s *pwl;
- struct omap_pwt_s *pwt;
- DeviceState *i2c[2];
-
- struct omap_rtc_s *rtc;
-
- struct omap_mcbsp_s *mcbsp2;
-
- struct omap_lpg_s *led[2];
-
- /* MPU private TIPB peripherals */
- DeviceState *ih[2];
-
- struct soc_dma_s *dma;
-
- struct omap_mpu_timer_s *timer[3];
- struct omap_watchdog_timer_s *wdt;
-
- struct omap_lcd_panel_s *lcd;
-
- uint32_t ulpd_pm_regs[21];
- int64_t ulpd_gauge_start;
-
- uint32_t func_mux_ctrl[14];
- uint32_t comp_mode_ctrl[1];
- uint32_t pull_dwn_ctrl[4];
- uint32_t gate_inh_ctrl[1];
- uint32_t voltage_ctrl[1];
- uint32_t test_dbg_ctrl[1];
- uint32_t mod_conf_ctrl[1];
- int compat1509;
-
- uint32_t mpui_ctrl;
-
- struct omap_tipb_bridge_s *private_tipb;
- struct omap_tipb_bridge_s *public_tipb;
-
- uint32_t tcmi_regs[17];
-
- struct dpll_ctl_s *dpll[3];
-
- omap_clk clks;
- struct {
- int cold_start;
- int clocking_scheme;
- uint16_t arm_ckctl;
- uint16_t arm_idlect1;
- uint16_t arm_idlect2;
- uint16_t arm_ewupct;
- uint16_t arm_rstct1;
- uint16_t arm_rstct2;
- uint16_t arm_ckout1;
- int dpll1_mode;
- uint16_t dsp_idlect1;
- uint16_t dsp_idlect2;
- uint16_t dsp_rstct2;
- } clkm;
-
- /* OMAP2-only peripherals */
- struct omap_l4_s *l4;
-
- struct omap_gp_timer_s *gptimer[12];
- struct omap_synctimer_s *synctimer;
-
- struct omap_prcm_s *prcm;
- struct omap_sdrc_s *sdrc;
- struct omap_gpmc_s *gpmc;
- struct omap_sysctl_s *sysc;
-
- struct omap_mcspi_s *mcspi[2];
-
- struct omap_dss_s *dss;
-
- struct omap_eac_s *eac;
-};
-
-/* omap1.c */
-struct omap_mpu_state_s *omap310_mpu_init(MemoryRegion *sdram,
- const char *core);
-
-/* omap2.c */
-struct omap_mpu_state_s *omap2420_mpu_init(MemoryRegion *sdram,
- const char *core);
-
-uint32_t omap_badwidth_read8(void *opaque, hwaddr addr);
-void omap_badwidth_write8(void *opaque, hwaddr addr,
- uint32_t value);
-uint32_t omap_badwidth_read16(void *opaque, hwaddr addr);
-void omap_badwidth_write16(void *opaque, hwaddr addr,
- uint32_t value);
-uint32_t omap_badwidth_read32(void *opaque, hwaddr addr);
-void omap_badwidth_write32(void *opaque, hwaddr addr,
- uint32_t value);
-
-void omap_mpu_wakeup(void *opaque, int irq, int req);
-
-# define OMAP_BAD_REG(paddr) \
- qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad register %#08"HWADDR_PRIx"\n", \
- __func__, paddr)
-# define OMAP_RO_REG(paddr) \
- qemu_log_mask(LOG_GUEST_ERROR, "%s: Read-only register %#08" \
- HWADDR_PRIx "\n", \
- __func__, paddr)
-
-/* OMAP-specific Linux bootloader tags for the ATAG_BOARD area
- (Board-specifc tags are not here) */
-#define OMAP_TAG_CLOCK 0x4f01
-#define OMAP_TAG_MMC 0x4f02
-#define OMAP_TAG_SERIAL_CONSOLE 0x4f03
-#define OMAP_TAG_USB 0x4f04
-#define OMAP_TAG_LCD 0x4f05
-#define OMAP_TAG_GPIO_SWITCH 0x4f06
-#define OMAP_TAG_UART 0x4f07
-#define OMAP_TAG_FBMEM 0x4f08
-#define OMAP_TAG_STI_CONSOLE 0x4f09
-#define OMAP_TAG_CAMERA_SENSOR 0x4f0a
-#define OMAP_TAG_PARTITION 0x4f0b
-#define OMAP_TAG_TEA5761 0x4f10
-#define OMAP_TAG_TMP105 0x4f11
-#define OMAP_TAG_BOOT_REASON 0x4f80
-#define OMAP_TAG_FLASH_PART_STR 0x4f81
-#define OMAP_TAG_VERSION_STR 0x4f82
-
-enum {
- OMAP_GPIOSW_TYPE_COVER = 0 << 4,
- OMAP_GPIOSW_TYPE_CONNECTION = 1 << 4,
- OMAP_GPIOSW_TYPE_ACTIVITY = 2 << 4,
-};
-
-#define OMAP_GPIOSW_INVERTED 0x0001
-#define OMAP_GPIOSW_OUTPUT 0x0002
-
-# define OMAP_MPUI_REG_MASK 0x000007ff
-
-#endif
+++ /dev/null
-#ifndef PRIMECELL_H
-#define PRIMECELL_H
-
-/* Declarations for ARM PrimeCell based periperals. */
-/* Also includes some devices that are currently only used by the
- ARM boards. */
-
-/* arm_sysctl GPIO lines */
-#define ARM_SYSCTL_GPIO_MMC_WPROT 0
-#define ARM_SYSCTL_GPIO_MMC_CARDIN 1
-
-#endif
+++ /dev/null
-/*
- * Intel XScale PXA255/270 processor support.
- *
- * Copyright (c) 2006 Openedhand Ltd.
- * Written by Andrzej Zaborowski <balrog@zabor.org>
- *
- * This code is licensed under the GNU GPL v2.
- */
-
-#ifndef PXA_H
-#define PXA_H
-
-#include "exec/memory.h"
-#include "target/arm/cpu-qom.h"
-#include "hw/pcmcia.h"
-#include "qom/object.h"
-
-/* Interrupt numbers */
-# define PXA2XX_PIC_SSP3 0
-# define PXA2XX_PIC_USBH2 2
-# define PXA2XX_PIC_USBH1 3
-# define PXA2XX_PIC_KEYPAD 4
-# define PXA2XX_PIC_PWRI2C 6
-# define PXA25X_PIC_HWUART 7
-# define PXA27X_PIC_OST_4_11 7
-# define PXA2XX_PIC_GPIO_0 8
-# define PXA2XX_PIC_GPIO_1 9
-# define PXA2XX_PIC_GPIO_X 10
-# define PXA2XX_PIC_I2S 13
-# define PXA26X_PIC_ASSP 15
-# define PXA25X_PIC_NSSP 16
-# define PXA27X_PIC_SSP2 16
-# define PXA2XX_PIC_LCD 17
-# define PXA2XX_PIC_I2C 18
-# define PXA2XX_PIC_ICP 19
-# define PXA2XX_PIC_STUART 20
-# define PXA2XX_PIC_BTUART 21
-# define PXA2XX_PIC_FFUART 22
-# define PXA2XX_PIC_MMC 23
-# define PXA2XX_PIC_SSP 24
-# define PXA2XX_PIC_DMA 25
-# define PXA2XX_PIC_OST_0 26
-# define PXA2XX_PIC_RTC1HZ 30
-# define PXA2XX_PIC_RTCALARM 31
-
-/* DMA requests */
-# define PXA2XX_RX_RQ_I2S 2
-# define PXA2XX_TX_RQ_I2S 3
-# define PXA2XX_RX_RQ_BTUART 4
-# define PXA2XX_TX_RQ_BTUART 5
-# define PXA2XX_RX_RQ_FFUART 6
-# define PXA2XX_TX_RQ_FFUART 7
-# define PXA2XX_RX_RQ_SSP1 13
-# define PXA2XX_TX_RQ_SSP1 14
-# define PXA2XX_RX_RQ_SSP2 15
-# define PXA2XX_TX_RQ_SSP2 16
-# define PXA2XX_RX_RQ_ICP 17
-# define PXA2XX_TX_RQ_ICP 18
-# define PXA2XX_RX_RQ_STUART 19
-# define PXA2XX_TX_RQ_STUART 20
-# define PXA2XX_RX_RQ_MMCI 21
-# define PXA2XX_TX_RQ_MMCI 22
-# define PXA2XX_USB_RQ(x) ((x) + 24)
-# define PXA2XX_RX_RQ_SSP3 66
-# define PXA2XX_TX_RQ_SSP3 67
-
-# define PXA2XX_SDRAM_BASE 0xa0000000
-# define PXA2XX_INTERNAL_BASE 0x5c000000
-# define PXA2XX_INTERNAL_SIZE 0x40000
-
-/* pxa2xx_pic.c */
-DeviceState *pxa2xx_pic_init(hwaddr base, ARMCPU *cpu);
-
-/* pxa2xx_gpio.c */
-DeviceState *pxa2xx_gpio_init(hwaddr base,
- ARMCPU *cpu, DeviceState *pic, int lines);
-void pxa2xx_gpio_read_notifier(DeviceState *dev, qemu_irq handler);
-
-/* pxa2xx_dma.c */
-DeviceState *pxa255_dma_init(hwaddr base, qemu_irq irq);
-DeviceState *pxa27x_dma_init(hwaddr base, qemu_irq irq);
-
-/* pxa2xx_lcd.c */
-typedef struct PXA2xxLCDState PXA2xxLCDState;
-PXA2xxLCDState *pxa2xx_lcdc_init(MemoryRegion *sysmem,
- hwaddr base, qemu_irq irq);
-void pxa2xx_lcd_vsync_notifier(PXA2xxLCDState *s, qemu_irq handler);
-
-/* pxa2xx_mmci.c */
-#define TYPE_PXA2XX_MMCI "pxa2xx-mmci"
-OBJECT_DECLARE_SIMPLE_TYPE(PXA2xxMMCIState, PXA2XX_MMCI)
-
-PXA2xxMMCIState *pxa2xx_mmci_init(MemoryRegion *sysmem,
- hwaddr base,
- qemu_irq irq, qemu_irq rx_dma, qemu_irq tx_dma);
-void pxa2xx_mmci_handlers(PXA2xxMMCIState *s, qemu_irq readonly,
- qemu_irq coverswitch);
-
-/* pxa2xx_pcmcia.c */
-#define TYPE_PXA2XX_PCMCIA "pxa2xx-pcmcia"
-OBJECT_DECLARE_SIMPLE_TYPE(PXA2xxPCMCIAState, PXA2XX_PCMCIA)
-
-PXA2xxPCMCIAState *pxa2xx_pcmcia_init(MemoryRegion *sysmem,
- hwaddr base);
-int pxa2xx_pcmcia_attach(void *opaque, PCMCIACardState *card);
-int pxa2xx_pcmcia_detach(void *opaque);
-void pxa2xx_pcmcia_set_irq_cb(void *opaque, qemu_irq irq, qemu_irq cd_irq);
-
-/* pxa2xx_keypad.c */
-struct keymap {
- int8_t column;
- int8_t row;
-};
-typedef struct PXA2xxKeyPadState PXA2xxKeyPadState;
-PXA2xxKeyPadState *pxa27x_keypad_init(MemoryRegion *sysmem,
- hwaddr base,
- qemu_irq irq);
-void pxa27x_register_keypad(PXA2xxKeyPadState *kp,
- const struct keymap *map, int size);
-
-/* pxa2xx.c */
-typedef struct PXA2xxI2CState PXA2xxI2CState;
-PXA2xxI2CState *pxa2xx_i2c_init(hwaddr base,
- qemu_irq irq, uint32_t page_size);
-I2CBus *pxa2xx_i2c_bus(PXA2xxI2CState *s);
-
-#define TYPE_PXA2XX_I2C "pxa2xx_i2c"
-typedef struct PXA2xxI2SState PXA2xxI2SState;
-OBJECT_DECLARE_SIMPLE_TYPE(PXA2xxI2CState, PXA2XX_I2C)
-
-#define TYPE_PXA2XX_FIR "pxa2xx-fir"
-OBJECT_DECLARE_SIMPLE_TYPE(PXA2xxFIrState, PXA2XX_FIR)
-
-typedef struct {
- ARMCPU *cpu;
- DeviceState *pic;
- qemu_irq reset;
- MemoryRegion sdram;
- MemoryRegion internal;
- MemoryRegion cm_iomem;
- MemoryRegion mm_iomem;
- MemoryRegion pm_iomem;
- DeviceState *dma;
- DeviceState *gpio;
- PXA2xxLCDState *lcd;
- SSIBus **ssp;
- PXA2xxI2CState *i2c[2];
- PXA2xxMMCIState *mmc;
- PXA2xxPCMCIAState *pcmcia[2];
- PXA2xxI2SState *i2s;
- PXA2xxFIrState *fir;
- PXA2xxKeyPadState *kp;
-
- /* Power management */
- hwaddr pm_base;
- uint32_t pm_regs[0x40];
-
- /* Clock management */
- hwaddr cm_base;
- uint32_t cm_regs[4];
- uint32_t clkcfg;
-
- /* Memory management */
- hwaddr mm_base;
- uint32_t mm_regs[0x1a];
-
- /* Performance monitoring */
- uint32_t pmnc;
-} PXA2xxState;
-
-struct PXA2xxI2SState {
- MemoryRegion iomem;
- qemu_irq irq;
- qemu_irq rx_dma;
- qemu_irq tx_dma;
- void (*data_req)(void *, int, int);
-
- uint32_t control[2];
- uint32_t status;
- uint32_t mask;
- uint32_t clk;
-
- int enable;
- int rx_len;
- int tx_len;
- void (*codec_out)(void *, uint32_t);
- uint32_t (*codec_in)(void *);
- void *opaque;
-
- int fifo_len;
- uint32_t fifo[16];
-};
-
-# define PA_FMT "0x%08lx"
-
-PXA2xxState *pxa270_init(MemoryRegion *address_space, unsigned int sdram_size,
- const char *revision);
-PXA2xxState *pxa255_init(MemoryRegion *address_space, unsigned int sdram_size);
-
-#endif /* PXA_H */
+++ /dev/null
-/*
- * bcm2708 aka bcm2835/2836 aka Raspberry Pi/Pi2 SoC platform defines
- *
- * These definitions are derived from those in Raspbian Linux at
- * arch/arm/mach-{bcm2708,bcm2709}/include/mach/platform.h
- * where they carry the following notice:
- *
- * Copyright (C) 2010 Broadcom
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
- *
- * Various undocumented addresses and names come from Herman Hermitage's VC4
- * documentation:
- * https://github.com/hermanhermitage/videocoreiv/wiki/MMIO-Register-map
- */
-
-#ifndef HW_ARM_RASPI_PLATFORM_H
-#define HW_ARM_RASPI_PLATFORM_H
-
-#define MSYNC_OFFSET 0x0000 /* Multicore Sync Block */
-#define CCPT_OFFSET 0x1000 /* Compact Camera Port 2 TX */
-#define INTE_OFFSET 0x2000 /* VC Interrupt controller */
-#define ST_OFFSET 0x3000 /* System Timer */
-#define TXP_OFFSET 0x4000 /* Transposer */
-#define JPEG_OFFSET 0x5000
-#define MPHI_OFFSET 0x6000 /* Message-based Parallel Host Intf. */
-#define DMA_OFFSET 0x7000 /* DMA controller, channels 0-14 */
-#define ARBA_OFFSET 0x9000
-#define BRDG_OFFSET 0xa000
-#define ARM_OFFSET 0xB000 /* ARM control block */
-#define ARMCTRL_OFFSET (ARM_OFFSET + 0x000)
-#define ARMCTRL_IC_OFFSET (ARM_OFFSET + 0x200) /* Interrupt controller */
-#define ARMCTRL_TIMER0_1_OFFSET (ARM_OFFSET + 0x400) /* Timer 0 and 1 (SP804) */
-#define ARMCTRL_0_SBM_OFFSET (ARM_OFFSET + 0x800) /* User 0 (ARM) Semaphores
- * Doorbells & Mailboxes */
-#define PM_OFFSET 0x100000 /* Power Management */
-#define CPRMAN_OFFSET 0x101000 /* Clock Management */
-#define AVS_OFFSET 0x103000 /* Audio Video Standard */
-#define RNG_OFFSET 0x104000
-#define GPIO_OFFSET 0x200000
-#define UART0_OFFSET 0x201000 /* PL011 */
-#define MMCI0_OFFSET 0x202000 /* Legacy MMC */
-#define I2S_OFFSET 0x203000 /* PCM */
-#define SPI0_OFFSET 0x204000 /* SPI master */
-#define BSC0_OFFSET 0x205000 /* BSC0 I2C/TWI */
-#define PIXV0_OFFSET 0x206000
-#define PIXV1_OFFSET 0x207000
-#define DPI_OFFSET 0x208000
-#define DSI0_OFFSET 0x209000 /* Display Serial Interface */
-#define PWM_OFFSET 0x20c000
-#define PERM_OFFSET 0x20d000
-#define TEC_OFFSET 0x20e000
-#define OTP_OFFSET 0x20f000
-#define SLIM_OFFSET 0x210000 /* SLIMbus */
-#define CPG_OFFSET 0x211000
-#define THERMAL_OFFSET 0x212000
-#define AVSP_OFFSET 0x213000
-#define BSC_SL_OFFSET 0x214000 /* SPI slave (bootrom) */
-#define AUX_OFFSET 0x215000 /* AUX: UART1/SPI1/SPI2 */
-#define EMMC1_OFFSET 0x300000
-#define EMMC2_OFFSET 0x340000
-#define HVS_OFFSET 0x400000
-#define SMI_OFFSET 0x600000
-#define DSI1_OFFSET 0x700000
-#define UCAM_OFFSET 0x800000
-#define CMI_OFFSET 0x802000
-#define BSC1_OFFSET 0x804000 /* BSC1 I2C/TWI */
-#define BSC2_OFFSET 0x805000 /* BSC2 I2C/TWI */
-#define VECA_OFFSET 0x806000
-#define PIXV2_OFFSET 0x807000
-#define HDMI_OFFSET 0x808000
-#define HDCP_OFFSET 0x809000
-#define ARBR0_OFFSET 0x80a000
-#define DBUS_OFFSET 0x900000
-#define AVE0_OFFSET 0x910000
-#define USB_OTG_OFFSET 0x980000 /* DTC_OTG USB controller */
-#define V3D_OFFSET 0xc00000
-#define SDRAMC_OFFSET 0xe00000
-#define L2CC_OFFSET 0xe01000 /* Level 2 Cache controller */
-#define L1CC_OFFSET 0xe02000 /* Level 1 Cache controller */
-#define ARBR1_OFFSET 0xe04000
-#define DMA15_OFFSET 0xE05000 /* DMA controller, channel 15 */
-#define DCRC_OFFSET 0xe07000
-#define AXIP_OFFSET 0xe08000
-
-/* GPU interrupts */
-#define INTERRUPT_TIMER0 0
-#define INTERRUPT_TIMER1 1
-#define INTERRUPT_TIMER2 2
-#define INTERRUPT_TIMER3 3
-#define INTERRUPT_CODEC0 4
-#define INTERRUPT_CODEC1 5
-#define INTERRUPT_CODEC2 6
-#define INTERRUPT_JPEG 7
-#define INTERRUPT_ISP 8
-#define INTERRUPT_USB 9
-#define INTERRUPT_3D 10
-#define INTERRUPT_TRANSPOSER 11
-#define INTERRUPT_MULTICORESYNC0 12
-#define INTERRUPT_MULTICORESYNC1 13
-#define INTERRUPT_MULTICORESYNC2 14
-#define INTERRUPT_MULTICORESYNC3 15
-#define INTERRUPT_DMA0 16
-#define INTERRUPT_DMA1 17
-#define INTERRUPT_DMA2 18
-#define INTERRUPT_DMA3 19
-#define INTERRUPT_DMA4 20
-#define INTERRUPT_DMA5 21
-#define INTERRUPT_DMA6 22
-#define INTERRUPT_DMA7 23
-#define INTERRUPT_DMA8 24
-#define INTERRUPT_DMA9 25
-#define INTERRUPT_DMA10 26
-#define INTERRUPT_DMA11 27
-#define INTERRUPT_DMA12 28
-#define INTERRUPT_AUX 29
-#define INTERRUPT_ARM 30
-#define INTERRUPT_VPUDMA 31
-#define INTERRUPT_HOSTPORT 32
-#define INTERRUPT_VIDEOSCALER 33
-#define INTERRUPT_CCP2TX 34
-#define INTERRUPT_SDC 35
-#define INTERRUPT_DSI0 36
-#define INTERRUPT_AVE 37
-#define INTERRUPT_CAM0 38
-#define INTERRUPT_CAM1 39
-#define INTERRUPT_HDMI0 40
-#define INTERRUPT_HDMI1 41
-#define INTERRUPT_PIXELVALVE1 42
-#define INTERRUPT_I2CSPISLV 43
-#define INTERRUPT_DSI1 44
-#define INTERRUPT_PWA0 45
-#define INTERRUPT_PWA1 46
-#define INTERRUPT_CPR 47
-#define INTERRUPT_SMI 48
-#define INTERRUPT_GPIO0 49
-#define INTERRUPT_GPIO1 50
-#define INTERRUPT_GPIO2 51
-#define INTERRUPT_GPIO3 52
-#define INTERRUPT_I2C 53
-#define INTERRUPT_SPI 54
-#define INTERRUPT_I2SPCM 55
-#define INTERRUPT_SDIO 56
-#define INTERRUPT_UART0 57
-#define INTERRUPT_SLIMBUS 58
-#define INTERRUPT_VEC 59
-#define INTERRUPT_CPG 60
-#define INTERRUPT_RNG 61
-#define INTERRUPT_ARASANSDIO 62
-#define INTERRUPT_AVSPMON 63
-
-/* ARM CPU IRQs use a private number space */
-#define INTERRUPT_ARM_TIMER 0
-#define INTERRUPT_ARM_MAILBOX 1
-#define INTERRUPT_ARM_DOORBELL_0 2
-#define INTERRUPT_ARM_DOORBELL_1 3
-#define INTERRUPT_VPU0_HALTED 4
-#define INTERRUPT_VPU1_HALTED 5
-#define INTERRUPT_ILLEGAL_TYPE0 6
-#define INTERRUPT_ILLEGAL_TYPE1 7
-
-#endif
+++ /dev/null
-/*
- * Common declarations for the Zaurii.
- *
- * This file is licensed under the GNU GPL.
- */
-
-#ifndef QEMU_SHARPSL_H
-#define QEMU_SHARPSL_H
-
-#include "exec/hwaddr.h"
-
-/* zaurus.c */
-
-#define SL_PXA_PARAM_BASE 0xa0000a00
-void sl_bootparam_write(hwaddr ptr);
-
-#endif
+++ /dev/null
-/*
- * ARM SMMU Support
- *
- * Copyright (C) 2015-2016 Broadcom Corporation
- * Copyright (c) 2017 Red Hat, Inc.
- * Written by Prem Mallappa, Eric Auger
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- */
-
-#ifndef HW_ARM_SMMU_COMMON_H
-#define HW_ARM_SMMU_COMMON_H
-
-#include "hw/sysbus.h"
-#include "hw/pci/pci.h"
-#include "qom/object.h"
-
-#define SMMU_PCI_BUS_MAX 256
-#define SMMU_PCI_DEVFN_MAX 256
-#define SMMU_PCI_DEVFN(sid) (sid & 0xFF)
-
-#define SMMU_MAX_VA_BITS 48
-
-/*
- * Page table walk error types
- */
-typedef enum {
- SMMU_PTW_ERR_NONE,
- SMMU_PTW_ERR_WALK_EABT, /* Translation walk external abort */
- SMMU_PTW_ERR_TRANSLATION, /* Translation fault */
- SMMU_PTW_ERR_ADDR_SIZE, /* Address Size fault */
- SMMU_PTW_ERR_ACCESS, /* Access fault */
- SMMU_PTW_ERR_PERMISSION, /* Permission fault */
-} SMMUPTWEventType;
-
-typedef struct SMMUPTWEventInfo {
- SMMUPTWEventType type;
- dma_addr_t addr; /* fetched address that induced an abort, if any */
-} SMMUPTWEventInfo;
-
-typedef struct SMMUTransTableInfo {
- bool disabled; /* is the translation table disabled? */
- uint64_t ttb; /* TT base address */
- uint8_t tsz; /* input range, ie. 2^(64 -tsz)*/
- uint8_t granule_sz; /* granule page shift */
- bool had; /* hierarchical attribute disable */
-} SMMUTransTableInfo;
-
-typedef struct SMMUTLBEntry {
- IOMMUTLBEntry entry;
- uint8_t level;
- uint8_t granule;
-} SMMUTLBEntry;
-
-/*
- * Generic structure populated by derived SMMU devices
- * after decoding the configuration information and used as
- * input to the page table walk
- */
-typedef struct SMMUTransCfg {
- int stage; /* translation stage */
- bool aa64; /* arch64 or aarch32 translation table */
- bool disabled; /* smmu is disabled */
- bool bypassed; /* translation is bypassed */
- bool aborted; /* translation is aborted */
- uint64_t ttb; /* TT base address */
- uint8_t oas; /* output address width */
- uint8_t tbi; /* Top Byte Ignore */
- uint16_t asid;
- SMMUTransTableInfo tt[2];
- uint32_t iotlb_hits; /* counts IOTLB hits for this asid */
- uint32_t iotlb_misses; /* counts IOTLB misses for this asid */
-} SMMUTransCfg;
-
-typedef struct SMMUDevice {
- void *smmu;
- PCIBus *bus;
- int devfn;
- IOMMUMemoryRegion iommu;
- AddressSpace as;
- uint32_t cfg_cache_hits;
- uint32_t cfg_cache_misses;
- QLIST_ENTRY(SMMUDevice) next;
-} SMMUDevice;
-
-typedef struct SMMUPciBus {
- PCIBus *bus;
- SMMUDevice *pbdev[]; /* Parent array is sparse, so dynamically alloc */
-} SMMUPciBus;
-
-typedef struct SMMUIOTLBKey {
- uint64_t iova;
- uint16_t asid;
- uint8_t tg;
- uint8_t level;
-} SMMUIOTLBKey;
-
-struct SMMUState {
- /* <private> */
- SysBusDevice dev;
- const char *mrtypename;
- MemoryRegion iomem;
-
- GHashTable *smmu_pcibus_by_busptr;
- GHashTable *configs; /* cache for configuration data */
- GHashTable *iotlb;
- SMMUPciBus *smmu_pcibus_by_bus_num[SMMU_PCI_BUS_MAX];
- PCIBus *pci_bus;
- QLIST_HEAD(, SMMUDevice) devices_with_notifiers;
- uint8_t bus_num;
- PCIBus *primary_bus;
-};
-
-struct SMMUBaseClass {
- /* <private> */
- SysBusDeviceClass parent_class;
-
- /*< public >*/
-
- DeviceRealize parent_realize;
-
-};
-
-#define TYPE_ARM_SMMU "arm-smmu"
-OBJECT_DECLARE_TYPE(SMMUState, SMMUBaseClass, ARM_SMMU)
-
-/* Return the SMMUPciBus handle associated to a PCI bus number */
-SMMUPciBus *smmu_find_smmu_pcibus(SMMUState *s, uint8_t bus_num);
-
-/* Return the stream ID of an SMMU device */
-static inline uint16_t smmu_get_sid(SMMUDevice *sdev)
-{
- return PCI_BUILD_BDF(pci_bus_num(sdev->bus), sdev->devfn);
-}
-
-/**
- * smmu_ptw - Perform the page table walk for a given iova / access flags
- * pair, according to @cfg translation config
- */
-int smmu_ptw(SMMUTransCfg *cfg, dma_addr_t iova, IOMMUAccessFlags perm,
- SMMUTLBEntry *tlbe, SMMUPTWEventInfo *info);
-
-/**
- * select_tt - compute which translation table shall be used according to
- * the input iova and translation config and return the TT specific info
- */
-SMMUTransTableInfo *select_tt(SMMUTransCfg *cfg, dma_addr_t iova);
-
-/* Return the iommu mr associated to @sid, or NULL if none */
-IOMMUMemoryRegion *smmu_iommu_mr(SMMUState *s, uint32_t sid);
-
-#define SMMU_IOTLB_MAX_SIZE 256
-
-SMMUTLBEntry *smmu_iotlb_lookup(SMMUState *bs, SMMUTransCfg *cfg,
- SMMUTransTableInfo *tt, hwaddr iova);
-void smmu_iotlb_insert(SMMUState *bs, SMMUTransCfg *cfg, SMMUTLBEntry *entry);
-SMMUIOTLBKey smmu_get_iotlb_key(uint16_t asid, uint64_t iova,
- uint8_t tg, uint8_t level);
-void smmu_iotlb_inv_all(SMMUState *s);
-void smmu_iotlb_inv_asid(SMMUState *s, uint16_t asid);
-void smmu_iotlb_inv_iova(SMMUState *s, int asid, dma_addr_t iova,
- uint8_t tg, uint64_t num_pages, uint8_t ttl);
-
-/* Unmap the range of all the notifiers registered to any IOMMU mr */
-void smmu_inv_notifiers_all(SMMUState *s);
-
-/* Unmap the range of all the notifiers registered to @mr */
-void smmu_inv_notifiers_mr(IOMMUMemoryRegion *mr);
-
-#endif /* HW_ARM_SMMU_COMMON_H */
+++ /dev/null
-/*
- * Copyright (C) 2014-2016 Broadcom Corporation
- * Copyright (c) 2017 Red Hat, Inc.
- * Written by Prem Mallappa, Eric Auger
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License along
- * with this program; if not, see <http://www.gnu.org/licenses/>.
- */
-
-#ifndef HW_ARM_SMMUV3_H
-#define HW_ARM_SMMUV3_H
-
-#include "hw/arm/smmu-common.h"
-#include "hw/registerfields.h"
-#include "qom/object.h"
-
-#define TYPE_SMMUV3_IOMMU_MEMORY_REGION "smmuv3-iommu-memory-region"
-
-typedef struct SMMUQueue {
- uint64_t base; /* base register */
- uint32_t prod;
- uint32_t cons;
- uint8_t entry_size;
- uint8_t log2size;
-} SMMUQueue;
-
-struct SMMUv3State {
- SMMUState smmu_state;
-
- uint32_t features;
- uint8_t sid_size;
- uint8_t sid_split;
-
- uint32_t idr[6];
- uint32_t iidr;
- uint32_t aidr;
- uint32_t cr[3];
- uint32_t cr0ack;
- uint32_t statusr;
- uint32_t irq_ctrl;
- uint32_t gerror;
- uint32_t gerrorn;
- uint64_t gerror_irq_cfg0;
- uint32_t gerror_irq_cfg1;
- uint32_t gerror_irq_cfg2;
- uint64_t strtab_base;
- uint32_t strtab_base_cfg;
- uint64_t eventq_irq_cfg0;
- uint32_t eventq_irq_cfg1;
- uint32_t eventq_irq_cfg2;
-
- SMMUQueue eventq, cmdq;
-
- qemu_irq irq[4];
- QemuMutex mutex;
-};
-
-typedef enum {
- SMMU_IRQ_EVTQ,
- SMMU_IRQ_PRIQ,
- SMMU_IRQ_CMD_SYNC,
- SMMU_IRQ_GERROR,
-} SMMUIrq;
-
-struct SMMUv3Class {
- /*< private >*/
- SMMUBaseClass smmu_base_class;
- /*< public >*/
-
- DeviceRealize parent_realize;
- DeviceReset parent_reset;
-};
-
-#define TYPE_ARM_SMMUV3 "arm-smmuv3"
-OBJECT_DECLARE_TYPE(SMMUv3State, SMMUv3Class, ARM_SMMUV3)
-
-#endif
+++ /dev/null
-/*
- * On-chip DMA controller framework.
- *
- * Copyright (C) 2008 Nokia Corporation
- * Written by Andrzej Zaborowski <andrew@openedhand.com>
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 or
- * (at your option) version 3 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License along
- * with this program; if not, see <http://www.gnu.org/licenses/>.
- */
-
-#ifndef HW_SOC_DMA_H
-#define HW_SOC_DMA_H
-
-#include "exec/hwaddr.h"
-
-struct soc_dma_s;
-struct soc_dma_ch_s;
-typedef void (*soc_dma_io_t)(void *opaque, uint8_t *buf, int len);
-typedef void (*soc_dma_transfer_t)(struct soc_dma_ch_s *ch);
-
-enum soc_dma_port_type {
- soc_dma_port_mem,
- soc_dma_port_fifo,
- soc_dma_port_other,
-};
-
-enum soc_dma_access_type {
- soc_dma_access_const,
- soc_dma_access_linear,
- soc_dma_access_other,
-};
-
-struct soc_dma_ch_s {
- /* Private */
- struct soc_dma_s *dma;
- int num;
- QEMUTimer *timer;
-
- /* Set by soc_dma.c */
- int enable;
- int update;
-
- /* This should be set by dma->setup_fn(). */
- int bytes;
- /* Initialised by the DMA module, call soc_dma_ch_update after writing. */
- enum soc_dma_access_type type[2];
- hwaddr vaddr[2]; /* Updated by .transfer_fn(). */
- /* Private */
- void *paddr[2];
- soc_dma_io_t io_fn[2];
- void *io_opaque[2];
-
- int running;
- soc_dma_transfer_t transfer_fn;
-
- /* Set and used by the DMA module. */
- void *opaque;
-};
-
-struct soc_dma_s {
- /* Following fields are set by the SoC DMA module and can be used
- * by anybody. */
- uint64_t drqbmp; /* Is zeroed by soc_dma_reset() */
- qemu_irq *drq;
- void *opaque;
- int64_t freq;
- soc_dma_transfer_t transfer_fn;
- soc_dma_transfer_t setup_fn;
- /* Set by soc_dma_init() for use by the DMA module. */
- struct soc_dma_ch_s *ch;
-};
-
-/* Call to activate or stop a DMA channel. */
-void soc_dma_set_request(struct soc_dma_ch_s *ch, int level);
-/* Call after every write to one of the following fields and before
- * calling soc_dma_set_request(ch, 1):
- * ch->type[0...1],
- * ch->vaddr[0...1],
- * ch->paddr[0...1],
- * or after a soc_dma_port_add_fifo() or soc_dma_port_add_mem(). */
-void soc_dma_ch_update(struct soc_dma_ch_s *ch);
-
-/* The SoC should call this when the DMA module is being reset. */
-void soc_dma_reset(struct soc_dma_s *s);
-struct soc_dma_s *soc_dma_init(int n);
-
-void soc_dma_port_add_fifo(struct soc_dma_s *dma, hwaddr virt_base,
- soc_dma_io_t fn, void *opaque, int out);
-void soc_dma_port_add_mem(struct soc_dma_s *dma, uint8_t *phys_base,
- hwaddr virt_base, size_t size);
-
-static inline void soc_dma_port_add_fifo_in(struct soc_dma_s *dma,
- hwaddr virt_base, soc_dma_io_t fn, void *opaque)
-{
- return soc_dma_port_add_fifo(dma, virt_base, fn, opaque, 0);
-}
-
-static inline void soc_dma_port_add_fifo_out(struct soc_dma_s *dma,
- hwaddr virt_base, soc_dma_io_t fn, void *opaque)
-{
- return soc_dma_port_add_fifo(dma, virt_base, fn, opaque, 1);
-}
-
-#endif
+++ /dev/null
-/*
- * STM32F205 SoC
- *
- * Copyright (c) 2014 Alistair Francis <alistair@alistair23.me>
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
- * furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
- * THE SOFTWARE.
- */
-
-#ifndef HW_ARM_STM32F205_SOC_H
-#define HW_ARM_STM32F205_SOC_H
-
-#include "hw/misc/stm32f2xx_syscfg.h"
-#include "hw/timer/stm32f2xx_timer.h"
-#include "hw/char/stm32f2xx_usart.h"
-#include "hw/adc/stm32f2xx_adc.h"
-#include "hw/or-irq.h"
-#include "hw/ssi/stm32f2xx_spi.h"
-#include "hw/arm/armv7m.h"
-#include "qom/object.h"
-
-#define TYPE_STM32F205_SOC "stm32f205-soc"
-OBJECT_DECLARE_SIMPLE_TYPE(STM32F205State, STM32F205_SOC)
-
-#define STM_NUM_USARTS 6
-#define STM_NUM_TIMERS 4
-#define STM_NUM_ADCS 3
-#define STM_NUM_SPIS 3
-
-#define FLASH_BASE_ADDRESS 0x08000000
-#define FLASH_SIZE (1024 * 1024)
-#define SRAM_BASE_ADDRESS 0x20000000
-#define SRAM_SIZE (128 * 1024)
-
-struct STM32F205State {
- /*< private >*/
- SysBusDevice parent_obj;
- /*< public >*/
-
- char *cpu_type;
-
- ARMv7MState armv7m;
-
- STM32F2XXSyscfgState syscfg;
- STM32F2XXUsartState usart[STM_NUM_USARTS];
- STM32F2XXTimerState timer[STM_NUM_TIMERS];
- STM32F2XXADCState adc[STM_NUM_ADCS];
- STM32F2XXSPIState spi[STM_NUM_SPIS];
-
- qemu_or_irq *adc_irqs;
-};
-
-#endif
+++ /dev/null
-/*
- * STM32F405 SoC
- *
- * Copyright (c) 2014 Alistair Francis <alistair@alistair23.me>
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
- * furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
- * THE SOFTWARE.
- */
-
-#ifndef HW_ARM_STM32F405_SOC_H
-#define HW_ARM_STM32F405_SOC_H
-
-#include "hw/misc/stm32f4xx_syscfg.h"
-#include "hw/timer/stm32f2xx_timer.h"
-#include "hw/char/stm32f2xx_usart.h"
-#include "hw/adc/stm32f2xx_adc.h"
-#include "hw/misc/stm32f4xx_exti.h"
-#include "hw/or-irq.h"
-#include "hw/ssi/stm32f2xx_spi.h"
-#include "hw/arm/armv7m.h"
-#include "qom/object.h"
-
-#define TYPE_STM32F405_SOC "stm32f405-soc"
-OBJECT_DECLARE_SIMPLE_TYPE(STM32F405State, STM32F405_SOC)
-
-#define STM_NUM_USARTS 7
-#define STM_NUM_TIMERS 4
-#define STM_NUM_ADCS 6
-#define STM_NUM_SPIS 6
-
-#define FLASH_BASE_ADDRESS 0x08000000
-#define FLASH_SIZE (1024 * 1024)
-#define SRAM_BASE_ADDRESS 0x20000000
-#define SRAM_SIZE (192 * 1024)
-
-struct STM32F405State {
- /*< private >*/
- SysBusDevice parent_obj;
- /*< public >*/
-
- char *cpu_type;
-
- ARMv7MState armv7m;
-
- STM32F4xxSyscfgState syscfg;
- STM32F4xxExtiState exti;
- STM32F2XXUsartState usart[STM_NUM_USARTS];
- STM32F2XXTimerState timer[STM_NUM_TIMERS];
- qemu_or_irq adc_irqs;
- STM32F2XXADCState adc[STM_NUM_ADCS];
- STM32F2XXSPIState spi[STM_NUM_SPIS];
-
- MemoryRegion sram;
- MemoryRegion flash;
- MemoryRegion flash_alias;
-};
-
-#endif
+++ /dev/null
-/*
- * Dynamic sysbus device tree node generation API
- *
- * Copyright Linaro Limited, 2014
- *
- * Authors:
- * Alex Graf <agraf@suse.de>
- * Eric Auger <eric.auger@linaro.org>
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms and conditions of the GNU General Public License,
- * version 2 or later, as published by the Free Software Foundation.
- *
- * This program is distributed in the hope it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License along with
- * this program. If not, see <http://www.gnu.org/licenses/>.
- *
- */
-
-#ifndef HW_ARM_SYSBUS_FDT_H
-#define HW_ARM_SYSBUS_FDT_H
-
-#include "exec/hwaddr.h"
-
-/**
- * platform_bus_add_all_fdt_nodes - create all the platform bus nodes
- *
- * builds the parent platform bus node and all the nodes of dynamic
- * sysbus devices attached to it.
- */
-void platform_bus_add_all_fdt_nodes(void *fdt, const char *intc, hwaddr addr,
- hwaddr bus_size, int irq_start);
-#endif
+++ /dev/null
-/*
- *
- * Copyright (c) 2015 Linaro Limited
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms and conditions of the GNU General Public License,
- * version 2 or later, as published by the Free Software Foundation.
- *
- * This program is distributed in the hope it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License along with
- * this program. If not, see <http://www.gnu.org/licenses/>.
- *
- * Emulate a virtual board which works by passing Linux all the information
- * it needs about what devices are present via the device tree.
- * There are some restrictions about what we can do here:
- * + we can only present devices whose Linux drivers will work based
- * purely on the device tree with no platform data at all
- * + we want to present a very stripped-down minimalist platform,
- * both because this reduces the security attack surface from the guest
- * and also because it reduces our exposure to being broken when
- * the kernel updates its device tree bindings and requires further
- * information in a device binding that we aren't providing.
- * This is essentially the same approach kvmtool uses.
- */
-
-#ifndef QEMU_ARM_VIRT_H
-#define QEMU_ARM_VIRT_H
-
-#include "exec/hwaddr.h"
-#include "qemu/notify.h"
-#include "hw/boards.h"
-#include "hw/arm/boot.h"
-#include "hw/block/flash.h"
-#include "sysemu/kvm.h"
-#include "hw/intc/arm_gicv3_common.h"
-#include "qom/object.h"
-
-#define NUM_GICV2M_SPIS 64
-#define NUM_VIRTIO_TRANSPORTS 32
-#define NUM_SMMU_IRQS 4
-
-#define ARCH_GIC_MAINT_IRQ 9
-
-#define ARCH_TIMER_VIRT_IRQ 11
-#define ARCH_TIMER_S_EL1_IRQ 13
-#define ARCH_TIMER_NS_EL1_IRQ 14
-#define ARCH_TIMER_NS_EL2_IRQ 10
-
-#define VIRTUAL_PMU_IRQ 7
-
-#define PPI(irq) ((irq) + 16)
-
-/* See Linux kernel arch/arm64/include/asm/pvclock-abi.h */
-#define PVTIME_SIZE_PER_CPU 64
-
-enum {
- VIRT_FLASH,
- VIRT_MEM,
- VIRT_CPUPERIPHS,
- VIRT_GIC_DIST,
- VIRT_GIC_CPU,
- VIRT_GIC_V2M,
- VIRT_GIC_HYP,
- VIRT_GIC_VCPU,
- VIRT_GIC_ITS,
- VIRT_GIC_REDIST,
- VIRT_SMMU,
- VIRT_UART,
- VIRT_MMIO,
- VIRT_RTC,
- VIRT_FW_CFG,
- VIRT_PCIE,
- VIRT_PCIE_MMIO,
- VIRT_PCIE_PIO,
- VIRT_PCIE_ECAM,
- VIRT_PLATFORM_BUS,
- VIRT_GPIO,
- VIRT_SECURE_UART,
- VIRT_SECURE_MEM,
- VIRT_PCDIMM_ACPI,
- VIRT_ACPI_GED,
- VIRT_NVDIMM_ACPI,
- VIRT_PVTIME,
- VIRT_LOWMEMMAP_LAST,
-};
-
-/* indices of IO regions located after the RAM */
-enum {
- VIRT_HIGH_GIC_REDIST2 = VIRT_LOWMEMMAP_LAST,
- VIRT_HIGH_PCIE_ECAM,
- VIRT_HIGH_PCIE_MMIO,
-};
-
-typedef enum VirtIOMMUType {
- VIRT_IOMMU_NONE,
- VIRT_IOMMU_SMMUV3,
- VIRT_IOMMU_VIRTIO,
-} VirtIOMMUType;
-
-typedef enum VirtMSIControllerType {
- VIRT_MSI_CTRL_NONE,
- VIRT_MSI_CTRL_GICV2M,
- VIRT_MSI_CTRL_ITS,
-} VirtMSIControllerType;
-
-typedef enum VirtGICType {
- VIRT_GIC_VERSION_MAX,
- VIRT_GIC_VERSION_HOST,
- VIRT_GIC_VERSION_2,
- VIRT_GIC_VERSION_3,
- VIRT_GIC_VERSION_NOSEL,
-} VirtGICType;
-
-struct VirtMachineClass {
- MachineClass parent;
- bool disallow_affinity_adjustment;
- bool no_its;
- bool no_pmu;
- bool claim_edge_triggered_timers;
- bool smbios_old_sys_ver;
- bool no_highmem_ecam;
- bool no_ged; /* Machines < 4.2 has no support for ACPI GED device */
- bool kvm_no_adjvtime;
- bool no_kvm_steal_time;
- bool acpi_expose_flash;
-};
-
-struct VirtMachineState {
- MachineState parent;
- Notifier machine_done;
- DeviceState *platform_bus_dev;
- FWCfgState *fw_cfg;
- PFlashCFI01 *flash[2];
- bool secure;
- bool highmem;
- bool highmem_ecam;
- bool its;
- bool virt;
- bool ras;
- bool mte;
- OnOffAuto acpi;
- VirtGICType gic_version;
- VirtIOMMUType iommu;
- VirtMSIControllerType msi_controller;
- uint16_t virtio_iommu_bdf;
- struct arm_boot_info bootinfo;
- MemMapEntry *memmap;
- char *pciehb_nodename;
- const int *irqmap;
- int smp_cpus;
- void *fdt;
- int fdt_size;
- uint32_t clock_phandle;
- uint32_t gic_phandle;
- uint32_t msi_phandle;
- uint32_t iommu_phandle;
- int psci_conduit;
- hwaddr highest_gpa;
- DeviceState *gic;
- DeviceState *acpi_dev;
- Notifier powerdown_notifier;
-};
-
-#define VIRT_ECAM_ID(high) (high ? VIRT_HIGH_PCIE_ECAM : VIRT_PCIE_ECAM)
-
-#define TYPE_VIRT_MACHINE MACHINE_TYPE_NAME("virt")
-OBJECT_DECLARE_TYPE(VirtMachineState, VirtMachineClass, VIRT_MACHINE)
-
-void virt_acpi_setup(VirtMachineState *vms);
-bool virt_is_acpi_enabled(VirtMachineState *vms);
-
-/* Return the number of used redistributor regions */
-static inline int virt_gicv3_redist_region_count(VirtMachineState *vms)
-{
- uint32_t redist0_capacity =
- vms->memmap[VIRT_GIC_REDIST].size / GICV3_REDIST_SIZE;
-
- assert(vms->gic_version == VIRT_GIC_VERSION_3);
-
- return vms->smp_cpus > redist0_capacity ? 2 : 1;
-}
-
-#endif /* QEMU_ARM_VIRT_H */
+++ /dev/null
-/*
- * Model of the Xilinx Versal
- *
- * Copyright (c) 2018 Xilinx Inc.
- * Written by Edgar E. Iglesias
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 or
- * (at your option) any later version.
- */
-
-#ifndef XLNX_VERSAL_H
-#define XLNX_VERSAL_H
-
-#include "hw/sysbus.h"
-#include "hw/arm/boot.h"
-#include "hw/sd/sdhci.h"
-#include "hw/intc/arm_gicv3.h"
-#include "hw/char/pl011.h"
-#include "hw/dma/xlnx-zdma.h"
-#include "hw/net/cadence_gem.h"
-#include "hw/rtc/xlnx-zynqmp-rtc.h"
-#include "qom/object.h"
-
-#define TYPE_XLNX_VERSAL "xlnx-versal"
-OBJECT_DECLARE_SIMPLE_TYPE(Versal, XLNX_VERSAL)
-
-#define XLNX_VERSAL_NR_ACPUS 2
-#define XLNX_VERSAL_NR_UARTS 2
-#define XLNX_VERSAL_NR_GEMS 2
-#define XLNX_VERSAL_NR_ADMAS 8
-#define XLNX_VERSAL_NR_SDS 2
-#define XLNX_VERSAL_NR_IRQS 192
-
-struct Versal {
- /*< private >*/
- SysBusDevice parent_obj;
-
- /*< public >*/
- struct {
- struct {
- MemoryRegion mr;
- ARMCPU cpu[XLNX_VERSAL_NR_ACPUS];
- GICv3State gic;
- } apu;
- } fpd;
-
- MemoryRegion mr_ps;
-
- struct {
- /* 4 ranges to access DDR. */
- MemoryRegion mr_ddr_ranges[4];
- } noc;
-
- struct {
- MemoryRegion mr_ocm;
-
- struct {
- PL011State uart[XLNX_VERSAL_NR_UARTS];
- CadenceGEMState gem[XLNX_VERSAL_NR_GEMS];
- XlnxZDMA adma[XLNX_VERSAL_NR_ADMAS];
- } iou;
- } lpd;
-
- /* The Platform Management Controller subsystem. */
- struct {
- struct {
- SDHCIState sd[XLNX_VERSAL_NR_SDS];
- } iou;
-
- XlnxZynqMPRTC rtc;
- } pmc;
-
- struct {
- MemoryRegion *mr_ddr;
- uint32_t psci_conduit;
- } cfg;
-};
-
-/* Memory-map and IRQ definitions. Copied a subset from
- * auto-generated files. */
-
-#define VERSAL_GIC_MAINT_IRQ 9
-#define VERSAL_TIMER_VIRT_IRQ 11
-#define VERSAL_TIMER_S_EL1_IRQ 13
-#define VERSAL_TIMER_NS_EL1_IRQ 14
-#define VERSAL_TIMER_NS_EL2_IRQ 10
-
-#define VERSAL_UART0_IRQ_0 18
-#define VERSAL_UART1_IRQ_0 19
-#define VERSAL_GEM0_IRQ_0 56
-#define VERSAL_GEM0_WAKE_IRQ_0 57
-#define VERSAL_GEM1_IRQ_0 58
-#define VERSAL_GEM1_WAKE_IRQ_0 59
-#define VERSAL_ADMA_IRQ_0 60
-#define VERSAL_RTC_APB_ERR_IRQ 121
-#define VERSAL_SD0_IRQ_0 126
-#define VERSAL_RTC_ALARM_IRQ 142
-#define VERSAL_RTC_SECONDS_IRQ 143
-
-/* Architecturally reserved IRQs suitable for virtualization. */
-#define VERSAL_RSVD_IRQ_FIRST 111
-#define VERSAL_RSVD_IRQ_LAST 118
-
-#define MM_TOP_RSVD 0xa0000000U
-#define MM_TOP_RSVD_SIZE 0x4000000
-#define MM_GIC_APU_DIST_MAIN 0xf9000000U
-#define MM_GIC_APU_DIST_MAIN_SIZE 0x10000
-#define MM_GIC_APU_REDIST_0 0xf9080000U
-#define MM_GIC_APU_REDIST_0_SIZE 0x80000
-
-#define MM_UART0 0xff000000U
-#define MM_UART0_SIZE 0x10000
-#define MM_UART1 0xff010000U
-#define MM_UART1_SIZE 0x10000
-
-#define MM_GEM0 0xff0c0000U
-#define MM_GEM0_SIZE 0x10000
-#define MM_GEM1 0xff0d0000U
-#define MM_GEM1_SIZE 0x10000
-
-#define MM_ADMA_CH0 0xffa80000U
-#define MM_ADMA_CH0_SIZE 0x10000
-
-#define MM_OCM 0xfffc0000U
-#define MM_OCM_SIZE 0x40000
-
-#define MM_TOP_DDR 0x0
-#define MM_TOP_DDR_SIZE 0x80000000U
-#define MM_TOP_DDR_2 0x800000000ULL
-#define MM_TOP_DDR_2_SIZE 0x800000000ULL
-#define MM_TOP_DDR_3 0xc000000000ULL
-#define MM_TOP_DDR_3_SIZE 0x4000000000ULL
-#define MM_TOP_DDR_4 0x10000000000ULL
-#define MM_TOP_DDR_4_SIZE 0xb780000000ULL
-
-#define MM_PSM_START 0xffc80000U
-#define MM_PSM_END 0xffcf0000U
-
-#define MM_CRL 0xff5e0000U
-#define MM_CRL_SIZE 0x300000
-#define MM_IOU_SCNTR 0xff130000U
-#define MM_IOU_SCNTR_SIZE 0x10000
-#define MM_IOU_SCNTRS 0xff140000U
-#define MM_IOU_SCNTRS_SIZE 0x10000
-#define MM_FPD_CRF 0xfd1a0000U
-#define MM_FPD_CRF_SIZE 0x140000
-
-#define MM_PMC_SD0 0xf1040000U
-#define MM_PMC_SD0_SIZE 0x10000
-#define MM_PMC_CRP 0xf1260000U
-#define MM_PMC_CRP_SIZE 0x10000
-#define MM_PMC_RTC 0xf12a0000
-#define MM_PMC_RTC_SIZE 0x10000
-#endif
+++ /dev/null
-/*
- * Xilinx Zynq MPSoC emulation
- *
- * Copyright (C) 2015 Xilinx Inc
- * Written by Peter Crosthwaite <peter.crosthwaite@xilinx.com>
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License as published by the
- * Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
- * for more details.
- */
-
-#ifndef XLNX_ZYNQMP_H
-#define XLNX_ZYNQMP_H
-
-#include "hw/arm/boot.h"
-#include "hw/intc/arm_gic.h"
-#include "hw/net/cadence_gem.h"
-#include "hw/char/cadence_uart.h"
-#include "hw/ide/ahci.h"
-#include "hw/sd/sdhci.h"
-#include "hw/ssi/xilinx_spips.h"
-#include "hw/dma/xlnx_dpdma.h"
-#include "hw/dma/xlnx-zdma.h"
-#include "hw/display/xlnx_dp.h"
-#include "hw/intc/xlnx-zynqmp-ipi.h"
-#include "hw/rtc/xlnx-zynqmp-rtc.h"
-#include "hw/cpu/cluster.h"
-#include "target/arm/cpu.h"
-#include "qom/object.h"
-
-#define TYPE_XLNX_ZYNQMP "xlnx,zynqmp"
-OBJECT_DECLARE_SIMPLE_TYPE(XlnxZynqMPState, XLNX_ZYNQMP)
-
-#define XLNX_ZYNQMP_NUM_APU_CPUS 4
-#define XLNX_ZYNQMP_NUM_RPU_CPUS 2
-#define XLNX_ZYNQMP_NUM_GEMS 4
-#define XLNX_ZYNQMP_NUM_UARTS 2
-#define XLNX_ZYNQMP_NUM_SDHCI 2
-#define XLNX_ZYNQMP_NUM_SPIS 2
-#define XLNX_ZYNQMP_NUM_GDMA_CH 8
-#define XLNX_ZYNQMP_NUM_ADMA_CH 8
-
-#define XLNX_ZYNQMP_NUM_QSPI_BUS 2
-#define XLNX_ZYNQMP_NUM_QSPI_BUS_CS 2
-#define XLNX_ZYNQMP_NUM_QSPI_FLASH 4
-
-#define XLNX_ZYNQMP_NUM_OCM_BANKS 4
-#define XLNX_ZYNQMP_OCM_RAM_0_ADDRESS 0xFFFC0000
-#define XLNX_ZYNQMP_OCM_RAM_SIZE 0x10000
-
-#define XLNX_ZYNQMP_GIC_REGIONS 6
-
-/* ZynqMP maps the ARM GIC regions (GICC, GICD ...) at consecutive 64k offsets
- * and under-decodes the 64k region. This mirrors the 4k regions to every 4k
- * aligned address in the 64k region. To implement each GIC region needs a
- * number of memory region aliases.
- */
-
-#define XLNX_ZYNQMP_GIC_REGION_SIZE 0x1000
-#define XLNX_ZYNQMP_GIC_ALIASES (0x10000 / XLNX_ZYNQMP_GIC_REGION_SIZE)
-
-#define XLNX_ZYNQMP_MAX_LOW_RAM_SIZE 0x80000000ull
-
-#define XLNX_ZYNQMP_MAX_HIGH_RAM_SIZE 0x800000000ull
-#define XLNX_ZYNQMP_HIGH_RAM_START 0x800000000ull
-
-#define XLNX_ZYNQMP_MAX_RAM_SIZE (XLNX_ZYNQMP_MAX_LOW_RAM_SIZE + \
- XLNX_ZYNQMP_MAX_HIGH_RAM_SIZE)
-
-struct XlnxZynqMPState {
- /*< private >*/
- DeviceState parent_obj;
-
- /*< public >*/
- CPUClusterState apu_cluster;
- CPUClusterState rpu_cluster;
- ARMCPU apu_cpu[XLNX_ZYNQMP_NUM_APU_CPUS];
- ARMCPU rpu_cpu[XLNX_ZYNQMP_NUM_RPU_CPUS];
- GICState gic;
- MemoryRegion gic_mr[XLNX_ZYNQMP_GIC_REGIONS][XLNX_ZYNQMP_GIC_ALIASES];
-
- MemoryRegion ocm_ram[XLNX_ZYNQMP_NUM_OCM_BANKS];
-
- MemoryRegion *ddr_ram;
- MemoryRegion ddr_ram_low, ddr_ram_high;
-
- CadenceGEMState gem[XLNX_ZYNQMP_NUM_GEMS];
- CadenceUARTState uart[XLNX_ZYNQMP_NUM_UARTS];
- SysbusAHCIState sata;
- SDHCIState sdhci[XLNX_ZYNQMP_NUM_SDHCI];
- XilinxSPIPS spi[XLNX_ZYNQMP_NUM_SPIS];
- XlnxZynqMPQSPIPS qspi;
- XlnxDPState dp;
- XlnxDPDMAState dpdma;
- XlnxZynqMPIPI ipi;
- XlnxZynqMPRTC rtc;
- XlnxZDMA gdma[XLNX_ZYNQMP_NUM_GDMA_CH];
- XlnxZDMA adma[XLNX_ZYNQMP_NUM_ADMA_CH];
-
- char *boot_cpu;
- ARMCPU *boot_cpu_ptr;
-
- /* Has the ARM Security extensions? */
- bool secure;
- /* Has the ARM Virtualization extensions? */
- bool virt;
- /* Has the RPU subsystem? */
- bool has_rpu;
-};
-
-#endif
+++ /dev/null
-/*
- * QEMU PC speaker emulation
- *
- * Copyright (c) 2006 Joachim Henke
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
- * furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
- * THE SOFTWARE.
- */
-
-#ifndef HW_PCSPK_H
-#define HW_PCSPK_H
-
-#include "hw/isa/isa.h"
-#include "hw/qdev-properties.h"
-#include "qapi/error.h"
-
-#define TYPE_PC_SPEAKER "isa-pcspk"
-
-static inline void pcspk_init(ISADevice *isadev, ISABus *bus, ISADevice *pit)
-{
- object_property_set_link(OBJECT(isadev), "pit", OBJECT(pit), NULL);
- isa_realize_and_unref(isadev, bus, &error_fatal);
-}
-
-#endif /* HW_PCSPK_H */
+++ /dev/null
-#ifndef HW_SOUNDHW_H
-#define HW_SOUNDHW_H
-
-void isa_register_soundhw(const char *name, const char *descr,
- int (*init_isa)(ISABus *bus));
-
-void pci_register_soundhw(const char *name, const char *descr,
- int (*init_pci)(PCIBus *bus));
-void deprecated_register_soundhw(const char *name, const char *descr,
- int isa, const char *typename);
-
-void soundhw_init(void);
-void select_soundhw(const char *optarg);
-
-#endif
+++ /dev/null
-/*
- * This program is free software; you can redistribute it and/or modify it
- * under the terms and conditions of the GNU General Public License,
- * version 2 or later, as published by the Free Software Foundation.
- *
- * This program is distributed in the hope it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License along with
- * this program. If not, see <http://www.gnu.org/licenses/>.
- */
-#ifndef HW_DAC_WM8750_H
-#define HW_DAC_WM8750_H
-
-
-#define TYPE_WM8750 "wm8750"
-#define TYPE_MV88W8618_AUDIO "mv88w8618_audio"
-
-typedef void data_req_cb(void *opaque, int free_out, int free_in);
-
-void wm8750_data_req_set(DeviceState *dev, data_req_cb *data_req, void *opaque);
-void wm8750_dac_dat(void *opaque, uint32_t sample);
-uint32_t wm8750_adc_dat(void *opaque);
-void *wm8750_dac_buffer(void *opaque, int samples);
-void wm8750_dac_commit(void *opaque);
-void wm8750_set_bclk_in(void *opaque, int new_hz);
-
-#endif
+++ /dev/null
-/*
- * AVR USART
- *
- * Copyright (c) 2018 University of Kent
- * Author: Sarah Harris
- *
- * This library is free software; you can redistribute it and/or
- * modify it under the terms of the GNU Lesser General Public
- * License as published by the Free Software Foundation; either
- * version 2.1 of the License, or (at your option) any later version.
- *
- * This library is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
- * Lesser General Public License for more details.
- *
- * You should have received a copy of the GNU Lesser General Public
- * License along with this library; if not, see
- * <http://www.gnu.org/licenses/lgpl-2.1.html>
- */
-
-#ifndef HW_CHAR_AVR_USART_H
-#define HW_CHAR_AVR_USART_H
-
-#include "hw/sysbus.h"
-#include "chardev/char-fe.h"
-#include "hw/hw.h"
-#include "qom/object.h"
-
-/* Offsets of registers. */
-#define USART_DR 0x06
-#define USART_CSRA 0x00
-#define USART_CSRB 0x01
-#define USART_CSRC 0x02
-#define USART_BRRH 0x05
-#define USART_BRRL 0x04
-
-/* Relevant bits in regiters. */
-#define USART_CSRA_RXC (1 << 7)
-#define USART_CSRA_TXC (1 << 6)
-#define USART_CSRA_DRE (1 << 5)
-#define USART_CSRA_MPCM (1 << 0)
-
-#define USART_CSRB_RXCIE (1 << 7)
-#define USART_CSRB_TXCIE (1 << 6)
-#define USART_CSRB_DREIE (1 << 5)
-#define USART_CSRB_RXEN (1 << 4)
-#define USART_CSRB_TXEN (1 << 3)
-#define USART_CSRB_CSZ2 (1 << 2)
-#define USART_CSRB_RXB8 (1 << 1)
-#define USART_CSRB_TXB8 (1 << 0)
-
-#define USART_CSRC_MSEL1 (1 << 7)
-#define USART_CSRC_MSEL0 (1 << 6)
-#define USART_CSRC_PM1 (1 << 5)
-#define USART_CSRC_PM0 (1 << 4)
-#define USART_CSRC_CSZ1 (1 << 2)
-#define USART_CSRC_CSZ0 (1 << 1)
-
-#define TYPE_AVR_USART "avr-usart"
-OBJECT_DECLARE_SIMPLE_TYPE(AVRUsartState, AVR_USART)
-
-struct AVRUsartState {
- /* <private> */
- SysBusDevice parent_obj;
-
- /* <public> */
- MemoryRegion mmio;
-
- CharBackend chr;
-
- bool enabled;
-
- uint8_t data;
- bool data_valid;
- uint8_t char_mask;
- /* Control and Status Registers */
- uint8_t csra;
- uint8_t csrb;
- uint8_t csrc;
- /* Baud Rate Registers (low/high byte) */
- uint8_t brrh;
- uint8_t brrl;
-
- /* Receive Complete */
- qemu_irq rxc_irq;
- /* Transmit Complete */
- qemu_irq txc_irq;
- /* Data Register Empty */
- qemu_irq dre_irq;
-};
-
-#endif /* HW_CHAR_AVR_USART_H */
+++ /dev/null
-/*
- * Rasperry Pi 2 emulation and refactoring Copyright (c) 2015, Microsoft
- * Written by Andrew Baumann
- *
- * This work is licensed under the terms of the GNU GPL, version 2 or later.
- * See the COPYING file in the top-level directory.
- */
-
-#ifndef BCM2835_AUX_H
-#define BCM2835_AUX_H
-
-#include "hw/sysbus.h"
-#include "chardev/char-fe.h"
-#include "qom/object.h"
-
-#define TYPE_BCM2835_AUX "bcm2835-aux"
-OBJECT_DECLARE_SIMPLE_TYPE(BCM2835AuxState, BCM2835_AUX)
-
-#define BCM2835_AUX_RX_FIFO_LEN 8
-
-struct BCM2835AuxState {
- /*< private >*/
- SysBusDevice parent_obj;
- /*< public >*/
-
- MemoryRegion iomem;
- CharBackend chr;
- qemu_irq irq;
-
- uint8_t read_fifo[BCM2835_AUX_RX_FIFO_LEN];
- uint8_t read_pos, read_count;
- uint8_t ier, iir;
-};
-
-#endif
+++ /dev/null
-/*
- * Device model for Cadence UART
- *
- * Copyright (c) 2010 Xilinx Inc.
- * Copyright (c) 2012 Peter A.G. Crosthwaite (peter.crosthwaite@petalogix.com)
- * Copyright (c) 2012 PetaLogix Pty Ltd.
- * Written by Haibing Ma
- * M.Habib
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version
- * 2 of the License, or (at your option) any later version.
- *
- * You should have received a copy of the GNU General Public License along
- * with this program; if not, see <http://www.gnu.org/licenses/>.
- */
-
-#ifndef CADENCE_UART_H
-#define CADENCE_UART_H
-
-#include "hw/qdev-properties.h"
-#include "hw/sysbus.h"
-#include "chardev/char-fe.h"
-#include "qapi/error.h"
-#include "qemu/timer.h"
-#include "qom/object.h"
-
-#define CADENCE_UART_RX_FIFO_SIZE 16
-#define CADENCE_UART_TX_FIFO_SIZE 16
-
-#define CADENCE_UART_R_MAX (0x48/4)
-
-#define TYPE_CADENCE_UART "cadence_uart"
-OBJECT_DECLARE_SIMPLE_TYPE(CadenceUARTState, CADENCE_UART)
-
-struct CadenceUARTState {
- /*< private >*/
- SysBusDevice parent_obj;
-
- /*< public >*/
- MemoryRegion iomem;
- uint32_t r[CADENCE_UART_R_MAX];
- uint8_t rx_fifo[CADENCE_UART_RX_FIFO_SIZE];
- uint8_t tx_fifo[CADENCE_UART_TX_FIFO_SIZE];
- uint32_t rx_wpos;
- uint32_t rx_count;
- uint32_t tx_count;
- uint64_t char_tx_time;
- CharBackend chr;
- qemu_irq irq;
- QEMUTimer *fifo_trigger_handle;
- Clock *refclk;
-};
-
-#endif
+++ /dev/null
-/*
- * ARM CMSDK APB UART emulation
- *
- * Copyright (c) 2017 Linaro Limited
- * Written by Peter Maydell
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 or
- * (at your option) any later version.
- */
-
-#ifndef CMSDK_APB_UART_H
-#define CMSDK_APB_UART_H
-
-#include "hw/qdev-properties.h"
-#include "hw/sysbus.h"
-#include "chardev/char-fe.h"
-#include "qom/object.h"
-
-#define TYPE_CMSDK_APB_UART "cmsdk-apb-uart"
-OBJECT_DECLARE_SIMPLE_TYPE(CMSDKAPBUART, CMSDK_APB_UART)
-
-struct CMSDKAPBUART {
- /*< private >*/
- SysBusDevice parent_obj;
-
- /*< public >*/
- MemoryRegion iomem;
- CharBackend chr;
- qemu_irq txint;
- qemu_irq rxint;
- qemu_irq txovrint;
- qemu_irq rxovrint;
- qemu_irq uartint;
- guint watch_tag;
- uint32_t pclk_frq;
-
- uint32_t state;
- uint32_t ctrl;
- uint32_t intstatus;
- uint32_t bauddiv;
- /* This UART has no FIFO, only a 1-character buffer for each of Tx and Rx */
- uint8_t txbuf;
- uint8_t rxbuf;
-};
-
-/**
- * cmsdk_apb_uart_create - convenience function to create TYPE_CMSDK_APB_UART
- * @addr: location in system memory to map registers
- * @chr: Chardev backend to connect UART to, or NULL if no backend
- * @pclk_frq: frequency in Hz of the PCLK clock (used for calculating baud rate)
- */
-static inline DeviceState *cmsdk_apb_uart_create(hwaddr addr,
- qemu_irq txint,
- qemu_irq rxint,
- qemu_irq txovrint,
- qemu_irq rxovrint,
- qemu_irq uartint,
- Chardev *chr,
- uint32_t pclk_frq)
-{
- DeviceState *dev;
- SysBusDevice *s;
-
- dev = qdev_new(TYPE_CMSDK_APB_UART);
- s = SYS_BUS_DEVICE(dev);
- qdev_prop_set_chr(dev, "chardev", chr);
- qdev_prop_set_uint32(dev, "pclk-frq", pclk_frq);
- sysbus_realize_and_unref(s, &error_fatal);
- sysbus_mmio_map(s, 0, addr);
- sysbus_connect_irq(s, 0, txint);
- sysbus_connect_irq(s, 1, rxint);
- sysbus_connect_irq(s, 2, txovrint);
- sysbus_connect_irq(s, 3, rxovrint);
- sysbus_connect_irq(s, 4, uartint);
- return dev;
-}
-
-#endif
+++ /dev/null
-/*
- * Canon DIGIC UART block declarations.
- *
- * Copyright (C) 2013 Antony Pavlov <antonynpavlov@gmail.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- */
-
-#ifndef HW_CHAR_DIGIC_UART_H
-#define HW_CHAR_DIGIC_UART_H
-
-#include "hw/sysbus.h"
-#include "chardev/char-fe.h"
-#include "qom/object.h"
-
-#define TYPE_DIGIC_UART "digic-uart"
-OBJECT_DECLARE_SIMPLE_TYPE(DigicUartState, DIGIC_UART)
-
-enum {
- R_TX = 0x00,
- R_RX,
- R_ST = (0x14 >> 2),
- R_MAX
-};
-
-struct DigicUartState {
- /*< private >*/
- SysBusDevice parent_obj;
- /*< public >*/
-
- MemoryRegion regs_region;
- CharBackend chr;
-
- uint32_t reg_rx;
- uint32_t reg_st;
-};
-
-#endif /* HW_CHAR_DIGIC_UART_H */
+++ /dev/null
-#ifndef HW_ESCC_H
-#define HW_ESCC_H
-
-#include "chardev/char-fe.h"
-#include "chardev/char-serial.h"
-#include "hw/sysbus.h"
-#include "ui/input.h"
-#include "qom/object.h"
-
-/* escc.c */
-#define TYPE_ESCC "escc"
-#define ESCC_SIZE 4
-
-OBJECT_DECLARE_SIMPLE_TYPE(ESCCState, ESCC)
-
-typedef enum {
- escc_chn_a, escc_chn_b,
-} ESCCChnID;
-
-typedef enum {
- escc_serial, escc_kbd, escc_mouse,
-} ESCCChnType;
-
-#define ESCC_SERIO_QUEUE_SIZE 256
-
-typedef struct {
- uint8_t data[ESCC_SERIO_QUEUE_SIZE];
- int rptr, wptr, count;
-} ESCCSERIOQueue;
-
-#define ESCC_SERIAL_REGS 16
-typedef struct ESCCChannelState {
- qemu_irq irq;
- uint32_t rxint, txint, rxint_under_svc, txint_under_svc;
- struct ESCCChannelState *otherchn;
- uint32_t reg;
- uint8_t wregs[ESCC_SERIAL_REGS], rregs[ESCC_SERIAL_REGS];
- ESCCSERIOQueue queue;
- CharBackend chr;
- int e0_mode, led_mode, caps_lock_mode, num_lock_mode;
- int disabled;
- int clock;
- uint32_t vmstate_dummy;
- ESCCChnID chn; /* this channel, A (base+4) or B (base+0) */
- ESCCChnType type;
- uint8_t rx, tx;
- QemuInputHandlerState *hs;
-} ESCCChannelState;
-
-struct ESCCState {
- SysBusDevice parent_obj;
-
- struct ESCCChannelState chn[2];
- uint32_t it_shift;
- bool bit_swap;
- MemoryRegion mmio;
- uint32_t disabled;
- uint32_t frequency;
-};
-
-#endif
+++ /dev/null
-/*
- * QEMU lowRISC Ibex UART device
- *
- * Copyright (c) 2020 Western Digital
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
- * furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
- * THE SOFTWARE.
- */
-
-#ifndef HW_IBEX_UART_H
-#define HW_IBEX_UART_H
-
-#include "hw/sysbus.h"
-#include "hw/registerfields.h"
-#include "chardev/char-fe.h"
-#include "qemu/timer.h"
-#include "qom/object.h"
-
-REG32(INTR_STATE, 0x00)
- FIELD(INTR_STATE, TX_WATERMARK, 0, 1)
- FIELD(INTR_STATE, RX_WATERMARK, 1, 1)
- FIELD(INTR_STATE, TX_EMPTY, 2, 1)
- FIELD(INTR_STATE, RX_OVERFLOW, 3, 1)
-REG32(INTR_ENABLE, 0x04)
-REG32(INTR_TEST, 0x08)
-REG32(CTRL, 0x0C)
- FIELD(CTRL, TX_ENABLE, 0, 1)
- FIELD(CTRL, RX_ENABLE, 1, 1)
- FIELD(CTRL, NF, 2, 1)
- FIELD(CTRL, SLPBK, 4, 1)
- FIELD(CTRL, LLPBK, 5, 1)
- FIELD(CTRL, PARITY_EN, 6, 1)
- FIELD(CTRL, PARITY_ODD, 7, 1)
- FIELD(CTRL, RXBLVL, 8, 2)
- FIELD(CTRL, NCO, 16, 16)
-REG32(STATUS, 0x10)
- FIELD(STATUS, TXFULL, 0, 1)
- FIELD(STATUS, RXFULL, 1, 1)
- FIELD(STATUS, TXEMPTY, 2, 1)
- FIELD(STATUS, RXIDLE, 4, 1)
- FIELD(STATUS, RXEMPTY, 5, 1)
-REG32(RDATA, 0x14)
-REG32(WDATA, 0x18)
-REG32(FIFO_CTRL, 0x1c)
- FIELD(FIFO_CTRL, RXRST, 0, 1)
- FIELD(FIFO_CTRL, TXRST, 1, 1)
- FIELD(FIFO_CTRL, RXILVL, 2, 3)
- FIELD(FIFO_CTRL, TXILVL, 5, 2)
-REG32(FIFO_STATUS, 0x20)
-REG32(OVRD, 0x24)
-REG32(VAL, 0x28)
-REG32(TIMEOUT_CTRL, 0x2c)
-
-#define IBEX_UART_TX_FIFO_SIZE 16
-#define IBEX_UART_CLOCK 50000000 /* 50MHz clock */
-
-#define TYPE_IBEX_UART "ibex-uart"
-OBJECT_DECLARE_SIMPLE_TYPE(IbexUartState, IBEX_UART)
-
-struct IbexUartState {
- /* <private> */
- SysBusDevice parent_obj;
-
- /* <public> */
- MemoryRegion mmio;
-
- uint8_t tx_fifo[IBEX_UART_TX_FIFO_SIZE];
- uint32_t tx_level;
-
- QEMUTimer *fifo_trigger_handle;
- uint64_t char_tx_time;
-
- uint32_t uart_intr_state;
- uint32_t uart_intr_enable;
- uint32_t uart_ctrl;
- uint32_t uart_status;
- uint32_t uart_rdata;
- uint32_t uart_fifo_ctrl;
- uint32_t uart_fifo_status;
- uint32_t uart_ovrd;
- uint32_t uart_val;
- uint32_t uart_timeout_ctrl;
-
- Clock *f_clk;
-
- CharBackend chr;
- qemu_irq tx_watermark;
- qemu_irq rx_watermark;
- qemu_irq tx_empty;
- qemu_irq rx_overflow;
-};
-#endif /* HW_IBEX_UART_H */
+++ /dev/null
-/*
- * Device model for i.MX UART
- *
- * Copyright (c) 2008 OKL
- * Originally Written by Hans Jiang
- * Copyright (c) 2011 NICTA Pty Ltd.
- * Updated by Jean-Christophe Dubois <jcd@tribudubois.net>
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version
- * 2 of the License, or (at your option) any later version.
- *
- * You should have received a copy of the GNU General Public License along
- * with this program; if not, see <http://www.gnu.org/licenses/>.
- */
-
-#ifndef IMX_SERIAL_H
-#define IMX_SERIAL_H
-
-#include "hw/sysbus.h"
-#include "chardev/char-fe.h"
-#include "qom/object.h"
-
-#define TYPE_IMX_SERIAL "imx.serial"
-OBJECT_DECLARE_SIMPLE_TYPE(IMXSerialState, IMX_SERIAL)
-
-#define URXD_CHARRDY (1<<15) /* character read is valid */
-#define URXD_ERR (1<<14) /* Character has error */
-#define URXD_FRMERR (1<<12) /* Character has frame error */
-#define URXD_BRK (1<<11) /* Break received */
-
-#define USR1_PARTYER (1<<15) /* Parity Error */
-#define USR1_RTSS (1<<14) /* RTS pin status */
-#define USR1_TRDY (1<<13) /* Tx ready */
-#define USR1_RTSD (1<<12) /* RTS delta: pin changed state */
-#define USR1_ESCF (1<<11) /* Escape sequence interrupt */
-#define USR1_FRAMERR (1<<10) /* Framing error */
-#define USR1_RRDY (1<<9) /* receiver ready */
-#define USR1_AGTIM (1<<8) /* Aging timer interrupt */
-#define USR1_DTRD (1<<7) /* DTR changed */
-#define USR1_RXDS (1<<6) /* Receiver is idle */
-#define USR1_AIRINT (1<<5) /* Aysnch IR interrupt */
-#define USR1_AWAKE (1<<4) /* Falling edge detected on RXd pin */
-
-#define USR2_ADET (1<<15) /* Autobaud complete */
-#define USR2_TXFE (1<<14) /* Transmit FIFO empty */
-#define USR2_DTRF (1<<13) /* DTR/DSR transition */
-#define USR2_IDLE (1<<12) /* UART has been idle for too long */
-#define USR2_ACST (1<<11) /* Autobaud counter stopped */
-#define USR2_RIDELT (1<<10) /* Ring Indicator delta */
-#define USR2_RIIN (1<<9) /* Ring Indicator Input */
-#define USR2_IRINT (1<<8) /* Serial Infrared Interrupt */
-#define USR2_WAKE (1<<7) /* Start bit detected */
-#define USR2_DCDDELT (1<<6) /* Data Carrier Detect delta */
-#define USR2_DCDIN (1<<5) /* Data Carrier Detect Input */
-#define USR2_RTSF (1<<4) /* RTS transition */
-#define USR2_TXDC (1<<3) /* Transmission complete */
-#define USR2_BRCD (1<<2) /* Break condition detected */
-#define USR2_ORE (1<<1) /* Overrun error */
-#define USR2_RDR (1<<0) /* Receive data ready */
-
-#define UCR1_TRDYEN (1<<13) /* Tx Ready Interrupt Enable */
-#define UCR1_RRDYEN (1<<9) /* Rx Ready Interrupt Enable */
-#define UCR1_TXMPTYEN (1<<6) /* Tx Empty Interrupt Enable */
-#define UCR1_UARTEN (1<<0) /* UART Enable */
-
-#define UCR2_TXEN (1<<2) /* Transmitter enable */
-#define UCR2_RXEN (1<<1) /* Receiver enable */
-#define UCR2_SRST (1<<0) /* Reset complete */
-
-#define UCR4_DREN BIT(0) /* Receive Data Ready interrupt enable */
-#define UCR4_TCEN BIT(3) /* TX complete interrupt enable */
-
-#define UTS1_TXEMPTY (1<<6)
-#define UTS1_RXEMPTY (1<<5)
-#define UTS1_TXFULL (1<<4)
-#define UTS1_RXFULL (1<<3)
-
-struct IMXSerialState {
- /*< private >*/
- SysBusDevice parent_obj;
-
- /*< public >*/
- MemoryRegion iomem;
- int32_t readbuff;
-
- uint32_t usr1;
- uint32_t usr2;
- uint32_t ucr1;
- uint32_t ucr2;
- uint32_t uts1;
-
- /*
- * The registers below are implemented just so that the
- * guest OS sees what it has written
- */
- uint32_t onems;
- uint32_t ufcr;
- uint32_t ubmr;
- uint32_t ubrc;
- uint32_t ucr3;
- uint32_t ucr4;
-
- qemu_irq irq;
- CharBackend chr;
-};
-
-#endif
+++ /dev/null
-#ifndef QEMU_HW_CHAR_LM32_JUART_H
-#define QEMU_HW_CHAR_LM32_JUART_H
-
-#include "hw/qdev-core.h"
-
-#define TYPE_LM32_JUART "lm32-juart"
-
-uint32_t lm32_juart_get_jtx(DeviceState *d);
-uint32_t lm32_juart_get_jrx(DeviceState *d);
-void lm32_juart_set_jtx(DeviceState *d, uint32_t jtx);
-void lm32_juart_set_jrx(DeviceState *d, uint32_t jrx);
-
-#endif /* QEMU_HW_CHAR_LM32_JUART_H */
+++ /dev/null
-/*
- * Microchip PolarFire SoC MMUART emulation
- *
- * Copyright (c) 2020 Wind River Systems, Inc.
- *
- * Author:
- * Bin Meng <bin.meng@windriver.com>
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
- * furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
- * THE SOFTWARE.
- */
-
-#ifndef HW_MCHP_PFSOC_MMUART_H
-#define HW_MCHP_PFSOC_MMUART_H
-
-#include "hw/char/serial.h"
-
-#define MCHP_PFSOC_MMUART_REG_SIZE 52
-
-typedef struct MchpPfSoCMMUartState {
- MemoryRegion iomem;
- hwaddr base;
- qemu_irq irq;
-
- SerialMM *serial;
-
- uint32_t reg[MCHP_PFSOC_MMUART_REG_SIZE / sizeof(uint32_t)];
-} MchpPfSoCMMUartState;
-
-/**
- * mchp_pfsoc_mmuart_create - Create a Microchip PolarFire SoC MMUART
- *
- * This is a helper routine for board to create a MMUART device that is
- * compatible with Microchip PolarFire SoC.
- *
- * @sysmem: system memory region to map
- * @base: base address of the MMUART registers
- * @irq: IRQ number of the MMUART device
- * @chr: character device to associate to
- *
- * @return: a pointer to the device specific control structure
- */
-MchpPfSoCMMUartState *mchp_pfsoc_mmuart_create(MemoryRegion *sysmem,
- hwaddr base, qemu_irq irq, Chardev *chr);
-
-#endif /* HW_MCHP_PFSOC_MMUART_H */
+++ /dev/null
-/*
- * nRF51 SoC UART emulation
- *
- * Copyright (c) 2018 Julia Suvorova <jusual@mail.ru>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 or
- * (at your option) any later version.
- */
-
-#ifndef NRF51_UART_H
-#define NRF51_UART_H
-
-#include "hw/sysbus.h"
-#include "chardev/char-fe.h"
-#include "hw/registerfields.h"
-#include "qom/object.h"
-
-#define UART_FIFO_LENGTH 6
-#define UART_SIZE 0x1000
-
-#define TYPE_NRF51_UART "nrf51_soc.uart"
-OBJECT_DECLARE_SIMPLE_TYPE(NRF51UARTState, NRF51_UART)
-
-REG32(UART_STARTRX, 0x000)
-REG32(UART_STOPRX, 0x004)
-REG32(UART_STARTTX, 0x008)
-REG32(UART_STOPTX, 0x00C)
-REG32(UART_SUSPEND, 0x01C)
-
-REG32(UART_CTS, 0x100)
-REG32(UART_NCTS, 0x104)
-REG32(UART_RXDRDY, 0x108)
-REG32(UART_TXDRDY, 0x11C)
-REG32(UART_ERROR, 0x124)
-REG32(UART_RXTO, 0x144)
-
-REG32(UART_INTEN, 0x300)
- FIELD(UART_INTEN, CTS, 0, 1)
- FIELD(UART_INTEN, NCTS, 1, 1)
- FIELD(UART_INTEN, RXDRDY, 2, 1)
- FIELD(UART_INTEN, TXDRDY, 7, 1)
- FIELD(UART_INTEN, ERROR, 9, 1)
- FIELD(UART_INTEN, RXTO, 17, 1)
-REG32(UART_INTENSET, 0x304)
-REG32(UART_INTENCLR, 0x308)
-REG32(UART_ERRORSRC, 0x480)
-REG32(UART_ENABLE, 0x500)
-REG32(UART_PSELRTS, 0x508)
-REG32(UART_PSELTXD, 0x50C)
-REG32(UART_PSELCTS, 0x510)
-REG32(UART_PSELRXD, 0x514)
-REG32(UART_RXD, 0x518)
-REG32(UART_TXD, 0x51C)
-REG32(UART_BAUDRATE, 0x524)
-REG32(UART_CONFIG, 0x56C)
-
-struct NRF51UARTState {
- SysBusDevice parent_obj;
-
- MemoryRegion iomem;
- CharBackend chr;
- qemu_irq irq;
- guint watch_tag;
-
- uint8_t rx_fifo[UART_FIFO_LENGTH];
- unsigned int rx_fifo_pos;
- unsigned int rx_fifo_len;
-
- uint32_t reg[0x56C];
-
- bool rx_started;
- bool tx_started;
- bool pending_tx_byte;
- bool enabled;
-};
-
-#endif
+++ /dev/null
-#ifndef HW_PARALLEL_H
-#define HW_PARALLEL_H
-
-#include "hw/isa/isa.h"
-#include "chardev/char.h"
-
-void parallel_hds_isa_init(ISABus *bus, int n);
-
-bool parallel_mm_init(MemoryRegion *address_space,
- hwaddr base, int it_shift, qemu_irq irq,
- Chardev *chr);
-
-#endif
+++ /dev/null
-/*
- * This program is free software; you can redistribute it and/or modify it
- * under the terms and conditions of the GNU General Public License,
- * version 2 or later, as published by the Free Software Foundation.
- *
- * This program is distributed in the hope it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License along with
- * this program. If not, see <http://www.gnu.org/licenses/>.
- */
-
-#ifndef HW_PL011_H
-#define HW_PL011_H
-
-#include "hw/qdev-properties.h"
-#include "hw/sysbus.h"
-#include "chardev/char-fe.h"
-#include "qapi/error.h"
-#include "qom/object.h"
-
-#define TYPE_PL011 "pl011"
-OBJECT_DECLARE_SIMPLE_TYPE(PL011State, PL011)
-
-/* This shares the same struct (and cast macro) as the base pl011 device */
-#define TYPE_PL011_LUMINARY "pl011_luminary"
-
-struct PL011State {
- SysBusDevice parent_obj;
-
- MemoryRegion iomem;
- uint32_t readbuff;
- uint32_t flags;
- uint32_t lcr;
- uint32_t rsr;
- uint32_t cr;
- uint32_t dmacr;
- uint32_t int_enabled;
- uint32_t int_level;
- uint32_t read_fifo[16];
- uint32_t ilpr;
- uint32_t ibrd;
- uint32_t fbrd;
- uint32_t ifl;
- int read_pos;
- int read_count;
- int read_trigger;
- CharBackend chr;
- qemu_irq irq[6];
- Clock *clk;
- bool migrate_clk;
- const unsigned char *id;
-};
-
-static inline DeviceState *pl011_create(hwaddr addr,
- qemu_irq irq,
- Chardev *chr)
-{
- DeviceState *dev;
- SysBusDevice *s;
-
- dev = qdev_new("pl011");
- s = SYS_BUS_DEVICE(dev);
- qdev_prop_set_chr(dev, "chardev", chr);
- sysbus_realize_and_unref(s, &error_fatal);
- sysbus_mmio_map(s, 0, addr);
- sysbus_connect_irq(s, 0, irq);
-
- return dev;
-}
-
-static inline DeviceState *pl011_luminary_create(hwaddr addr,
- qemu_irq irq,
- Chardev *chr)
-{
- DeviceState *dev;
- SysBusDevice *s;
-
- dev = qdev_new("pl011_luminary");
- s = SYS_BUS_DEVICE(dev);
- qdev_prop_set_chr(dev, "chardev", chr);
- sysbus_realize_and_unref(s, &error_fatal);
- sysbus_mmio_map(s, 0, addr);
- sysbus_connect_irq(s, 0, irq);
-
- return dev;
-}
-
-#endif
+++ /dev/null
-/*
- * Renesas Serial Communication Interface
- *
- * Copyright (c) 2018 Yoshinori Sato
- *
- * SPDX-License-Identifier: GPL-2.0-or-later
- */
-
-#ifndef HW_CHAR_RENESAS_SCI_H
-#define HW_CHAR_RENESAS_SCI_H
-
-#include "chardev/char-fe.h"
-#include "hw/sysbus.h"
-#include "qom/object.h"
-
-#define TYPE_RENESAS_SCI "renesas-sci"
-typedef struct RSCIState RSCIState;
-DECLARE_INSTANCE_CHECKER(RSCIState, RSCI,
- TYPE_RENESAS_SCI)
-
-enum {
- ERI = 0,
- RXI = 1,
- TXI = 2,
- TEI = 3,
- SCI_NR_IRQ = 4
-};
-
-struct RSCIState {
- /*< private >*/
- SysBusDevice parent_obj;
- /*< public >*/
-
- MemoryRegion memory;
- QEMUTimer timer;
- CharBackend chr;
- qemu_irq irq[SCI_NR_IRQ];
-
- uint8_t smr;
- uint8_t brr;
- uint8_t scr;
- uint8_t tdr;
- uint8_t ssr;
- uint8_t rdr;
- uint8_t scmr;
- uint8_t semr;
-
- uint8_t read_ssr;
- int64_t trtime;
- int64_t rx_next;
- uint64_t input_freq;
-};
-
-#endif
+++ /dev/null
-/*
- * QEMU RISCV Host Target Interface (HTIF) Emulation
- *
- * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu
- * Copyright (c) 2017-2018 SiFive, Inc.
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms and conditions of the GNU General Public License,
- * version 2 or later, as published by the Free Software Foundation.
- *
- * This program is distributed in the hope it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License along with
- * this program. If not, see <http://www.gnu.org/licenses/>.
- */
-
-#ifndef HW_RISCV_HTIF_H
-#define HW_RISCV_HTIF_H
-
-#include "chardev/char.h"
-#include "chardev/char-fe.h"
-#include "exec/memory.h"
-#include "target/riscv/cpu.h"
-
-#define TYPE_HTIF_UART "riscv.htif.uart"
-
-typedef struct HTIFState {
- int allow_tohost;
- int fromhost_inprogress;
-
- hwaddr tohost_offset;
- hwaddr fromhost_offset;
- uint64_t tohost_size;
- uint64_t fromhost_size;
- MemoryRegion mmio;
- MemoryRegion *address_space;
- MemoryRegion *main_mem;
- void *main_mem_ram_ptr;
-
- CPURISCVState *env;
- CharBackend chr;
- uint64_t pending_read;
-} HTIFState;
-
-extern const VMStateDescription vmstate_htif;
-extern const MemoryRegionOps htif_io_ops;
-
-/* HTIF symbol callback */
-void htif_symbol_callback(const char *st_name, int st_info, uint64_t st_value,
- uint64_t st_size);
-
-/* legacy pre qom */
-HTIFState *htif_mm_init(MemoryRegion *address_space, MemoryRegion *main_mem,
- CPURISCVState *env, Chardev *chr);
-
-#endif
+++ /dev/null
-/*
- * QEMU 16550A UART emulation
- *
- * Copyright (c) 2003-2004 Fabrice Bellard
- * Copyright (c) 2008 Citrix Systems, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
- * furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
- * THE SOFTWARE.
- */
-
-#ifndef HW_SERIAL_H
-#define HW_SERIAL_H
-
-#include "chardev/char-fe.h"
-#include "exec/memory.h"
-#include "qemu/fifo8.h"
-#include "chardev/char.h"
-#include "hw/sysbus.h"
-#include "qom/object.h"
-
-#define UART_FIFO_LENGTH 16 /* 16550A Fifo Length */
-
-struct SerialState {
- DeviceState parent;
-
- uint16_t divider;
- uint8_t rbr; /* receive register */
- uint8_t thr; /* transmit holding register */
- uint8_t tsr; /* transmit shift register */
- uint8_t ier;
- uint8_t iir; /* read only */
- uint8_t lcr;
- uint8_t mcr;
- uint8_t lsr; /* read only */
- uint8_t msr; /* read only */
- uint8_t scr;
- uint8_t fcr;
- uint8_t fcr_vmstate; /* we can't write directly this value
- it has side effects */
- /* NOTE: this hidden state is necessary for tx irq generation as
- it can be reset while reading iir */
- int thr_ipending;
- qemu_irq irq;
- CharBackend chr;
- int last_break_enable;
- uint32_t baudbase;
- uint32_t tsr_retry;
- guint watch_tag;
- bool wakeup;
-
- /* Time when the last byte was successfully sent out of the tsr */
- uint64_t last_xmit_ts;
- Fifo8 recv_fifo;
- Fifo8 xmit_fifo;
- /* Interrupt trigger level for recv_fifo */
- uint8_t recv_fifo_itl;
-
- QEMUTimer *fifo_timeout_timer;
- int timeout_ipending; /* timeout interrupt pending state */
-
- uint64_t char_transmit_time; /* time to transmit a char in ticks */
- int poll_msl;
-
- QEMUTimer *modem_status_poll;
- MemoryRegion io;
-};
-typedef struct SerialState SerialState;
-
-struct SerialMM {
- SysBusDevice parent;
-
- SerialState serial;
-
- uint8_t regshift;
- uint8_t endianness;
-};
-
-extern const VMStateDescription vmstate_serial;
-extern const MemoryRegionOps serial_io_ops;
-
-void serial_set_frequency(SerialState *s, uint32_t frequency);
-
-#define TYPE_SERIAL "serial"
-OBJECT_DECLARE_SIMPLE_TYPE(SerialState, SERIAL)
-
-#define TYPE_SERIAL_MM "serial-mm"
-OBJECT_DECLARE_SIMPLE_TYPE(SerialMM, SERIAL_MM)
-
-SerialMM *serial_mm_init(MemoryRegion *address_space,
- hwaddr base, int regshift,
- qemu_irq irq, int baudbase,
- Chardev *chr, enum device_endian end);
-
-/* serial-isa.c */
-
-#define MAX_ISA_SERIAL_PORTS 4
-
-#define TYPE_ISA_SERIAL "isa-serial"
-void serial_hds_isa_init(ISABus *bus, int from, int to);
-
-#endif
+++ /dev/null
-/*
- * SiFive UART interface
- *
- * Copyright (c) 2016 Stefan O'Rear
- * Copyright (c) 2017 SiFive, Inc.
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms and conditions of the GNU General Public License,
- * version 2 or later, as published by the Free Software Foundation.
- *
- * This program is distributed in the hope it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License along with
- * this program. If not, see <http://www.gnu.org/licenses/>.
- */
-
-#ifndef HW_SIFIVE_UART_H
-#define HW_SIFIVE_UART_H
-
-#include "chardev/char-fe.h"
-#include "hw/sysbus.h"
-#include "qom/object.h"
-
-enum {
- SIFIVE_UART_TXFIFO = 0,
- SIFIVE_UART_RXFIFO = 4,
- SIFIVE_UART_TXCTRL = 8,
- SIFIVE_UART_TXMARK = 10,
- SIFIVE_UART_RXCTRL = 12,
- SIFIVE_UART_RXMARK = 14,
- SIFIVE_UART_IE = 16,
- SIFIVE_UART_IP = 20,
- SIFIVE_UART_DIV = 24,
- SIFIVE_UART_MAX = 32
-};
-
-enum {
- SIFIVE_UART_IE_TXWM = 1, /* Transmit watermark interrupt enable */
- SIFIVE_UART_IE_RXWM = 2 /* Receive watermark interrupt enable */
-};
-
-enum {
- SIFIVE_UART_IP_TXWM = 1, /* Transmit watermark interrupt pending */
- SIFIVE_UART_IP_RXWM = 2 /* Receive watermark interrupt pending */
-};
-
-#define SIFIVE_UART_GET_TXCNT(txctrl) ((txctrl >> 16) & 0x7)
-#define SIFIVE_UART_GET_RXCNT(rxctrl) ((rxctrl >> 16) & 0x7)
-
-#define TYPE_SIFIVE_UART "riscv.sifive.uart"
-
-typedef struct SiFiveUARTState SiFiveUARTState;
-DECLARE_INSTANCE_CHECKER(SiFiveUARTState, SIFIVE_UART,
- TYPE_SIFIVE_UART)
-
-struct SiFiveUARTState {
- /*< private >*/
- SysBusDevice parent_obj;
-
- /*< public >*/
- qemu_irq irq;
- MemoryRegion mmio;
- CharBackend chr;
- uint8_t rx_fifo[8];
- unsigned int rx_fifo_len;
- uint32_t ie;
- uint32_t ip;
- uint32_t txctrl;
- uint32_t rxctrl;
- uint32_t div;
-};
-
-SiFiveUARTState *sifive_uart_create(MemoryRegion *address_space, hwaddr base,
- Chardev *chr, qemu_irq irq);
-
-#endif
+++ /dev/null
-/*
- * STM32F2XX USART
- *
- * Copyright (c) 2014 Alistair Francis <alistair@alistair23.me>
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
- * furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
- * THE SOFTWARE.
- */
-
-#ifndef HW_STM32F2XX_USART_H
-#define HW_STM32F2XX_USART_H
-
-#include "hw/sysbus.h"
-#include "chardev/char-fe.h"
-#include "qom/object.h"
-
-#define USART_SR 0x00
-#define USART_DR 0x04
-#define USART_BRR 0x08
-#define USART_CR1 0x0C
-#define USART_CR2 0x10
-#define USART_CR3 0x14
-#define USART_GTPR 0x18
-
-/*
- * NB: The reset value mentioned in "24.6.1 Status register" seems bogus.
- * Looking at "Table 98 USART register map and reset values", it seems it
- * should be 0xc0, and that's how real hardware behaves.
- */
-#define USART_SR_RESET (USART_SR_TXE | USART_SR_TC)
-
-#define USART_SR_TXE (1 << 7)
-#define USART_SR_TC (1 << 6)
-#define USART_SR_RXNE (1 << 5)
-
-#define USART_CR1_UE (1 << 13)
-#define USART_CR1_RXNEIE (1 << 5)
-#define USART_CR1_TE (1 << 3)
-#define USART_CR1_RE (1 << 2)
-
-#define TYPE_STM32F2XX_USART "stm32f2xx-usart"
-OBJECT_DECLARE_SIMPLE_TYPE(STM32F2XXUsartState, STM32F2XX_USART)
-
-struct STM32F2XXUsartState {
- /* <private> */
- SysBusDevice parent_obj;
-
- /* <public> */
- MemoryRegion mmio;
-
- uint32_t usart_sr;
- uint32_t usart_dr;
- uint32_t usart_brr;
- uint32_t usart_cr1;
- uint32_t usart_cr2;
- uint32_t usart_cr3;
- uint32_t usart_gtpr;
-
- CharBackend chr;
- qemu_irq irq;
-};
-#endif /* HW_STM32F2XX_USART_H */
+++ /dev/null
-/*
- * This program is free software; you can redistribute it and/or modify it
- * under the terms and conditions of the GNU General Public License,
- * version 2 or later, as published by the Free Software Foundation.
- *
- * This program is distributed in the hope it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License along with
- * this program. If not, see <http://www.gnu.org/licenses/>.
- */
-
-#ifndef XILINX_UARTLITE_H
-#define XILINX_UARTLITE_H
-
-#include "hw/qdev-properties.h"
-#include "hw/sysbus.h"
-
-static inline DeviceState *xilinx_uartlite_create(hwaddr addr,
- qemu_irq irq,
- Chardev *chr)
-{
- DeviceState *dev;
- SysBusDevice *s;
-
- dev = qdev_new("xlnx.xps-uartlite");
- s = SYS_BUS_DEVICE(dev);
- qdev_prop_set_chr(dev, "chardev", chr);
- sysbus_realize_and_unref(s, &error_fatal);
- sysbus_mmio_map(s, 0, addr);
- sysbus_connect_irq(s, 0, irq);
-
- return dev;
-}
-
-#endif
+++ /dev/null
-/*
- * Cortex-A15MPCore internal peripheral emulation.
- *
- * Copyright (c) 2012 Linaro Limited.
- * Written by Peter Maydell.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License along
- * with this program; if not, see <http://www.gnu.org/licenses/>.
- */
-#ifndef HW_CPU_A15MPCORE_H
-#define HW_CPU_A15MPCORE_H
-
-#include "hw/sysbus.h"
-#include "hw/intc/arm_gic.h"
-#include "qom/object.h"
-
-/* A15MP private memory region. */
-
-#define TYPE_A15MPCORE_PRIV "a15mpcore_priv"
-OBJECT_DECLARE_SIMPLE_TYPE(A15MPPrivState, A15MPCORE_PRIV)
-
-struct A15MPPrivState {
- /*< private >*/
- SysBusDevice parent_obj;
- /*< public >*/
-
- uint32_t num_cpu;
- uint32_t num_irq;
- MemoryRegion container;
-
- GICState gic;
-};
-
-#endif
+++ /dev/null
-/*
- * Cortex-A9MPCore internal peripheral emulation.
- *
- * Copyright (c) 2009 CodeSourcery.
- * Copyright (c) 2011 Linaro Limited.
- * Written by Paul Brook, Peter Maydell.
- *
- * This code is licensed under the GPL.
- */
-#ifndef HW_CPU_A9MPCORE_H
-#define HW_CPU_A9MPCORE_H
-
-#include "hw/sysbus.h"
-#include "hw/intc/arm_gic.h"
-#include "hw/misc/a9scu.h"
-#include "hw/timer/arm_mptimer.h"
-#include "hw/timer/a9gtimer.h"
-#include "qom/object.h"
-
-#define TYPE_A9MPCORE_PRIV "a9mpcore_priv"
-OBJECT_DECLARE_SIMPLE_TYPE(A9MPPrivState, A9MPCORE_PRIV)
-
-struct A9MPPrivState {
- /*< private >*/
- SysBusDevice parent_obj;
- /*< public >*/
-
- uint32_t num_cpu;
- MemoryRegion container;
- uint32_t num_irq;
-
- A9SCUState scu;
- GICState gic;
- A9GTimerState gtimer;
- ARMMPTimerState mptimer;
- ARMMPTimerState wdt;
-};
-
-#endif
+++ /dev/null
-/*
- * ARM11MPCore internal peripheral emulation.
- *
- * Copyright (c) 2006-2007 CodeSourcery.
- * Written by Paul Brook
- *
- * This code is licensed under the GPL.
- */
-
-#ifndef HW_CPU_ARM11MPCORE_H
-#define HW_CPU_ARM11MPCORE_H
-
-#include "hw/sysbus.h"
-#include "hw/misc/arm11scu.h"
-#include "hw/intc/arm_gic.h"
-#include "hw/timer/arm_mptimer.h"
-#include "qom/object.h"
-
-#define TYPE_ARM11MPCORE_PRIV "arm11mpcore_priv"
-OBJECT_DECLARE_SIMPLE_TYPE(ARM11MPCorePriveState, ARM11MPCORE_PRIV)
-
-struct ARM11MPCorePriveState {
- SysBusDevice parent_obj;
-
- uint32_t num_cpu;
- MemoryRegion container;
- uint32_t num_irq;
-
- ARM11SCUState scu;
- GICState gic;
- ARMMPTimerState mptimer;
- ARMMPTimerState wdtimer;
-};
-
-#endif
+++ /dev/null
-/*
- * QEMU CPU cluster
- *
- * Copyright (c) 2018 GreenSocs SAS
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version 2
- * of the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, see
- * <http://www.gnu.org/licenses/gpl-2.0.html>
- */
-#ifndef HW_CPU_CLUSTER_H
-#define HW_CPU_CLUSTER_H
-
-#include "hw/qdev-core.h"
-#include "qom/object.h"
-
-/*
- * CPU Cluster type
- *
- * A cluster is a group of CPUs which are all identical and have the same view
- * of the rest of the system. It is mainly an internal QEMU representation and
- * does not necessarily match with the notion of clusters on the real hardware.
- *
- * If CPUs are not identical (for example, Cortex-A53 and Cortex-A57 CPUs in an
- * Arm big.LITTLE system) they should be in different clusters. If the CPUs do
- * not have the same view of memory (for example the main CPU and a management
- * controller processor) they should be in different clusters.
- *
- * A cluster is created by creating an object of TYPE_CPU_CLUSTER, and then
- * adding the CPUs to it as QOM child objects (e.g. using the
- * object_initialize_child() or object_property_add_child() functions).
- * The CPUs may be either direct children of the cluster object, or indirect
- * children (e.g. children of children of the cluster object).
- *
- * All CPUs must be added as children before the cluster is realized.
- * (Regrettably QOM provides no way to prevent adding children to a realized
- * object and no way for the parent to be notified when a new child is added
- * to it, so this restriction is not checked for, but the system will not
- * behave correctly if it is not adhered to. The cluster will assert that
- * it contains at least one CPU, which should catch most inadvertent
- * violations of this constraint.)
- *
- * A CPU which is not put into any cluster will be considered implicitly
- * to be in a cluster with all the other "loose" CPUs, so all CPUs that are
- * not assigned to clusters must be identical.
- */
-
-#define TYPE_CPU_CLUSTER "cpu-cluster"
-OBJECT_DECLARE_SIMPLE_TYPE(CPUClusterState, CPU_CLUSTER)
-
-/*
- * This limit is imposed by TCG, which puts the cluster ID into an
- * 8 bit field (and uses all-1s for the default "not in any cluster").
- */
-#define MAX_CLUSTERS 255
-
-/**
- * CPUClusterState:
- * @cluster_id: The cluster ID. This value is for internal use only and should
- * not be exposed directly to the user or to the guest.
- *
- * State of a CPU cluster.
- */
-struct CPUClusterState {
- /*< private >*/
- DeviceState parent_obj;
-
- /*< public >*/
- uint32_t cluster_id;
-};
-
-#endif
+++ /dev/null
-/*
- * CPU core abstract device
- *
- * Copyright (C) 2016 Bharata B Rao <bharata@linux.vnet.ibm.com>
- *
- * This work is licensed under the terms of the GNU GPL, version 2 or later.
- * See the COPYING file in the top-level directory.
- */
-#ifndef HW_CPU_CORE_H
-#define HW_CPU_CORE_H
-
-#include "hw/qdev-core.h"
-#include "qom/object.h"
-
-#define TYPE_CPU_CORE "cpu-core"
-
-OBJECT_DECLARE_SIMPLE_TYPE(CPUCore, CPU_CORE)
-
-struct CPUCore {
- /*< private >*/
- DeviceState parent_obj;
-
- /*< public >*/
- int core_id;
- int nr_threads;
-};
-
-/* Note: topology field names need to be kept in sync with
- * 'CpuInstanceProperties' */
-
-#define CPU_CORE_PROP_CORE_ID "core-id"
-
-#endif
+++ /dev/null
-/*
- * QEMU ETRAX System Emulator
- *
- * Copyright (c) 2008 Edgar E. Iglesias, Axis Communications AB.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
- * furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
- * THE SOFTWARE.
- */
-
-#ifndef HW_ETRAXFS_H
-#define HW_ETRAXFS_H
-
-#include "net/net.h"
-#include "hw/cris/etraxfs_dma.h"
-#include "hw/qdev-properties.h"
-#include "hw/sysbus.h"
-
-DeviceState *etraxfs_eth_init(NICInfo *nd, hwaddr base, int phyaddr,
- struct etraxfs_dma_client *dma_out,
- struct etraxfs_dma_client *dma_in);
-
-static inline DeviceState *etraxfs_ser_create(hwaddr addr,
- qemu_irq irq,
- Chardev *chr)
-{
- DeviceState *dev;
- SysBusDevice *s;
-
- dev = qdev_new("etraxfs,serial");
- s = SYS_BUS_DEVICE(dev);
- qdev_prop_set_chr(dev, "chardev", chr);
- sysbus_realize_and_unref(s, &error_fatal);
- sysbus_mmio_map(s, 0, addr);
- sysbus_connect_irq(s, 0, irq);
- return dev;
-}
-
-#endif
+++ /dev/null
-#ifndef HW_ETRAXFS_DMA_H
-#define HW_ETRAXFS_DMA_H
-
-#include "exec/hwaddr.h"
-
-struct dma_context_metadata {
- /* data descriptor md */
- uint16_t metadata;
-};
-
-struct etraxfs_dma_client
-{
- /* DMA controller. */
- int channel;
- void *ctrl;
-
- /* client. */
- struct {
- int (*push)(void *opaque, unsigned char *buf,
- int len, bool eop);
- void (*pull)(void *opaque);
- void (*metadata_push)(void *opaque,
- const struct dma_context_metadata *md);
- void *opaque;
- } client;
-};
-
-void *etraxfs_dmac_init(hwaddr base, int nr_channels);
-void etraxfs_dmac_connect(void *opaque, int channel, qemu_irq *line,
- int input);
-void etraxfs_dmac_connect_client(void *opaque, int c,
- struct etraxfs_dma_client *cl);
-int etraxfs_dmac_input(struct etraxfs_dma_client *client,
- void *buf, int len, int eop);
-
-#endif
+++ /dev/null
-/*
- * Raspberry Pi emulation (c) 2012 Gregory Estrade
- *
- * This work is licensed under the terms of the GNU GPL, version 2 or later.
- * See the COPYING file in the top-level directory.
- */
-
-#ifndef BCM2835_DMA_H
-#define BCM2835_DMA_H
-
-#include "hw/sysbus.h"
-#include "qom/object.h"
-
-typedef struct {
- uint32_t cs;
- uint32_t conblk_ad;
- uint32_t ti;
- uint32_t source_ad;
- uint32_t dest_ad;
- uint32_t txfr_len;
- uint32_t stride;
- uint32_t nextconbk;
- uint32_t debug;
-
- qemu_irq irq;
-} BCM2835DMAChan;
-
-#define TYPE_BCM2835_DMA "bcm2835-dma"
-OBJECT_DECLARE_SIMPLE_TYPE(BCM2835DMAState, BCM2835_DMA)
-
-#define BCM2835_DMA_NCHANS 16
-
-struct BCM2835DMAState {
- /*< private >*/
- SysBusDevice busdev;
- /*< public >*/
-
- MemoryRegion iomem0, iomem15;
- MemoryRegion *dma_mr;
- AddressSpace dma_as;
-
- BCM2835DMAChan chan[BCM2835_DMA_NCHANS];
- uint32_t int_status;
- uint32_t enable;
-};
-
-#endif
+++ /dev/null
-#ifndef HW_I8257_H
-#define HW_I8257_H
-
-#include "hw/isa/isa.h"
-#include "exec/ioport.h"
-#include "qom/object.h"
-
-#define TYPE_I8257 "i8257"
-OBJECT_DECLARE_SIMPLE_TYPE(I8257State, I8257)
-
-typedef struct I8257Regs {
- int now[2];
- uint16_t base[2];
- uint8_t mode;
- uint8_t page;
- uint8_t pageh;
- uint8_t dack;
- uint8_t eop;
- IsaDmaTransferHandler transfer_handler;
- void *opaque;
-} I8257Regs;
-
-struct I8257State {
- /* <private> */
- ISADevice parent_obj;
-
- /* <public> */
- int32_t base;
- int32_t page_base;
- int32_t pageh_base;
- int32_t dshift;
-
- uint8_t status;
- uint8_t command;
- uint8_t mask;
- uint8_t flip_flop;
- I8257Regs regs[4];
- MemoryRegion channel_io;
- MemoryRegion cont_io;
-
- QEMUBH *dma_bh;
- bool dma_bh_scheduled;
- int running;
- PortioList portio_page;
- PortioList portio_pageh;
-};
-
-void i8257_dma_init(ISABus *bus, bool high_page_enable);
-
-#endif
+++ /dev/null
-/*
- * ARM PrimeCell PL080/PL081 DMA controller
- *
- * Copyright (c) 2006 CodeSourcery.
- * Copyright (c) 2018 Linaro Limited
- * Written by Paul Brook, Peter Maydell
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 or
- * (at your option) any later version.
- */
-
-/* This is a model of the Arm PrimeCell PL080/PL081 DMA controller:
- * The PL080 TRM is:
- * http://infocenter.arm.com/help/topic/com.arm.doc.ddi0196g/DDI0196.pdf
- * and the PL081 TRM is:
- * http://infocenter.arm.com/help/topic/com.arm.doc.ddi0218e/DDI0218.pdf
- *
- * QEMU interface:
- * + sysbus IRQ 0: DMACINTR combined interrupt line
- * + sysbus IRQ 1: DMACINTERR error interrupt request
- * + sysbus IRQ 2: DMACINTTC count interrupt request
- * + sysbus MMIO region 0: MemoryRegion for the device's registers
- * + QOM property "downstream": MemoryRegion defining where DMA
- * bus master transactions are made
- */
-
-#ifndef HW_DMA_PL080_H
-#define HW_DMA_PL080_H
-
-#include "hw/sysbus.h"
-#include "qom/object.h"
-
-#define PL080_MAX_CHANNELS 8
-
-typedef struct {
- uint32_t src;
- uint32_t dest;
- uint32_t lli;
- uint32_t ctrl;
- uint32_t conf;
-} pl080_channel;
-
-#define TYPE_PL080 "pl080"
-#define TYPE_PL081 "pl081"
-OBJECT_DECLARE_SIMPLE_TYPE(PL080State, PL080)
-
-struct PL080State {
- SysBusDevice parent_obj;
-
- MemoryRegion iomem;
- uint8_t tc_int;
- uint8_t tc_mask;
- uint8_t err_int;
- uint8_t err_mask;
- uint32_t conf;
- uint32_t sync;
- uint32_t req_single;
- uint32_t req_burst;
- pl080_channel chan[PL080_MAX_CHANNELS];
- int nchannels;
- /* Flag to avoid recursive DMA invocations. */
- int running;
- qemu_irq irq;
- qemu_irq interr;
- qemu_irq inttc;
-
- MemoryRegion *downstream;
- AddressSpace downstream_as;
-};
-
-#endif
+++ /dev/null
-/*
- * SiFive Platform DMA emulation
- *
- * Copyright (c) 2020 Wind River Systems, Inc.
- *
- * Author:
- * Bin Meng <bin.meng@windriver.com>
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 or
- * (at your option) version 3 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License along
- * with this program; if not, see <http://www.gnu.org/licenses/>.
- */
-
-#ifndef SIFIVE_PDMA_H
-#define SIFIVE_PDMA_H
-
-struct sifive_pdma_chan {
- uint32_t control;
- uint32_t next_config;
- uint64_t next_bytes;
- uint64_t next_dst;
- uint64_t next_src;
- uint32_t exec_config;
- uint64_t exec_bytes;
- uint64_t exec_dst;
- uint64_t exec_src;
- int state;
-};
-
-#define SIFIVE_PDMA_CHANS 4
-#define SIFIVE_PDMA_IRQS (SIFIVE_PDMA_CHANS * 2)
-#define SIFIVE_PDMA_REG_SIZE 0x100000
-#define SIFIVE_PDMA_CHAN_NO(reg) ((reg & (SIFIVE_PDMA_REG_SIZE - 1)) >> 12)
-
-typedef struct SiFivePDMAState {
- SysBusDevice parent;
- MemoryRegion iomem;
- qemu_irq irq[SIFIVE_PDMA_IRQS];
-
- struct sifive_pdma_chan chan[SIFIVE_PDMA_CHANS];
-} SiFivePDMAState;
-
-#define TYPE_SIFIVE_PDMA "sifive.pdma"
-
-#define SIFIVE_PDMA(obj) \
- OBJECT_CHECK(SiFivePDMAState, (obj), TYPE_SIFIVE_PDMA)
-
-#endif /* SIFIVE_PDMA_H */
+++ /dev/null
-/*
- * QEMU model of the ZynqMP generic DMA
- *
- * Copyright (c) 2014 Xilinx Inc.
- * Copyright (c) 2018 FEIMTECH AB
- *
- * Written by Edgar E. Iglesias <edgar.iglesias@xilinx.com>,
- * Francisco Iglesias <francisco.iglesias@feimtech.se>
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
- * furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
- * THE SOFTWARE.
- */
-
-#ifndef XLNX_ZDMA_H
-#define XLNX_ZDMA_H
-
-#include "hw/sysbus.h"
-#include "hw/register.h"
-#include "sysemu/dma.h"
-#include "qom/object.h"
-
-#define ZDMA_R_MAX (0x204 / 4)
-
-typedef enum {
- DISABLED = 0,
- ENABLED = 1,
- PAUSED = 2,
-} XlnxZDMAState;
-
-typedef union {
- struct {
- uint64_t addr;
- uint32_t size;
- uint32_t attr;
- };
- uint32_t words[4];
-} XlnxZDMADescr;
-
-struct XlnxZDMA {
- SysBusDevice parent_obj;
- MemoryRegion iomem;
- MemTxAttrs attr;
- MemoryRegion *dma_mr;
- AddressSpace *dma_as;
- qemu_irq irq_zdma_ch_imr;
-
- struct {
- uint32_t bus_width;
- } cfg;
-
- XlnxZDMAState state;
- bool error;
-
- XlnxZDMADescr dsc_src;
- XlnxZDMADescr dsc_dst;
-
- uint32_t regs[ZDMA_R_MAX];
- RegisterInfo regs_info[ZDMA_R_MAX];
-
- /* We don't model the common bufs. Must be at least 16 bytes
- to model write only mode. */
- uint8_t buf[2048];
-};
-
-#define TYPE_XLNX_ZDMA "xlnx.zdma"
-
-OBJECT_DECLARE_SIMPLE_TYPE(XlnxZDMA, XLNX_ZDMA)
-
-#endif /* XLNX_ZDMA_H */
+++ /dev/null
-/*
- * QEMU model of the Xilinx Devcfg Interface
- *
- * (C) 2011 PetaLogix Pty Ltd
- * (C) 2014 Xilinx Inc.
- * Written by Peter Crosthwaite <peter.crosthwaite@xilinx.com>
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
- * furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
- * THE SOFTWARE.
- */
-
-#ifndef XLNX_ZYNQ_DEVCFG_H
-#define XLNX_ZYNQ_DEVCFG_H
-
-#include "hw/register.h"
-#include "hw/sysbus.h"
-#include "qom/object.h"
-
-#define TYPE_XLNX_ZYNQ_DEVCFG "xlnx.ps7-dev-cfg"
-
-OBJECT_DECLARE_SIMPLE_TYPE(XlnxZynqDevcfg, XLNX_ZYNQ_DEVCFG)
-
-#define XLNX_ZYNQ_DEVCFG_R_MAX (0x100 / 4)
-
-#define XLNX_ZYNQ_DEVCFG_DMA_CMD_FIFO_LEN 10
-
-typedef struct XlnxZynqDevcfgDMACmd {
- uint32_t src_addr;
- uint32_t dest_addr;
- uint32_t src_len;
- uint32_t dest_len;
-} XlnxZynqDevcfgDMACmd;
-
-struct XlnxZynqDevcfg {
- SysBusDevice parent_obj;
-
- MemoryRegion iomem;
- qemu_irq irq;
-
- XlnxZynqDevcfgDMACmd dma_cmd_fifo[XLNX_ZYNQ_DEVCFG_DMA_CMD_FIFO_LEN];
- uint8_t dma_cmd_fifo_num;
-
- uint32_t regs[XLNX_ZYNQ_DEVCFG_R_MAX];
- RegisterInfo regs_info[XLNX_ZYNQ_DEVCFG_R_MAX];
-};
-
-#endif
+++ /dev/null
-/*
- * xlnx_dpdma.h
- *
- * Copyright (C) 2015 : GreenSocs Ltd
- * http://www.greensocs.com/ , email: info@greensocs.com
- *
- * Developed by :
- * Frederic Konrad <fred.konrad@greensocs.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation, either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License along
- * with this program; if not, see <http://www.gnu.org/licenses/>.
- *
- */
-
-#ifndef XLNX_DPDMA_H
-#define XLNX_DPDMA_H
-
-#include "hw/sysbus.h"
-#include "ui/console.h"
-#include "sysemu/dma.h"
-#include "qom/object.h"
-
-#define XLNX_DPDMA_REG_ARRAY_SIZE (0x1000 >> 2)
-
-struct XlnxDPDMAState {
- /*< private >*/
- SysBusDevice parent_obj;
- /*< public >*/
- MemoryRegion iomem;
- uint32_t registers[XLNX_DPDMA_REG_ARRAY_SIZE];
- uint8_t *data[6];
- bool operation_finished[6];
- qemu_irq irq;
-};
-
-
-#define TYPE_XLNX_DPDMA "xlnx.dpdma"
-OBJECT_DECLARE_SIMPLE_TYPE(XlnxDPDMAState, XLNX_DPDMA)
-
-/*
- * xlnx_dpdma_start_operation: Start the operation on the specified channel. The
- * DPDMA gets the current descriptor and retrieves
- * data to the buffer specified by
- * dpdma_set_host_data_location().
- *
- * Returns The number of bytes transferred by the DPDMA
- * or 0 if an error occurred.
- *
- * @s The DPDMA state.
- * @channel The channel to start.
- */
-size_t xlnx_dpdma_start_operation(XlnxDPDMAState *s, uint8_t channel,
- bool one_desc);
-
-/*
- * xlnx_dpdma_set_host_data_location: Set the location in the host memory where
- * to store the data out from the dma
- * channel.
- *
- * @s The DPDMA state.
- * @channel The channel associated to the pointer.
- * @p The buffer where to store the data.
- */
-/* XXX: add a maximum size arg and send an interrupt in case of overflow. */
-void xlnx_dpdma_set_host_data_location(XlnxDPDMAState *s, uint8_t channel,
- void *p);
-
-/*
- * xlnx_dpdma_trigger_vsync_irq: Trigger a VSYNC IRQ when the display is
- * updated.
- *
- * @s The DPDMA state.
- */
-void xlnx_dpdma_trigger_vsync_irq(XlnxDPDMAState *s);
-
-#endif /* XLNX_DPDMA_H */
+++ /dev/null
-#ifndef QEMU_SMBIOS_H
-#define QEMU_SMBIOS_H
-
-/*
- * SMBIOS Support
- *
- * Copyright (C) 2009 Hewlett-Packard Development Company, L.P.
- *
- * Authors:
- * Alex Williamson <alex.williamson@hp.com>
- *
- * This work is licensed under the terms of the GNU GPL, version 2. See
- * the COPYING file in the top-level directory.
- *
- */
-
-
-#define SMBIOS_MAX_TYPE 127
-
-/* memory area description, used by type 19 table */
-struct smbios_phys_mem_area {
- uint64_t address;
- uint64_t length;
-};
-
-/*
- * SMBIOS spec defined tables
- */
-typedef enum SmbiosEntryPointType {
- SMBIOS_ENTRY_POINT_21,
- SMBIOS_ENTRY_POINT_30,
-} SmbiosEntryPointType;
-
-/* SMBIOS Entry Point
- * There are two types of entry points defined in the SMBIOS specification
- * (see below). BIOS must place the entry point(s) at a 16-byte-aligned
- * address between 0xf0000 and 0xfffff. Note that either entry point type
- * can be used in a 64-bit target system, except that SMBIOS 2.1 entry point
- * only allows the SMBIOS struct table to reside below 4GB address space.
- */
-
-/* SMBIOS 2.1 (32-bit) Entry Point
- * - introduced since SMBIOS 2.1
- * - supports structure table below 4GB only
- */
-struct smbios_21_entry_point {
- uint8_t anchor_string[4];
- uint8_t checksum;
- uint8_t length;
- uint8_t smbios_major_version;
- uint8_t smbios_minor_version;
- uint16_t max_structure_size;
- uint8_t entry_point_revision;
- uint8_t formatted_area[5];
- uint8_t intermediate_anchor_string[5];
- uint8_t intermediate_checksum;
- uint16_t structure_table_length;
- uint32_t structure_table_address;
- uint16_t number_of_structures;
- uint8_t smbios_bcd_revision;
-} QEMU_PACKED;
-
-/* SMBIOS 3.0 (64-bit) Entry Point
- * - introduced since SMBIOS 3.0
- * - supports structure table at 64-bit address space
- */
-struct smbios_30_entry_point {
- uint8_t anchor_string[5];
- uint8_t checksum;
- uint8_t length;
- uint8_t smbios_major_version;
- uint8_t smbios_minor_version;
- uint8_t smbios_doc_rev;
- uint8_t entry_point_revision;
- uint8_t reserved;
- uint32_t structure_table_max_size;
- uint64_t structure_table_address;
-} QEMU_PACKED;
-
-typedef union {
- struct smbios_21_entry_point ep21;
- struct smbios_30_entry_point ep30;
-} QEMU_PACKED SmbiosEntryPoint;
-
-/* This goes at the beginning of every SMBIOS structure. */
-struct smbios_structure_header {
- uint8_t type;
- uint8_t length;
- uint16_t handle;
-} QEMU_PACKED;
-
-/* SMBIOS type 0 - BIOS Information */
-struct smbios_type_0 {
- struct smbios_structure_header header;
- uint8_t vendor_str;
- uint8_t bios_version_str;
- uint16_t bios_starting_address_segment;
- uint8_t bios_release_date_str;
- uint8_t bios_rom_size;
- uint64_t bios_characteristics;
- uint8_t bios_characteristics_extension_bytes[2];
- uint8_t system_bios_major_release;
- uint8_t system_bios_minor_release;
- uint8_t embedded_controller_major_release;
- uint8_t embedded_controller_minor_release;
-} QEMU_PACKED;
-
-/* UUID encoding. The time_* fields are little-endian, as specified by SMBIOS
- * version 2.6.
- */
-struct smbios_uuid {
- uint32_t time_low;
- uint16_t time_mid;
- uint16_t time_hi_and_version;
- uint8_t clock_seq_hi_and_reserved;
- uint8_t clock_seq_low;
- uint8_t node[6];
-} QEMU_PACKED;
-
-/* SMBIOS type 1 - System Information */
-struct smbios_type_1 {
- struct smbios_structure_header header;
- uint8_t manufacturer_str;
- uint8_t product_name_str;
- uint8_t version_str;
- uint8_t serial_number_str;
- struct smbios_uuid uuid;
- uint8_t wake_up_type;
- uint8_t sku_number_str;
- uint8_t family_str;
-} QEMU_PACKED;
-
-/* SMBIOS type 2 - Base Board */
-struct smbios_type_2 {
- struct smbios_structure_header header;
- uint8_t manufacturer_str;
- uint8_t product_str;
- uint8_t version_str;
- uint8_t serial_number_str;
- uint8_t asset_tag_number_str;
- uint8_t feature_flags;
- uint8_t location_str;
- uint16_t chassis_handle;
- uint8_t board_type;
- uint8_t contained_element_count;
- /* contained elements follow */
-} QEMU_PACKED;
-
-/* SMBIOS type 3 - System Enclosure (v2.7) */
-struct smbios_type_3 {
- struct smbios_structure_header header;
- uint8_t manufacturer_str;
- uint8_t type;
- uint8_t version_str;
- uint8_t serial_number_str;
- uint8_t asset_tag_number_str;
- uint8_t boot_up_state;
- uint8_t power_supply_state;
- uint8_t thermal_state;
- uint8_t security_status;
- uint32_t oem_defined;
- uint8_t height;
- uint8_t number_of_power_cords;
- uint8_t contained_element_count;
- uint8_t contained_element_record_length;
- uint8_t sku_number_str;
- /* contained elements follow */
-} QEMU_PACKED;
-
-/* SMBIOS type 4 - Processor Information (v2.6) */
-struct smbios_type_4 {
- struct smbios_structure_header header;
- uint8_t socket_designation_str;
- uint8_t processor_type;
- uint8_t processor_family;
- uint8_t processor_manufacturer_str;
- uint32_t processor_id[2];
- uint8_t processor_version_str;
- uint8_t voltage;
- uint16_t external_clock;
- uint16_t max_speed;
- uint16_t current_speed;
- uint8_t status;
- uint8_t processor_upgrade;
- uint16_t l1_cache_handle;
- uint16_t l2_cache_handle;
- uint16_t l3_cache_handle;
- uint8_t serial_number_str;
- uint8_t asset_tag_number_str;
- uint8_t part_number_str;
- uint8_t core_count;
- uint8_t core_enabled;
- uint8_t thread_count;
- uint16_t processor_characteristics;
- uint16_t processor_family2;
-} QEMU_PACKED;
-
-/* SMBIOS type 11 - OEM strings */
-struct smbios_type_11 {
- struct smbios_structure_header header;
- uint8_t count;
-} QEMU_PACKED;
-
-/* SMBIOS type 16 - Physical Memory Array (v2.7) */
-struct smbios_type_16 {
- struct smbios_structure_header header;
- uint8_t location;
- uint8_t use;
- uint8_t error_correction;
- uint32_t maximum_capacity;
- uint16_t memory_error_information_handle;
- uint16_t number_of_memory_devices;
- uint64_t extended_maximum_capacity;
-} QEMU_PACKED;
-
-/* SMBIOS type 17 - Memory Device (v2.8) */
-struct smbios_type_17 {
- struct smbios_structure_header header;
- uint16_t physical_memory_array_handle;
- uint16_t memory_error_information_handle;
- uint16_t total_width;
- uint16_t data_width;
- uint16_t size;
- uint8_t form_factor;
- uint8_t device_set;
- uint8_t device_locator_str;
- uint8_t bank_locator_str;
- uint8_t memory_type;
- uint16_t type_detail;
- uint16_t speed;
- uint8_t manufacturer_str;
- uint8_t serial_number_str;
- uint8_t asset_tag_number_str;
- uint8_t part_number_str;
- uint8_t attributes;
- uint32_t extended_size;
- uint16_t configured_clock_speed;
- uint16_t minimum_voltage;
- uint16_t maximum_voltage;
- uint16_t configured_voltage;
-} QEMU_PACKED;
-
-/* SMBIOS type 19 - Memory Array Mapped Address (v2.7) */
-struct smbios_type_19 {
- struct smbios_structure_header header;
- uint32_t starting_address;
- uint32_t ending_address;
- uint16_t memory_array_handle;
- uint8_t partition_width;
- uint64_t extended_starting_address;
- uint64_t extended_ending_address;
-} QEMU_PACKED;
-
-/* SMBIOS type 32 - System Boot Information */
-struct smbios_type_32 {
- struct smbios_structure_header header;
- uint8_t reserved[6];
- uint8_t boot_status;
-} QEMU_PACKED;
-
-/* SMBIOS type 127 -- End-of-table */
-struct smbios_type_127 {
- struct smbios_structure_header header;
-} QEMU_PACKED;
-
-void smbios_entry_add(QemuOpts *opts, Error **errp);
-void smbios_set_cpuid(uint32_t version, uint32_t features);
-void smbios_set_defaults(const char *manufacturer, const char *product,
- const char *version, bool legacy_mode,
- bool uuid_encoded, SmbiosEntryPointType ep_type);
-uint8_t *smbios_get_table_legacy(MachineState *ms, size_t *length);
-void smbios_get_tables(MachineState *ms,
- const struct smbios_phys_mem_area *mem_array,
- const unsigned int mem_array_size,
- uint8_t **tables, size_t *tables_len,
- uint8_t **anchor, size_t *anchor_len);
-#endif /* QEMU_SMBIOS_H */
+++ /dev/null
-/*
- * ASPEED GPIO Controller
- *
- * Copyright (C) 2017-2018 IBM Corp.
- *
- * This code is licensed under the GPL version 2 or later. See
- * the COPYING file in the top-level directory.
- */
-
-#ifndef ASPEED_GPIO_H
-#define ASPEED_GPIO_H
-
-#include "hw/sysbus.h"
-#include "qom/object.h"
-
-#define TYPE_ASPEED_GPIO "aspeed.gpio"
-OBJECT_DECLARE_TYPE(AspeedGPIOState, AspeedGPIOClass, ASPEED_GPIO)
-
-#define ASPEED_GPIO_MAX_NR_SETS 8
-#define ASPEED_REGS_PER_BANK 14
-#define ASPEED_GPIO_MAX_NR_REGS (ASPEED_REGS_PER_BANK * ASPEED_GPIO_MAX_NR_SETS)
-#define ASPEED_GPIO_NR_PINS 228
-#define ASPEED_GROUPS_PER_SET 4
-#define ASPEED_GPIO_NR_DEBOUNCE_REGS 3
-#define ASPEED_CHARS_PER_GROUP_LABEL 4
-
-typedef struct GPIOSets GPIOSets;
-
-typedef struct GPIOSetProperties {
- uint32_t input;
- uint32_t output;
- char group_label[ASPEED_GROUPS_PER_SET][ASPEED_CHARS_PER_GROUP_LABEL];
-} GPIOSetProperties;
-
-enum GPIORegType {
- gpio_not_a_reg,
- gpio_reg_data_value,
- gpio_reg_direction,
- gpio_reg_int_enable,
- gpio_reg_int_sens_0,
- gpio_reg_int_sens_1,
- gpio_reg_int_sens_2,
- gpio_reg_int_status,
- gpio_reg_reset_tolerant,
- gpio_reg_debounce_1,
- gpio_reg_debounce_2,
- gpio_reg_cmd_source_0,
- gpio_reg_cmd_source_1,
- gpio_reg_data_read,
- gpio_reg_input_mask,
-};
-
-typedef struct AspeedGPIOReg {
- uint16_t set_idx;
- enum GPIORegType type;
- } AspeedGPIOReg;
-
-struct AspeedGPIOClass {
- SysBusDevice parent_obj;
- const GPIOSetProperties *props;
- uint32_t nr_gpio_pins;
- uint32_t nr_gpio_sets;
- uint32_t gap;
- const AspeedGPIOReg *reg_table;
-};
-
-struct AspeedGPIOState {
- /* <private> */
- SysBusDevice parent;
-
- /*< public >*/
- MemoryRegion iomem;
- int pending;
- qemu_irq irq;
- qemu_irq gpios[ASPEED_GPIO_NR_PINS];
-
-/* Parallel GPIO Registers */
- uint32_t debounce_regs[ASPEED_GPIO_NR_DEBOUNCE_REGS];
- struct GPIOSets {
- uint32_t data_value; /* Reflects pin values */
- uint32_t data_read; /* Contains last value written to data value */
- uint32_t direction;
- uint32_t int_enable;
- uint32_t int_sens_0;
- uint32_t int_sens_1;
- uint32_t int_sens_2;
- uint32_t int_status;
- uint32_t reset_tol;
- uint32_t cmd_source_0;
- uint32_t cmd_source_1;
- uint32_t debounce_1;
- uint32_t debounce_2;
- uint32_t input_mask;
- } sets[ASPEED_GPIO_MAX_NR_SETS];
-};
-
-#endif /* _ASPEED_GPIO_H_ */
+++ /dev/null
-/*
- * Raspberry Pi (BCM2835) GPIO Controller
- *
- * Copyright (c) 2017 Antfield SAS
- *
- * Authors:
- * Clement Deschamps <clement.deschamps@antfield.fr>
- * Luc Michel <luc.michel@antfield.fr>
- *
- * This work is licensed under the terms of the GNU GPL, version 2 or later.
- * See the COPYING file in the top-level directory.
- */
-
-#ifndef BCM2835_GPIO_H
-#define BCM2835_GPIO_H
-
-#include "hw/sd/sd.h"
-#include "hw/sysbus.h"
-#include "qom/object.h"
-
-struct BCM2835GpioState {
- SysBusDevice parent_obj;
-
- MemoryRegion iomem;
-
- /* SDBus selector */
- SDBus sdbus;
- SDBus *sdbus_sdhci;
- SDBus *sdbus_sdhost;
-
- uint8_t fsel[54];
- uint32_t lev0, lev1;
- uint8_t sd_fsel;
- qemu_irq out[54];
-};
-
-#define TYPE_BCM2835_GPIO "bcm2835_gpio"
-OBJECT_DECLARE_SIMPLE_TYPE(BCM2835GpioState, BCM2835_GPIO)
-
-#endif
+++ /dev/null
-/*
- * i.MX processors GPIO registers definition.
- *
- * Copyright (C) 2015 Jean-Christophe Dubois <jcd@tribudubois.net>
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 or
- * (at your option) version 3 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License along
- * with this program; if not, see <http://www.gnu.org/licenses/>.
- */
-
-#ifndef IMX_GPIO_H
-#define IMX_GPIO_H
-
-#include "hw/sysbus.h"
-#include "qom/object.h"
-
-#define TYPE_IMX_GPIO "imx.gpio"
-OBJECT_DECLARE_SIMPLE_TYPE(IMXGPIOState, IMX_GPIO)
-
-#define IMX_GPIO_MEM_SIZE 0x20
-
-/* i.MX GPIO memory map */
-#define DR_ADDR 0x00 /* DATA REGISTER */
-#define GDIR_ADDR 0x04 /* DIRECTION REGISTER */
-#define PSR_ADDR 0x08 /* PAD STATUS REGISTER */
-#define ICR1_ADDR 0x0c /* INTERRUPT CONFIGURATION REGISTER 1 */
-#define ICR2_ADDR 0x10 /* INTERRUPT CONFIGURATION REGISTER 2 */
-#define IMR_ADDR 0x14 /* INTERRUPT MASK REGISTER */
-#define ISR_ADDR 0x18 /* INTERRUPT STATUS REGISTER */
-#define EDGE_SEL_ADDR 0x1c /* EDGE SEL REGISTER */
-
-#define IMX_GPIO_PIN_COUNT 32
-
-struct IMXGPIOState {
- /*< private >*/
- SysBusDevice parent_obj;
-
- /*< public >*/
- MemoryRegion iomem;
-
- uint32_t dr;
- uint32_t gdir;
- uint32_t psr;
- uint64_t icr;
- uint32_t imr;
- uint32_t isr;
- bool has_edge_sel;
- uint32_t edge_sel;
- bool has_upper_pin_irq;
-
- qemu_irq irq[2];
- qemu_irq output[IMX_GPIO_PIN_COUNT];
-};
-
-#endif /* IMX_GPIO_H */
+++ /dev/null
-/*
- * Nuvoton NPCM7xx General Purpose Input / Output (GPIO)
- *
- * Copyright 2020 Google LLC
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * version 2 as published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-#ifndef NPCM7XX_GPIO_H
-#define NPCM7XX_GPIO_H
-
-#include "exec/memory.h"
-#include "hw/sysbus.h"
-
-/* Number of pins managed by each controller. */
-#define NPCM7XX_GPIO_NR_PINS (32)
-
-/*
- * Number of registers in our device state structure. Don't change this without
- * incrementing the version_id in the vmstate.
- */
-#define NPCM7XX_GPIO_NR_REGS (0x80 / sizeof(uint32_t))
-
-typedef struct NPCM7xxGPIOState {
- SysBusDevice parent;
-
- /* Properties to be defined by the SoC */
- uint32_t reset_pu;
- uint32_t reset_pd;
- uint32_t reset_osrc;
- uint32_t reset_odsc;
-
- MemoryRegion mmio;
-
- qemu_irq irq;
- qemu_irq output[NPCM7XX_GPIO_NR_PINS];
-
- uint32_t pin_level;
- uint32_t ext_level;
- uint32_t ext_driven;
-
- uint32_t regs[NPCM7XX_GPIO_NR_REGS];
-} NPCM7xxGPIOState;
-
-#define TYPE_NPCM7XX_GPIO "npcm7xx-gpio"
-#define NPCM7XX_GPIO(obj) \
- OBJECT_CHECK(NPCM7xxGPIOState, (obj), TYPE_NPCM7XX_GPIO)
-
-#endif /* NPCM7XX_GPIO_H */
+++ /dev/null
-/*
- * nRF51 System-on-Chip general purpose input/output register definition
- *
- * QEMU interface:
- * + sysbus MMIO regions 0: GPIO registers
- * + Unnamed GPIO inputs 0-31: Set tri-state input level for GPIO pin.
- * Level -1: Externally Disconnected/Floating; Pull-up/down will be regarded
- * Level 0: Input externally driven LOW
- * Level 1: Input externally driven HIGH
- * + Unnamed GPIO outputs 0-31:
- * Level -1: Disconnected/Floating
- * Level 0: Driven LOW
- * Level 1: Driven HIGH
- *
- * Accuracy of the peripheral model:
- * + The nRF51 GPIO output driver supports two modes, standard and high-current
- * mode. These different drive modes are not modeled and handled the same.
- * + Pin SENSEing is not modeled/implemented.
- *
- * Copyright 2018 Steffen Görtz <contrib@steffen-goertz.de>
- *
- * This code is licensed under the GPL version 2 or later. See
- * the COPYING file in the top-level directory.
- *
- */
-#ifndef NRF51_GPIO_H
-#define NRF51_GPIO_H
-
-#include "hw/sysbus.h"
-#include "qom/object.h"
-#define TYPE_NRF51_GPIO "nrf51_soc.gpio"
-OBJECT_DECLARE_SIMPLE_TYPE(NRF51GPIOState, NRF51_GPIO)
-
-#define NRF51_GPIO_PINS 32
-
-#define NRF51_GPIO_SIZE 0x1000
-
-#define NRF51_GPIO_REG_OUT 0x504
-#define NRF51_GPIO_REG_OUTSET 0x508
-#define NRF51_GPIO_REG_OUTCLR 0x50C
-#define NRF51_GPIO_REG_IN 0x510
-#define NRF51_GPIO_REG_DIR 0x514
-#define NRF51_GPIO_REG_DIRSET 0x518
-#define NRF51_GPIO_REG_DIRCLR 0x51C
-#define NRF51_GPIO_REG_CNF_START 0x700
-#define NRF51_GPIO_REG_CNF_END 0x77C
-
-#define NRF51_GPIO_PULLDOWN 1
-#define NRF51_GPIO_PULLUP 3
-
-struct NRF51GPIOState {
- SysBusDevice parent_obj;
-
- MemoryRegion mmio;
- qemu_irq irq;
-
- uint32_t out;
- uint32_t in;
- uint32_t in_mask;
- uint32_t dir;
- uint32_t cnf[NRF51_GPIO_PINS];
-
- uint32_t old_out;
- uint32_t old_out_connected;
-
- qemu_irq output[NRF51_GPIO_PINS];
-};
-
-
-#endif
+++ /dev/null
-/*
- * SiFive System-on-Chip general purpose input/output register definition
- *
- * Copyright 2019 AdaCore
- *
- * Base on nrf51_gpio.c:
- *
- * Copyright 2018 Steffen Görtz <contrib@steffen-goertz.de>
- *
- * This code is licensed under the GPL version 2 or later. See
- * the COPYING file in the top-level directory.
- */
-
-#ifndef SIFIVE_GPIO_H
-#define SIFIVE_GPIO_H
-
-#include "hw/sysbus.h"
-#include "qom/object.h"
-
-#define TYPE_SIFIVE_GPIO "sifive_soc.gpio"
-typedef struct SIFIVEGPIOState SIFIVEGPIOState;
-DECLARE_INSTANCE_CHECKER(SIFIVEGPIOState, SIFIVE_GPIO,
- TYPE_SIFIVE_GPIO)
-
-#define SIFIVE_GPIO_PINS 32
-
-#define SIFIVE_GPIO_SIZE 0x100
-
-#define SIFIVE_GPIO_REG_VALUE 0x000
-#define SIFIVE_GPIO_REG_INPUT_EN 0x004
-#define SIFIVE_GPIO_REG_OUTPUT_EN 0x008
-#define SIFIVE_GPIO_REG_PORT 0x00C
-#define SIFIVE_GPIO_REG_PUE 0x010
-#define SIFIVE_GPIO_REG_DS 0x014
-#define SIFIVE_GPIO_REG_RISE_IE 0x018
-#define SIFIVE_GPIO_REG_RISE_IP 0x01C
-#define SIFIVE_GPIO_REG_FALL_IE 0x020
-#define SIFIVE_GPIO_REG_FALL_IP 0x024
-#define SIFIVE_GPIO_REG_HIGH_IE 0x028
-#define SIFIVE_GPIO_REG_HIGH_IP 0x02C
-#define SIFIVE_GPIO_REG_LOW_IE 0x030
-#define SIFIVE_GPIO_REG_LOW_IP 0x034
-#define SIFIVE_GPIO_REG_IOF_EN 0x038
-#define SIFIVE_GPIO_REG_IOF_SEL 0x03C
-#define SIFIVE_GPIO_REG_OUT_XOR 0x040
-
-struct SIFIVEGPIOState {
- SysBusDevice parent_obj;
-
- MemoryRegion mmio;
-
- qemu_irq irq[SIFIVE_GPIO_PINS];
- qemu_irq output[SIFIVE_GPIO_PINS];
-
- uint32_t value; /* Actual value of the pin */
- uint32_t input_en;
- uint32_t output_en;
- uint32_t port; /* Pin value requested by the user */
- uint32_t pue;
- uint32_t ds;
- uint32_t rise_ie;
- uint32_t rise_ip;
- uint32_t fall_ie;
- uint32_t fall_ip;
- uint32_t high_ie;
- uint32_t high_ip;
- uint32_t low_ie;
- uint32_t low_ip;
- uint32_t iof_en;
- uint32_t iof_sel;
- uint32_t out_xor;
- uint32_t in;
- uint32_t in_mask;
-
- /* config */
- uint32_t ngpio;
-};
-
-#endif /* SIFIVE_GPIO_H */
+++ /dev/null
-/*
- * Definitions for Hyper-V guest/hypervisor interaction
- *
- * Copyright (c) 2017-2018 Virtuozzo International GmbH.
- *
- * This work is licensed under the terms of the GNU GPL, version 2 or later.
- * See the COPYING file in the top-level directory.
- */
-
-#ifndef HW_HYPERV_HYPERV_PROTO_H
-#define HW_HYPERV_HYPERV_PROTO_H
-
-#include "qemu/bitmap.h"
-
-/*
- * Hypercall status code
- */
-#define HV_STATUS_SUCCESS 0
-#define HV_STATUS_INVALID_HYPERCALL_CODE 2
-#define HV_STATUS_INVALID_HYPERCALL_INPUT 3
-#define HV_STATUS_INVALID_ALIGNMENT 4
-#define HV_STATUS_INVALID_PARAMETER 5
-#define HV_STATUS_INSUFFICIENT_MEMORY 11
-#define HV_STATUS_INVALID_PORT_ID 17
-#define HV_STATUS_INVALID_CONNECTION_ID 18
-#define HV_STATUS_INSUFFICIENT_BUFFERS 19
-
-/*
- * Hypercall numbers
- */
-#define HV_POST_MESSAGE 0x005c
-#define HV_SIGNAL_EVENT 0x005d
-#define HV_HYPERCALL_FAST (1u << 16)
-
-/*
- * Message size
- */
-#define HV_MESSAGE_PAYLOAD_SIZE 240
-
-/*
- * Message types
- */
-#define HV_MESSAGE_NONE 0x00000000
-#define HV_MESSAGE_VMBUS 0x00000001
-#define HV_MESSAGE_UNMAPPED_GPA 0x80000000
-#define HV_MESSAGE_GPA_INTERCEPT 0x80000001
-#define HV_MESSAGE_TIMER_EXPIRED 0x80000010
-#define HV_MESSAGE_INVALID_VP_REGISTER_VALUE 0x80000020
-#define HV_MESSAGE_UNRECOVERABLE_EXCEPTION 0x80000021
-#define HV_MESSAGE_UNSUPPORTED_FEATURE 0x80000022
-#define HV_MESSAGE_EVENTLOG_BUFFERCOMPLETE 0x80000040
-#define HV_MESSAGE_X64_IOPORT_INTERCEPT 0x80010000
-#define HV_MESSAGE_X64_MSR_INTERCEPT 0x80010001
-#define HV_MESSAGE_X64_CPUID_INTERCEPT 0x80010002
-#define HV_MESSAGE_X64_EXCEPTION_INTERCEPT 0x80010003
-#define HV_MESSAGE_X64_APIC_EOI 0x80010004
-#define HV_MESSAGE_X64_LEGACY_FP_ERROR 0x80010005
-
-/*
- * Message flags
- */
-#define HV_MESSAGE_FLAG_PENDING 0x1
-
-/*
- * Number of synthetic interrupts
- */
-#define HV_SINT_COUNT 16
-
-/*
- * Event flags number per SINT
- */
-#define HV_EVENT_FLAGS_COUNT (256 * 8)
-
-/*
- * Connection id valid bits
- */
-#define HV_CONNECTION_ID_MASK 0x00ffffff
-
-/*
- * Input structure for POST_MESSAGE hypercall
- */
-struct hyperv_post_message_input {
- uint32_t connection_id;
- uint32_t _reserved;
- uint32_t message_type;
- uint32_t payload_size;
- uint8_t payload[HV_MESSAGE_PAYLOAD_SIZE];
-};
-
-/*
- * Input structure for SIGNAL_EVENT hypercall
- */
-struct hyperv_signal_event_input {
- uint32_t connection_id;
- uint16_t flag_number;
- uint16_t _reserved_zero;
-};
-
-/*
- * SynIC message structures
- */
-struct hyperv_message_header {
- uint32_t message_type;
- uint8_t payload_size;
- uint8_t message_flags; /* HV_MESSAGE_FLAG_XX */
- uint8_t _reserved[2];
- uint64_t sender;
-};
-
-struct hyperv_message {
- struct hyperv_message_header header;
- uint8_t payload[HV_MESSAGE_PAYLOAD_SIZE];
-};
-
-struct hyperv_message_page {
- struct hyperv_message slot[HV_SINT_COUNT];
-};
-
-/*
- * SynIC event flags structures
- */
-struct hyperv_event_flags {
- DECLARE_BITMAP(flags, HV_EVENT_FLAGS_COUNT);
-};
-
-struct hyperv_event_flags_page {
- struct hyperv_event_flags slot[HV_SINT_COUNT];
-};
-
-#endif
+++ /dev/null
-/*
- * Hyper-V guest/hypervisor interaction
- *
- * Copyright (c) 2015-2018 Virtuozzo International GmbH.
- *
- * This work is licensed under the terms of the GNU GPL, version 2 or later.
- * See the COPYING file in the top-level directory.
- */
-
-#ifndef HW_HYPERV_HYPERV_H
-#define HW_HYPERV_HYPERV_H
-
-#include "cpu-qom.h"
-#include "hw/hyperv/hyperv-proto.h"
-
-typedef struct HvSintRoute HvSintRoute;
-
-/*
- * Callback executed in a bottom-half when the status of posting the message
- * becomes known, before unblocking the connection for further messages
- */
-typedef void (*HvSintMsgCb)(void *data, int status);
-
-HvSintRoute *hyperv_sint_route_new(uint32_t vp_index, uint32_t sint,
- HvSintMsgCb cb, void *cb_data);
-void hyperv_sint_route_ref(HvSintRoute *sint_route);
-void hyperv_sint_route_unref(HvSintRoute *sint_route);
-
-int hyperv_sint_route_set_sint(HvSintRoute *sint_route);
-
-/*
- * Submit a message to be posted in vcpu context. If the submission succeeds,
- * the status of posting the message is reported via the callback associated
- * with the @sint_route; until then no more messages are accepted.
- */
-int hyperv_post_msg(HvSintRoute *sint_route, struct hyperv_message *msg);
-/*
- * Set event flag @eventno, and signal the SINT if the flag has changed.
- */
-int hyperv_set_event_flag(HvSintRoute *sint_route, unsigned eventno);
-
-/*
- * Handler for messages arriving from the guest via HV_POST_MESSAGE hypercall.
- * Executed in vcpu context.
- */
-typedef uint16_t (*HvMsgHandler)(const struct hyperv_post_message_input *msg,
- void *data);
-/*
- * Associate @handler with the message connection @conn_id, such that @handler
- * is called with @data when the guest executes HV_POST_MESSAGE hypercall on
- * @conn_id. If @handler is NULL clear the association.
- */
-int hyperv_set_msg_handler(uint32_t conn_id, HvMsgHandler handler, void *data);
-/*
- * Associate @notifier with the event connection @conn_id, such that @notifier
- * is signaled when the guest executes HV_SIGNAL_EVENT hypercall on @conn_id.
- * If @notifier is NULL clear the association.
- */
-int hyperv_set_event_flag_handler(uint32_t conn_id, EventNotifier *notifier);
-
-/*
- * Process HV_POST_MESSAGE hypercall: parse the data in the guest memory as
- * specified in @param, and call the HvMsgHandler associated with the
- * connection on the message contained therein.
- */
-uint16_t hyperv_hcall_post_message(uint64_t param, bool fast);
-/*
- * Process HV_SIGNAL_EVENT hypercall: signal the EventNotifier associated with
- * the connection as specified in @param.
- */
-uint16_t hyperv_hcall_signal_event(uint64_t param, bool fast);
-
-static inline uint32_t hyperv_vp_index(CPUState *cs)
-{
- return cs->cpu_index;
-}
-
-void hyperv_synic_add(CPUState *cs);
-void hyperv_synic_reset(CPUState *cs);
-void hyperv_synic_update(CPUState *cs, bool enable,
- hwaddr msg_page_addr, hwaddr event_page_addr);
-bool hyperv_is_synic_enabled(void);
-
-#endif
+++ /dev/null
-/*
- * QEMU Hyper-V VMBus root bridge
- *
- * Copyright (c) 2017-2018 Virtuozzo International GmbH.
- *
- * This work is licensed under the terms of the GNU GPL, version 2 or later.
- * See the COPYING file in the top-level directory.
- */
-
-#ifndef HW_HYPERV_VMBUS_BRIDGE_H
-#define HW_HYPERV_VMBUS_BRIDGE_H
-
-#include "hw/sysbus.h"
-#include "hw/hyperv/vmbus.h"
-#include "qom/object.h"
-
-#define TYPE_VMBUS_BRIDGE "vmbus-bridge"
-
-struct VMBusBridge {
- SysBusDevice parent_obj;
-
- uint8_t irq;
-
- VMBus *bus;
-};
-
-OBJECT_DECLARE_SIMPLE_TYPE(VMBusBridge, VMBUS_BRIDGE)
-
-static inline VMBusBridge *vmbus_bridge_find(void)
-{
- return VMBUS_BRIDGE(object_resolve_path_type("", TYPE_VMBUS_BRIDGE, NULL));
-}
-
-#endif
+++ /dev/null
-/*
- * QEMU Hyper-V VMBus support
- *
- * Copyright (c) 2017-2018 Virtuozzo International GmbH.
- *
- * This work is licensed under the terms of the GNU GPL, version 2 or later.
- * See the COPYING file in the top-level directory.
- */
-
-#ifndef HW_HYPERV_VMBUS_PROTO_H
-#define HW_HYPERV_VMBUS_PROTO_H
-
-#define VMBUS_VERSION_WS2008 ((0 << 16) | (13))
-#define VMBUS_VERSION_WIN7 ((1 << 16) | (1))
-#define VMBUS_VERSION_WIN8 ((2 << 16) | (4))
-#define VMBUS_VERSION_WIN8_1 ((3 << 16) | (0))
-#define VMBUS_VERSION_WIN10 ((4 << 16) | (0))
-#define VMBUS_VERSION_INVAL -1
-#define VMBUS_VERSION_CURRENT VMBUS_VERSION_WIN10
-
-#define VMBUS_MESSAGE_CONNECTION_ID 1
-#define VMBUS_EVENT_CONNECTION_ID 2
-#define VMBUS_MONITOR_CONNECTION_ID 3
-#define VMBUS_SINT 2
-
-#define VMBUS_MSG_INVALID 0
-#define VMBUS_MSG_OFFERCHANNEL 1
-#define VMBUS_MSG_RESCIND_CHANNELOFFER 2
-#define VMBUS_MSG_REQUESTOFFERS 3
-#define VMBUS_MSG_ALLOFFERS_DELIVERED 4
-#define VMBUS_MSG_OPENCHANNEL 5
-#define VMBUS_MSG_OPENCHANNEL_RESULT 6
-#define VMBUS_MSG_CLOSECHANNEL 7
-#define VMBUS_MSG_GPADL_HEADER 8
-#define VMBUS_MSG_GPADL_BODY 9
-#define VMBUS_MSG_GPADL_CREATED 10
-#define VMBUS_MSG_GPADL_TEARDOWN 11
-#define VMBUS_MSG_GPADL_TORNDOWN 12
-#define VMBUS_MSG_RELID_RELEASED 13
-#define VMBUS_MSG_INITIATE_CONTACT 14
-#define VMBUS_MSG_VERSION_RESPONSE 15
-#define VMBUS_MSG_UNLOAD 16
-#define VMBUS_MSG_UNLOAD_RESPONSE 17
-#define VMBUS_MSG_COUNT 18
-
-#define VMBUS_MESSAGE_SIZE_ALIGN sizeof(uint64_t)
-
-#define VMBUS_PACKET_INVALID 0x0
-#define VMBUS_PACKET_SYNCH 0x1
-#define VMBUS_PACKET_ADD_XFER_PAGESET 0x2
-#define VMBUS_PACKET_RM_XFER_PAGESET 0x3
-#define VMBUS_PACKET_ESTABLISH_GPADL 0x4
-#define VMBUS_PACKET_TEARDOWN_GPADL 0x5
-#define VMBUS_PACKET_DATA_INBAND 0x6
-#define VMBUS_PACKET_DATA_USING_XFER_PAGES 0x7
-#define VMBUS_PACKET_DATA_USING_GPADL 0x8
-#define VMBUS_PACKET_DATA_USING_GPA_DIRECT 0x9
-#define VMBUS_PACKET_CANCEL_REQUEST 0xa
-#define VMBUS_PACKET_COMP 0xb
-#define VMBUS_PACKET_DATA_USING_ADDITIONAL_PKT 0xc
-#define VMBUS_PACKET_ADDITIONAL_DATA 0xd
-
-#define VMBUS_CHANNEL_USER_DATA_SIZE 120
-
-#define VMBUS_OFFER_MONITOR_ALLOCATED 0x1
-#define VMBUS_OFFER_INTERRUPT_DEDICATED 0x1
-
-#define VMBUS_RING_BUFFER_FEAT_PENDING_SZ (1ul << 0)
-
-#define VMBUS_CHANNEL_ENUMERATE_DEVICE_INTERFACE 0x1
-#define VMBUS_CHANNEL_SERVER_SUPPORTS_TRANSFER_PAGES 0x2
-#define VMBUS_CHANNEL_SERVER_SUPPORTS_GPADLS 0x4
-#define VMBUS_CHANNEL_NAMED_PIPE_MODE 0x10
-#define VMBUS_CHANNEL_LOOPBACK_OFFER 0x100
-#define VMBUS_CHANNEL_PARENT_OFFER 0x200
-#define VMBUS_CHANNEL_REQUEST_MONITORED_NOTIFICATION 0x400
-#define VMBUS_CHANNEL_TLNPI_PROVIDER_OFFER 0x2000
-
-#define VMBUS_PACKET_FLAG_REQUEST_COMPLETION 1
-
-typedef struct vmbus_message_header {
- uint32_t message_type;
- uint32_t _padding;
-} vmbus_message_header;
-
-typedef struct vmbus_message_initiate_contact {
- vmbus_message_header header;
- uint32_t version_requested;
- uint32_t target_vcpu;
- uint64_t interrupt_page;
- uint64_t monitor_page1;
- uint64_t monitor_page2;
-} vmbus_message_initiate_contact;
-
-typedef struct vmbus_message_version_response {
- vmbus_message_header header;
- uint8_t version_supported;
- uint8_t status;
-} vmbus_message_version_response;
-
-typedef struct vmbus_message_offer_channel {
- vmbus_message_header header;
- uint8_t type_uuid[16];
- uint8_t instance_uuid[16];
- uint64_t _reserved1;
- uint64_t _reserved2;
- uint16_t channel_flags;
- uint16_t mmio_size_mb;
- uint8_t user_data[VMBUS_CHANNEL_USER_DATA_SIZE];
- uint16_t sub_channel_index;
- uint16_t _reserved3;
- uint32_t child_relid;
- uint8_t monitor_id;
- uint8_t monitor_flags;
- uint16_t interrupt_flags;
- uint32_t connection_id;
-} vmbus_message_offer_channel;
-
-typedef struct vmbus_message_rescind_channel_offer {
- vmbus_message_header header;
- uint32_t child_relid;
-} vmbus_message_rescind_channel_offer;
-
-typedef struct vmbus_gpa_range {
- uint32_t byte_count;
- uint32_t byte_offset;
- uint64_t pfn_array[];
-} vmbus_gpa_range;
-
-typedef struct vmbus_message_gpadl_header {
- vmbus_message_header header;
- uint32_t child_relid;
- uint32_t gpadl_id;
- uint16_t range_buflen;
- uint16_t rangecount;
- vmbus_gpa_range range[];
-} QEMU_PACKED vmbus_message_gpadl_header;
-
-typedef struct vmbus_message_gpadl_body {
- vmbus_message_header header;
- uint32_t message_number;
- uint32_t gpadl_id;
- uint64_t pfn_array[];
-} vmbus_message_gpadl_body;
-
-typedef struct vmbus_message_gpadl_created {
- vmbus_message_header header;
- uint32_t child_relid;
- uint32_t gpadl_id;
- uint32_t status;
-} vmbus_message_gpadl_created;
-
-typedef struct vmbus_message_gpadl_teardown {
- vmbus_message_header header;
- uint32_t child_relid;
- uint32_t gpadl_id;
-} vmbus_message_gpadl_teardown;
-
-typedef struct vmbus_message_gpadl_torndown {
- vmbus_message_header header;
- uint32_t gpadl_id;
-} vmbus_message_gpadl_torndown;
-
-typedef struct vmbus_message_open_channel {
- vmbus_message_header header;
- uint32_t child_relid;
- uint32_t open_id;
- uint32_t ring_buffer_gpadl_id;
- uint32_t target_vp;
- uint32_t ring_buffer_offset;
- uint8_t user_data[VMBUS_CHANNEL_USER_DATA_SIZE];
-} vmbus_message_open_channel;
-
-typedef struct vmbus_message_open_result {
- vmbus_message_header header;
- uint32_t child_relid;
- uint32_t open_id;
- uint32_t status;
-} vmbus_message_open_result;
-
-typedef struct vmbus_message_close_channel {
- vmbus_message_header header;
- uint32_t child_relid;
-} vmbus_message_close_channel;
-
-typedef struct vmbus_ring_buffer {
- uint32_t write_index;
- uint32_t read_index;
- uint32_t interrupt_mask;
- uint32_t pending_send_sz;
- uint32_t _reserved1[12];
- uint32_t feature_bits;
-} vmbus_ring_buffer;
-
-typedef struct vmbus_packet_hdr {
- uint16_t type;
- uint16_t offset_qwords;
- uint16_t len_qwords;
- uint16_t flags;
- uint64_t transaction_id;
-} vmbus_packet_hdr;
-
-typedef struct vmbus_pkt_gpa_direct {
- uint32_t _reserved;
- uint32_t rangecount;
- vmbus_gpa_range range[];
-} vmbus_pkt_gpa_direct;
-
-typedef struct vmbus_xferpg_range {
- uint32_t byte_count;
- uint32_t byte_offset;
-} vmbus_xferpg_range;
-
-typedef struct vmbus_pkt_xferpg {
- uint16_t buffer_id;
- uint8_t sender_owns_set;
- uint8_t _reserved;
- uint32_t rangecount;
- vmbus_xferpg_range range[];
-} vmbus_pkt_xferpg;
-
-#endif
+++ /dev/null
-/*
- * QEMU Hyper-V VMBus
- *
- * Copyright (c) 2017-2018 Virtuozzo International GmbH.
- *
- * This work is licensed under the terms of the GNU GPL, version 2 or later.
- * See the COPYING file in the top-level directory.
- */
-
-#ifndef HW_HYPERV_VMBUS_H
-#define HW_HYPERV_VMBUS_H
-
-#include "sysemu/sysemu.h"
-#include "sysemu/dma.h"
-#include "hw/qdev-core.h"
-#include "migration/vmstate.h"
-#include "hw/hyperv/vmbus-proto.h"
-#include "qemu/uuid.h"
-#include "qom/object.h"
-
-#define TYPE_VMBUS_DEVICE "vmbus-dev"
-
-OBJECT_DECLARE_TYPE(VMBusDevice, VMBusDeviceClass,
- VMBUS_DEVICE)
-
-#define TYPE_VMBUS "vmbus"
-OBJECT_DECLARE_SIMPLE_TYPE(VMBus, VMBUS)
-
-/*
- * Object wrapping a GPADL -- GPA Descriptor List -- an array of guest physical
- * pages, to be used for various buffers shared between the host and the guest.
- */
-typedef struct VMBusGpadl VMBusGpadl;
-/*
- * VMBus channel -- a pair of ring buffers for either direction, placed within
- * one GPADL, and the associated notification means.
- */
-typedef struct VMBusChannel VMBusChannel;
-/*
- * Base class for VMBus devices. Includes one or more channels. Identified by
- * class GUID and instance GUID.
- */
-
-typedef void(*VMBusChannelNotifyCb)(struct VMBusChannel *chan);
-
-struct VMBusDeviceClass {
- DeviceClass parent;
-
- QemuUUID classid;
- QemuUUID instanceid; /* Fixed UUID for singleton devices */
- uint16_t channel_flags;
- uint16_t mmio_size_mb;
-
- /* Extentions to standard device callbacks */
- void (*vmdev_realize)(VMBusDevice *vdev, Error **errp);
- void (*vmdev_unrealize)(VMBusDevice *vdev);
- void (*vmdev_reset)(VMBusDevice *vdev);
- /*
- * Calculate the number of channels based on the device properties. Called
- * at realize time.
- **/
- uint16_t (*num_channels)(VMBusDevice *vdev);
- /*
- * Device-specific actions to complete the otherwise successful process of
- * opening a channel.
- * Return 0 on success, -errno on failure.
- */
- int (*open_channel)(VMBusChannel *chan);
- /*
- * Device-specific actions to perform before closing a channel.
- */
- void (*close_channel)(VMBusChannel *chan);
- /*
- * Main device worker; invoked in response to notifications from either
- * side, when there's work to do with the data in the channel ring buffers.
- */
- VMBusChannelNotifyCb chan_notify_cb;
-};
-
-struct VMBusDevice {
- DeviceState parent;
- QemuUUID instanceid;
- uint16_t num_channels;
- VMBusChannel *channels;
- AddressSpace *dma_as;
-};
-
-extern const VMStateDescription vmstate_vmbus_dev;
-
-/*
- * A unit of work parsed out of a message in the receive (i.e. guest->host)
- * ring buffer of a channel. It's supposed to be subclassed (through
- * embedding) by the specific devices.
- */
-typedef struct VMBusChanReq {
- VMBusChannel *chan;
- uint16_t pkt_type;
- uint32_t msglen;
- void *msg;
- uint64_t transaction_id;
- bool need_comp;
- QEMUSGList sgl;
-} VMBusChanReq;
-
-VMBusDevice *vmbus_channel_device(VMBusChannel *chan);
-VMBusChannel *vmbus_device_channel(VMBusDevice *dev, uint32_t chan_idx);
-uint32_t vmbus_channel_idx(VMBusChannel *chan);
-bool vmbus_channel_is_open(VMBusChannel *chan);
-
-/*
- * Notify (on guest's behalf) the host side of the channel that there's data in
- * the ringbuffer to process.
- */
-void vmbus_channel_notify_host(VMBusChannel *chan);
-
-/*
- * Reserve space for a packet in the send (i.e. host->guest) ringbuffer. If
- * there isn't enough room, indicate that to the guest, to be notified when it
- * becomes available.
- * Return 0 on success, negative errno on failure.
- * The ringbuffer indices are NOT updated, the requested space indicator may.
- */
-int vmbus_channel_reserve(VMBusChannel *chan,
- uint32_t desclen, uint32_t msglen);
-
-/*
- * Send a packet to the guest. The space for the packet MUST be reserved
- * first.
- * Return total number of bytes placed in the send ringbuffer on success,
- * negative errno on failure.
- * The ringbuffer indices are updated on success, and the guest is signaled if
- * needed.
- */
-ssize_t vmbus_channel_send(VMBusChannel *chan, uint16_t pkt_type,
- void *desc, uint32_t desclen,
- void *msg, uint32_t msglen,
- bool need_comp, uint64_t transaction_id);
-
-/*
- * Prepare to fetch a batch of packets from the receive ring buffer.
- * Return 0 on success, negative errno on failure.
- */
-int vmbus_channel_recv_start(VMBusChannel *chan);
-
-/*
- * Shortcut for a common case of sending a simple completion packet with no
- * auxiliary descriptors.
- */
-ssize_t vmbus_channel_send_completion(VMBusChanReq *req,
- void *msg, uint32_t msglen);
-
-/*
- * Peek at the receive (i.e. guest->host) ring buffer and extract a unit of
- * work (a device-specific subclass of VMBusChanReq) from a packet if there's
- * one.
- * Return an allocated buffer, containing the request of @size with filled
- * VMBusChanReq at the beginning, followed by the message payload, or NULL on
- * failure.
- * The ringbuffer indices are NOT updated, nor is the private copy of the read
- * index.
- */
-void *vmbus_channel_recv_peek(VMBusChannel *chan, uint32_t size);
-
-/*
- * Update the private copy of the read index once the preceding peek is deemed
- * successful.
- * The ringbuffer indices are NOT updated.
- */
-void vmbus_channel_recv_pop(VMBusChannel *chan);
-
-/*
- * Propagate the private copy of the read index into the receive ring buffer,
- * and thus complete the reception of a series of packets. Notify guest if
- * needed.
- * Return the number of bytes popped off the receive ring buffer by the
- * preceding recv_peek/recv_pop calls on success, negative errno on failure.
- */
-ssize_t vmbus_channel_recv_done(VMBusChannel *chan);
-
-/*
- * Free the request allocated by vmbus_channel_recv_peek, together with its
- * fields.
- */
-void vmbus_free_req(void *req);
-
-/*
- * Find and reference a GPADL by @gpadl_id.
- * If not found return NULL.
- */
-VMBusGpadl *vmbus_get_gpadl(VMBusChannel *chan, uint32_t gpadl_id);
-
-/*
- * Unreference @gpadl. If the reference count drops to zero, free it.
- * @gpadl may be NULL, in which case nothing is done.
- */
-void vmbus_put_gpadl(VMBusGpadl *gpadl);
-
-/*
- * Calculate total length in bytes of @gpadl.
- * @gpadl must be valid.
- */
-uint32_t vmbus_gpadl_len(VMBusGpadl *gpadl);
-
-/*
- * Copy data from @iov to @gpadl at offset @off.
- * Return the number of bytes copied, or a negative status on failure.
- */
-ssize_t vmbus_iov_to_gpadl(VMBusChannel *chan, VMBusGpadl *gpadl, uint32_t off,
- const struct iovec *iov, size_t iov_cnt);
-
-/*
- * Map SGList contained in the request @req, at offset @off and no more than
- * @len bytes, for io in direction @dir, and populate @iov with the mapped
- * iovecs.
- * Return the number of iovecs mapped, or negative status on failure.
- */
-int vmbus_map_sgl(VMBusChanReq *req, DMADirection dir, struct iovec *iov,
- unsigned iov_cnt, size_t len, size_t off);
-
-/*
- * Unmap *iov mapped with vmbus_map_sgl, marking the number of bytes @accessed.
- */
-void vmbus_unmap_sgl(VMBusChanReq *req, DMADirection dir, struct iovec *iov,
- unsigned iov_cnt, size_t accessed);
-
-void vmbus_save_req(QEMUFile *f, VMBusChanReq *req);
-void *vmbus_load_req(QEMUFile *f, VMBusDevice *dev, uint32_t size);
-
-#endif
+++ /dev/null
-/*
- * ARM SBCon two-wire serial bus interface (I2C bitbang)
- * a.k.a.
- * ARM Versatile I2C controller
- *
- * Copyright (c) 2006-2007 CodeSourcery.
- * Copyright (c) 2012 Oskar Andero <oskar.andero@gmail.com>
- * Copyright (C) 2020 Philippe Mathieu-Daudé <f4bug@amsat.org>
- *
- * SPDX-License-Identifier: GPL-2.0-or-later
- */
-#ifndef HW_I2C_ARM_SBCON_H
-#define HW_I2C_ARM_SBCON_H
-
-#include "hw/sysbus.h"
-#include "hw/i2c/bitbang_i2c.h"
-#include "qom/object.h"
-
-#define TYPE_VERSATILE_I2C "versatile_i2c"
-#define TYPE_ARM_SBCON_I2C TYPE_VERSATILE_I2C
-
-typedef struct ArmSbconI2CState ArmSbconI2CState;
-DECLARE_INSTANCE_CHECKER(ArmSbconI2CState, ARM_SBCON_I2C,
- TYPE_ARM_SBCON_I2C)
-
-struct ArmSbconI2CState {
- /*< private >*/
- SysBusDevice parent_obj;
- /*< public >*/
-
- MemoryRegion iomem;
- bitbang_i2c_interface bitbang;
- int out;
- int in;
-};
-
-#endif /* HW_I2C_ARM_SBCON_H */
+++ /dev/null
-/*
- * ASPEED AST2400 I2C Controller
- *
- * Copyright (C) 2016 IBM Corp.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License along
- * with this program; if not, write to the Free Software Foundation, Inc.,
- * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
- */
-
-#ifndef ASPEED_I2C_H
-#define ASPEED_I2C_H
-
-#include "hw/i2c/i2c.h"
-#include "hw/sysbus.h"
-#include "qom/object.h"
-
-#define TYPE_ASPEED_I2C "aspeed.i2c"
-#define TYPE_ASPEED_2400_I2C TYPE_ASPEED_I2C "-ast2400"
-#define TYPE_ASPEED_2500_I2C TYPE_ASPEED_I2C "-ast2500"
-#define TYPE_ASPEED_2600_I2C TYPE_ASPEED_I2C "-ast2600"
-OBJECT_DECLARE_TYPE(AspeedI2CState, AspeedI2CClass, ASPEED_I2C)
-
-#define ASPEED_I2C_NR_BUSSES 16
-#define ASPEED_I2C_MAX_POOL_SIZE 0x800
-
-struct AspeedI2CState;
-
-typedef struct AspeedI2CBus {
- struct AspeedI2CState *controller;
-
- MemoryRegion mr;
-
- I2CBus *bus;
- uint8_t id;
- qemu_irq irq;
-
- uint32_t ctrl;
- uint32_t timing[2];
- uint32_t intr_ctrl;
- uint32_t intr_status;
- uint32_t cmd;
- uint32_t buf;
- uint32_t pool_ctrl;
- uint32_t dma_addr;
- uint32_t dma_len;
-} AspeedI2CBus;
-
-struct AspeedI2CState {
- SysBusDevice parent_obj;
-
- MemoryRegion iomem;
- qemu_irq irq;
-
- uint32_t intr_status;
- uint32_t ctrl_global;
- MemoryRegion pool_iomem;
- uint8_t pool[ASPEED_I2C_MAX_POOL_SIZE];
-
- AspeedI2CBus busses[ASPEED_I2C_NR_BUSSES];
- MemoryRegion *dram_mr;
- AddressSpace dram_as;
-};
-
-
-struct AspeedI2CClass {
- SysBusDeviceClass parent_class;
-
- uint8_t num_busses;
- uint8_t reg_size;
- uint8_t gap;
- qemu_irq (*bus_get_irq)(AspeedI2CBus *);
-
- uint64_t pool_size;
- hwaddr pool_base;
- uint8_t *(*bus_pool_base)(AspeedI2CBus *);
- bool check_sram;
- bool has_dma;
-
-};
-
-I2CBus *aspeed_i2c_get_bus(AspeedI2CState *s, int busnr);
-
-#endif /* ASPEED_I2C_H */
+++ /dev/null
-#ifndef BITBANG_I2C_H
-#define BITBANG_I2C_H
-
-#include "hw/i2c/i2c.h"
-
-typedef struct bitbang_i2c_interface bitbang_i2c_interface;
-
-#define BITBANG_I2C_SDA 0
-#define BITBANG_I2C_SCL 1
-
-typedef enum bitbang_i2c_state {
- STOPPED = 0,
- SENDING_BIT7,
- SENDING_BIT6,
- SENDING_BIT5,
- SENDING_BIT4,
- SENDING_BIT3,
- SENDING_BIT2,
- SENDING_BIT1,
- SENDING_BIT0,
- WAITING_FOR_ACK,
- RECEIVING_BIT7,
- RECEIVING_BIT6,
- RECEIVING_BIT5,
- RECEIVING_BIT4,
- RECEIVING_BIT3,
- RECEIVING_BIT2,
- RECEIVING_BIT1,
- RECEIVING_BIT0,
- SENDING_ACK,
- SENT_NACK
-} bitbang_i2c_state;
-
-struct bitbang_i2c_interface {
- I2CBus *bus;
- bitbang_i2c_state state;
- int last_data;
- int last_clock;
- int device_out;
- uint8_t buffer;
- int current_addr;
-};
-
-/**
- * bitbang_i2c_init: in-place initialize the bitbang_i2c_interface struct
- */
-void bitbang_i2c_init(bitbang_i2c_interface *s, I2CBus *bus);
-int bitbang_i2c_set(bitbang_i2c_interface *i2c, int line, int level);
-
-#endif
+++ /dev/null
-#ifndef QEMU_I2C_H
-#define QEMU_I2C_H
-
-#include "hw/qdev-core.h"
-#include "qom/object.h"
-
-/* The QEMU I2C implementation only supports simple transfers that complete
- immediately. It does not support slave devices that need to be able to
- defer their response (eg. CPU slave interfaces where the data is supplied
- by the device driver in response to an interrupt). */
-
-enum i2c_event {
- I2C_START_RECV,
- I2C_START_SEND,
- I2C_FINISH,
- I2C_NACK /* Masker NACKed a receive byte. */
-};
-
-
-#define TYPE_I2C_SLAVE "i2c-slave"
-OBJECT_DECLARE_TYPE(I2CSlave, I2CSlaveClass,
- I2C_SLAVE)
-
-struct I2CSlaveClass {
- DeviceClass parent_class;
-
- /* Master to slave. Returns non-zero for a NAK, 0 for success. */
- int (*send)(I2CSlave *s, uint8_t data);
-
- /*
- * Slave to master. This cannot fail, the device should always
- * return something here.
- */
- uint8_t (*recv)(I2CSlave *s);
-
- /*
- * Notify the slave of a bus state change. For start event,
- * returns non-zero to NAK an operation. For other events the
- * return code is not used and should be zero.
- */
- int (*event)(I2CSlave *s, enum i2c_event event);
-};
-
-struct I2CSlave {
- DeviceState qdev;
-
- /* Remaining fields for internal use by the I2C code. */
- uint8_t address;
-};
-
-#define TYPE_I2C_BUS "i2c-bus"
-OBJECT_DECLARE_SIMPLE_TYPE(I2CBus, I2C_BUS)
-
-typedef struct I2CNode I2CNode;
-
-struct I2CNode {
- I2CSlave *elt;
- QLIST_ENTRY(I2CNode) next;
-};
-
-struct I2CBus {
- BusState qbus;
- QLIST_HEAD(, I2CNode) current_devs;
- uint8_t saved_address;
- bool broadcast;
-};
-
-I2CBus *i2c_init_bus(DeviceState *parent, const char *name);
-void i2c_set_slave_address(I2CSlave *dev, uint8_t address);
-int i2c_bus_busy(I2CBus *bus);
-int i2c_start_transfer(I2CBus *bus, uint8_t address, int recv);
-void i2c_end_transfer(I2CBus *bus);
-void i2c_nack(I2CBus *bus);
-int i2c_send_recv(I2CBus *bus, uint8_t *data, bool send);
-int i2c_send(I2CBus *bus, uint8_t data);
-uint8_t i2c_recv(I2CBus *bus);
-
-/**
- * Create an I2C slave device on the heap.
- * @name: a device type name
- * @addr: I2C address of the slave when put on a bus
- *
- * This only initializes the device state structure and allows
- * properties to be set. Type @name must exist. The device still
- * needs to be realized. See qdev-core.h.
- */
-I2CSlave *i2c_slave_new(const char *name, uint8_t addr);
-
-/**
- * Create and realize an I2C slave device on the heap.
- * @bus: I2C bus to put it on
- * @name: I2C slave device type name
- * @addr: I2C address of the slave when put on a bus
- *
- * Create the device state structure, initialize it, put it on the
- * specified @bus, and drop the reference to it (the device is realized).
- */
-I2CSlave *i2c_slave_create_simple(I2CBus *bus, const char *name, uint8_t addr);
-
-/**
- * Realize and drop a reference an I2C slave device
- * @dev: I2C slave device to realize
- * @bus: I2C bus to put it on
- * @addr: I2C address of the slave on the bus
- * @errp: pointer to NULL initialized error object
- *
- * Returns: %true on success, %false on failure.
- *
- * Call 'realize' on @dev, put it on the specified @bus, and drop the
- * reference to it.
- *
- * This function is useful if you have created @dev via qdev_new(),
- * i2c_slave_new() or i2c_slave_try_new() (which take a reference to
- * the device it returns to you), so that you can set properties on it
- * before realizing it. If you don't need to set properties then
- * i2c_slave_create_simple() is probably better (as it does the create,
- * init and realize in one step).
- *
- * If you are embedding the I2C slave into another QOM device and
- * initialized it via some variant on object_initialize_child() then
- * do not use this function, because that family of functions arrange
- * for the only reference to the child device to be held by the parent
- * via the child<> property, and so the reference-count-drop done here
- * would be incorrect. (Instead you would want i2c_slave_realize(),
- * which doesn't currently exist but would be trivial to create if we
- * had any code that wanted it.)
- */
-bool i2c_slave_realize_and_unref(I2CSlave *dev, I2CBus *bus, Error **errp);
-
-/* lm832x.c */
-void lm832x_key_event(DeviceState *dev, int key, int state);
-
-extern const VMStateDescription vmstate_i2c_slave;
-
-#define VMSTATE_I2C_SLAVE(_field, _state) { \
- .name = (stringify(_field)), \
- .size = sizeof(I2CSlave), \
- .vmsd = &vmstate_i2c_slave, \
- .flags = VMS_STRUCT, \
- .offset = vmstate_offset_value(_state, _field, I2CSlave), \
-}
-
-#endif
+++ /dev/null
-/*
- * i.MX I2C Bus Serial Interface registers definition
- *
- * Copyright (C) 2013 Jean-Christophe Dubois. <jcd@tribudubois.net>
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License as published by the
- * Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
- * for more details.
- *
- * You should have received a copy of the GNU General Public License along
- * with this program; if not, see <http://www.gnu.org/licenses/>.
- *
- */
-
-#ifndef IMX_I2C_H
-#define IMX_I2C_H
-
-#include "hw/sysbus.h"
-#include "qom/object.h"
-
-#define TYPE_IMX_I2C "imx.i2c"
-OBJECT_DECLARE_SIMPLE_TYPE(IMXI2CState, IMX_I2C)
-
-#define IMX_I2C_MEM_SIZE 0x14
-
-/* i.MX I2C memory map */
-#define IADR_ADDR 0x00 /* address register */
-#define IFDR_ADDR 0x04 /* frequency divider register */
-#define I2CR_ADDR 0x08 /* control register */
-#define I2SR_ADDR 0x0c /* status register */
-#define I2DR_ADDR 0x10 /* data register */
-
-#define IADR_MASK 0xFE
-#define IADR_RESET 0
-
-#define IFDR_MASK 0x3F
-#define IFDR_RESET 0
-
-#define I2CR_IEN (1 << 7)
-#define I2CR_IIEN (1 << 6)
-#define I2CR_MSTA (1 << 5)
-#define I2CR_MTX (1 << 4)
-#define I2CR_TXAK (1 << 3)
-#define I2CR_RSTA (1 << 2)
-#define I2CR_MASK 0xFC
-#define I2CR_RESET 0
-
-#define I2SR_ICF (1 << 7)
-#define I2SR_IAAF (1 << 6)
-#define I2SR_IBB (1 << 5)
-#define I2SR_IAL (1 << 4)
-#define I2SR_SRW (1 << 2)
-#define I2SR_IIF (1 << 1)
-#define I2SR_RXAK (1 << 0)
-#define I2SR_MASK 0xE9
-#define I2SR_RESET 0x81
-
-#define I2DR_MASK 0xFF
-#define I2DR_RESET 0
-
-#define ADDR_RESET 0xFF00
-
-struct IMXI2CState {
- /*< private >*/
- SysBusDevice parent_obj;
-
- /*< public >*/
- MemoryRegion iomem;
- I2CBus *bus;
- qemu_irq irq;
-
- uint16_t address;
-
- uint16_t iadr;
- uint16_t ifdr;
- uint16_t i2cr;
- uint16_t i2sr;
- uint16_t i2dr_read;
- uint16_t i2dr_write;
-};
-
-#endif /* IMX_I2C_H */
+++ /dev/null
-/*
- * Microbit stub for Nordic Semiconductor nRF51 SoC Two-Wire Interface
- * http://infocenter.nordicsemi.com/pdf/nRF51_RM_v3.0.1.pdf
- *
- * Copyright 2019 Red Hat, Inc.
- *
- * This code is licensed under the GPL version 2 or later. See
- * the COPYING file in the top-level directory.
- */
-
-#ifndef MICROBIT_I2C_H
-#define MICROBIT_I2C_H
-
-#include "hw/sysbus.h"
-#include "hw/arm/nrf51.h"
-#include "qom/object.h"
-
-#define NRF51_TWI_TASK_STARTRX 0x000
-#define NRF51_TWI_TASK_STARTTX 0x008
-#define NRF51_TWI_TASK_STOP 0x014
-#define NRF51_TWI_EVENT_STOPPED 0x104
-#define NRF51_TWI_EVENT_RXDREADY 0x108
-#define NRF51_TWI_EVENT_TXDSENT 0x11c
-#define NRF51_TWI_REG_ENABLE 0x500
-#define NRF51_TWI_REG_RXD 0x518
-#define NRF51_TWI_REG_TXD 0x51c
-#define NRF51_TWI_REG_ADDRESS 0x588
-
-#define TYPE_MICROBIT_I2C "microbit.i2c"
-OBJECT_DECLARE_SIMPLE_TYPE(MicrobitI2CState, MICROBIT_I2C)
-
-#define MICROBIT_I2C_NREGS (NRF51_PERIPHERAL_SIZE / sizeof(uint32_t))
-
-struct MicrobitI2CState {
- SysBusDevice parent_obj;
-
- MemoryRegion iomem;
- uint32_t regs[MICROBIT_I2C_NREGS];
- uint32_t read_idx;
-};
-
-#endif /* MICROBIT_I2C_H */
+++ /dev/null
-#ifndef PM_SMBUS_H
-#define PM_SMBUS_H
-
-#include "exec/memory.h"
-#include "hw/i2c/smbus_master.h"
-
-#define PM_SMBUS_MAX_MSG_SIZE 32
-
-typedef struct PMSMBus {
- I2CBus *smbus;
- MemoryRegion io;
-
- uint8_t smb_stat;
- uint8_t smb_ctl;
- uint8_t smb_cmd;
- uint8_t smb_addr;
- uint8_t smb_data0;
- uint8_t smb_data1;
- uint8_t smb_data[PM_SMBUS_MAX_MSG_SIZE];
- uint8_t smb_blkdata;
- uint8_t smb_auxctl;
- uint32_t smb_index;
-
- /* Set by pm_smbus.c */
- void (*reset)(struct PMSMBus *s);
-
- /* Set by the user. */
- bool i2c_enable;
- void (*set_irq)(struct PMSMBus *s, bool enabled);
- void *opaque;
-
- /* Internally used by pm_smbus. */
-
- /* Set on block transfers after the last byte has been read, so the
- INTR bit can be set at the right time. */
- bool op_done;
-
- /* Set during an I2C block read, so we know how to handle data. */
- bool in_i2c_block_read;
-
- /* Used to work around a bug in AMIBIOS, see smb_transaction_start() */
- bool start_transaction_on_status_read;
-} PMSMBus;
-
-void pm_smbus_init(DeviceState *parent, PMSMBus *smb, bool force_aux_blk);
-
-/*
- * For backwards compatibility on migration, older versions don't have
- * working migration for pm_smbus, this lets us ignore the migrations
- * for older machine versions.
- */
-bool pm_smbus_vmstate_needed(void);
-
-extern const VMStateDescription pmsmb_vmstate;
-
-#endif /* PM_SMBUS_H */
+++ /dev/null
-/*
- * PPC4xx I2C controller emulation
- *
- * Copyright (c) 2007 Jocelyn Mayer
- * Copyright (c) 2012 François Revol
- * Copyright (c) 2016-2018 BALATON Zoltan
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
- * furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
- * THE SOFTWARE.
- */
-
-#ifndef PPC4XX_I2C_H
-#define PPC4XX_I2C_H
-
-#include "hw/sysbus.h"
-#include "hw/i2c/bitbang_i2c.h"
-#include "qom/object.h"
-
-#define TYPE_PPC4xx_I2C "ppc4xx-i2c"
-OBJECT_DECLARE_SIMPLE_TYPE(PPC4xxI2CState, PPC4xx_I2C)
-
-struct PPC4xxI2CState {
- /*< private >*/
- SysBusDevice parent_obj;
-
- /*< public >*/
- I2CBus *bus;
- qemu_irq irq;
- MemoryRegion iomem;
- bitbang_i2c_interface bitbang;
- int mdidx;
- uint8_t mdata[4];
- uint8_t lmadr;
- uint8_t hmadr;
- uint8_t cntl;
- uint8_t mdcntl;
- uint8_t sts;
- uint8_t extsts;
- uint8_t lsadr;
- uint8_t hsadr;
- uint8_t clkdiv;
- uint8_t intrmsk;
- uint8_t xfrcnt;
- uint8_t xtcntlss;
- uint8_t directcntl;
-};
-
-#endif /* PPC4XX_I2C_H */
+++ /dev/null
-/*
- * QEMU SMBus EEPROM API
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
- * furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
- * THE SOFTWARE.
- */
-
-#ifndef HW_SMBUS_EEPROM_H
-#define HW_SMBUS_EEPROM_H
-
-#include "exec/cpu-common.h"
-#include "hw/i2c/i2c.h"
-
-void smbus_eeprom_init_one(I2CBus *bus, uint8_t address, uint8_t *eeprom_buf);
-void smbus_eeprom_init(I2CBus *bus, int nb_eeprom,
- const uint8_t *eeprom_spd, int size);
-
-enum sdram_type { SDR = 0x4, DDR = 0x7, DDR2 = 0x8 };
-uint8_t *spd_data_generate(enum sdram_type type, ram_addr_t size);
-
-#endif
+++ /dev/null
-/*
- * QEMU SMBus host (master) API
- *
- * Copyright (c) 2007 Arastra, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
- * furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
- * THE SOFTWARE.
- */
-
-#ifndef HW_SMBUS_MASTER_H
-#define HW_SMBUS_MASTER_H
-
-#include "hw/i2c/i2c.h"
-
-/* Master device commands. */
-int smbus_quick_command(I2CBus *bus, uint8_t addr, int read);
-int smbus_receive_byte(I2CBus *bus, uint8_t addr);
-int smbus_send_byte(I2CBus *bus, uint8_t addr, uint8_t data);
-int smbus_read_byte(I2CBus *bus, uint8_t addr, uint8_t command);
-int smbus_write_byte(I2CBus *bus, uint8_t addr, uint8_t command, uint8_t data);
-int smbus_read_word(I2CBus *bus, uint8_t addr, uint8_t command);
-int smbus_write_word(I2CBus *bus, uint8_t addr, uint8_t command, uint16_t data);
-
-/*
- * Do a block transfer from an I2C device. If recv_len is set, then the
- * first received byte is a length field and is used to know how much data
- * to receive. Otherwise receive "len" bytes. If send_cmd is set, send
- * the command byte first before receiving the data.
- */
-int smbus_read_block(I2CBus *bus, uint8_t addr, uint8_t command, uint8_t *data,
- int len, bool recv_len, bool send_cmd);
-
-/*
- * Do a block transfer to an I2C device. If send_len is set, send the
- * "len" value before the data.
- */
-int smbus_write_block(I2CBus *bus, uint8_t addr, uint8_t command, uint8_t *data,
- int len, bool send_len);
-
-#endif
+++ /dev/null
-/*
- * QEMU SMBus device (slave) API
- *
- * Copyright (c) 2007 Arastra, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
- * furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
- * THE SOFTWARE.
- */
-
-#ifndef HW_SMBUS_SLAVE_H
-#define HW_SMBUS_SLAVE_H
-
-#include "hw/i2c/i2c.h"
-#include "qom/object.h"
-
-#define TYPE_SMBUS_DEVICE "smbus-device"
-OBJECT_DECLARE_TYPE(SMBusDevice, SMBusDeviceClass,
- SMBUS_DEVICE)
-
-
-struct SMBusDeviceClass {
- I2CSlaveClass parent_class;
-
- /*
- * An operation with no data, special in SMBus.
- * This may be NULL, quick commands are ignore in that case.
- */
- void (*quick_cmd)(SMBusDevice *dev, uint8_t read);
-
- /*
- * We can't distinguish between a word write and a block write with
- * length 1, so pass the whole data block including the length byte
- * (if present). The device is responsible figuring out what type of
- * command this is.
- * This may be NULL if no data is written to the device. Writes
- * will be ignore in that case.
- */
- int (*write_data)(SMBusDevice *dev, uint8_t *buf, uint8_t len);
-
- /*
- * Likewise we can't distinguish between different reads, or even know
- * the length of the read until the read is complete, so read data a
- * byte at a time. The device is responsible for adding the length
- * byte on block reads. This call cannot fail, it should return
- * something, preferably 0xff if nothing is available.
- * This may be NULL if no data is read from the device. Reads will
- * return 0xff in that case.
- */
- uint8_t (*receive_byte)(SMBusDevice *dev);
-};
-
-#define SMBUS_DATA_MAX_LEN 34 /* command + len + 32 bytes of data. */
-
-struct SMBusDevice {
- /* The SMBus protocol is implemented on top of I2C. */
- I2CSlave i2c;
-
- /* Remaining fields for internal use only. */
- int32_t mode;
- int32_t data_len;
- uint8_t data_buf[SMBUS_DATA_MAX_LEN];
-};
-
-extern const VMStateDescription vmstate_smbus_device;
-
-#define VMSTATE_SMBUS_DEVICE(_field, _state) { \
- .name = (stringify(_field)), \
- .size = sizeof(SMBusDevice), \
- .vmsd = &vmstate_smbus_device, \
- .flags = VMS_STRUCT, \
- .offset = vmstate_offset_value(_state, _field, SMBusDevice), \
-}
-
-/*
- * Users should call this in their .needed functions to know if the
- * SMBus slave data needs to be transferred.
- */
-bool smbus_vmstate_needed(SMBusDevice *dev);
-
-#endif
+++ /dev/null
-#ifndef HW_APIC_MSIDEF_H
-#define HW_APIC_MSIDEF_H
-
-/*
- * Intel APIC constants: from include/asm/msidef.h
- */
-
-/*
- * Shifts for MSI data
- */
-
-#define MSI_DATA_VECTOR_SHIFT 0
-#define MSI_DATA_VECTOR_MASK 0x000000ff
-
-#define MSI_DATA_DELIVERY_MODE_SHIFT 8
-#define MSI_DATA_LEVEL_SHIFT 14
-#define MSI_DATA_TRIGGER_SHIFT 15
-
-/*
- * Shift/mask fields for msi address
- */
-
-#define MSI_ADDR_DEST_MODE_SHIFT 2
-
-#define MSI_ADDR_REDIRECTION_SHIFT 3
-
-#define MSI_ADDR_DEST_ID_SHIFT 12
-#define MSI_ADDR_DEST_IDX_SHIFT 4
-#define MSI_ADDR_DEST_ID_MASK 0x000ff000
-
-#endif /* HW_APIC_MSIDEF_H */
+++ /dev/null
-#ifndef APIC_H
-#define APIC_H
-
-
-/* apic.c */
-void apic_deliver_irq(uint8_t dest, uint8_t dest_mode, uint8_t delivery_mode,
- uint8_t vector_num, uint8_t trigger_mode);
-int apic_accept_pic_intr(DeviceState *s);
-void apic_deliver_pic_intr(DeviceState *s, int level);
-void apic_deliver_nmi(DeviceState *d);
-int apic_get_interrupt(DeviceState *s);
-void apic_reset_irq_delivered(void);
-int apic_get_irq_delivered(void);
-void cpu_set_apic_base(DeviceState *s, uint64_t val);
-uint64_t cpu_get_apic_base(DeviceState *s);
-void cpu_set_apic_tpr(DeviceState *s, uint8_t val);
-uint8_t cpu_get_apic_tpr(DeviceState *s);
-void apic_init_reset(DeviceState *s);
-void apic_sipi(DeviceState *s);
-void apic_poll_irq(DeviceState *d);
-void apic_designate_bsp(DeviceState *d, bool bsp);
-int apic_get_highest_priority_irr(DeviceState *dev);
-
-/* pc.c */
-DeviceState *cpu_get_current_apic(void);
-
-#endif
+++ /dev/null
-/*
- * APIC support - internal interfaces
- *
- * Copyright (c) 2004-2005 Fabrice Bellard
- * Copyright (c) 2011 Jan Kiszka, Siemens AG
- *
- * This library is free software; you can redistribute it and/or
- * modify it under the terms of the GNU Lesser General Public
- * License as published by the Free Software Foundation; either
- * version 2.1 of the License, or (at your option) any later version.
- *
- * This library is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
- * Lesser General Public License for more details.
- *
- * You should have received a copy of the GNU Lesser General Public
- * License along with this library; if not, see <http://www.gnu.org/licenses/>
- */
-
-#ifndef QEMU_APIC_INTERNAL_H
-#define QEMU_APIC_INTERNAL_H
-
-#include "cpu.h"
-#include "exec/memory.h"
-#include "qemu/timer.h"
-#include "target/i386/cpu-qom.h"
-#include "qom/object.h"
-
-/* APIC Local Vector Table */
-#define APIC_LVT_TIMER 0
-#define APIC_LVT_THERMAL 1
-#define APIC_LVT_PERFORM 2
-#define APIC_LVT_LINT0 3
-#define APIC_LVT_LINT1 4
-#define APIC_LVT_ERROR 5
-#define APIC_LVT_NB 6
-
-/* APIC delivery modes */
-#define APIC_DM_FIXED 0
-#define APIC_DM_LOWPRI 1
-#define APIC_DM_SMI 2
-#define APIC_DM_NMI 4
-#define APIC_DM_INIT 5
-#define APIC_DM_SIPI 6
-#define APIC_DM_EXTINT 7
-
-/* APIC destination mode */
-#define APIC_DESTMODE_FLAT 0xf
-#define APIC_DESTMODE_CLUSTER 1
-
-#define APIC_TRIGGER_EDGE 0
-#define APIC_TRIGGER_LEVEL 1
-
-#define APIC_VECTOR_MASK 0xff
-#define APIC_DCR_MASK 0xf
-
-#define APIC_LVT_TIMER_SHIFT 17
-#define APIC_LVT_MASKED_SHIFT 16
-#define APIC_LVT_LEVEL_TRIGGER_SHIFT 15
-#define APIC_LVT_REMOTE_IRR_SHIFT 14
-#define APIC_LVT_INT_POLARITY_SHIFT 13
-#define APIC_LVT_DELIV_STS_SHIFT 12
-#define APIC_LVT_DELIV_MOD_SHIFT 8
-
-#define APIC_LVT_TIMER_TSCDEADLINE (2 << APIC_LVT_TIMER_SHIFT)
-#define APIC_LVT_TIMER_PERIODIC (1 << APIC_LVT_TIMER_SHIFT)
-#define APIC_LVT_MASKED (1 << APIC_LVT_MASKED_SHIFT)
-#define APIC_LVT_LEVEL_TRIGGER (1 << APIC_LVT_LEVEL_TRIGGER_SHIFT)
-#define APIC_LVT_REMOTE_IRR (1 << APIC_LVT_REMOTE_IRR_SHIFT)
-#define APIC_LVT_INT_POLARITY (1 << APIC_LVT_INT_POLARITY_SHIFT)
-#define APIC_LVT_DELIV_STS (1 << APIC_LVT_DELIV_STS_SHIFT)
-#define APIC_LVT_DELIV_MOD (7 << APIC_LVT_DELIV_MOD_SHIFT)
-
-#define APIC_ESR_ILL_ADDRESS_SHIFT 7
-#define APIC_ESR_RECV_ILL_VECT_SHIFT 6
-#define APIC_ESR_SEND_ILL_VECT_SHIFT 5
-#define APIC_ESR_RECV_ACCEPT_SHIFT 3
-#define APIC_ESR_SEND_ACCEPT_SHIFT 2
-#define APIC_ESR_RECV_CHECK_SUM_SHIFT 1
-
-#define APIC_ESR_ILLEGAL_ADDRESS (1 << APIC_ESR_ILL_ADDRESS_SHIFT)
-#define APIC_ESR_RECV_ILLEGAL_VECT (1 << APIC_ESR_RECV_ILL_VECT_SHIFT)
-#define APIC_ESR_SEND_ILLEGAL_VECT (1 << APIC_ESR_SEND_ILL_VECT_SHIFT)
-#define APIC_ESR_RECV_ACCEPT (1 << APIC_ESR_RECV_ACCEPT_SHIFT)
-#define APIC_ESR_SEND_ACCEPT (1 << APIC_ESR_SEND_ACCEPT_SHIFT)
-#define APIC_ESR_RECV_CHECK_SUM (1 << APIC_ESR_RECV_CHECK_SUM_SHIFT)
-#define APIC_ESR_SEND_CHECK_SUM 1
-
-#define APIC_ICR_DEST_SHIFT 24
-#define APIC_ICR_DEST_SHORT_SHIFT 18
-#define APIC_ICR_TRIGGER_MOD_SHIFT 15
-#define APIC_ICR_LEVEL_SHIFT 14
-#define APIC_ICR_DELIV_STS_SHIFT 12
-#define APIC_ICR_DEST_MOD_SHIFT 11
-#define APIC_ICR_DELIV_MOD_SHIFT 8
-
-#define APIC_ICR_DEST_SHORT (3 << APIC_ICR_DEST_SHORT_SHIFT)
-#define APIC_ICR_TRIGGER_MOD (1 << APIC_ICR_TRIGGER_MOD_SHIFT)
-#define APIC_ICR_LEVEL (1 << APIC_ICR_LEVEL_SHIFT)
-#define APIC_ICR_DELIV_STS (1 << APIC_ICR_DELIV_STS_SHIFT)
-#define APIC_ICR_DEST_MOD (1 << APIC_ICR_DEST_MOD_SHIFT)
-#define APIC_ICR_DELIV_MOD (7 << APIC_ICR_DELIV_MOD_SHIFT)
-
-#define APIC_PR_CLASS_SHIFT 4
-#define APIC_PR_SUB_CLASS 0xf
-
-#define APIC_LOGDEST_XAPIC_SHIFT 4
-#define APIC_LOGDEST_XAPIC_ID 0xf
-
-#define APIC_LOGDEST_X2APIC_SHIFT 16
-#define APIC_LOGDEST_X2APIC_ID 0xffff
-
-#define APIC_SPURIO_FOCUS_SHIFT 9
-#define APIC_SPURIO_ENABLED_SHIFT 8
-
-#define APIC_SPURIO_FOCUS (1 << APIC_SPURIO_FOCUS_SHIFT)
-#define APIC_SPURIO_ENABLED (1 << APIC_SPURIO_ENABLED_SHIFT)
-
-#define APIC_SV_DIRECTED_IO (1 << 12)
-#define APIC_SV_ENABLE (1 << 8)
-
-#define VAPIC_ENABLE_BIT 0
-#define VAPIC_ENABLE_MASK (1 << VAPIC_ENABLE_BIT)
-
-typedef struct APICCommonState APICCommonState;
-
-#define TYPE_APIC_COMMON "apic-common"
-typedef struct APICCommonClass APICCommonClass;
-DECLARE_OBJ_CHECKERS(APICCommonState, APICCommonClass,
- APIC_COMMON, TYPE_APIC_COMMON)
-
-struct APICCommonClass {
- DeviceClass parent_class;
-
- DeviceRealize realize;
- DeviceUnrealize unrealize;
- void (*set_base)(APICCommonState *s, uint64_t val);
- void (*set_tpr)(APICCommonState *s, uint8_t val);
- uint8_t (*get_tpr)(APICCommonState *s);
- void (*enable_tpr_reporting)(APICCommonState *s, bool enable);
- void (*vapic_base_update)(APICCommonState *s);
- void (*external_nmi)(APICCommonState *s);
- void (*pre_save)(APICCommonState *s);
- void (*post_load)(APICCommonState *s);
- void (*reset)(APICCommonState *s);
- /* send_msi emulates an APIC bus and its proper place would be in a new
- * device, but it's convenient to have it here for now.
- */
- void (*send_msi)(MSIMessage *msi);
-};
-
-struct APICCommonState {
- /*< private >*/
- DeviceState parent_obj;
- /*< public >*/
-
- MemoryRegion io_memory;
- X86CPU *cpu;
- uint32_t apicbase;
- uint8_t id; /* legacy APIC ID */
- uint32_t initial_apic_id;
- uint8_t version;
- uint8_t arb_id;
- uint8_t tpr;
- uint32_t spurious_vec;
- uint8_t log_dest;
- uint8_t dest_mode;
- uint32_t isr[8]; /* in service register */
- uint32_t tmr[8]; /* trigger mode register */
- uint32_t irr[8]; /* interrupt request register */
- uint32_t lvt[APIC_LVT_NB];
- uint32_t esr; /* error register */
- uint32_t icr[2];
-
- uint32_t divide_conf;
- int count_shift;
- uint32_t initial_count;
- int64_t initial_count_load_time;
- int64_t next_time;
- QEMUTimer *timer;
- int64_t timer_expiry;
- int sipi_vector;
- int wait_for_sipi;
-
- uint32_t vapic_control;
- DeviceState *vapic;
- hwaddr vapic_paddr; /* note: persistence via kvmvapic */
- bool legacy_instance_id;
-};
-
-typedef struct VAPICState {
- uint8_t tpr;
- uint8_t isr;
- uint8_t zero;
- uint8_t irr;
- uint8_t enabled;
-} QEMU_PACKED VAPICState;
-
-extern bool apic_report_tpr_access;
-
-void apic_report_irq_delivered(int delivered);
-bool apic_next_timer(APICCommonState *s, int64_t current_time);
-void apic_enable_tpr_access_reporting(DeviceState *d, bool enable);
-void apic_enable_vapic(DeviceState *d, hwaddr paddr);
-
-void vapic_report_tpr_access(DeviceState *dev, CPUState *cpu, target_ulong ip,
- TPRAccess access);
-
-int apic_get_ppr(APICCommonState *s);
-uint32_t apic_get_current_count(APICCommonState *s);
-
-static inline void apic_set_bit(uint32_t *tab, int index)
-{
- int i, mask;
- i = index >> 5;
- mask = 1 << (index & 0x1f);
- tab[i] |= mask;
-}
-
-static inline int apic_get_bit(uint32_t *tab, int index)
-{
- int i, mask;
- i = index >> 5;
- mask = 1 << (index & 0x1f);
- return !!(tab[i] & mask);
-}
-
-APICCommonClass *apic_get_class(void);
-
-#endif /* QEMU_APIC_INTERNAL_H */
+++ /dev/null
-#ifndef HW_ICH9_H
-#define HW_ICH9_H
-
-#include "hw/isa/isa.h"
-#include "hw/sysbus.h"
-#include "hw/i386/pc.h"
-#include "hw/isa/apm.h"
-#include "hw/pci/pci.h"
-#include "hw/pci/pcie_host.h"
-#include "hw/pci/pci_bridge.h"
-#include "hw/acpi/acpi.h"
-#include "hw/acpi/ich9.h"
-#include "hw/pci/pci_bus.h"
-#include "qom/object.h"
-
-void ich9_lpc_set_irq(void *opaque, int irq_num, int level);
-int ich9_lpc_map_irq(PCIDevice *pci_dev, int intx);
-PCIINTxRoute ich9_route_intx_pin_to_irq(void *opaque, int pirq_pin);
-void ich9_lpc_pm_init(PCIDevice *pci_lpc, bool smm_enabled);
-I2CBus *ich9_smb_init(PCIBus *bus, int devfn, uint32_t smb_io_base);
-
-void ich9_generate_smi(void);
-
-#define ICH9_CC_SIZE (16 * 1024) /* 16KB. Chipset configuration registers */
-
-#define TYPE_ICH9_LPC_DEVICE "ICH9-LPC"
-OBJECT_DECLARE_SIMPLE_TYPE(ICH9LPCState, ICH9_LPC_DEVICE)
-
-struct ICH9LPCState {
- /* ICH9 LPC PCI to ISA bridge */
- PCIDevice d;
-
- /* (pci device, intx) -> pirq
- * In real chipset case, the unused slots are never used
- * as ICH9 supports only D25-D31 irq routing.
- * On the other hand in qemu case, any slot/function can be populated
- * via command line option.
- * So fallback interrupt routing for any devices in any slots is necessary.
- */
- uint8_t irr[PCI_SLOT_MAX][PCI_NUM_PINS];
-
- APMState apm;
- ICH9LPCPMRegs pm;
- uint32_t sci_level; /* track sci level */
- uint8_t sci_gsi;
-
- /* 2.24 Pin Straps */
- struct {
- bool spkr_hi;
- } pin_strap;
-
- /* 10.1 Chipset Configuration registers(Memory Space)
- which is pointed by RCBA */
- uint8_t chip_config[ICH9_CC_SIZE];
-
- /*
- * 13.7.5 RST_CNT---Reset Control Register (LPC I/F---D31:F0)
- *
- * register contents and IO memory region
- */
- uint8_t rst_cnt;
- MemoryRegion rst_cnt_mem;
-
- /* SMI feature negotiation via fw_cfg */
- uint64_t smi_host_features; /* guest-invisible, host endian */
- uint8_t smi_host_features_le[8]; /* guest-visible, read-only, little
- * endian uint64_t */
- uint8_t smi_guest_features_le[8]; /* guest-visible, read-write, little
- * endian uint64_t */
- uint8_t smi_features_ok; /* guest-visible, read-only; selecting it
- * triggers feature lockdown */
- uint64_t smi_negotiated_features; /* guest-invisible, host endian */
-
- /* isa bus */
- ISABus *isa_bus;
- MemoryRegion rcrb_mem; /* root complex register block */
- Notifier machine_ready;
-
- qemu_irq gsi[GSI_NUM_PINS];
-};
-
-#define Q35_MASK(bit, ms_bit, ls_bit) \
-((uint##bit##_t)(((1ULL << ((ms_bit) + 1)) - 1) & ~((1ULL << ls_bit) - 1)))
-
-/* ICH9: Chipset Configuration Registers */
-#define ICH9_CC_ADDR_MASK (ICH9_CC_SIZE - 1)
-
-#define ICH9_CC
-#define ICH9_CC_D28IP 0x310C
-#define ICH9_CC_D28IP_SHIFT 4
-#define ICH9_CC_D28IP_MASK 0xf
-#define ICH9_CC_D28IP_DEFAULT 0x00214321
-#define ICH9_CC_D31IR 0x3140
-#define ICH9_CC_D30IR 0x3142
-#define ICH9_CC_D29IR 0x3144
-#define ICH9_CC_D28IR 0x3146
-#define ICH9_CC_D27IR 0x3148
-#define ICH9_CC_D26IR 0x314C
-#define ICH9_CC_D25IR 0x3150
-#define ICH9_CC_DIR_DEFAULT 0x3210
-#define ICH9_CC_D30IR_DEFAULT 0x0
-#define ICH9_CC_DIR_SHIFT 4
-#define ICH9_CC_DIR_MASK 0x7
-#define ICH9_CC_OIC 0x31FF
-#define ICH9_CC_OIC_AEN 0x1
-#define ICH9_CC_GCS 0x3410
-#define ICH9_CC_GCS_DEFAULT 0x00000020
-#define ICH9_CC_GCS_NO_REBOOT (1 << 5)
-
-/* D28:F[0-5] */
-#define ICH9_PCIE_DEV 28
-#define ICH9_PCIE_FUNC_MAX 6
-
-
-/* D29:F0 USB UHCI Controller #1 */
-#define ICH9_USB_UHCI1_DEV 29
-#define ICH9_USB_UHCI1_FUNC 0
-
-/* D30:F0 DMI-to-PCI bridge */
-#define ICH9_D2P_BRIDGE "ICH9 D2P BRIDGE"
-#define ICH9_D2P_BRIDGE_SAVEVM_VERSION 0
-
-#define ICH9_D2P_BRIDGE_DEV 30
-#define ICH9_D2P_BRIDGE_FUNC 0
-
-#define ICH9_D2P_SECONDARY_DEFAULT (256 - 8)
-
-#define ICH9_D2P_A2_REVISION 0x92
-
-/* D31:F0 LPC Processor Interface */
-#define ICH9_RST_CNT_IOPORT 0xCF9
-
-/* D31:F1 LPC controller */
-#define ICH9_A2_LPC "ICH9 A2 LPC"
-#define ICH9_A2_LPC_SAVEVM_VERSION 0
-
-#define ICH9_LPC_DEV 31
-#define ICH9_LPC_FUNC 0
-
-#define ICH9_A2_LPC_REVISION 0x2
-#define ICH9_LPC_NB_PIRQS 8 /* PCI A-H */
-
-#define ICH9_LPC_PMBASE 0x40
-#define ICH9_LPC_PMBASE_BASE_ADDRESS_MASK Q35_MASK(32, 15, 7)
-#define ICH9_LPC_PMBASE_RTE 0x1
-#define ICH9_LPC_PMBASE_DEFAULT 0x1
-
-#define ICH9_LPC_ACPI_CTRL 0x44
-#define ICH9_LPC_ACPI_CTRL_ACPI_EN 0x80
-#define ICH9_LPC_ACPI_CTRL_SCI_IRQ_SEL_MASK Q35_MASK(8, 2, 0)
-#define ICH9_LPC_ACPI_CTRL_9 0x0
-#define ICH9_LPC_ACPI_CTRL_10 0x1
-#define ICH9_LPC_ACPI_CTRL_11 0x2
-#define ICH9_LPC_ACPI_CTRL_20 0x4
-#define ICH9_LPC_ACPI_CTRL_21 0x5
-#define ICH9_LPC_ACPI_CTRL_DEFAULT 0x0
-
-#define ICH9_LPC_PIRQA_ROUT 0x60
-#define ICH9_LPC_PIRQB_ROUT 0x61
-#define ICH9_LPC_PIRQC_ROUT 0x62
-#define ICH9_LPC_PIRQD_ROUT 0x63
-
-#define ICH9_LPC_PIRQE_ROUT 0x68
-#define ICH9_LPC_PIRQF_ROUT 0x69
-#define ICH9_LPC_PIRQG_ROUT 0x6a
-#define ICH9_LPC_PIRQH_ROUT 0x6b
-
-#define ICH9_LPC_PIRQ_ROUT_IRQEN 0x80
-#define ICH9_LPC_PIRQ_ROUT_MASK Q35_MASK(8, 3, 0)
-#define ICH9_LPC_PIRQ_ROUT_DEFAULT 0x80
-
-#define ICH9_LPC_GEN_PMCON_1 0xa0
-#define ICH9_LPC_GEN_PMCON_1_SMI_LOCK (1 << 4)
-#define ICH9_LPC_GEN_PMCON_2 0xa2
-#define ICH9_LPC_GEN_PMCON_3 0xa4
-#define ICH9_LPC_GEN_PMCON_LOCK 0xa6
-
-#define ICH9_LPC_RCBA 0xf0
-#define ICH9_LPC_RCBA_BA_MASK Q35_MASK(32, 31, 14)
-#define ICH9_LPC_RCBA_EN 0x1
-#define ICH9_LPC_RCBA_DEFAULT 0x0
-
-#define ICH9_LPC_PIC_NUM_PINS 16
-#define ICH9_LPC_IOAPIC_NUM_PINS 24
-
-#define ICH9_GPIO_GSI "gsi"
-
-/* D31:F2 SATA Controller #1 */
-#define ICH9_SATA1_DEV 31
-#define ICH9_SATA1_FUNC 2
-
-/* D31:F0 power management I/O registers
- offset from the address ICH9_LPC_PMBASE */
-
-/* ICH9 LPC PM I/O registers are 128 ports and 128-aligned */
-#define ICH9_PMIO_SIZE 128
-#define ICH9_PMIO_MASK (ICH9_PMIO_SIZE - 1)
-
-#define ICH9_PMIO_PM1_STS 0x00
-#define ICH9_PMIO_PM1_EN 0x02
-#define ICH9_PMIO_PM1_CNT 0x04
-#define ICH9_PMIO_PM1_TMR 0x08
-#define ICH9_PMIO_GPE0_STS 0x20
-#define ICH9_PMIO_GPE0_EN 0x28
-#define ICH9_PMIO_GPE0_LEN 16
-#define ICH9_PMIO_SMI_EN 0x30
-#define ICH9_PMIO_SMI_EN_APMC_EN (1 << 5)
-#define ICH9_PMIO_SMI_EN_TCO_EN (1 << 13)
-#define ICH9_PMIO_SMI_STS 0x34
-#define ICH9_PMIO_TCO_RLD 0x60
-#define ICH9_PMIO_TCO_LEN 32
-
-/* FADT ACPI_ENABLE/ACPI_DISABLE */
-#define ICH9_APM_ACPI_ENABLE 0x2
-#define ICH9_APM_ACPI_DISABLE 0x3
-
-
-/* D31:F3 SMBus controller */
-#define TYPE_ICH9_SMB_DEVICE "ICH9 SMB"
-
-#define ICH9_A2_SMB_REVISION 0x02
-#define ICH9_SMB_PI 0x00
-
-#define ICH9_SMB_SMBMBAR0 0x10
-#define ICH9_SMB_SMBMBAR1 0x14
-#define ICH9_SMB_SMBM_BAR 0
-#define ICH9_SMB_SMBM_SIZE (1 << 8)
-#define ICH9_SMB_SMB_BASE 0x20
-#define ICH9_SMB_SMB_BASE_BAR 4
-#define ICH9_SMB_SMB_BASE_SIZE (1 << 5)
-#define ICH9_SMB_HOSTC 0x40
-#define ICH9_SMB_HOSTC_SSRESET ((uint8_t)(1 << 3))
-#define ICH9_SMB_HOSTC_I2C_EN ((uint8_t)(1 << 2))
-#define ICH9_SMB_HOSTC_SMB_SMI_EN ((uint8_t)(1 << 1))
-#define ICH9_SMB_HOSTC_HST_EN ((uint8_t)(1 << 0))
-
-/* D31:F3 SMBus I/O and memory mapped I/O registers */
-#define ICH9_SMB_DEV 31
-#define ICH9_SMB_FUNC 3
-
-#define ICH9_SMB_HST_STS 0x00
-#define ICH9_SMB_HST_CNT 0x02
-#define ICH9_SMB_HST_CMD 0x03
-#define ICH9_SMB_XMIT_SLVA 0x04
-#define ICH9_SMB_HST_D0 0x05
-#define ICH9_SMB_HST_D1 0x06
-#define ICH9_SMB_HOST_BLOCK_DB 0x07
-
-#define ICH9_LPC_SMI_NEGOTIATED_FEAT_PROP "x-smi-negotiated-features"
-
-/* bit positions used in fw_cfg SMI feature negotiation */
-#define ICH9_LPC_SMI_F_BROADCAST_BIT 0
-#define ICH9_LPC_SMI_F_CPU_HOTPLUG_BIT 1
-#define ICH9_LPC_SMI_F_CPU_HOT_UNPLUG_BIT 2
-
-#endif /* HW_ICH9_H */
+++ /dev/null
-/*
- * QEMU emulation of an Intel IOMMU (VT-d)
- * (DMA Remapping device)
- *
- * Copyright (C) 2013 Knut Omang, Oracle <knut.omang@oracle.com>
- * Copyright (C) 2014 Le Tan, <tamlokveer@gmail.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
-
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
-
- * You should have received a copy of the GNU General Public License along
- * with this program; if not, see <http://www.gnu.org/licenses/>.
- */
-
-#ifndef INTEL_IOMMU_H
-#define INTEL_IOMMU_H
-
-#include "hw/i386/x86-iommu.h"
-#include "qemu/iova-tree.h"
-#include "qom/object.h"
-
-#define TYPE_INTEL_IOMMU_DEVICE "intel-iommu"
-OBJECT_DECLARE_SIMPLE_TYPE(IntelIOMMUState, INTEL_IOMMU_DEVICE)
-
-#define TYPE_INTEL_IOMMU_MEMORY_REGION "intel-iommu-iommu-memory-region"
-
-/* DMAR Hardware Unit Definition address (IOMMU unit) */
-#define Q35_HOST_BRIDGE_IOMMU_ADDR 0xfed90000ULL
-
-#define VTD_PCI_BUS_MAX 256
-#define VTD_PCI_SLOT_MAX 32
-#define VTD_PCI_FUNC_MAX 8
-#define VTD_PCI_SLOT(devfn) (((devfn) >> 3) & 0x1f)
-#define VTD_PCI_FUNC(devfn) ((devfn) & 0x07)
-#define VTD_SID_TO_BUS(sid) (((sid) >> 8) & 0xff)
-#define VTD_SID_TO_DEVFN(sid) ((sid) & 0xff)
-
-#define DMAR_REG_SIZE 0x230
-#define VTD_HOST_AW_39BIT 39
-#define VTD_HOST_AW_48BIT 48
-#define VTD_HOST_ADDRESS_WIDTH VTD_HOST_AW_39BIT
-#define VTD_HAW_MASK(aw) ((1ULL << (aw)) - 1)
-
-#define DMAR_REPORT_F_INTR (1)
-
-#define VTD_MSI_ADDR_HI_MASK (0xffffffff00000000ULL)
-#define VTD_MSI_ADDR_HI_SHIFT (32)
-#define VTD_MSI_ADDR_LO_MASK (0x00000000ffffffffULL)
-
-typedef struct VTDContextEntry VTDContextEntry;
-typedef struct VTDContextCacheEntry VTDContextCacheEntry;
-typedef struct VTDAddressSpace VTDAddressSpace;
-typedef struct VTDIOTLBEntry VTDIOTLBEntry;
-typedef struct VTDBus VTDBus;
-typedef union VTD_IR_TableEntry VTD_IR_TableEntry;
-typedef union VTD_IR_MSIAddress VTD_IR_MSIAddress;
-typedef struct VTDPASIDDirEntry VTDPASIDDirEntry;
-typedef struct VTDPASIDEntry VTDPASIDEntry;
-
-/* Context-Entry */
-struct VTDContextEntry {
- union {
- struct {
- uint64_t lo;
- uint64_t hi;
- };
- struct {
- uint64_t val[4];
- };
- };
-};
-
-struct VTDContextCacheEntry {
- /* The cache entry is obsolete if
- * context_cache_gen!=IntelIOMMUState.context_cache_gen
- */
- uint32_t context_cache_gen;
- struct VTDContextEntry context_entry;
-};
-
-/* PASID Directory Entry */
-struct VTDPASIDDirEntry {
- uint64_t val;
-};
-
-/* PASID Table Entry */
-struct VTDPASIDEntry {
- uint64_t val[8];
-};
-
-struct VTDAddressSpace {
- PCIBus *bus;
- uint8_t devfn;
- AddressSpace as;
- IOMMUMemoryRegion iommu;
- MemoryRegion root; /* The root container of the device */
- MemoryRegion nodmar; /* The alias of shared nodmar MR */
- MemoryRegion iommu_ir; /* Interrupt region: 0xfeeXXXXX */
- IntelIOMMUState *iommu_state;
- VTDContextCacheEntry context_cache_entry;
- QLIST_ENTRY(VTDAddressSpace) next;
- /* Superset of notifier flags that this address space has */
- IOMMUNotifierFlag notifier_flags;
- IOVATree *iova_tree; /* Traces mapped IOVA ranges */
-};
-
-struct VTDBus {
- PCIBus* bus; /* A reference to the bus to provide translation for */
- /* A table of VTDAddressSpace objects indexed by devfn */
- VTDAddressSpace *dev_as[];
-};
-
-struct VTDIOTLBEntry {
- uint64_t gfn;
- uint16_t domain_id;
- uint64_t slpte;
- uint64_t mask;
- uint8_t access_flags;
-};
-
-/* VT-d Source-ID Qualifier types */
-enum {
- VTD_SQ_FULL = 0x00, /* Full SID verification */
- VTD_SQ_IGN_3 = 0x01, /* Ignore bit 3 */
- VTD_SQ_IGN_2_3 = 0x02, /* Ignore bits 2 & 3 */
- VTD_SQ_IGN_1_3 = 0x03, /* Ignore bits 1-3 */
- VTD_SQ_MAX,
-};
-
-/* VT-d Source Validation Types */
-enum {
- VTD_SVT_NONE = 0x00, /* No validation */
- VTD_SVT_ALL = 0x01, /* Do full validation */
- VTD_SVT_BUS = 0x02, /* Validate bus range */
- VTD_SVT_MAX,
-};
-
-/* Interrupt Remapping Table Entry Definition */
-union VTD_IR_TableEntry {
- struct {
-#ifdef HOST_WORDS_BIGENDIAN
- uint32_t __reserved_1:8; /* Reserved 1 */
- uint32_t vector:8; /* Interrupt Vector */
- uint32_t irte_mode:1; /* IRTE Mode */
- uint32_t __reserved_0:3; /* Reserved 0 */
- uint32_t __avail:4; /* Available spaces for software */
- uint32_t delivery_mode:3; /* Delivery Mode */
- uint32_t trigger_mode:1; /* Trigger Mode */
- uint32_t redir_hint:1; /* Redirection Hint */
- uint32_t dest_mode:1; /* Destination Mode */
- uint32_t fault_disable:1; /* Fault Processing Disable */
- uint32_t present:1; /* Whether entry present/available */
-#else
- uint32_t present:1; /* Whether entry present/available */
- uint32_t fault_disable:1; /* Fault Processing Disable */
- uint32_t dest_mode:1; /* Destination Mode */
- uint32_t redir_hint:1; /* Redirection Hint */
- uint32_t trigger_mode:1; /* Trigger Mode */
- uint32_t delivery_mode:3; /* Delivery Mode */
- uint32_t __avail:4; /* Available spaces for software */
- uint32_t __reserved_0:3; /* Reserved 0 */
- uint32_t irte_mode:1; /* IRTE Mode */
- uint32_t vector:8; /* Interrupt Vector */
- uint32_t __reserved_1:8; /* Reserved 1 */
-#endif
- uint32_t dest_id; /* Destination ID */
- uint16_t source_id; /* Source-ID */
-#ifdef HOST_WORDS_BIGENDIAN
- uint64_t __reserved_2:44; /* Reserved 2 */
- uint64_t sid_vtype:2; /* Source-ID Validation Type */
- uint64_t sid_q:2; /* Source-ID Qualifier */
-#else
- uint64_t sid_q:2; /* Source-ID Qualifier */
- uint64_t sid_vtype:2; /* Source-ID Validation Type */
- uint64_t __reserved_2:44; /* Reserved 2 */
-#endif
- } QEMU_PACKED irte;
- uint64_t data[2];
-};
-
-#define VTD_IR_INT_FORMAT_COMPAT (0) /* Compatible Interrupt */
-#define VTD_IR_INT_FORMAT_REMAP (1) /* Remappable Interrupt */
-
-/* Programming format for MSI/MSI-X addresses */
-union VTD_IR_MSIAddress {
- struct {
-#ifdef HOST_WORDS_BIGENDIAN
- uint32_t __head:12; /* Should always be: 0x0fee */
- uint32_t index_l:15; /* Interrupt index bit 14-0 */
- uint32_t int_mode:1; /* Interrupt format */
- uint32_t sub_valid:1; /* SHV: Sub-Handle Valid bit */
- uint32_t index_h:1; /* Interrupt index bit 15 */
- uint32_t __not_care:2;
-#else
- uint32_t __not_care:2;
- uint32_t index_h:1; /* Interrupt index bit 15 */
- uint32_t sub_valid:1; /* SHV: Sub-Handle Valid bit */
- uint32_t int_mode:1; /* Interrupt format */
- uint32_t index_l:15; /* Interrupt index bit 14-0 */
- uint32_t __head:12; /* Should always be: 0x0fee */
-#endif
- } QEMU_PACKED addr;
- uint32_t data;
-};
-
-/* When IR is enabled, all MSI/MSI-X data bits should be zero */
-#define VTD_IR_MSI_DATA (0)
-
-/* The iommu (DMAR) device state struct */
-struct IntelIOMMUState {
- X86IOMMUState x86_iommu;
- MemoryRegion csrmem;
- MemoryRegion mr_nodmar;
- MemoryRegion mr_ir;
- MemoryRegion mr_sys_alias;
- uint8_t csr[DMAR_REG_SIZE]; /* register values */
- uint8_t wmask[DMAR_REG_SIZE]; /* R/W bytes */
- uint8_t w1cmask[DMAR_REG_SIZE]; /* RW1C(Write 1 to Clear) bytes */
- uint8_t womask[DMAR_REG_SIZE]; /* WO (write only - read returns 0) */
- uint32_t version;
-
- bool caching_mode; /* RO - is cap CM enabled? */
- bool scalable_mode; /* RO - is Scalable Mode supported? */
-
- dma_addr_t root; /* Current root table pointer */
- bool root_scalable; /* Type of root table (scalable or not) */
- bool dmar_enabled; /* Set if DMA remapping is enabled */
-
- uint16_t iq_head; /* Current invalidation queue head */
- uint16_t iq_tail; /* Current invalidation queue tail */
- dma_addr_t iq; /* Current invalidation queue pointer */
- uint16_t iq_size; /* IQ Size in number of entries */
- bool iq_dw; /* IQ descriptor width 256bit or not */
- bool qi_enabled; /* Set if the QI is enabled */
- uint8_t iq_last_desc_type; /* The type of last completed descriptor */
-
- /* The index of the Fault Recording Register to be used next.
- * Wraps around from N-1 to 0, where N is the number of FRCD_REG.
- */
- uint16_t next_frcd_reg;
-
- uint64_t cap; /* The value of capability reg */
- uint64_t ecap; /* The value of extended capability reg */
-
- uint32_t context_cache_gen; /* Should be in [1,MAX] */
- GHashTable *iotlb; /* IOTLB */
-
- GHashTable *vtd_as_by_busptr; /* VTDBus objects indexed by PCIBus* reference */
- VTDBus *vtd_as_by_bus_num[VTD_PCI_BUS_MAX]; /* VTDBus objects indexed by bus number */
- /* list of registered notifiers */
- QLIST_HEAD(, VTDAddressSpace) vtd_as_with_notifiers;
-
- /* interrupt remapping */
- bool intr_enabled; /* Whether guest enabled IR */
- dma_addr_t intr_root; /* Interrupt remapping table pointer */
- uint32_t intr_size; /* Number of IR table entries */
- bool intr_eime; /* Extended interrupt mode enabled */
- OnOffAuto intr_eim; /* Toggle for EIM cabability */
- bool buggy_eim; /* Force buggy EIM unless eim=off */
- uint8_t aw_bits; /* Host/IOVA address width (in bits) */
- bool dma_drain; /* Whether DMA r/w draining enabled */
-
- /*
- * Protects IOMMU states in general. Currently it protects the
- * per-IOMMU IOTLB cache, and context entry cache in VTDAddressSpace.
- */
- QemuMutex iommu_lock;
-};
-
-/* Find the VTD Address space associated with the given bus pointer,
- * create a new one if none exists
- */
-VTDAddressSpace *vtd_find_add_as(IntelIOMMUState *s, PCIBus *bus, int devfn);
-
-#endif
+++ /dev/null
-/*
- * ioapic.c IOAPIC emulation logic
- *
- * Copyright (c) 2011 Jan Kiszka, Siemens AG
- *
- * This library is free software; you can redistribute it and/or
- * modify it under the terms of the GNU Lesser General Public
- * License as published by the Free Software Foundation; either
- * version 2.1 of the License, or (at your option) any later version.
- *
- * This library is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
- * Lesser General Public License for more details.
- *
- * You should have received a copy of the GNU Lesser General Public
- * License along with this library; if not, see <http://www.gnu.org/licenses/>.
- */
-
-#ifndef HW_IOAPIC_H
-#define HW_IOAPIC_H
-
-#define IOAPIC_NUM_PINS 24
-#define IO_APIC_DEFAULT_ADDRESS 0xfec00000
-
-#define TYPE_KVM_IOAPIC "kvm-ioapic"
-#define TYPE_IOAPIC "ioapic"
-
-void ioapic_eoi_broadcast(int vector);
-
-#endif /* HW_IOAPIC_H */
+++ /dev/null
-/*
- * IOAPIC emulation logic - internal interfaces
- *
- * Copyright (c) 2004-2005 Fabrice Bellard
- * Copyright (c) 2009 Xiantao Zhang, Intel
- * Copyright (c) 2011 Jan Kiszka, Siemens AG
- *
- * This library is free software; you can redistribute it and/or
- * modify it under the terms of the GNU Lesser General Public
- * License as published by the Free Software Foundation; either
- * version 2.1 of the License, or (at your option) any later version.
- *
- * This library is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
- * Lesser General Public License for more details.
- *
- * You should have received a copy of the GNU Lesser General Public
- * License along with this library; if not, see <http://www.gnu.org/licenses/>.
- */
-
-#ifndef QEMU_IOAPIC_INTERNAL_H
-#define QEMU_IOAPIC_INTERNAL_H
-
-#include "exec/memory.h"
-#include "hw/sysbus.h"
-#include "qemu/notify.h"
-#include "qom/object.h"
-
-#define MAX_IOAPICS 1
-
-#define IOAPIC_LVT_DEST_SHIFT 56
-#define IOAPIC_LVT_DEST_IDX_SHIFT 48
-#define IOAPIC_LVT_MASKED_SHIFT 16
-#define IOAPIC_LVT_TRIGGER_MODE_SHIFT 15
-#define IOAPIC_LVT_REMOTE_IRR_SHIFT 14
-#define IOAPIC_LVT_POLARITY_SHIFT 13
-#define IOAPIC_LVT_DELIV_STATUS_SHIFT 12
-#define IOAPIC_LVT_DEST_MODE_SHIFT 11
-#define IOAPIC_LVT_DELIV_MODE_SHIFT 8
-
-#define IOAPIC_LVT_MASKED (1 << IOAPIC_LVT_MASKED_SHIFT)
-#define IOAPIC_LVT_TRIGGER_MODE (1 << IOAPIC_LVT_TRIGGER_MODE_SHIFT)
-#define IOAPIC_LVT_REMOTE_IRR (1 << IOAPIC_LVT_REMOTE_IRR_SHIFT)
-#define IOAPIC_LVT_POLARITY (1 << IOAPIC_LVT_POLARITY_SHIFT)
-#define IOAPIC_LVT_DELIV_STATUS (1 << IOAPIC_LVT_DELIV_STATUS_SHIFT)
-#define IOAPIC_LVT_DEST_MODE (1 << IOAPIC_LVT_DEST_MODE_SHIFT)
-#define IOAPIC_LVT_DELIV_MODE (7 << IOAPIC_LVT_DELIV_MODE_SHIFT)
-
-/* Bits that are read-only for IOAPIC entry */
-#define IOAPIC_RO_BITS (IOAPIC_LVT_REMOTE_IRR | \
- IOAPIC_LVT_DELIV_STATUS)
-#define IOAPIC_RW_BITS (~(uint64_t)IOAPIC_RO_BITS)
-
-#define IOAPIC_TRIGGER_EDGE 0
-#define IOAPIC_TRIGGER_LEVEL 1
-
-/*io{apic,sapic} delivery mode*/
-#define IOAPIC_DM_FIXED 0x0
-#define IOAPIC_DM_LOWEST_PRIORITY 0x1
-#define IOAPIC_DM_PMI 0x2
-#define IOAPIC_DM_NMI 0x4
-#define IOAPIC_DM_INIT 0x5
-#define IOAPIC_DM_SIPI 0x6
-#define IOAPIC_DM_EXTINT 0x7
-#define IOAPIC_DM_MASK 0x7
-
-#define IOAPIC_VECTOR_MASK 0xff
-
-#define IOAPIC_IOREGSEL 0x00
-#define IOAPIC_IOWIN 0x10
-#define IOAPIC_EOI 0x40
-
-#define IOAPIC_REG_ID 0x00
-#define IOAPIC_REG_VER 0x01
-#define IOAPIC_REG_ARB 0x02
-#define IOAPIC_REG_REDTBL_BASE 0x10
-#define IOAPIC_ID 0x00
-
-#define IOAPIC_ID_SHIFT 24
-#define IOAPIC_ID_MASK 0xf
-
-#define IOAPIC_VER_ENTRIES_SHIFT 16
-
-
-#define TYPE_IOAPIC_COMMON "ioapic-common"
-OBJECT_DECLARE_TYPE(IOAPICCommonState, IOAPICCommonClass, IOAPIC_COMMON)
-
-struct IOAPICCommonClass {
- SysBusDeviceClass parent_class;
-
- DeviceRealize realize;
- DeviceUnrealize unrealize;
- void (*pre_save)(IOAPICCommonState *s);
- void (*post_load)(IOAPICCommonState *s);
-};
-
-struct IOAPICCommonState {
- SysBusDevice busdev;
- MemoryRegion io_memory;
- uint8_t id;
- uint8_t ioregsel;
- uint32_t irr;
- uint64_t ioredtbl[IOAPIC_NUM_PINS];
- Notifier machine_done;
- uint8_t version;
- uint64_t irq_count[IOAPIC_NUM_PINS];
- int irq_level[IOAPIC_NUM_PINS];
- int irq_eoi[IOAPIC_NUM_PINS];
- QEMUTimer *delayed_ioapic_service_timer;
-};
-
-void ioapic_reset_common(DeviceState *dev);
-
-void ioapic_print_redtbl(Monitor *mon, IOAPICCommonState *s);
-void ioapic_stat_update_irq(IOAPICCommonState *s, int irq, int level);
-
-#endif /* QEMU_IOAPIC_INTERNAL_H */
+++ /dev/null
-/*
- * Copyright (c) 2018 Intel Corporation
- * Copyright (c) 2019 Red Hat, Inc.
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms and conditions of the GNU General Public License,
- * version 2 or later, as published by the Free Software Foundation.
- *
- * This program is distributed in the hope it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License along with
- * this program. If not, see <http://www.gnu.org/licenses/>.
- */
-
-#ifndef HW_I386_MICROVM_H
-#define HW_I386_MICROVM_H
-
-#include "qemu-common.h"
-#include "exec/hwaddr.h"
-#include "qemu/notify.h"
-
-#include "hw/boards.h"
-#include "hw/i386/x86.h"
-#include "hw/acpi/acpi_dev_interface.h"
-#include "hw/pci-host/gpex.h"
-#include "qom/object.h"
-
-/*
- * IRQ | pc | microvm (acpi=on)
- * --------+------------+------------------
- * 0 | pit |
- * 1 | kbd |
- * 2 | cascade |
- * 3 | serial 1 |
- * 4 | serial 0 | serial
- * 5 | - |
- * 6 | floppy |
- * 7 | parallel |
- * 8 | rtc | rtc (rtc=on)
- * 9 | acpi | acpi (ged)
- * 10 | pci lnk | xhci (usb=on)
- * 11 | pci lnk |
- * 12 | ps2 | pcie
- * 13 | fpu | pcie
- * 14 | ide 0 | pcie
- * 15 | ide 1 | pcie
- * 16-23 | pci gsi | virtio
- */
-
-/* Platform virtio definitions */
-#define VIRTIO_MMIO_BASE 0xfeb00000
-#define VIRTIO_NUM_TRANSPORTS 8
-#define VIRTIO_CMDLINE_MAXLEN 64
-
-#define GED_MMIO_BASE 0xfea00000
-#define GED_MMIO_BASE_MEMHP (GED_MMIO_BASE + 0x100)
-#define GED_MMIO_BASE_REGS (GED_MMIO_BASE + 0x200)
-#define GED_MMIO_IRQ 9
-
-#define MICROVM_XHCI_BASE 0xfe900000
-#define MICROVM_XHCI_IRQ 10
-
-#define PCIE_MMIO_BASE 0xc0000000
-#define PCIE_MMIO_SIZE 0x20000000
-#define PCIE_ECAM_BASE 0xe0000000
-#define PCIE_ECAM_SIZE 0x10000000
-#define PCIE_IRQ_BASE 12
-
-/* Machine type options */
-#define MICROVM_MACHINE_PIT "pit"
-#define MICROVM_MACHINE_PIC "pic"
-#define MICROVM_MACHINE_RTC "rtc"
-#define MICROVM_MACHINE_PCIE "pcie"
-#define MICROVM_MACHINE_ISA_SERIAL "isa-serial"
-#define MICROVM_MACHINE_OPTION_ROMS "x-option-roms"
-#define MICROVM_MACHINE_AUTO_KERNEL_CMDLINE "auto-kernel-cmdline"
-
-struct MicrovmMachineClass {
- X86MachineClass parent;
- HotplugHandler *(*orig_hotplug_handler)(MachineState *machine,
- DeviceState *dev);
-};
-
-struct MicrovmMachineState {
- X86MachineState parent;
-
- /* Machine type options */
- OnOffAuto pic;
- OnOffAuto pit;
- OnOffAuto rtc;
- OnOffAuto pcie;
- bool isa_serial;
- bool option_roms;
- bool auto_kernel_cmdline;
-
- /* Machine state */
- uint32_t virtio_irq_base;
- bool kernel_cmdline_fixed;
- Notifier machine_done;
- Notifier powerdown_req;
- struct GPEXConfig gpex;
-};
-
-#define TYPE_MICROVM_MACHINE MACHINE_TYPE_NAME("microvm")
-OBJECT_DECLARE_TYPE(MicrovmMachineState, MicrovmMachineClass, MICROVM_MACHINE)
-
-#endif
+++ /dev/null
-#ifndef HW_PC_H
-#define HW_PC_H
-
-#include "qemu/notify.h"
-#include "qapi/qapi-types-common.h"
-#include "hw/boards.h"
-#include "hw/block/fdc.h"
-#include "hw/block/flash.h"
-#include "hw/i386/x86.h"
-
-#include "hw/acpi/acpi_dev_interface.h"
-#include "hw/hotplug.h"
-#include "qom/object.h"
-
-#define HPET_INTCAP "hpet-intcap"
-
-/**
- * PCMachineState:
- * @acpi_dev: link to ACPI PM device that performs ACPI hotplug handling
- * @boot_cpus: number of present VCPUs
- * @smp_dies: number of dies per one package
- */
-typedef struct PCMachineState {
- /*< private >*/
- X86MachineState parent_obj;
-
- /* <public> */
-
- /* State for other subsystems/APIs: */
- Notifier machine_done;
-
- /* Pointers to devices and objects: */
- PCIBus *bus;
- I2CBus *smbus;
- PFlashCFI01 *flash[2];
- ISADevice *pcspk;
-
- /* Configuration options: */
- uint64_t max_ram_below_4g;
- OnOffAuto vmport;
-
- bool acpi_build_enabled;
- bool smbus_enabled;
- bool sata_enabled;
- bool pit_enabled;
- bool hpet_enabled;
-
- /* NUMA information: */
- uint64_t numa_nodes;
- uint64_t *node_mem;
-
- /* ACPI Memory hotplug IO base address */
- hwaddr memhp_io_base;
-} PCMachineState;
-
-#define PC_MACHINE_ACPI_DEVICE_PROP "acpi-device"
-#define PC_MACHINE_MAX_RAM_BELOW_4G "max-ram-below-4g"
-#define PC_MACHINE_DEVMEM_REGION_SIZE "device-memory-region-size"
-#define PC_MACHINE_VMPORT "vmport"
-#define PC_MACHINE_SMBUS "smbus"
-#define PC_MACHINE_SATA "sata"
-#define PC_MACHINE_PIT "pit"
-
-/**
- * PCMachineClass:
- *
- * Compat fields:
- *
- * @enforce_aligned_dimm: check that DIMM's address/size is aligned by
- * backend's alignment value if provided
- * @acpi_data_size: Size of the chunk of memory at the top of RAM
- * for the BIOS ACPI tables and other BIOS
- * datastructures.
- * @gigabyte_align: Make sure that guest addresses aligned at
- * 1Gbyte boundaries get mapped to host
- * addresses aligned at 1Gbyte boundaries. This
- * way we can use 1GByte pages in the host.
- *
- */
-struct PCMachineClass {
- /*< private >*/
- X86MachineClass parent_class;
-
- /*< public >*/
-
- /* Device configuration: */
- bool pci_enabled;
- bool kvmclock_enabled;
- const char *default_nic_model;
-
- /* Compat options: */
-
- /* Default CPU model version. See x86_cpu_set_default_version(). */
- int default_cpu_version;
-
- /* ACPI compat: */
- bool has_acpi_build;
- bool rsdp_in_ram;
- int legacy_acpi_table_size;
- unsigned acpi_data_size;
- bool do_not_add_smb_acpi;
- int pci_root_uid;
-
- /* SMBIOS compat: */
- bool smbios_defaults;
- bool smbios_legacy_mode;
- bool smbios_uuid_encoded;
-
- /* RAM / address space compat: */
- bool gigabyte_align;
- bool has_reserved_memory;
- bool enforce_aligned_dimm;
- bool broken_reserved_end;
-
- /* generate legacy CPU hotplug AML */
- bool legacy_cpu_hotplug;
-
- /* use DMA capable linuxboot option rom */
- bool linuxboot_dma_enabled;
-
- /* use PVH to load kernels that support this feature */
- bool pvh_enabled;
-
- /* create kvmclock device even when KVM PV features are not exposed */
- bool kvmclock_create_always;
-};
-
-#define TYPE_PC_MACHINE "generic-pc-machine"
-OBJECT_DECLARE_TYPE(PCMachineState, PCMachineClass, PC_MACHINE)
-
-/* ioapic.c */
-
-GSIState *pc_gsi_create(qemu_irq **irqs, bool pci_enabled);
-
-/* pc.c */
-extern int fd_bootchk;
-
-void pc_acpi_smi_interrupt(void *opaque, int irq, int level);
-
-void pc_smp_parse(MachineState *ms, QemuOpts *opts);
-
-void pc_guest_info_init(PCMachineState *pcms);
-
-#define PCI_HOST_PROP_PCI_HOLE_START "pci-hole-start"
-#define PCI_HOST_PROP_PCI_HOLE_END "pci-hole-end"
-#define PCI_HOST_PROP_PCI_HOLE64_START "pci-hole64-start"
-#define PCI_HOST_PROP_PCI_HOLE64_END "pci-hole64-end"
-#define PCI_HOST_PROP_PCI_HOLE64_SIZE "pci-hole64-size"
-#define PCI_HOST_BELOW_4G_MEM_SIZE "below-4g-mem-size"
-#define PCI_HOST_ABOVE_4G_MEM_SIZE "above-4g-mem-size"
-
-
-void pc_pci_as_mapping_init(Object *owner, MemoryRegion *system_memory,
- MemoryRegion *pci_address_space);
-
-void xen_load_linux(PCMachineState *pcms);
-void pc_memory_init(PCMachineState *pcms,
- MemoryRegion *system_memory,
- MemoryRegion *rom_memory,
- MemoryRegion **ram_memory);
-uint64_t pc_pci_hole64_start(void);
-DeviceState *pc_vga_init(ISABus *isa_bus, PCIBus *pci_bus);
-void pc_basic_device_init(struct PCMachineState *pcms,
- ISABus *isa_bus, qemu_irq *gsi,
- ISADevice **rtc_state,
- bool create_fdctrl,
- uint32_t hpet_irqs);
-void pc_init_ne2k_isa(ISABus *bus, NICInfo *nd);
-void pc_cmos_init(PCMachineState *pcms,
- BusState *ide0, BusState *ide1,
- ISADevice *s);
-void pc_nic_init(PCMachineClass *pcmc, ISABus *isa_bus, PCIBus *pci_bus);
-void pc_pci_device_init(PCIBus *pci_bus);
-
-typedef void (*cpu_set_smm_t)(int smm, void *arg);
-
-void pc_i8259_create(ISABus *isa_bus, qemu_irq *i8259_irqs);
-
-ISADevice *pc_find_fdc0(void);
-
-/* port92.c */
-#define PORT92_A20_LINE "a20"
-
-#define TYPE_PORT92 "port92"
-
-/* pc_sysfw.c */
-void pc_system_flash_create(PCMachineState *pcms);
-void pc_system_flash_cleanup_unused(PCMachineState *pcms);
-void pc_system_firmware_init(PCMachineState *pcms, MemoryRegion *rom_memory);
-
-/* acpi-build.c */
-void pc_madt_cpu_entry(AcpiDeviceIf *adev, int uid,
- const CPUArchIdList *apic_ids, GArray *entry);
-
-extern GlobalProperty pc_compat_5_1[];
-extern const size_t pc_compat_5_1_len;
-
-extern GlobalProperty pc_compat_5_0[];
-extern const size_t pc_compat_5_0_len;
-
-extern GlobalProperty pc_compat_4_2[];
-extern const size_t pc_compat_4_2_len;
-
-extern GlobalProperty pc_compat_4_1[];
-extern const size_t pc_compat_4_1_len;
-
-extern GlobalProperty pc_compat_4_0[];
-extern const size_t pc_compat_4_0_len;
-
-extern GlobalProperty pc_compat_3_1[];
-extern const size_t pc_compat_3_1_len;
-
-extern GlobalProperty pc_compat_3_0[];
-extern const size_t pc_compat_3_0_len;
-
-extern GlobalProperty pc_compat_2_12[];
-extern const size_t pc_compat_2_12_len;
-
-extern GlobalProperty pc_compat_2_11[];
-extern const size_t pc_compat_2_11_len;
-
-extern GlobalProperty pc_compat_2_10[];
-extern const size_t pc_compat_2_10_len;
-
-extern GlobalProperty pc_compat_2_9[];
-extern const size_t pc_compat_2_9_len;
-
-extern GlobalProperty pc_compat_2_8[];
-extern const size_t pc_compat_2_8_len;
-
-extern GlobalProperty pc_compat_2_7[];
-extern const size_t pc_compat_2_7_len;
-
-extern GlobalProperty pc_compat_2_6[];
-extern const size_t pc_compat_2_6_len;
-
-extern GlobalProperty pc_compat_2_5[];
-extern const size_t pc_compat_2_5_len;
-
-extern GlobalProperty pc_compat_2_4[];
-extern const size_t pc_compat_2_4_len;
-
-extern GlobalProperty pc_compat_2_3[];
-extern const size_t pc_compat_2_3_len;
-
-extern GlobalProperty pc_compat_2_2[];
-extern const size_t pc_compat_2_2_len;
-
-extern GlobalProperty pc_compat_2_1[];
-extern const size_t pc_compat_2_1_len;
-
-extern GlobalProperty pc_compat_2_0[];
-extern const size_t pc_compat_2_0_len;
-
-extern GlobalProperty pc_compat_1_7[];
-extern const size_t pc_compat_1_7_len;
-
-extern GlobalProperty pc_compat_1_6[];
-extern const size_t pc_compat_1_6_len;
-
-extern GlobalProperty pc_compat_1_5[];
-extern const size_t pc_compat_1_5_len;
-
-extern GlobalProperty pc_compat_1_4[];
-extern const size_t pc_compat_1_4_len;
-
-/* Helper for setting model-id for CPU models that changed model-id
- * depending on QEMU versions up to QEMU 2.4.
- */
-#define PC_CPU_MODEL_IDS(v) \
- { "qemu32-" TYPE_X86_CPU, "model-id", "QEMU Virtual CPU version " v, },\
- { "qemu64-" TYPE_X86_CPU, "model-id", "QEMU Virtual CPU version " v, },\
- { "athlon-" TYPE_X86_CPU, "model-id", "QEMU Virtual CPU version " v, },
-
-#define DEFINE_PC_MACHINE(suffix, namestr, initfn, optsfn) \
- static void pc_machine_##suffix##_class_init(ObjectClass *oc, void *data) \
- { \
- MachineClass *mc = MACHINE_CLASS(oc); \
- optsfn(mc); \
- mc->init = initfn; \
- } \
- static const TypeInfo pc_machine_type_##suffix = { \
- .name = namestr TYPE_MACHINE_SUFFIX, \
- .parent = TYPE_PC_MACHINE, \
- .class_init = pc_machine_##suffix##_class_init, \
- }; \
- static void pc_machine_init_##suffix(void) \
- { \
- type_register(&pc_machine_type_##suffix); \
- } \
- type_init(pc_machine_init_##suffix)
-
-extern void igd_passthrough_isa_bridge_create(PCIBus *bus, uint16_t gpu_dev_id);
-#endif
+++ /dev/null
-/*
- * x86 CPU topology data structures and functions
- *
- * Copyright (c) 2012 Red Hat Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
- * furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
- * THE SOFTWARE.
- */
-#ifndef HW_I386_TOPOLOGY_H
-#define HW_I386_TOPOLOGY_H
-
-/* This file implements the APIC-ID-based CPU topology enumeration logic,
- * documented at the following document:
- * Intel® 64 Architecture Processor Topology Enumeration
- * http://software.intel.com/en-us/articles/intel-64-architecture-processor-topology-enumeration/
- *
- * This code should be compatible with AMD's "Extended Method" described at:
- * AMD CPUID Specification (Publication #25481)
- * Section 3: Multiple Core Calcuation
- * as long as:
- * nr_threads is set to 1;
- * OFFSET_IDX is assumed to be 0;
- * CPUID Fn8000_0008_ECX[ApicIdCoreIdSize[3:0]] is set to apicid_core_width().
- */
-
-
-#include "qemu/bitops.h"
-
-/* APIC IDs can be 32-bit, but beware: APIC IDs > 255 require x2APIC support
- */
-typedef uint32_t apic_id_t;
-
-typedef struct X86CPUTopoIDs {
- unsigned pkg_id;
- unsigned die_id;
- unsigned core_id;
- unsigned smt_id;
-} X86CPUTopoIDs;
-
-typedef struct X86CPUTopoInfo {
- unsigned dies_per_pkg;
- unsigned cores_per_die;
- unsigned threads_per_core;
-} X86CPUTopoInfo;
-
-/* Return the bit width needed for 'count' IDs
- */
-static unsigned apicid_bitwidth_for_count(unsigned count)
-{
- g_assert(count >= 1);
- count -= 1;
- return count ? 32 - clz32(count) : 0;
-}
-
-/* Bit width of the SMT_ID (thread ID) field on the APIC ID
- */
-static inline unsigned apicid_smt_width(X86CPUTopoInfo *topo_info)
-{
- return apicid_bitwidth_for_count(topo_info->threads_per_core);
-}
-
-/* Bit width of the Core_ID field
- */
-static inline unsigned apicid_core_width(X86CPUTopoInfo *topo_info)
-{
- return apicid_bitwidth_for_count(topo_info->cores_per_die);
-}
-
-/* Bit width of the Die_ID field */
-static inline unsigned apicid_die_width(X86CPUTopoInfo *topo_info)
-{
- return apicid_bitwidth_for_count(topo_info->dies_per_pkg);
-}
-
-/* Bit offset of the Core_ID field
- */
-static inline unsigned apicid_core_offset(X86CPUTopoInfo *topo_info)
-{
- return apicid_smt_width(topo_info);
-}
-
-/* Bit offset of the Die_ID field */
-static inline unsigned apicid_die_offset(X86CPUTopoInfo *topo_info)
-{
- return apicid_core_offset(topo_info) + apicid_core_width(topo_info);
-}
-
-/* Bit offset of the Pkg_ID (socket ID) field
- */
-static inline unsigned apicid_pkg_offset(X86CPUTopoInfo *topo_info)
-{
- return apicid_die_offset(topo_info) + apicid_die_width(topo_info);
-}
-
-/* Make APIC ID for the CPU based on Pkg_ID, Core_ID, SMT_ID
- *
- * The caller must make sure core_id < nr_cores and smt_id < nr_threads.
- */
-static inline apic_id_t x86_apicid_from_topo_ids(X86CPUTopoInfo *topo_info,
- const X86CPUTopoIDs *topo_ids)
-{
- return (topo_ids->pkg_id << apicid_pkg_offset(topo_info)) |
- (topo_ids->die_id << apicid_die_offset(topo_info)) |
- (topo_ids->core_id << apicid_core_offset(topo_info)) |
- topo_ids->smt_id;
-}
-
-/* Calculate thread/core/package IDs for a specific topology,
- * based on (contiguous) CPU index
- */
-static inline void x86_topo_ids_from_idx(X86CPUTopoInfo *topo_info,
- unsigned cpu_index,
- X86CPUTopoIDs *topo_ids)
-{
- unsigned nr_dies = topo_info->dies_per_pkg;
- unsigned nr_cores = topo_info->cores_per_die;
- unsigned nr_threads = topo_info->threads_per_core;
-
- topo_ids->pkg_id = cpu_index / (nr_dies * nr_cores * nr_threads);
- topo_ids->die_id = cpu_index / (nr_cores * nr_threads) % nr_dies;
- topo_ids->core_id = cpu_index / nr_threads % nr_cores;
- topo_ids->smt_id = cpu_index % nr_threads;
-}
-
-/* Calculate thread/core/package IDs for a specific topology,
- * based on APIC ID
- */
-static inline void x86_topo_ids_from_apicid(apic_id_t apicid,
- X86CPUTopoInfo *topo_info,
- X86CPUTopoIDs *topo_ids)
-{
- topo_ids->smt_id = apicid &
- ~(0xFFFFFFFFUL << apicid_smt_width(topo_info));
- topo_ids->core_id =
- (apicid >> apicid_core_offset(topo_info)) &
- ~(0xFFFFFFFFUL << apicid_core_width(topo_info));
- topo_ids->die_id =
- (apicid >> apicid_die_offset(topo_info)) &
- ~(0xFFFFFFFFUL << apicid_die_width(topo_info));
- topo_ids->pkg_id = apicid >> apicid_pkg_offset(topo_info);
-}
-
-/* Make APIC ID for the CPU 'cpu_index'
- *
- * 'cpu_index' is a sequential, contiguous ID for the CPU.
- */
-static inline apic_id_t x86_apicid_from_cpu_idx(X86CPUTopoInfo *topo_info,
- unsigned cpu_index)
-{
- X86CPUTopoIDs topo_ids;
- x86_topo_ids_from_idx(topo_info, cpu_index, &topo_ids);
- return x86_apicid_from_topo_ids(topo_info, &topo_ids);
-}
-
-#endif /* HW_I386_TOPOLOGY_H */
+++ /dev/null
-#ifndef HW_VMPORT_H
-#define HW_VMPORT_H
-
-#include "hw/isa/isa.h"
-
-#define TYPE_VMPORT "vmport"
-typedef uint32_t VMPortReadFunc(void *opaque, uint32_t address);
-
-typedef enum {
- VMPORT_CMD_GETVERSION = 10,
- VMPORT_CMD_GETBIOSUUID = 19,
- VMPORT_CMD_GETRAMSIZE = 20,
- VMPORT_CMD_VMMOUSE_DATA = 39,
- VMPORT_CMD_VMMOUSE_STATUS = 40,
- VMPORT_CMD_VMMOUSE_COMMAND = 41,
- VMPORT_CMD_GETHZ = 45,
- VMPORT_CMD_GET_VCPU_INFO = 68,
- VMPORT_ENTRIES
-} VMPortCommand;
-
-static inline void vmport_init(ISABus *bus)
-{
- isa_create_simple(bus, TYPE_VMPORT);
-}
-
-void vmport_register(VMPortCommand command, VMPortReadFunc *func, void *opaque);
-
-#endif
+++ /dev/null
-/*
- * Common IOMMU interface for X86 platform
- *
- * Copyright (C) 2016 Peter Xu, Red Hat <peterx@redhat.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
-
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
-
- * You should have received a copy of the GNU General Public License along
- * with this program; if not, see <http://www.gnu.org/licenses/>.
- */
-
-#ifndef HW_I386_X86_IOMMU_H
-#define HW_I386_X86_IOMMU_H
-
-#include "hw/sysbus.h"
-#include "hw/pci/pci.h"
-#include "hw/pci/msi.h"
-#include "qom/object.h"
-
-#define TYPE_X86_IOMMU_DEVICE ("x86-iommu")
-OBJECT_DECLARE_TYPE(X86IOMMUState, X86IOMMUClass, X86_IOMMU_DEVICE)
-
-#define X86_IOMMU_SID_INVALID (0xffff)
-
-typedef struct X86IOMMUIrq X86IOMMUIrq;
-typedef struct X86IOMMU_MSIMessage X86IOMMU_MSIMessage;
-
-typedef enum IommuType {
- TYPE_INTEL,
- TYPE_AMD,
- TYPE_NONE
-} IommuType;
-
-struct X86IOMMUClass {
- SysBusDeviceClass parent;
- /* Intel/AMD specific realize() hook */
- DeviceRealize realize;
- /* MSI-based interrupt remapping */
- int (*int_remap)(X86IOMMUState *iommu, MSIMessage *src,
- MSIMessage *dst, uint16_t sid);
-};
-
-/**
- * iec_notify_fn - IEC (Interrupt Entry Cache) notifier hook,
- * triggered when IR invalidation happens.
- * @private: private data
- * @global: whether this is a global IEC invalidation
- * @index: IRTE index to invalidate (start from)
- * @mask: invalidation mask
- */
-typedef void (*iec_notify_fn)(void *private, bool global,
- uint32_t index, uint32_t mask);
-
-struct IEC_Notifier {
- iec_notify_fn iec_notify;
- void *private;
- QLIST_ENTRY(IEC_Notifier) list;
-};
-typedef struct IEC_Notifier IEC_Notifier;
-
-struct X86IOMMUState {
- SysBusDevice busdev;
- OnOffAuto intr_supported; /* Whether vIOMMU supports IR */
- bool dt_supported; /* Whether vIOMMU supports DT */
- bool pt_supported; /* Whether vIOMMU supports pass-through */
- IommuType type; /* IOMMU type - AMD/Intel */
- QLIST_HEAD(, IEC_Notifier) iec_notifiers; /* IEC notify list */
-};
-
-bool x86_iommu_ir_supported(X86IOMMUState *s);
-
-/* Generic IRQ entry information when interrupt remapping is enabled */
-struct X86IOMMUIrq {
- /* Used by both IOAPIC/MSI interrupt remapping */
- uint8_t trigger_mode;
- uint8_t vector;
- uint8_t delivery_mode;
- uint32_t dest;
- uint8_t dest_mode;
-
- /* only used by MSI interrupt remapping */
- uint8_t redir_hint;
- uint8_t msi_addr_last_bits;
-};
-
-struct X86IOMMU_MSIMessage {
- union {
- struct {
-#ifdef HOST_WORDS_BIGENDIAN
- uint32_t __addr_head:12; /* 0xfee */
- uint32_t dest:8;
- uint32_t __reserved:8;
- uint32_t redir_hint:1;
- uint32_t dest_mode:1;
- uint32_t __not_used:2;
-#else
- uint32_t __not_used:2;
- uint32_t dest_mode:1;
- uint32_t redir_hint:1;
- uint32_t __reserved:8;
- uint32_t dest:8;
- uint32_t __addr_head:12; /* 0xfee */
-#endif
- uint32_t __addr_hi;
- } QEMU_PACKED;
- uint64_t msi_addr;
- };
- union {
- struct {
-#ifdef HOST_WORDS_BIGENDIAN
- uint16_t trigger_mode:1;
- uint16_t level:1;
- uint16_t __resved:3;
- uint16_t delivery_mode:3;
- uint16_t vector:8;
-#else
- uint16_t vector:8;
- uint16_t delivery_mode:3;
- uint16_t __resved:3;
- uint16_t level:1;
- uint16_t trigger_mode:1;
-#endif
- uint16_t __resved1;
- } QEMU_PACKED;
- uint32_t msi_data;
- };
-};
-
-/**
- * x86_iommu_get_default - get default IOMMU device
- * @return: pointer to default IOMMU device
- */
-X86IOMMUState *x86_iommu_get_default(void);
-
-/*
- * x86_iommu_get_type - get IOMMU type
- */
-IommuType x86_iommu_get_type(void);
-
-/**
- * x86_iommu_iec_register_notifier - register IEC (Interrupt Entry
- * Cache) notifiers
- * @iommu: IOMMU device to register
- * @fn: IEC notifier hook function
- * @data: notifier private data
- */
-void x86_iommu_iec_register_notifier(X86IOMMUState *iommu,
- iec_notify_fn fn, void *data);
-
-/**
- * x86_iommu_iec_notify_all - Notify IEC invalidations
- * @iommu: IOMMU device that sends the notification
- * @global: whether this is a global invalidation. If true, @index
- * and @mask are undefined.
- * @index: starting index of interrupt entry to invalidate
- * @mask: index mask for the invalidation
- */
-void x86_iommu_iec_notify_all(X86IOMMUState *iommu, bool global,
- uint32_t index, uint32_t mask);
-
-/**
- * x86_iommu_irq_to_msi_message - Populate one MSIMessage from X86IOMMUIrq
- * @X86IOMMUIrq: The IRQ information
- * @out: Output MSI message
- */
-void x86_iommu_irq_to_msi_message(X86IOMMUIrq *irq, MSIMessage *out);
-#endif
+++ /dev/null
-/*
- * Copyright (c) 2019 Red Hat, Inc.
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms and conditions of the GNU General Public License,
- * version 2 or later, as published by the Free Software Foundation.
- *
- * This program is distributed in the hope it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License along with
- * this program. If not, see <http://www.gnu.org/licenses/>.
- */
-
-#ifndef HW_I386_X86_H
-#define HW_I386_X86_H
-
-#include "qemu-common.h"
-#include "exec/hwaddr.h"
-#include "qemu/notify.h"
-
-#include "hw/i386/topology.h"
-#include "hw/boards.h"
-#include "hw/nmi.h"
-#include "hw/isa/isa.h"
-#include "hw/i386/ioapic.h"
-#include "qom/object.h"
-
-struct X86MachineClass {
- /*< private >*/
- MachineClass parent;
-
- /*< public >*/
-
- /* TSC rate migration: */
- bool save_tsc_khz;
- /* Enables contiguous-apic-ID mode */
- bool compat_apic_id_mode;
-};
-
-struct X86MachineState {
- /*< private >*/
- MachineState parent;
-
- /*< public >*/
-
- /* Pointers to devices and objects: */
- ISADevice *rtc;
- FWCfgState *fw_cfg;
- qemu_irq *gsi;
- GMappedFile *initrd_mapped_file;
- HotplugHandler *acpi_dev;
-
- /* RAM information (sizes, addresses, configuration): */
- ram_addr_t below_4g_mem_size, above_4g_mem_size;
-
- /* CPU and apic information: */
- bool apic_xrupt_override;
- unsigned pci_irq_mask;
- unsigned apic_id_limit;
- uint16_t boot_cpus;
- unsigned smp_dies;
-
- OnOffAuto smm;
- OnOffAuto acpi;
-
- /*
- * Address space used by IOAPIC device. All IOAPIC interrupts
- * will be translated to MSI messages in the address space.
- */
- AddressSpace *ioapic_as;
-};
-
-#define X86_MACHINE_SMM "smm"
-#define X86_MACHINE_ACPI "acpi"
-
-#define TYPE_X86_MACHINE MACHINE_TYPE_NAME("x86")
-OBJECT_DECLARE_TYPE(X86MachineState, X86MachineClass, X86_MACHINE)
-
-void init_topo_info(X86CPUTopoInfo *topo_info, const X86MachineState *x86ms);
-
-uint32_t x86_cpu_apic_id_from_index(X86MachineState *pcms,
- unsigned int cpu_index);
-
-void x86_cpu_new(X86MachineState *pcms, int64_t apic_id, Error **errp);
-void x86_cpus_init(X86MachineState *pcms, int default_cpu_version);
-CpuInstanceProperties x86_cpu_index_to_props(MachineState *ms,
- unsigned cpu_index);
-int64_t x86_get_default_cpu_node_id(const MachineState *ms, int idx);
-const CPUArchIdList *x86_possible_cpu_arch_ids(MachineState *ms);
-CPUArchId *x86_find_cpu_slot(MachineState *ms, uint32_t id, int *idx);
-void x86_rtc_set_cpus_count(ISADevice *rtc, uint16_t cpus_count);
-void x86_cpu_pre_plug(HotplugHandler *hotplug_dev,
- DeviceState *dev, Error **errp);
-void x86_cpu_plug(HotplugHandler *hotplug_dev,
- DeviceState *dev, Error **errp);
-void x86_cpu_unplug_request_cb(HotplugHandler *hotplug_dev,
- DeviceState *dev, Error **errp);
-void x86_cpu_unplug_cb(HotplugHandler *hotplug_dev,
- DeviceState *dev, Error **errp);
-
-void x86_bios_rom_init(MemoryRegion *rom_memory, bool isapc_ram_fw);
-
-void x86_load_linux(X86MachineState *x86ms,
- FWCfgState *fw_cfg,
- int acpi_data_size,
- bool pvh_enabled,
- bool linuxboot_dma_enabled);
-
-bool x86_machine_is_smm_enabled(const X86MachineState *x86ms);
-bool x86_machine_is_acpi_enabled(const X86MachineState *x86ms);
-
-/* Global System Interrupts */
-
-#define GSI_NUM_PINS IOAPIC_NUM_PINS
-#define ACPI_BUILD_PCI_IRQS ((1<<5) | (1<<9) | (1<<10) | (1<<11))
-
-typedef struct GSIState {
- qemu_irq i8259_irq[ISA_NUM_IRQS];
- qemu_irq ioapic_irq[IOAPIC_NUM_PINS];
-} GSIState;
-
-qemu_irq x86_allocate_cpu_irq(void);
-void gsi_handler(void *opaque, int n, int level);
-void ioapic_init_gsi(GSIState *gsi_state, const char *parent_name);
-
-#endif
+++ /dev/null
-/*
- * QEMU AHCI Emulation
- *
- * Copyright (c) 2010 qiaochong@loongson.cn
- * Copyright (c) 2010 Roland Elek <elek.roland@gmail.com>
- * Copyright (c) 2010 Sebastian Herbszt <herbszt@gmx.de>
- * Copyright (c) 2010 Alexander Graf <agraf@suse.de>
- *
- * This library is free software; you can redistribute it and/or
- * modify it under the terms of the GNU Lesser General Public
- * License as published by the Free Software Foundation; either
- * version 2.1 of the License, or (at your option) any later version.
- *
- * This library is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
- * Lesser General Public License for more details.
- *
- * You should have received a copy of the GNU Lesser General Public
- * License along with this library; if not, see <http://www.gnu.org/licenses/>.
- *
- */
-
-#ifndef HW_IDE_AHCI_H
-#define HW_IDE_AHCI_H
-
-#include "hw/sysbus.h"
-#include "qom/object.h"
-
-typedef struct AHCIDevice AHCIDevice;
-
-typedef struct AHCIControlRegs {
- uint32_t cap;
- uint32_t ghc;
- uint32_t irqstatus;
- uint32_t impl;
- uint32_t version;
-} AHCIControlRegs;
-
-typedef struct AHCIState {
- DeviceState *container;
-
- AHCIDevice *dev;
- AHCIControlRegs control_regs;
- MemoryRegion mem;
- MemoryRegion idp; /* Index-Data Pair I/O port space */
- unsigned idp_offset; /* Offset of index in I/O port space */
- uint32_t idp_index; /* Current IDP index */
- int32_t ports;
- qemu_irq irq;
- AddressSpace *as;
-} AHCIState;
-
-
-#define TYPE_ICH9_AHCI "ich9-ahci"
-OBJECT_DECLARE_SIMPLE_TYPE(AHCIPCIState, ICH9_AHCI)
-
-int32_t ahci_get_num_ports(PCIDevice *dev);
-void ahci_ide_create_devs(PCIDevice *dev, DriveInfo **hd);
-
-#define TYPE_SYSBUS_AHCI "sysbus-ahci"
-OBJECT_DECLARE_SIMPLE_TYPE(SysbusAHCIState, SYSBUS_AHCI)
-
-struct SysbusAHCIState {
- /*< private >*/
- SysBusDevice parent_obj;
- /*< public >*/
-
- AHCIState ahci;
- uint32_t num_ports;
-};
-
-#define TYPE_ALLWINNER_AHCI "allwinner-ahci"
-OBJECT_DECLARE_SIMPLE_TYPE(AllwinnerAHCIState, ALLWINNER_AHCI)
-
-#define ALLWINNER_AHCI_MMIO_OFF 0x80
-#define ALLWINNER_AHCI_MMIO_SIZE 0x80
-
-struct AllwinnerAHCIState {
- /*< private >*/
- SysbusAHCIState parent_obj;
- /*< public >*/
-
- MemoryRegion mmio;
- uint32_t regs[ALLWINNER_AHCI_MMIO_SIZE/4];
-};
-
-#endif /* HW_IDE_AHCI_H */
+++ /dev/null
-#ifndef HW_IDE_INTERNAL_H
-#define HW_IDE_INTERNAL_H
-
-/*
- * QEMU IDE Emulation -- internal header file
- * only files in hw/ide/ are supposed to include this file.
- * non-internal declarations are in hw/ide.h
- */
-
-#include "qapi/qapi-types-run-state.h"
-#include "hw/ide.h"
-#include "hw/irq.h"
-#include "hw/isa/isa.h"
-#include "sysemu/dma.h"
-#include "hw/block/block.h"
-#include "scsi/constants.h"
-
-/* debug IDE devices */
-#define USE_DMA_CDROM
-#include "qom/object.h"
-
-typedef struct IDEDevice IDEDevice;
-typedef struct IDEState IDEState;
-typedef struct IDEDMA IDEDMA;
-typedef struct IDEDMAOps IDEDMAOps;
-
-#define TYPE_IDE_BUS "IDE"
-OBJECT_DECLARE_SIMPLE_TYPE(IDEBus, IDE_BUS)
-
-#define MAX_IDE_DEVS 2
-
-/* Device/Head ("select") Register */
-#define ATA_DEV_SELECT 0x10
-/* ATA1,3: Defined as '1'.
- * ATA2: Reserved.
- * ATA3-7: obsolete. */
-#define ATA_DEV_ALWAYS_ON 0xA0
-#define ATA_DEV_LBA 0x40
-#define ATA_DEV_LBA_MSB 0x0F /* LBA 24:27 */
-#define ATA_DEV_HS 0x0F /* HS 3:0 */
-
-
-/* Bits of HD_STATUS */
-#define ERR_STAT 0x01
-#define INDEX_STAT 0x02
-#define ECC_STAT 0x04 /* Corrected error */
-#define DRQ_STAT 0x08
-#define SEEK_STAT 0x10
-#define SRV_STAT 0x10
-#define WRERR_STAT 0x20
-#define READY_STAT 0x40
-#define BUSY_STAT 0x80
-
-/* Bits for HD_ERROR */
-#define MARK_ERR 0x01 /* Bad address mark */
-#define TRK0_ERR 0x02 /* couldn't find track 0 */
-#define ABRT_ERR 0x04 /* Command aborted */
-#define MCR_ERR 0x08 /* media change request */
-#define ID_ERR 0x10 /* ID field not found */
-#define MC_ERR 0x20 /* media changed */
-#define ECC_ERR 0x40 /* Uncorrectable ECC error */
-#define BBD_ERR 0x80 /* pre-EIDE meaning: block marked bad */
-#define ICRC_ERR 0x80 /* new meaning: CRC error during transfer */
-
-/* Bits of HD_NSECTOR */
-#define CD 0x01
-#define IO 0x02
-#define REL 0x04
-#define TAG_MASK 0xf8
-
-/* Bits of Device Control register */
-#define IDE_CTRL_HOB 0x80
-#define IDE_CTRL_RESET 0x04
-#define IDE_CTRL_DISABLE_IRQ 0x02
-
-/* ACS-2 T13/2015-D Table B.2 Command codes */
-#define WIN_NOP 0x00
-/* reserved 0x01..0x02 */
-#define CFA_REQ_EXT_ERROR_CODE 0x03 /* CFA Request Extended Error Code */
-/* reserved 0x04..0x05 */
-#define WIN_DSM 0x06
-/* reserved 0x07 */
-#define WIN_DEVICE_RESET 0x08
-/* reserved 0x09..0x0a */
-/* REQUEST SENSE DATA EXT 0x0B */
-/* reserved 0x0C..0x0F */
-#define WIN_RECAL 0x10 /* obsolete since ATA4 */
-/* obsolete since ATA3, retired in ATA4 0x11..0x1F */
-#define WIN_READ 0x20 /* 28-Bit */
-#define WIN_READ_ONCE 0x21 /* 28-Bit w/o retries, obsolete since ATA5 */
-/* obsolete since ATA4 0x22..0x23 */
-#define WIN_READ_EXT 0x24 /* 48-Bit */
-#define WIN_READDMA_EXT 0x25 /* 48-Bit */
-#define WIN_READDMA_QUEUED_EXT 0x26 /* 48-Bit, obsolete since ACS2 */
-#define WIN_READ_NATIVE_MAX_EXT 0x27 /* 48-Bit */
-/* reserved 0x28 */
-#define WIN_MULTREAD_EXT 0x29 /* 48-Bit */
-/* READ STREAM DMA EXT 0x2A */
-/* READ STREAM EXT 0x2B */
-/* reserved 0x2C..0x2E */
-/* READ LOG EXT 0x2F */
-#define WIN_WRITE 0x30 /* 28-Bit */
-#define WIN_WRITE_ONCE 0x31 /* 28-Bit w/o retries, obsolete since ATA5 */
-/* obsolete since ATA4 0x32..0x33 */
-#define WIN_WRITE_EXT 0x34 /* 48-Bit */
-#define WIN_WRITEDMA_EXT 0x35 /* 48-Bit */
-#define WIN_WRITEDMA_QUEUED_EXT 0x36 /* 48-Bit */
-#define WIN_SET_MAX_EXT 0x37 /* 48-Bit, obsolete since ACS2 */
-#define WIN_SET_MAX_EXT 0x37 /* 48-Bit */
-#define CFA_WRITE_SECT_WO_ERASE 0x38 /* CFA Write Sectors without erase */
-#define WIN_MULTWRITE_EXT 0x39 /* 48-Bit */
-/* WRITE STREAM DMA EXT 0x3A */
-/* WRITE STREAM EXT 0x3B */
-#define WIN_WRITE_VERIFY 0x3C /* 28-Bit, obsolete since ATA4 */
-/* WRITE DMA FUA EXT 0x3D */
-/* obsolete since ACS2 0x3E */
-/* WRITE LOG EXT 0x3F */
-#define WIN_VERIFY 0x40 /* 28-Bit - Read Verify Sectors */
-#define WIN_VERIFY_ONCE 0x41 /* 28-Bit - w/o retries, obsolete since ATA5 */
-#define WIN_VERIFY_EXT 0x42 /* 48-Bit */
-/* reserved 0x43..0x44 */
-/* WRITE UNCORRECTABLE EXT 0x45 */
-/* reserved 0x46 */
-/* READ LOG DMA EXT 0x47 */
-/* reserved 0x48..0x4F */
-/* obsolete since ATA4 0x50 */
-/* CONFIGURE STREAM 0x51 */
-/* reserved 0x52..0x56 */
-/* WRITE LOG DMA EXT 0x57 */
-/* reserved 0x58..0x5A */
-/* TRUSTED NON DATA 0x5B */
-/* TRUSTED RECEIVE 0x5C */
-/* TRUSTED RECEIVE DMA 0x5D */
-/* TRUSTED SEND 0x5E */
-/* TRUSTED SEND DMA 0x5F */
-/* READ FPDMA QUEUED 0x60 */
-/* WRITE FPDMA QUEUED 0x61 */
-/* reserved 0x62->0x6F */
-#define WIN_SEEK 0x70 /* obsolete since ATA7 */
-/* reserved 0x71-0x7F */
-/* vendor specific 0x80-0x86 */
-#define CFA_TRANSLATE_SECTOR 0x87 /* CFA Translate Sector */
-/* vendor specific 0x88-0x8F */
-#define WIN_DIAGNOSE 0x90
-#define WIN_SPECIFY 0x91 /* set drive geometry translation, obsolete since ATA6 */
-#define WIN_DOWNLOAD_MICROCODE 0x92
-/* DOWNLOAD MICROCODE DMA 0x93 */
-#define WIN_STANDBYNOW2 0x94 /* retired in ATA4 */
-#define WIN_IDLEIMMEDIATE2 0x95 /* force drive to become "ready", retired in ATA4 */
-#define WIN_STANDBY2 0x96 /* retired in ATA4 */
-#define WIN_SETIDLE2 0x97 /* retired in ATA4 */
-#define WIN_CHECKPOWERMODE2 0x98 /* retired in ATA4 */
-#define WIN_SLEEPNOW2 0x99 /* retired in ATA4 */
-/* vendor specific 0x9A */
-/* reserved 0x9B..0x9F */
-#define WIN_PACKETCMD 0xA0 /* Send a packet command. */
-#define WIN_PIDENTIFY 0xA1 /* identify ATAPI device */
-#define WIN_QUEUED_SERVICE 0xA2 /* obsolete since ACS2 */
-/* reserved 0xA3..0xAF */
-#define WIN_SMART 0xB0 /* self-monitoring and reporting */
-/* Device Configuration Overlay 0xB1 */
-/* reserved 0xB2..0xB3 */
-/* Sanitize Device 0xB4 */
-/* reserved 0xB5 */
-/* NV Cache 0xB6 */
-/* reserved for CFA 0xB7..0xBB */
-#define CFA_ACCESS_METADATA_STORAGE 0xB8
-/* reserved 0xBC..0xBF */
-#define CFA_ERASE_SECTORS 0xC0 /* microdrives implement as NOP */
-/* vendor specific 0xC1..0xC3 */
-#define WIN_MULTREAD 0xC4 /* read sectors using multiple mode*/
-#define WIN_MULTWRITE 0xC5 /* write sectors using multiple mode */
-#define WIN_SETMULT 0xC6 /* enable/disable multiple mode */
-#define WIN_READDMA_QUEUED 0xC7 /* read sectors using Queued DMA transfers, obsolete since ACS2 */
-#define WIN_READDMA 0xC8 /* read sectors using DMA transfers */
-#define WIN_READDMA_ONCE 0xC9 /* 28-Bit - w/o retries, obsolete since ATA5 */
-#define WIN_WRITEDMA 0xCA /* write sectors using DMA transfers */
-#define WIN_WRITEDMA_ONCE 0xCB /* 28-Bit - w/o retries, obsolete since ATA5 */
-#define WIN_WRITEDMA_QUEUED 0xCC /* write sectors using Queued DMA transfers, obsolete since ACS2 */
-#define CFA_WRITE_MULTI_WO_ERASE 0xCD /* CFA Write multiple without erase */
-/* WRITE MULTIPLE FUA EXT 0xCE */
-/* reserved 0xCF..0xDO */
-/* CHECK MEDIA CARD TYPE 0xD1 */
-/* reserved for media card pass through 0xD2..0xD4 */
-/* reserved 0xD5..0xD9 */
-#define WIN_GETMEDIASTATUS 0xDA /* obsolete since ATA8 */
-/* obsolete since ATA3, retired in ATA4 0xDB..0xDD */
-#define WIN_DOORLOCK 0xDE /* lock door on removable drives, obsolete since ATA8 */
-#define WIN_DOORUNLOCK 0xDF /* unlock door on removable drives, obsolete since ATA8 */
-#define WIN_STANDBYNOW1 0xE0
-#define WIN_IDLEIMMEDIATE 0xE1 /* force drive to become "ready" */
-#define WIN_STANDBY 0xE2 /* Set device in Standby Mode */
-#define WIN_SETIDLE1 0xE3
-#define WIN_READ_BUFFER 0xE4 /* force read only 1 sector */
-#define WIN_CHECKPOWERMODE1 0xE5
-#define WIN_SLEEPNOW1 0xE6
-#define WIN_FLUSH_CACHE 0xE7
-#define WIN_WRITE_BUFFER 0xE8 /* force write only 1 sector */
-/* READ BUFFER DMA 0xE9 */
-#define WIN_FLUSH_CACHE_EXT 0xEA /* 48-Bit */
-/* WRITE BUFFER DMA 0xEB */
-#define WIN_IDENTIFY 0xEC /* ask drive to identify itself */
-#define WIN_MEDIAEJECT 0xED /* obsolete since ATA8 */
-/* obsolete since ATA4 0xEE */
-#define WIN_SETFEATURES 0xEF /* set special drive features */
-#define IBM_SENSE_CONDITION 0xF0 /* measure disk temperature, vendor specific */
-#define WIN_SECURITY_SET_PASS 0xF1
-#define WIN_SECURITY_UNLOCK 0xF2
-#define WIN_SECURITY_ERASE_PREPARE 0xF3
-#define WIN_SECURITY_ERASE_UNIT 0xF4
-#define WIN_SECURITY_FREEZE_LOCK 0xF5
-#define CFA_WEAR_LEVEL 0xF5 /* microdrives implement as NOP; not specified in T13! */
-#define WIN_SECURITY_DISABLE 0xF6
-/* vendor specific 0xF7 */
-#define WIN_READ_NATIVE_MAX 0xF8 /* return the native maximum address */
-#define WIN_SET_MAX 0xF9
-/* vendor specific 0xFA..0xFF */
-
-/* set to 1 set disable mult support */
-#define MAX_MULT_SECTORS 16
-
-#define IDE_DMA_BUF_SECTORS 256
-
-/* feature values for Data Set Management */
-#define DSM_TRIM 0x01
-
-#if (IDE_DMA_BUF_SECTORS < MAX_MULT_SECTORS)
-#error "IDE_DMA_BUF_SECTORS must be bigger or equal to MAX_MULT_SECTORS"
-#endif
-
-/* ATAPI defines */
-
-#define ATAPI_PACKET_SIZE 12
-
-/* The generic packet command opcodes for CD/DVD Logical Units,
- * From Table 57 of the SFF8090 Ver. 3 (Mt. Fuji) draft standard. */
-#define GPCMD_BLANK 0xa1
-#define GPCMD_CLOSE_TRACK 0x5b
-#define GPCMD_FLUSH_CACHE 0x35
-#define GPCMD_FORMAT_UNIT 0x04
-#define GPCMD_GET_CONFIGURATION 0x46
-#define GPCMD_GET_EVENT_STATUS_NOTIFICATION 0x4a
-#define GPCMD_GET_PERFORMANCE 0xac
-#define GPCMD_INQUIRY 0x12
-#define GPCMD_LOAD_UNLOAD 0xa6
-#define GPCMD_MECHANISM_STATUS 0xbd
-#define GPCMD_MODE_SELECT_10 0x55
-#define GPCMD_MODE_SENSE_10 0x5a
-#define GPCMD_PAUSE_RESUME 0x4b
-#define GPCMD_PLAY_AUDIO_10 0x45
-#define GPCMD_PLAY_AUDIO_MSF 0x47
-#define GPCMD_PLAY_AUDIO_TI 0x48
-#define GPCMD_PLAY_CD 0xbc
-#define GPCMD_PREVENT_ALLOW_MEDIUM_REMOVAL 0x1e
-#define GPCMD_READ_10 0x28
-#define GPCMD_READ_12 0xa8
-#define GPCMD_READ_CDVD_CAPACITY 0x25
-#define GPCMD_READ_CD 0xbe
-#define GPCMD_READ_CD_MSF 0xb9
-#define GPCMD_READ_DISC_INFO 0x51
-#define GPCMD_READ_DVD_STRUCTURE 0xad
-#define GPCMD_READ_FORMAT_CAPACITIES 0x23
-#define GPCMD_READ_HEADER 0x44
-#define GPCMD_READ_TRACK_RZONE_INFO 0x52
-#define GPCMD_READ_SUBCHANNEL 0x42
-#define GPCMD_READ_TOC_PMA_ATIP 0x43
-#define GPCMD_REPAIR_RZONE_TRACK 0x58
-#define GPCMD_REPORT_KEY 0xa4
-#define GPCMD_REQUEST_SENSE 0x03
-#define GPCMD_RESERVE_RZONE_TRACK 0x53
-#define GPCMD_SCAN 0xba
-#define GPCMD_SEEK 0x2b
-#define GPCMD_SEND_DVD_STRUCTURE 0xad
-#define GPCMD_SEND_EVENT 0xa2
-#define GPCMD_SEND_KEY 0xa3
-#define GPCMD_SEND_OPC 0x54
-#define GPCMD_SET_READ_AHEAD 0xa7
-#define GPCMD_SET_STREAMING 0xb6
-#define GPCMD_START_STOP_UNIT 0x1b
-#define GPCMD_STOP_PLAY_SCAN 0x4e
-#define GPCMD_TEST_UNIT_READY 0x00
-#define GPCMD_VERIFY_10 0x2f
-#define GPCMD_WRITE_10 0x2a
-#define GPCMD_WRITE_AND_VERIFY_10 0x2e
-/* This is listed as optional in ATAPI 2.6, but is (curiously)
- * missing from Mt. Fuji, Table 57. It _is_ mentioned in Mt. Fuji
- * Table 377 as an MMC command for SCSi devices though... Most ATAPI
- * drives support it. */
-#define GPCMD_SET_SPEED 0xbb
-/* This seems to be a SCSI specific CD-ROM opcode
- * to play data at track/index */
-#define GPCMD_PLAYAUDIO_TI 0x48
-/*
- * From MS Media Status Notification Support Specification. For
- * older drives only.
- */
-#define GPCMD_GET_MEDIA_STATUS 0xda
-#define GPCMD_MODE_SENSE_6 0x1a
-
-#define ATAPI_INT_REASON_CD 0x01 /* 0 = data transfer */
-#define ATAPI_INT_REASON_IO 0x02 /* 1 = transfer to the host */
-#define ATAPI_INT_REASON_REL 0x04
-#define ATAPI_INT_REASON_TAG 0xf8
-
-/* same constants as bochs */
-#define ASC_NO_SEEK_COMPLETE 0x02
-#define ASC_ILLEGAL_OPCODE 0x20
-#define ASC_LOGICAL_BLOCK_OOR 0x21
-#define ASC_INV_FIELD_IN_CMD_PACKET 0x24
-#define ASC_MEDIUM_MAY_HAVE_CHANGED 0x28
-#define ASC_INCOMPATIBLE_FORMAT 0x30
-#define ASC_MEDIUM_NOT_PRESENT 0x3a
-#define ASC_SAVING_PARAMETERS_NOT_SUPPORTED 0x39
-#define ASC_DATA_PHASE_ERROR 0x4b
-#define ASC_MEDIA_REMOVAL_PREVENTED 0x53
-
-#define CFA_NO_ERROR 0x00
-#define CFA_MISC_ERROR 0x09
-#define CFA_INVALID_COMMAND 0x20
-#define CFA_INVALID_ADDRESS 0x21
-#define CFA_ADDRESS_OVERFLOW 0x2f
-
-#define SMART_READ_DATA 0xd0
-#define SMART_READ_THRESH 0xd1
-#define SMART_ATTR_AUTOSAVE 0xd2
-#define SMART_SAVE_ATTR 0xd3
-#define SMART_EXECUTE_OFFLINE 0xd4
-#define SMART_READ_LOG 0xd5
-#define SMART_WRITE_LOG 0xd6
-#define SMART_ENABLE 0xd8
-#define SMART_DISABLE 0xd9
-#define SMART_STATUS 0xda
-
-typedef enum { IDE_HD, IDE_CD, IDE_CFATA } IDEDriveKind;
-
-typedef void EndTransferFunc(IDEState *);
-
-typedef void DMAStartFunc(const IDEDMA *, IDEState *, BlockCompletionFunc *);
-typedef void DMAVoidFunc(const IDEDMA *);
-typedef int DMAIntFunc(const IDEDMA *, bool);
-typedef int32_t DMAInt32Func(const IDEDMA *, int32_t len);
-typedef void DMAu32Func(const IDEDMA *, uint32_t);
-typedef void DMAStopFunc(const IDEDMA *, bool);
-
-struct unreported_events {
- bool eject_request;
- bool new_media;
-};
-
-enum ide_dma_cmd {
- IDE_DMA_READ = 0,
- IDE_DMA_WRITE,
- IDE_DMA_TRIM,
- IDE_DMA_ATAPI,
- IDE_DMA__COUNT
-};
-
-extern const char *IDE_DMA_CMD_lookup[IDE_DMA__COUNT];
-
-#define ide_cmd_is_read(s) \
- ((s)->dma_cmd == IDE_DMA_READ)
-
-typedef struct IDEBufferedRequest {
- QLIST_ENTRY(IDEBufferedRequest) list;
- QEMUIOVector qiov;
- QEMUIOVector *original_qiov;
- BlockCompletionFunc *original_cb;
- void *original_opaque;
- bool orphaned;
-} IDEBufferedRequest;
-
-/* NOTE: IDEState represents in fact one drive */
-struct IDEState {
- IDEBus *bus;
- uint8_t unit;
- /* ide config */
- IDEDriveKind drive_kind;
- int cylinders, heads, sectors, chs_trans;
- int64_t nb_sectors;
- int mult_sectors;
- int identify_set;
- uint8_t identify_data[512];
- int drive_serial;
- char drive_serial_str[21];
- char drive_model_str[41];
- uint64_t wwn;
- /* ide regs */
- uint8_t feature;
- uint8_t error;
- uint32_t nsector;
- uint8_t sector;
- uint8_t lcyl;
- uint8_t hcyl;
- /* other part of tf for lba48 support */
- uint8_t hob_feature;
- uint8_t hob_nsector;
- uint8_t hob_sector;
- uint8_t hob_lcyl;
- uint8_t hob_hcyl;
-
- uint8_t select;
- uint8_t status;
-
- /* set for lba48 access */
- uint8_t lba48;
- BlockBackend *blk;
- char version[9];
- /* ATAPI specific */
- struct unreported_events events;
- uint8_t sense_key;
- uint8_t asc;
- bool tray_open;
- bool tray_locked;
- uint8_t cdrom_changed;
- int packet_transfer_size;
- int elementary_transfer_size;
- int32_t io_buffer_index;
- int lba;
- int cd_sector_size;
- int atapi_dma; /* true if dma is requested for the packet cmd */
- BlockAcctCookie acct;
- BlockAIOCB *pio_aiocb;
- QEMUIOVector qiov;
- QLIST_HEAD(, IDEBufferedRequest) buffered_requests;
- /* ATA DMA state */
- uint64_t io_buffer_offset;
- int32_t io_buffer_size;
- QEMUSGList sg;
- /* PIO transfer handling */
- int req_nb_sectors; /* number of sectors per interrupt */
- EndTransferFunc *end_transfer_func;
- uint8_t *data_ptr;
- uint8_t *data_end;
- uint8_t *io_buffer;
- /* PIO save/restore */
- int32_t io_buffer_total_len;
- int32_t cur_io_buffer_offset;
- int32_t cur_io_buffer_len;
- uint8_t end_transfer_fn_idx;
- QEMUTimer *sector_write_timer; /* only used for win2k install hack */
- uint32_t irq_count; /* counts IRQs when using win2k install hack */
- /* CF-ATA extended error */
- uint8_t ext_error;
- /* CF-ATA metadata storage */
- uint32_t mdata_size;
- uint8_t *mdata_storage;
- int media_changed;
- enum ide_dma_cmd dma_cmd;
- /* SMART */
- uint8_t smart_enabled;
- uint8_t smart_autosave;
- int smart_errors;
- uint8_t smart_selftest_count;
- uint8_t *smart_selftest_data;
- /* AHCI */
- int ncq_queues;
-};
-
-struct IDEDMAOps {
- DMAStartFunc *start_dma;
- DMAVoidFunc *pio_transfer;
- DMAInt32Func *prepare_buf;
- DMAu32Func *commit_buf;
- DMAIntFunc *rw_buf;
- DMAVoidFunc *restart;
- DMAVoidFunc *restart_dma;
- DMAStopFunc *set_inactive;
- DMAVoidFunc *cmd_done;
- DMAVoidFunc *reset;
-};
-
-struct IDEDMA {
- const struct IDEDMAOps *ops;
- QEMUIOVector qiov;
- BlockAIOCB *aiocb;
-};
-
-struct IDEBus {
- BusState qbus;
- IDEDevice *master;
- IDEDevice *slave;
- IDEState ifs[2];
- QEMUBH *bh;
-
- int bus_id;
- int max_units;
- IDEDMA *dma;
- uint8_t unit;
- uint8_t cmd;
- qemu_irq irq;
-
- int error_status;
- uint8_t retry_unit;
- int64_t retry_sector_num;
- uint32_t retry_nsector;
- PortioList portio_list;
- PortioList portio2_list;
- VMChangeStateEntry *vmstate;
-};
-
-#define TYPE_IDE_DEVICE "ide-device"
-OBJECT_DECLARE_TYPE(IDEDevice, IDEDeviceClass, IDE_DEVICE)
-
-struct IDEDeviceClass {
- DeviceClass parent_class;
- void (*realize)(IDEDevice *dev, Error **errp);
-};
-
-struct IDEDevice {
- DeviceState qdev;
- uint32_t unit;
- BlockConf conf;
- int chs_trans;
- char *version;
- char *serial;
- char *model;
- uint64_t wwn;
- /*
- * 0x0000 - rotation rate not reported
- * 0x0001 - non-rotating medium (SSD)
- * 0x0002-0x0400 - reserved
- * 0x0401-0xffe - rotations per minute
- * 0xffff - reserved
- */
- uint16_t rotation_rate;
-};
-
-/* These are used for the error_status field of IDEBus */
-#define IDE_RETRY_MASK 0xf8
-#define IDE_RETRY_DMA 0x08
-#define IDE_RETRY_PIO 0x10
-#define IDE_RETRY_ATAPI 0x20 /* reused IDE_RETRY_READ bit */
-#define IDE_RETRY_READ 0x20
-#define IDE_RETRY_FLUSH 0x40
-#define IDE_RETRY_TRIM 0x80
-#define IDE_RETRY_HBA 0x100
-
-#define IS_IDE_RETRY_DMA(_status) \
- ((_status) & IDE_RETRY_DMA)
-
-#define IS_IDE_RETRY_PIO(_status) \
- ((_status) & IDE_RETRY_PIO)
-
-/*
- * The method of the IDE_RETRY_ATAPI determination is to use a previously
- * impossible bit combination as a new status value.
- */
-#define IS_IDE_RETRY_ATAPI(_status) \
- (((_status) & IDE_RETRY_MASK) == IDE_RETRY_ATAPI)
-
-static inline uint8_t ide_dma_cmd_to_retry(uint8_t dma_cmd)
-{
- switch (dma_cmd) {
- case IDE_DMA_READ:
- return IDE_RETRY_DMA | IDE_RETRY_READ;
- case IDE_DMA_WRITE:
- return IDE_RETRY_DMA;
- case IDE_DMA_TRIM:
- return IDE_RETRY_DMA | IDE_RETRY_TRIM;
- case IDE_DMA_ATAPI:
- return IDE_RETRY_ATAPI;
- default:
- break;
- }
- return 0;
-}
-
-static inline IDEState *idebus_active_if(IDEBus *bus)
-{
- return bus->ifs + bus->unit;
-}
-
-static inline void ide_set_irq(IDEBus *bus)
-{
- if (!(bus->cmd & IDE_CTRL_DISABLE_IRQ)) {
- qemu_irq_raise(bus->irq);
- }
-}
-
-/* hw/ide/core.c */
-extern const VMStateDescription vmstate_ide_bus;
-
-#define VMSTATE_IDE_BUS(_field, _state) \
- VMSTATE_STRUCT(_field, _state, 1, vmstate_ide_bus, IDEBus)
-
-#define VMSTATE_IDE_BUS_ARRAY(_field, _state, _num) \
- VMSTATE_STRUCT_ARRAY(_field, _state, _num, 1, vmstate_ide_bus, IDEBus)
-
-extern const VMStateDescription vmstate_ide_drive;
-
-#define VMSTATE_IDE_DRIVES(_field, _state) \
- VMSTATE_STRUCT_ARRAY(_field, _state, 2, 3, vmstate_ide_drive, IDEState)
-
-#define VMSTATE_IDE_DRIVE(_field, _state) \
- VMSTATE_STRUCT(_field, _state, 1, vmstate_ide_drive, IDEState)
-
-void ide_bus_reset(IDEBus *bus);
-int64_t ide_get_sector(IDEState *s);
-void ide_set_sector(IDEState *s, int64_t sector_num);
-
-void ide_start_dma(IDEState *s, BlockCompletionFunc *cb);
-void dma_buf_commit(IDEState *s, uint32_t tx_bytes);
-void ide_dma_error(IDEState *s);
-void ide_abort_command(IDEState *s);
-
-void ide_atapi_cmd_ok(IDEState *s);
-void ide_atapi_cmd_error(IDEState *s, int sense_key, int asc);
-void ide_atapi_dma_restart(IDEState *s);
-void ide_atapi_io_error(IDEState *s, int ret);
-
-void ide_ioport_write(void *opaque, uint32_t addr, uint32_t val);
-uint32_t ide_ioport_read(void *opaque, uint32_t addr1);
-uint32_t ide_status_read(void *opaque, uint32_t addr);
-void ide_ctrl_write(void *opaque, uint32_t addr, uint32_t val);
-void ide_data_writew(void *opaque, uint32_t addr, uint32_t val);
-uint32_t ide_data_readw(void *opaque, uint32_t addr);
-void ide_data_writel(void *opaque, uint32_t addr, uint32_t val);
-uint32_t ide_data_readl(void *opaque, uint32_t addr);
-
-int ide_init_drive(IDEState *s, BlockBackend *blk, IDEDriveKind kind,
- const char *version, const char *serial, const char *model,
- uint64_t wwn,
- uint32_t cylinders, uint32_t heads, uint32_t secs,
- int chs_trans, Error **errp);
-void ide_init2(IDEBus *bus, qemu_irq irq);
-void ide_exit(IDEState *s);
-void ide_init_ioport(IDEBus *bus, ISADevice *isa, int iobase, int iobase2);
-void ide_register_restart_cb(IDEBus *bus);
-
-void ide_exec_cmd(IDEBus *bus, uint32_t val);
-
-void ide_transfer_start(IDEState *s, uint8_t *buf, int size,
- EndTransferFunc *end_transfer_func);
-bool ide_transfer_start_norecurse(IDEState *s, uint8_t *buf, int size,
- EndTransferFunc *end_transfer_func);
-void ide_transfer_stop(IDEState *s);
-void ide_set_inactive(IDEState *s, bool more);
-BlockAIOCB *ide_issue_trim(
- int64_t offset, QEMUIOVector *qiov,
- BlockCompletionFunc *cb, void *cb_opaque, void *opaque);
-BlockAIOCB *ide_buffered_readv(IDEState *s, int64_t sector_num,
- QEMUIOVector *iov, int nb_sectors,
- BlockCompletionFunc *cb, void *opaque);
-void ide_cancel_dma_sync(IDEState *s);
-
-/* hw/ide/atapi.c */
-void ide_atapi_cmd(IDEState *s);
-void ide_atapi_cmd_reply_end(IDEState *s);
-
-/* hw/ide/qdev.c */
-void ide_bus_new(IDEBus *idebus, size_t idebus_size, DeviceState *dev,
- int bus_id, int max_units);
-IDEDevice *ide_create_drive(IDEBus *bus, int unit, DriveInfo *drive);
-
-int ide_handle_rw_error(IDEState *s, int error, int op);
-
-#endif /* HW_IDE_INTERNAL_H */
+++ /dev/null
-#ifndef HW_IDE_PCI_H
-#define HW_IDE_PCI_H
-
-#include "hw/ide/internal.h"
-#include "hw/pci/pci.h"
-#include "qom/object.h"
-
-#define BM_STATUS_DMAING 0x01
-#define BM_STATUS_ERROR 0x02
-#define BM_STATUS_INT 0x04
-
-#define BM_CMD_START 0x01
-#define BM_CMD_READ 0x08
-
-typedef struct BMDMAState {
- IDEDMA dma;
- uint8_t cmd;
- uint8_t status;
- uint32_t addr;
-
- IDEBus *bus;
- /* current transfer state */
- uint32_t cur_addr;
- uint32_t cur_prd_last;
- uint32_t cur_prd_addr;
- uint32_t cur_prd_len;
- BlockCompletionFunc *dma_cb;
- MemoryRegion addr_ioport;
- MemoryRegion extra_io;
- qemu_irq irq;
-
- /* Bit 0-2 and 7: BM status register
- * Bit 3-6: bus->error_status */
- uint8_t migration_compat_status;
- uint8_t migration_retry_unit;
- int64_t migration_retry_sector_num;
- uint32_t migration_retry_nsector;
-
- struct PCIIDEState *pci_dev;
-} BMDMAState;
-
-#define TYPE_PCI_IDE "pci-ide"
-OBJECT_DECLARE_SIMPLE_TYPE(PCIIDEState, PCI_IDE)
-
-struct PCIIDEState {
- /*< private >*/
- PCIDevice parent_obj;
- /*< public >*/
-
- IDEBus bus[2];
- BMDMAState bmdma[2];
- uint32_t secondary; /* used only for cmd646 */
- MemoryRegion bmdma_bar;
- MemoryRegion cmd_bar[2];
- MemoryRegion data_bar[2];
-};
-
-static inline IDEState *bmdma_active_if(BMDMAState *bmdma)
-{
- assert(bmdma->bus->retry_unit != (uint8_t)-1);
- return bmdma->bus->ifs + bmdma->bus->retry_unit;
-}
-
-void bmdma_init(IDEBus *bus, BMDMAState *bm, PCIIDEState *d);
-void bmdma_cmd_writeb(BMDMAState *bm, uint32_t val);
-extern MemoryRegionOps bmdma_addr_ioport_ops;
-void pci_ide_create_devs(PCIDevice *dev);
-
-extern const VMStateDescription vmstate_ide_pci;
-extern const MemoryRegionOps pci_ide_cmd_le_ops;
-extern const MemoryRegionOps pci_ide_data_le_ops;
-#endif
+++ /dev/null
-/*
- * QEMU System Emulator
- *
- * Copyright (c) 2016 John Arbuckle
- *
- * This work is licensed under the terms of the GNU GPL, version 2 or later.
- * See the COPYING file in the top-level directory.
- */
-
-/*
- * adb-keys.h
- *
- * Provides an enum of all the Macintosh keycodes.
- * Additional information: http://www.archive.org/stream/apple-guide-macintosh-family-hardware/Apple_Guide_to_the_Macintosh_Family_Hardware_2e#page/n345/mode/2up
- * page 308
- */
-
-#ifndef ADB_KEYS_H
-#define ADB_KEYS_H
-
-enum {
- ADB_KEY_A = 0x00,
- ADB_KEY_B = 0x0b,
- ADB_KEY_C = 0x08,
- ADB_KEY_D = 0x02,
- ADB_KEY_E = 0x0e,
- ADB_KEY_F = 0x03,
- ADB_KEY_G = 0x05,
- ADB_KEY_H = 0x04,
- ADB_KEY_I = 0x22,
- ADB_KEY_J = 0x26,
- ADB_KEY_K = 0x28,
- ADB_KEY_L = 0x25,
- ADB_KEY_M = 0x2e,
- ADB_KEY_N = 0x2d,
- ADB_KEY_O = 0x1f,
- ADB_KEY_P = 0x23,
- ADB_KEY_Q = 0x0c,
- ADB_KEY_R = 0x0f,
- ADB_KEY_S = 0x01,
- ADB_KEY_T = 0x11,
- ADB_KEY_U = 0x20,
- ADB_KEY_V = 0x09,
- ADB_KEY_W = 0x0d,
- ADB_KEY_X = 0x07,
- ADB_KEY_Y = 0x10,
- ADB_KEY_Z = 0x06,
-
- ADB_KEY_0 = 0x1d,
- ADB_KEY_1 = 0x12,
- ADB_KEY_2 = 0x13,
- ADB_KEY_3 = 0x14,
- ADB_KEY_4 = 0x15,
- ADB_KEY_5 = 0x17,
- ADB_KEY_6 = 0x16,
- ADB_KEY_7 = 0x1a,
- ADB_KEY_8 = 0x1c,
- ADB_KEY_9 = 0x19,
-
- ADB_KEY_GRAVE_ACCENT = 0x32,
- ADB_KEY_MINUS = 0x1b,
- ADB_KEY_EQUAL = 0x18,
- ADB_KEY_DELETE = 0x33,
- ADB_KEY_CAPS_LOCK = 0x39,
- ADB_KEY_TAB = 0x30,
- ADB_KEY_RETURN = 0x24,
- ADB_KEY_LEFT_BRACKET = 0x21,
- ADB_KEY_RIGHT_BRACKET = 0x1e,
- ADB_KEY_BACKSLASH = 0x2a,
- ADB_KEY_SEMICOLON = 0x29,
- ADB_KEY_APOSTROPHE = 0x27,
- ADB_KEY_COMMA = 0x2b,
- ADB_KEY_PERIOD = 0x2f,
- ADB_KEY_FORWARD_SLASH = 0x2c,
- ADB_KEY_LEFT_SHIFT = 0x38,
- ADB_KEY_RIGHT_SHIFT = 0x7b,
- ADB_KEY_SPACEBAR = 0x31,
- ADB_KEY_LEFT_CONTROL = 0x36,
- ADB_KEY_RIGHT_CONTROL = 0x7d,
- ADB_KEY_LEFT_OPTION = 0x3a,
- ADB_KEY_RIGHT_OPTION = 0x7c,
- ADB_KEY_COMMAND = 0x37,
-
- ADB_KEY_KP_0 = 0x52,
- ADB_KEY_KP_1 = 0x53,
- ADB_KEY_KP_2 = 0x54,
- ADB_KEY_KP_3 = 0x55,
- ADB_KEY_KP_4 = 0x56,
- ADB_KEY_KP_5 = 0x57,
- ADB_KEY_KP_6 = 0x58,
- ADB_KEY_KP_7 = 0x59,
- ADB_KEY_KP_8 = 0x5b,
- ADB_KEY_KP_9 = 0x5c,
- ADB_KEY_KP_PERIOD = 0x41,
- ADB_KEY_KP_ENTER = 0x4c,
- ADB_KEY_KP_PLUS = 0x45,
- ADB_KEY_KP_SUBTRACT = 0x4e,
- ADB_KEY_KP_MULTIPLY = 0x43,
- ADB_KEY_KP_DIVIDE = 0x4b,
- ADB_KEY_KP_EQUAL = 0x51,
- ADB_KEY_KP_CLEAR = 0x47,
-
- ADB_KEY_UP = 0x3e,
- ADB_KEY_DOWN = 0x3d,
- ADB_KEY_LEFT = 0x3b,
- ADB_KEY_RIGHT = 0x3c,
-
- ADB_KEY_HELP = 0x72,
- ADB_KEY_HOME = 0x73,
- ADB_KEY_PAGE_UP = 0x74,
- ADB_KEY_PAGE_DOWN = 0x79,
- ADB_KEY_END = 0x77,
- ADB_KEY_FORWARD_DELETE = 0x75,
-
- ADB_KEY_ESC = 0x35,
- ADB_KEY_F1 = 0x7a,
- ADB_KEY_F2 = 0x78,
- ADB_KEY_F3 = 0x63,
- ADB_KEY_F4 = 0x76,
- ADB_KEY_F5 = 0x60,
- ADB_KEY_F6 = 0x61,
- ADB_KEY_F7 = 0x62,
- ADB_KEY_F8 = 0x64,
- ADB_KEY_F9 = 0x65,
- ADB_KEY_F10 = 0x6d,
- ADB_KEY_F11 = 0x67,
- ADB_KEY_F12 = 0x6f,
- ADB_KEY_F13 = 0x69,
- ADB_KEY_F14 = 0x6b,
- ADB_KEY_F15 = 0x71,
-
- ADB_KEY_VOLUME_UP = 0x48,
- ADB_KEY_VOLUME_DOWN = 0x49,
- ADB_KEY_VOLUME_MUTE = 0x4a,
- ADB_KEY_POWER = 0x7f7f
-};
-
-/* Could not find the value for this key. */
-/* #define ADB_KEY_EJECT */
-
-#endif /* ADB_KEYS_H */
+++ /dev/null
-/*
- * QEMU ADB emulation shared definitions and prototypes
- *
- * Copyright (c) 2004-2007 Fabrice Bellard
- * Copyright (c) 2007 Jocelyn Mayer
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
- * furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
- * THE SOFTWARE.
- */
-
-#ifndef ADB_H
-#define ADB_H
-
-#include "hw/qdev-core.h"
-#include "qom/object.h"
-
-#define MAX_ADB_DEVICES 16
-
-#define ADB_MAX_OUT_LEN 16
-
-typedef struct ADBDevice ADBDevice;
-
-/* buf = NULL means polling */
-typedef int ADBDeviceRequest(ADBDevice *d, uint8_t *buf_out,
- const uint8_t *buf, int len);
-
-typedef bool ADBDeviceHasData(ADBDevice *d);
-
-#define TYPE_ADB_DEVICE "adb-device"
-OBJECT_DECLARE_TYPE(ADBDevice, ADBDeviceClass, ADB_DEVICE)
-
-struct ADBDevice {
- /*< private >*/
- DeviceState parent_obj;
- /*< public >*/
-
- int devaddr;
- int handler;
-};
-
-
-struct ADBDeviceClass {
- /*< private >*/
- DeviceClass parent_class;
- /*< public >*/
-
- ADBDeviceRequest *devreq;
- ADBDeviceHasData *devhasdata;
-};
-
-#define TYPE_ADB_BUS "apple-desktop-bus"
-OBJECT_DECLARE_SIMPLE_TYPE(ADBBusState, ADB_BUS)
-
-#define ADB_STATUS_BUSTIMEOUT 0x1
-#define ADB_STATUS_POLLREPLY 0x2
-
-struct ADBBusState {
- /*< private >*/
- BusState parent_obj;
- /*< public >*/
-
- ADBDevice *devices[MAX_ADB_DEVICES];
- uint16_t pending;
- int nb_devices;
- int poll_index;
- uint8_t status;
-
- QEMUTimer *autopoll_timer;
- bool autopoll_enabled;
- bool autopoll_blocked;
- uint8_t autopoll_rate_ms;
- uint16_t autopoll_mask;
- void (*autopoll_cb)(void *opaque);
- void *autopoll_cb_opaque;
-};
-
-int adb_request(ADBBusState *s, uint8_t *buf_out,
- const uint8_t *buf, int len);
-int adb_poll(ADBBusState *s, uint8_t *buf_out, uint16_t poll_mask);
-
-void adb_autopoll_block(ADBBusState *s);
-void adb_autopoll_unblock(ADBBusState *s);
-
-void adb_set_autopoll_enabled(ADBBusState *s, bool enabled);
-void adb_set_autopoll_rate_ms(ADBBusState *s, int rate_ms);
-void adb_set_autopoll_mask(ADBBusState *s, uint16_t mask);
-void adb_register_autopoll_callback(ADBBusState *s, void (*cb)(void *opaque),
- void *opaque);
-
-#define TYPE_ADB_KEYBOARD "adb-keyboard"
-#define TYPE_ADB_MOUSE "adb-mouse"
-
-#endif /* ADB_H */
+++ /dev/null
-/*
- * Gamepad style buttons connected to IRQ/GPIO lines
- *
- * Copyright (c) 2007 CodeSourcery.
- * Written by Paul Brook
- *
- * This work is licensed under the terms of the GNU GPL, version 2 or later.
- * See the COPYING file in the top-level directory.
- */
-
-#ifndef HW_INPUT_GAMEPAD_H
-#define HW_INPUT_GAMEPAD_H
-
-
-/* stellaris_input.c */
-void stellaris_gamepad_init(int n, qemu_irq *irq, const int *keycode);
-
-#endif
+++ /dev/null
-#ifndef QEMU_HID_H
-#define QEMU_HID_H
-
-#include "ui/input.h"
-
-#define HID_MOUSE 1
-#define HID_TABLET 2
-#define HID_KEYBOARD 3
-
-typedef struct HIDPointerEvent {
- int32_t xdx, ydy; /* relative iff it's a mouse, otherwise absolute */
- int32_t dz, buttons_state;
-} HIDPointerEvent;
-
-#define QUEUE_LENGTH 16 /* should be enough for a triple-click */
-#define QUEUE_MASK (QUEUE_LENGTH-1u)
-#define QUEUE_INCR(v) ((v)++, (v) &= QUEUE_MASK)
-
-typedef struct HIDState HIDState;
-typedef void (*HIDEventFunc)(HIDState *s);
-
-typedef struct HIDMouseState {
- HIDPointerEvent queue[QUEUE_LENGTH];
- int mouse_grabbed;
-} HIDMouseState;
-
-typedef struct HIDKeyboardState {
- uint32_t keycodes[QUEUE_LENGTH];
- uint16_t modifiers;
- uint8_t leds;
- uint8_t key[16];
- int32_t keys;
-} HIDKeyboardState;
-
-struct HIDState {
- union {
- HIDMouseState ptr;
- HIDKeyboardState kbd;
- };
- uint32_t head; /* index into circular queue */
- uint32_t n;
- int kind;
- int32_t protocol;
- uint8_t idle;
- bool idle_pending;
- QEMUTimer *idle_timer;
- HIDEventFunc event;
- QemuInputHandlerState *s;
-};
-
-void hid_init(HIDState *hs, int kind, HIDEventFunc event);
-void hid_reset(HIDState *hs);
-void hid_free(HIDState *hs);
-
-bool hid_has_events(HIDState *hs);
-void hid_set_next_idle(HIDState *hs);
-void hid_pointer_activate(HIDState *hs);
-int hid_pointer_poll(HIDState *hs, uint8_t *buf, int len);
-int hid_keyboard_poll(HIDState *hs, uint8_t *buf, int len);
-int hid_keyboard_write(HIDState *hs, uint8_t *buf, int len);
-
-extern const VMStateDescription vmstate_hid_keyboard_device;
-
-#define VMSTATE_HID_KEYBOARD_DEVICE(_field, _state) { \
- .name = (stringify(_field)), \
- .size = sizeof(HIDState), \
- .vmsd = &vmstate_hid_keyboard_device, \
- .flags = VMS_STRUCT, \
- .offset = vmstate_offset_value(_state, _field, HIDState), \
-}
-
-extern const VMStateDescription vmstate_hid_ptr_device;
-
-#define VMSTATE_HID_POINTER_DEVICE(_field, _state) { \
- .name = (stringify(_field)), \
- .size = sizeof(HIDState), \
- .vmsd = &vmstate_hid_ptr_device, \
- .flags = VMS_STRUCT, \
- .offset = vmstate_offset_value(_state, _field, HIDState), \
-}
-
-
-#endif /* QEMU_HID_H */
+++ /dev/null
-/*
- * QEMU PS/2 Controller
- *
- * Copyright (c) 2003 Fabrice Bellard
- *
- * SPDX-License-Identifier: MIT
- */
-#ifndef HW_INPUT_I8042_H
-#define HW_INPUT_I8042_H
-
-#include "hw/isa/isa.h"
-#include "qom/object.h"
-
-#define TYPE_I8042 "i8042"
-OBJECT_DECLARE_SIMPLE_TYPE(ISAKBDState, I8042)
-
-#define I8042_A20_LINE "a20"
-
-
-void i8042_mm_init(qemu_irq kbd_irq, qemu_irq mouse_irq,
- MemoryRegion *region, ram_addr_t size,
- hwaddr mask);
-void i8042_isa_mouse_fake_event(ISAKBDState *isa);
-void i8042_setup_a20_line(ISADevice *dev, qemu_irq a20_out);
-
-#endif /* HW_INPUT_I8042_H */
+++ /dev/null
-/*
- * QEMU LASI PS/2 emulation
- *
- * Copyright (c) 2019 Sven Schnelle
- *
- */
-#ifndef HW_INPUT_LASIPS2_H
-#define HW_INPUT_LASIPS2_H
-
-#include "exec/hwaddr.h"
-
-#define TYPE_LASIPS2 "lasips2"
-
-void lasips2_init(MemoryRegion *address_space, hwaddr base, qemu_irq irq);
-
-#endif /* HW_INPUT_LASIPS2_H */
+++ /dev/null
-/*
- * QEMU PS/2 keyboard/mouse emulation
- *
- * Copyright (C) 2003 Fabrice Bellard
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
- * furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
- * THE SOFTWARE.
- */
-
-#ifndef HW_PS2_H
-#define HW_PS2_H
-
-#define PS2_MOUSE_BUTTON_LEFT 0x01
-#define PS2_MOUSE_BUTTON_RIGHT 0x02
-#define PS2_MOUSE_BUTTON_MIDDLE 0x04
-#define PS2_MOUSE_BUTTON_SIDE 0x08
-#define PS2_MOUSE_BUTTON_EXTRA 0x10
-
-typedef struct PS2State PS2State;
-
-/* ps2.c */
-void *ps2_kbd_init(void (*update_irq)(void *, int), void *update_arg);
-void *ps2_mouse_init(void (*update_irq)(void *, int), void *update_arg);
-void ps2_write_mouse(void *, int val);
-void ps2_write_keyboard(void *, int val);
-uint32_t ps2_read_data(PS2State *s);
-void ps2_queue_noirq(PS2State *s, int b);
-void ps2_raise_irq(PS2State *s);
-void ps2_queue(PS2State *s, int b);
-void ps2_queue_2(PS2State *s, int b1, int b2);
-void ps2_queue_3(PS2State *s, int b1, int b2, int b3);
-void ps2_queue_4(PS2State *s, int b1, int b2, int b3, int b4);
-void ps2_keyboard_set_translation(void *opaque, int mode);
-void ps2_mouse_fake_event(void *opaque);
-int ps2_queue_empty(PS2State *s);
-
-#endif /* HW_PS2_H */
+++ /dev/null
-/*
- * TI touchscreen controller
- *
- * Copyright (c) 2006 Andrzej Zaborowski
- * Copyright (C) 2008 Nokia Corporation
- *
- * This work is licensed under the terms of the GNU GPL, version 2 or later.
- * See the COPYING file in the top-level directory.
- */
-
-#ifndef HW_INPUT_TSC2XXX_H
-#define HW_INPUT_TSC2XXX_H
-
-typedef struct MouseTransformInfo {
- /* Touchscreen resolution */
- int x;
- int y;
- /* Calibration values as used/generated by tslib */
- int a[7];
-} MouseTransformInfo;
-
-typedef struct uWireSlave {
- uint16_t (*receive)(void *opaque);
- void (*send)(void *opaque, uint16_t data);
- void *opaque;
-} uWireSlave;
-
-/* tsc210x.c */
-uWireSlave *tsc2102_init(qemu_irq pint);
-uWireSlave *tsc2301_init(qemu_irq penirq, qemu_irq kbirq, qemu_irq dav);
-I2SCodec *tsc210x_codec(uWireSlave *chip);
-uint32_t tsc210x_txrx(void *opaque, uint32_t value, int len);
-void tsc210x_set_transform(uWireSlave *chip, MouseTransformInfo *info);
-void tsc210x_key_event(uWireSlave *chip, int key, int down);
-
-/* tsc2005.c */
-void *tsc2005_init(qemu_irq pintdav);
-uint32_t tsc2005_txrx(void *opaque, uint32_t value, int len);
-void tsc2005_set_transform(void *opaque, MouseTransformInfo *info);
-
-#endif
+++ /dev/null
-#ifndef ALLWINNER_A10_PIC_H
-#define ALLWINNER_A10_PIC_H
-
-#include "hw/sysbus.h"
-#include "qom/object.h"
-
-#define TYPE_AW_A10_PIC "allwinner-a10-pic"
-OBJECT_DECLARE_SIMPLE_TYPE(AwA10PICState, AW_A10_PIC)
-
-#define AW_A10_PIC_VECTOR 0
-#define AW_A10_PIC_BASE_ADDR 4
-#define AW_A10_PIC_PROTECT 8
-#define AW_A10_PIC_NMI 0xc
-#define AW_A10_PIC_IRQ_PENDING 0x10
-#define AW_A10_PIC_FIQ_PENDING 0x20
-#define AW_A10_PIC_SELECT 0x30
-#define AW_A10_PIC_ENABLE 0x40
-#define AW_A10_PIC_MASK 0x50
-
-#define AW_A10_PIC_INT_NR 95
-#define AW_A10_PIC_REG_NUM DIV_ROUND_UP(AW_A10_PIC_INT_NR, 32)
-
-struct AwA10PICState {
- /*< private >*/
- SysBusDevice parent_obj;
- /*< public >*/
- MemoryRegion iomem;
- qemu_irq parent_fiq;
- qemu_irq parent_irq;
-
- uint32_t vector;
- uint32_t base_addr;
- uint32_t protect;
- uint32_t nmi;
- uint32_t irq_pending[AW_A10_PIC_REG_NUM];
- uint32_t fiq_pending[AW_A10_PIC_REG_NUM];
- uint32_t select[AW_A10_PIC_REG_NUM];
- uint32_t enable[AW_A10_PIC_REG_NUM];
- uint32_t mask[AW_A10_PIC_REG_NUM];
- /*priority setting here*/
-};
-
-#endif
+++ /dev/null
-/*
- * ARM GIC support
- *
- * Copyright (c) 2012 Linaro Limited
- * Written by Peter Maydell
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation, either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License along
- * with this program; if not, see <http://www.gnu.org/licenses/>.
- */
-
-/*
- * QEMU interface:
- * + QOM property "num-cpu": number of CPUs to support
- * + QOM property "num-irq": number of IRQs (including both SPIs and PPIs)
- * + QOM property "revision": GIC version (1 or 2), or 0 for the 11MPCore GIC
- * + QOM property "has-security-extensions": set true if the GIC should
- * implement the security extensions
- * + QOM property "has-virtualization-extensions": set true if the GIC should
- * implement the virtualization extensions
- * + unnamed GPIO inputs: (where P is number of SPIs, i.e. num-irq - 32)
- * [0..P-1] SPIs
- * [P..P+31] PPIs for CPU 0
- * [P+32..P+63] PPIs for CPU 1
- * ...
- * + sysbus IRQs: (in order; number will vary depending on number of cores)
- * - IRQ for CPU 0
- * - IRQ for CPU 1
- * ...
- * - FIQ for CPU 0
- * - FIQ for CPU 1
- * ...
- * - VIRQ for CPU 0 (exists even if virt extensions not present)
- * - VIRQ for CPU 1 (exists even if virt extensions not present)
- * ...
- * - VFIQ for CPU 0 (exists even if virt extensions not present)
- * - VFIQ for CPU 1 (exists even if virt extensions not present)
- * ...
- * - maintenance IRQ for CPU i/f 0 (only if virt extensions present)
- * - maintenance IRQ for CPU i/f 1 (only if virt extensions present)
- * + sysbus MMIO regions: (in order; numbers will vary depending on
- * whether virtualization extensions are present and on number of cores)
- * - distributor registers (GICD*)
- * - CPU interface for the accessing core (GICC*)
- * - virtual interface control registers (GICH*) (only if virt extns present)
- * - virtual CPU interface for the accessing core (GICV*) (only if virt)
- * - CPU 0 CPU interface registers
- * - CPU 1 CPU interface registers
- * ...
- * - CPU 0 virtual interface control registers (only if virt extns present)
- * - CPU 1 virtual interface control registers (only if virt extns present)
- * ...
- */
-
-#ifndef HW_ARM_GIC_H
-#define HW_ARM_GIC_H
-
-#include "arm_gic_common.h"
-#include "qom/object.h"
-
-/* Number of SGI target-list bits */
-#define GIC_TARGETLIST_BITS 8
-#define GIC_MAX_PRIORITY_BITS 8
-#define GIC_MIN_PRIORITY_BITS 4
-
-#define TYPE_ARM_GIC "arm_gic"
-typedef struct ARMGICClass ARMGICClass;
-/* This is reusing the GICState typedef from TYPE_ARM_GIC_COMMON */
-DECLARE_OBJ_CHECKERS(GICState, ARMGICClass,
- ARM_GIC, TYPE_ARM_GIC)
-
-struct ARMGICClass {
- /*< private >*/
- ARMGICCommonClass parent_class;
- /*< public >*/
-
- DeviceRealize parent_realize;
-};
-
-#endif
+++ /dev/null
-/*
- * ARM GIC support
- *
- * Copyright (c) 2012 Linaro Limited
- * Written by Peter Maydell
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation, either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License along
- * with this program; if not, see <http://www.gnu.org/licenses/>.
- */
-
-#ifndef HW_ARM_GIC_COMMON_H
-#define HW_ARM_GIC_COMMON_H
-
-#include "hw/sysbus.h"
-#include "qom/object.h"
-
-/* Maximum number of possible interrupts, determined by the GIC architecture */
-#define GIC_MAXIRQ 1020
-/* First 32 are private to each CPU (SGIs and PPIs). */
-#define GIC_INTERNAL 32
-#define GIC_NR_SGIS 16
-/* Maximum number of possible CPU interfaces, determined by GIC architecture */
-#define GIC_NCPU 8
-/* Maximum number of possible CPU interfaces with their respective vCPU */
-#define GIC_NCPU_VCPU (GIC_NCPU * 2)
-
-#define MAX_NR_GROUP_PRIO 128
-#define GIC_NR_APRS (MAX_NR_GROUP_PRIO / 32)
-
-#define GIC_MIN_BPR 0
-#define GIC_MIN_ABPR (GIC_MIN_BPR + 1)
-
-/* Architectural maximum number of list registers in the virtual interface */
-#define GIC_MAX_LR 64
-
-/* Only 32 priority levels and 32 preemption levels in the vCPU interfaces */
-#define GIC_VIRT_MAX_GROUP_PRIO_BITS 5
-#define GIC_VIRT_MAX_NR_GROUP_PRIO (1 << GIC_VIRT_MAX_GROUP_PRIO_BITS)
-#define GIC_VIRT_NR_APRS (GIC_VIRT_MAX_NR_GROUP_PRIO / 32)
-
-#define GIC_VIRT_MIN_BPR 2
-#define GIC_VIRT_MIN_ABPR (GIC_VIRT_MIN_BPR + 1)
-
-typedef struct gic_irq_state {
- /* The enable bits are only banked for per-cpu interrupts. */
- uint8_t enabled;
- uint8_t pending;
- uint8_t active;
- uint8_t level;
- bool model; /* 0 = N:N, 1 = 1:N */
- bool edge_trigger; /* true: edge-triggered, false: level-triggered */
- uint8_t group;
-} gic_irq_state;
-
-struct GICState {
- /*< private >*/
- SysBusDevice parent_obj;
- /*< public >*/
-
- qemu_irq parent_irq[GIC_NCPU];
- qemu_irq parent_fiq[GIC_NCPU];
- qemu_irq parent_virq[GIC_NCPU];
- qemu_irq parent_vfiq[GIC_NCPU];
- qemu_irq maintenance_irq[GIC_NCPU];
-
- /* GICD_CTLR; for a GIC with the security extensions the NS banked version
- * of this register is just an alias of bit 1 of the S banked version.
- */
- uint32_t ctlr;
- /* GICC_CTLR; again, the NS banked version is just aliases of bits of
- * the S banked register, so our state only needs to store the S version.
- */
- uint32_t cpu_ctlr[GIC_NCPU_VCPU];
-
- gic_irq_state irq_state[GIC_MAXIRQ];
- uint8_t irq_target[GIC_MAXIRQ];
- uint8_t priority1[GIC_INTERNAL][GIC_NCPU];
- uint8_t priority2[GIC_MAXIRQ - GIC_INTERNAL];
- /* For each SGI on the target CPU, we store 8 bits
- * indicating which source CPUs have made this SGI
- * pending on the target CPU. These correspond to
- * the bytes in the GIC_SPENDSGIR* registers as
- * read by the target CPU.
- */
- uint8_t sgi_pending[GIC_NR_SGIS][GIC_NCPU];
-
- uint16_t priority_mask[GIC_NCPU_VCPU];
- uint16_t running_priority[GIC_NCPU_VCPU];
- uint16_t current_pending[GIC_NCPU_VCPU];
- uint32_t n_prio_bits;
-
- /* If we present the GICv2 without security extensions to a guest,
- * the guest can configure the GICC_CTLR to configure group 1 binary point
- * in the abpr.
- * For a GIC with Security Extensions we use use bpr for the
- * secure copy and abpr as storage for the non-secure copy of the register.
- */
- uint8_t bpr[GIC_NCPU_VCPU];
- uint8_t abpr[GIC_NCPU_VCPU];
-
- /* The APR is implementation defined, so we choose a layout identical to
- * the KVM ABI layout for QEMU's implementation of the gic:
- * If an interrupt for preemption level X is active, then
- * APRn[X mod 32] == 0b1, where n = X / 32
- * otherwise the bit is clear.
- */
- uint32_t apr[GIC_NR_APRS][GIC_NCPU];
- uint32_t nsapr[GIC_NR_APRS][GIC_NCPU];
-
- /* Virtual interface control registers */
- uint32_t h_hcr[GIC_NCPU];
- uint32_t h_misr[GIC_NCPU];
- uint32_t h_lr[GIC_MAX_LR][GIC_NCPU];
- uint32_t h_apr[GIC_NCPU];
-
- /* Number of LRs implemented in this GIC instance */
- uint32_t num_lrs;
-
- uint32_t num_cpu;
-
- MemoryRegion iomem; /* Distributor */
- /* This is just so we can have an opaque pointer which identifies
- * both this GIC and which CPU interface we should be accessing.
- */
- struct GICState *backref[GIC_NCPU];
- MemoryRegion cpuiomem[GIC_NCPU + 1]; /* CPU interfaces */
- MemoryRegion vifaceiomem[GIC_NCPU + 1]; /* Virtual interfaces */
- MemoryRegion vcpuiomem; /* vCPU interface */
-
- uint32_t num_irq;
- uint32_t revision;
- bool security_extn;
- bool virt_extn;
- bool irq_reset_nonsecure; /* configure IRQs as group 1 (NS) on reset? */
- int dev_fd; /* kvm device fd if backed by kvm vgic support */
- Error *migration_blocker;
-};
-typedef struct GICState GICState;
-
-#define TYPE_ARM_GIC_COMMON "arm_gic_common"
-typedef struct ARMGICCommonClass ARMGICCommonClass;
-DECLARE_OBJ_CHECKERS(GICState, ARMGICCommonClass,
- ARM_GIC_COMMON, TYPE_ARM_GIC_COMMON)
-
-struct ARMGICCommonClass {
- /*< private >*/
- SysBusDeviceClass parent_class;
- /*< public >*/
-
- void (*pre_save)(GICState *s);
- void (*post_load)(GICState *s);
-};
-
-void gic_init_irqs_and_mmio(GICState *s, qemu_irq_handler handler,
- const MemoryRegionOps *ops,
- const MemoryRegionOps *virt_ops);
-
-#endif
+++ /dev/null
-/*
- * ARM Generic Interrupt Controller v3
- *
- * Copyright (c) 2015 Huawei.
- * Copyright (c) 2016 Linaro Limited
- * Written by Shlomo Pongratz, Peter Maydell
- *
- * This code is licensed under the GPL, version 2 or (at your option)
- * any later version.
- */
-
-#ifndef HW_ARM_GICV3_H
-#define HW_ARM_GICV3_H
-
-#include "arm_gicv3_common.h"
-#include "qom/object.h"
-
-#define TYPE_ARM_GICV3 "arm-gicv3"
-typedef struct ARMGICv3Class ARMGICv3Class;
-/* This is reusing the GICState typedef from TYPE_ARM_GICV3_COMMON */
-DECLARE_OBJ_CHECKERS(GICv3State, ARMGICv3Class,
- ARM_GICV3, TYPE_ARM_GICV3)
-
-struct ARMGICv3Class {
- /*< private >*/
- ARMGICv3CommonClass parent_class;
- /*< public >*/
-
- DeviceRealize parent_realize;
-};
-
-#endif
+++ /dev/null
-/*
- * ARM GIC support
- *
- * Copyright (c) 2012 Linaro Limited
- * Copyright (c) 2015 Huawei.
- * Copyright (c) 2015 Samsung Electronics Co., Ltd.
- * Written by Peter Maydell
- * Reworked for GICv3 by Shlomo Pongratz and Pavel Fedin
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation, either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License along
- * with this program; if not, see <http://www.gnu.org/licenses/>.
- */
-
-#ifndef HW_ARM_GICV3_COMMON_H
-#define HW_ARM_GICV3_COMMON_H
-
-#include "hw/sysbus.h"
-#include "hw/intc/arm_gic_common.h"
-#include "qom/object.h"
-
-/*
- * Maximum number of possible interrupts, determined by the GIC architecture.
- * Note that this does not include LPIs. When implemented, these should be
- * dealt with separately.
- */
-#define GICV3_MAXIRQ 1020
-#define GICV3_MAXSPI (GICV3_MAXIRQ - GIC_INTERNAL)
-
-#define GICV3_REDIST_SIZE 0x20000
-
-/* Number of SGI target-list bits */
-#define GICV3_TARGETLIST_BITS 16
-
-/* Maximum number of list registers (architectural limit) */
-#define GICV3_LR_MAX 16
-
-/* Minimum BPR for Secure, or when security not enabled */
-#define GIC_MIN_BPR 0
-/* Minimum BPR for Nonsecure when security is enabled */
-#define GIC_MIN_BPR_NS (GIC_MIN_BPR + 1)
-
-/* For some distributor fields we want to model the array of 32-bit
- * register values which hold various bitmaps corresponding to enabled,
- * pending, etc bits. These macros and functions facilitate that; the
- * APIs are generally modelled on the generic bitmap.h functions
- * (which are unsuitable here because they use 'unsigned long' as the
- * underlying storage type, which is very awkward when you need to
- * access the data as 32-bit values.)
- * Each bitmap contains a bit for each interrupt. Although there is
- * space for the PPIs and SGIs, those bits (the first 32) are never
- * used as that state lives in the redistributor. The unused bits are
- * provided purely so that interrupt X's state is always in bit X; this
- * avoids bugs where we forget to subtract GIC_INTERNAL from an
- * interrupt number.
- */
-#define GICV3_BMP_SIZE DIV_ROUND_UP(GICV3_MAXIRQ, 32)
-
-#define GIC_DECLARE_BITMAP(name) \
- uint32_t name[GICV3_BMP_SIZE]
-
-#define GIC_BIT_MASK(nr) (1U << ((nr) % 32))
-#define GIC_BIT_WORD(nr) ((nr) / 32)
-
-static inline void gic_bmp_set_bit(int nr, uint32_t *addr)
-{
- uint32_t mask = GIC_BIT_MASK(nr);
- uint32_t *p = addr + GIC_BIT_WORD(nr);
-
- *p |= mask;
-}
-
-static inline void gic_bmp_clear_bit(int nr, uint32_t *addr)
-{
- uint32_t mask = GIC_BIT_MASK(nr);
- uint32_t *p = addr + GIC_BIT_WORD(nr);
-
- *p &= ~mask;
-}
-
-static inline int gic_bmp_test_bit(int nr, const uint32_t *addr)
-{
- return 1U & (addr[GIC_BIT_WORD(nr)] >> (nr & 31));
-}
-
-static inline void gic_bmp_replace_bit(int nr, uint32_t *addr, int val)
-{
- uint32_t mask = GIC_BIT_MASK(nr);
- uint32_t *p = addr + GIC_BIT_WORD(nr);
-
- *p &= ~mask;
- *p |= (val & 1U) << (nr % 32);
-}
-
-/* Return a pointer to the 32-bit word containing the specified bit. */
-static inline uint32_t *gic_bmp_ptr32(uint32_t *addr, int nr)
-{
- return addr + GIC_BIT_WORD(nr);
-}
-
-typedef struct GICv3State GICv3State;
-typedef struct GICv3CPUState GICv3CPUState;
-
-/* Some CPU interface registers come in three flavours:
- * Group0, Group1 (Secure) and Group1 (NonSecure)
- * (where the latter two are exposed as a single banked system register).
- * In the state struct they are implemented as a 3-element array which
- * can be indexed into by the GICV3_G0, GICV3_G1 and GICV3_G1NS constants.
- * If the CPU doesn't support EL3 then the G1 element is unused.
- *
- * These constants are also used to communicate the group to use for
- * an interrupt or SGI when it is passed between the cpu interface and
- * the redistributor or distributor. For those purposes the receiving end
- * must be prepared to cope with a Group 1 Secure interrupt even if it does
- * not have security support enabled, because security can be disabled
- * independently in the CPU and in the GIC. In that case the receiver should
- * treat an incoming Group 1 Secure interrupt as if it were Group 0.
- * (This architectural requirement is why the _G1 element is the unused one
- * in a no-EL3 CPU: we would otherwise have to translate back and forth
- * between (G0, G1NS) from the distributor and (G0, G1) in the CPU i/f.)
- */
-#define GICV3_G0 0
-#define GICV3_G1 1
-#define GICV3_G1NS 2
-
-/* ICC_CTLR_EL1, GICD_STATUSR and GICR_STATUSR are banked but not
- * group-related, so those indices are just 0 for S and 1 for NS.
- * (If the CPU or the GIC, respectively, don't support the Security
- * extensions then the S element is unused.)
- */
-#define GICV3_S 0
-#define GICV3_NS 1
-
-typedef struct {
- int irq;
- uint8_t prio;
- int grp;
-} PendingIrq;
-
-struct GICv3CPUState {
- GICv3State *gic;
- CPUState *cpu;
- qemu_irq parent_irq;
- qemu_irq parent_fiq;
- qemu_irq parent_virq;
- qemu_irq parent_vfiq;
-
- /* Redistributor */
- uint32_t level; /* Current IRQ level */
- /* RD_base page registers */
- uint32_t gicr_ctlr;
- uint64_t gicr_typer;
- uint32_t gicr_statusr[2];
- uint32_t gicr_waker;
- uint64_t gicr_propbaser;
- uint64_t gicr_pendbaser;
- /* SGI_base page registers */
- uint32_t gicr_igroupr0;
- uint32_t gicr_ienabler0;
- uint32_t gicr_ipendr0;
- uint32_t gicr_iactiver0;
- uint32_t edge_trigger; /* ICFGR0 and ICFGR1 even bits */
- uint32_t gicr_igrpmodr0;
- uint32_t gicr_nsacr;
- uint8_t gicr_ipriorityr[GIC_INTERNAL];
-
- /* CPU interface */
- uint64_t icc_sre_el1;
- uint64_t icc_ctlr_el1[2];
- uint64_t icc_pmr_el1;
- uint64_t icc_bpr[3];
- uint64_t icc_apr[3][4];
- uint64_t icc_igrpen[3];
- uint64_t icc_ctlr_el3;
-
- /* Virtualization control interface */
- uint64_t ich_apr[3][4]; /* ich_apr[GICV3_G1][x] never used */
- uint64_t ich_hcr_el2;
- uint64_t ich_lr_el2[GICV3_LR_MAX];
- uint64_t ich_vmcr_el2;
-
- /* Properties of the CPU interface. These are initialized from
- * the settings in the CPU proper.
- * If the number of implemented list registers is 0 then the
- * virtualization support is not implemented.
- */
- int num_list_regs;
- int vpribits; /* number of virtual priority bits */
- int vprebits; /* number of virtual preemption bits */
-
- /* Current highest priority pending interrupt for this CPU.
- * This is cached information that can be recalculated from the
- * real state above; it doesn't need to be migrated.
- */
- PendingIrq hppi;
- /* This is temporary working state, to avoid a malloc in gicv3_update() */
- bool seenbetter;
-};
-
-struct GICv3State {
- /*< private >*/
- SysBusDevice parent_obj;
- /*< public >*/
-
- MemoryRegion iomem_dist; /* Distributor */
- MemoryRegion *iomem_redist; /* Redistributor Regions */
- uint32_t *redist_region_count; /* redistributor count within each region */
- uint32_t nb_redist_regions; /* number of redist regions */
-
- uint32_t num_cpu;
- uint32_t num_irq;
- uint32_t revision;
- bool security_extn;
- bool irq_reset_nonsecure;
- bool gicd_no_migration_shift_bug;
-
- int dev_fd; /* kvm device fd if backed by kvm vgic support */
- Error *migration_blocker;
-
- /* Distributor */
-
- /* for a GIC with the security extensions the NS banked version of this
- * register is just an alias of bit 1 of the S banked version.
- */
- uint32_t gicd_ctlr;
- uint32_t gicd_statusr[2];
- GIC_DECLARE_BITMAP(group); /* GICD_IGROUPR */
- GIC_DECLARE_BITMAP(grpmod); /* GICD_IGRPMODR */
- GIC_DECLARE_BITMAP(enabled); /* GICD_ISENABLER */
- GIC_DECLARE_BITMAP(pending); /* GICD_ISPENDR */
- GIC_DECLARE_BITMAP(active); /* GICD_ISACTIVER */
- GIC_DECLARE_BITMAP(level); /* Current level */
- GIC_DECLARE_BITMAP(edge_trigger); /* GICD_ICFGR even bits */
- uint8_t gicd_ipriority[GICV3_MAXIRQ];
- uint64_t gicd_irouter[GICV3_MAXIRQ];
- /* Cached information: pointer to the cpu i/f for the CPUs specified
- * in the IROUTER registers
- */
- GICv3CPUState *gicd_irouter_target[GICV3_MAXIRQ];
- uint32_t gicd_nsacr[DIV_ROUND_UP(GICV3_MAXIRQ, 16)];
-
- GICv3CPUState *cpu;
-};
-
-#define GICV3_BITMAP_ACCESSORS(BMP) \
- static inline void gicv3_gicd_##BMP##_set(GICv3State *s, int irq) \
- { \
- gic_bmp_set_bit(irq, s->BMP); \
- } \
- static inline int gicv3_gicd_##BMP##_test(GICv3State *s, int irq) \
- { \
- return gic_bmp_test_bit(irq, s->BMP); \
- } \
- static inline void gicv3_gicd_##BMP##_clear(GICv3State *s, int irq) \
- { \
- gic_bmp_clear_bit(irq, s->BMP); \
- } \
- static inline void gicv3_gicd_##BMP##_replace(GICv3State *s, \
- int irq, int value) \
- { \
- gic_bmp_replace_bit(irq, s->BMP, value); \
- }
-
-GICV3_BITMAP_ACCESSORS(group)
-GICV3_BITMAP_ACCESSORS(grpmod)
-GICV3_BITMAP_ACCESSORS(enabled)
-GICV3_BITMAP_ACCESSORS(pending)
-GICV3_BITMAP_ACCESSORS(active)
-GICV3_BITMAP_ACCESSORS(level)
-GICV3_BITMAP_ACCESSORS(edge_trigger)
-
-#define TYPE_ARM_GICV3_COMMON "arm-gicv3-common"
-typedef struct ARMGICv3CommonClass ARMGICv3CommonClass;
-DECLARE_OBJ_CHECKERS(GICv3State, ARMGICv3CommonClass,
- ARM_GICV3_COMMON, TYPE_ARM_GICV3_COMMON)
-
-struct ARMGICv3CommonClass {
- /*< private >*/
- SysBusDeviceClass parent_class;
- /*< public >*/
-
- void (*pre_save)(GICv3State *s);
- void (*post_load)(GICv3State *s);
-};
-
-void gicv3_init_irqs_and_mmio(GICv3State *s, qemu_irq_handler handler,
- const MemoryRegionOps *ops, Error **errp);
-
-#endif
+++ /dev/null
-/*
- * ITS support for ARM GICv3
- *
- * Copyright (c) 2015 Samsung Electronics Co., Ltd.
- * Written by Pavel Fedin
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation, either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License along
- * with this program; if not, see <http://www.gnu.org/licenses/>.
- */
-
-#ifndef QEMU_ARM_GICV3_ITS_COMMON_H
-#define QEMU_ARM_GICV3_ITS_COMMON_H
-
-#include "hw/sysbus.h"
-#include "hw/intc/arm_gicv3_common.h"
-#include "qom/object.h"
-
-#define ITS_CONTROL_SIZE 0x10000
-#define ITS_TRANS_SIZE 0x10000
-#define ITS_SIZE (ITS_CONTROL_SIZE + ITS_TRANS_SIZE)
-
-#define GITS_CTLR 0x0
-#define GITS_IIDR 0x4
-#define GITS_CBASER 0x80
-#define GITS_CWRITER 0x88
-#define GITS_CREADR 0x90
-#define GITS_BASER 0x100
-
-struct GICv3ITSState {
- SysBusDevice parent_obj;
-
- MemoryRegion iomem_main;
- MemoryRegion iomem_its_cntrl;
- MemoryRegion iomem_its_translation;
-
- GICv3State *gicv3;
-
- int dev_fd; /* kvm device fd if backed by kvm vgic support */
- uint64_t gits_translater_gpa;
- bool translater_gpa_known;
-
- /* Registers */
- uint32_t ctlr;
- uint32_t iidr;
- uint64_t cbaser;
- uint64_t cwriter;
- uint64_t creadr;
- uint64_t baser[8];
-
- Error *migration_blocker;
-};
-
-typedef struct GICv3ITSState GICv3ITSState;
-
-void gicv3_its_init_mmio(GICv3ITSState *s, const MemoryRegionOps *ops);
-
-#define TYPE_ARM_GICV3_ITS_COMMON "arm-gicv3-its-common"
-typedef struct GICv3ITSCommonClass GICv3ITSCommonClass;
-DECLARE_OBJ_CHECKERS(GICv3ITSState, GICv3ITSCommonClass,
- ARM_GICV3_ITS_COMMON, TYPE_ARM_GICV3_ITS_COMMON)
-
-struct GICv3ITSCommonClass {
- /*< private >*/
- SysBusDeviceClass parent_class;
- /*< public >*/
-
- int (*send_msi)(GICv3ITSState *s, uint32_t data, uint16_t devid);
- void (*pre_save)(GICv3ITSState *s);
- void (*post_load)(GICv3ITSState *s);
-};
-
-
-#endif
+++ /dev/null
-/*
- * ARMv7M NVIC object
- *
- * Copyright (c) 2017 Linaro Ltd
- * Written by Peter Maydell <peter.maydell@linaro.org>
- *
- * This code is licensed under the GPL version 2 or later.
- */
-
-#ifndef HW_ARM_ARMV7M_NVIC_H
-#define HW_ARM_ARMV7M_NVIC_H
-
-#include "target/arm/cpu.h"
-#include "hw/sysbus.h"
-#include "hw/timer/armv7m_systick.h"
-#include "qom/object.h"
-
-#define TYPE_NVIC "armv7m_nvic"
-
-typedef struct NVICState NVICState;
-DECLARE_INSTANCE_CHECKER(NVICState, NVIC,
- TYPE_NVIC)
-
-/* Highest permitted number of exceptions (architectural limit) */
-#define NVIC_MAX_VECTORS 512
-/* Number of internal exceptions */
-#define NVIC_INTERNAL_VECTORS 16
-
-typedef struct VecInfo {
- /* Exception priorities can range from -3 to 255; only the unmodifiable
- * priority values for RESET, NMI and HardFault can be negative.
- */
- int16_t prio;
- uint8_t enabled;
- uint8_t pending;
- uint8_t active;
- uint8_t level; /* exceptions <=15 never set level */
-} VecInfo;
-
-struct NVICState {
- /*< private >*/
- SysBusDevice parent_obj;
- /*< public >*/
-
- ARMCPU *cpu;
-
- VecInfo vectors[NVIC_MAX_VECTORS];
- /* If the v8M security extension is implemented, some of the internal
- * exceptions are banked between security states (ie there exists both
- * a Secure and a NonSecure version of the exception and its state):
- * HardFault, MemManage, UsageFault, SVCall, PendSV, SysTick (R_PJHV)
- * The rest (including all the external exceptions) are not banked, though
- * they may be configurable to target either Secure or NonSecure state.
- * We store the secure exception state in sec_vectors[] for the banked
- * exceptions, and otherwise use only vectors[] (including for exceptions
- * like SecureFault that unconditionally target Secure state).
- * Entries in sec_vectors[] for non-banked exception numbers are unused.
- */
- VecInfo sec_vectors[NVIC_INTERNAL_VECTORS];
- /* The PRIGROUP field in AIRCR is banked */
- uint32_t prigroup[M_REG_NUM_BANKS];
- uint8_t num_prio_bits;
-
- /* v8M NVIC_ITNS state (stored as a bool per bit) */
- bool itns[NVIC_MAX_VECTORS];
-
- /* The following fields are all cached state that can be recalculated
- * from the vectors[] and sec_vectors[] arrays and the prigroup field:
- * - vectpending
- * - vectpending_is_secure
- * - exception_prio
- * - vectpending_prio
- */
- unsigned int vectpending; /* highest prio pending enabled exception */
- /* true if vectpending is a banked secure exception, ie it is in
- * sec_vectors[] rather than vectors[]
- */
- bool vectpending_is_s_banked;
- int exception_prio; /* group prio of the highest prio active exception */
- int vectpending_prio; /* group prio of the exeception in vectpending */
-
- MemoryRegion sysregmem;
- MemoryRegion sysreg_ns_mem;
- MemoryRegion systickmem;
- MemoryRegion systick_ns_mem;
- MemoryRegion container;
-
- uint32_t num_irq;
- qemu_irq excpout;
- qemu_irq sysresetreq;
-
- SysTickState systick[M_REG_NUM_BANKS];
-};
-
-#endif
+++ /dev/null
-/*
- * ASPEED Interrupt Controller (New)
- *
- * Andrew Jeffery <andrew@aj.id.au>
- *
- * Copyright 2016 IBM Corp.
- *
- * This code is licensed under the GPL version 2 or later. See
- * the COPYING file in the top-level directory.
- *
- * Need to add SVIC and CVIC support
- */
-#ifndef ASPEED_VIC_H
-#define ASPEED_VIC_H
-
-#include "hw/sysbus.h"
-#include "qom/object.h"
-
-#define TYPE_ASPEED_VIC "aspeed.vic"
-OBJECT_DECLARE_SIMPLE_TYPE(AspeedVICState, ASPEED_VIC)
-
-#define ASPEED_VIC_NR_IRQS 51
-
-struct AspeedVICState {
- /*< private >*/
- SysBusDevice parent_obj;
-
- /*< public >*/
- MemoryRegion iomem;
- qemu_irq irq;
- qemu_irq fiq;
-
- uint64_t level;
- uint64_t raw;
- uint64_t select;
- uint64_t enable;
- uint64_t trigger;
-
- /* 0=edge, 1=level */
- uint64_t sense;
-
- /* 0=single-edge, 1=dual-edge */
- uint64_t dual_edge;
-
- /* 0=low-sensitive/falling-edge, 1=high-sensitive/rising-edge */
- uint64_t event;
-};
-
-#endif /* ASPEED_VIC_H */
+++ /dev/null
-/*
- * Raspberry Pi emulation (c) 2012 Gregory Estrade
- *
- * This work is licensed under the terms of the GNU GPL, version 2 or later.
- * See the COPYING file in the top-level directory.
- */
-
-#ifndef BCM2835_IC_H
-#define BCM2835_IC_H
-
-#include "hw/sysbus.h"
-#include "qom/object.h"
-
-#define TYPE_BCM2835_IC "bcm2835-ic"
-OBJECT_DECLARE_SIMPLE_TYPE(BCM2835ICState, BCM2835_IC)
-
-#define BCM2835_IC_GPU_IRQ "gpu-irq"
-#define BCM2835_IC_ARM_IRQ "arm-irq"
-
-struct BCM2835ICState {
- /*< private >*/
- SysBusDevice busdev;
- /*< public >*/
-
- MemoryRegion iomem;
- qemu_irq irq;
- qemu_irq fiq;
-
- /* 64 GPU IRQs + 8 ARM IRQs = 72 total (GPU first) */
- uint64_t gpu_irq_level, gpu_irq_enable;
- uint8_t arm_irq_level, arm_irq_enable;
- bool fiq_enable;
- uint8_t fiq_select;
-};
-
-#endif
+++ /dev/null
-/*
- * Raspberry Pi emulation (c) 2012 Gregory Estrade
- * Upstreaming code cleanup [including bcm2835_*] (c) 2013 Jan Petrous
- *
- * Rasperry Pi 2 emulation and refactoring Copyright (c) 2015, Microsoft
- * Written by Andrew Baumann
- *
- * ARM Local Timer IRQ Copyright (c) 2019. Zoltán Baldaszti
- * Added basic IRQ_TIMER interrupt support
- *
- * This work is licensed under the terms of the GNU GPL, version 2 or later.
- * See the COPYING file in the top-level directory.
- */
-
-#ifndef BCM2836_CONTROL_H
-#define BCM2836_CONTROL_H
-
-#include "hw/sysbus.h"
-#include "qemu/timer.h"
-#include "qom/object.h"
-
-/* 4 mailboxes per core, for 16 total */
-#define BCM2836_NCORES 4
-#define BCM2836_MBPERCORE 4
-
-#define TYPE_BCM2836_CONTROL "bcm2836-control"
-OBJECT_DECLARE_SIMPLE_TYPE(BCM2836ControlState, BCM2836_CONTROL)
-
-struct BCM2836ControlState {
- /*< private >*/
- SysBusDevice busdev;
- /*< public >*/
- MemoryRegion iomem;
-
- /* mailbox state */
- uint32_t mailboxes[BCM2836_NCORES * BCM2836_MBPERCORE];
-
- /* interrupt routing/control registers */
- uint8_t route_gpu_irq, route_gpu_fiq;
- uint32_t timercontrol[BCM2836_NCORES];
- uint32_t mailboxcontrol[BCM2836_NCORES];
-
- /* interrupt status regs (derived from input pins; not visible to user) */
- bool gpu_irq, gpu_fiq;
- uint8_t timerirqs[BCM2836_NCORES];
-
- /* local timer */
- QEMUTimer timer;
- uint32_t local_timer_control;
- uint8_t route_localtimer;
-
- /* interrupt source registers, post-routing (also input-derived; visible) */
- uint32_t irqsrc[BCM2836_NCORES];
- uint32_t fiqsrc[BCM2836_NCORES];
-
- /* outputs to CPU cores */
- qemu_irq irq[BCM2836_NCORES];
- qemu_irq fiq[BCM2836_NCORES];
-};
-
-#endif
+++ /dev/null
-/*
- * Heathrow PIC support (OldWorld PowerMac)
- *
- * Copyright (c) 2005-2007 Fabrice Bellard
- * Copyright (c) 2007 Jocelyn Mayer
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
- * furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
- * THE SOFTWARE.
- */
-
-#ifndef HW_INTC_HEATHROW_PIC_H
-#define HW_INTC_HEATHROW_PIC_H
-
-#include "hw/sysbus.h"
-#include "qom/object.h"
-
-#define TYPE_HEATHROW "heathrow"
-OBJECT_DECLARE_SIMPLE_TYPE(HeathrowState, HEATHROW)
-
-typedef struct HeathrowPICState {
- uint32_t events;
- uint32_t mask;
- uint32_t levels;
- uint32_t level_triggered;
-} HeathrowPICState;
-
-struct HeathrowState {
- SysBusDevice parent_obj;
-
- MemoryRegion mem;
- HeathrowPICState pics[2];
- qemu_irq irqs[1];
-};
-
-#define HEATHROW_NUM_IRQS 64
-
-#endif /* HW_INTC_HEATHROW_PIC_H */
+++ /dev/null
-#ifndef HW_I8259_H
-#define HW_I8259_H
-
-/* i8259.c */
-
-extern DeviceState *isa_pic;
-qemu_irq *i8259_init(ISABus *bus, qemu_irq parent_irq);
-qemu_irq *kvm_i8259_init(ISABus *bus);
-int pic_get_output(DeviceState *d);
-int pic_read_irq(DeviceState *d);
-
-#endif
+++ /dev/null
-/*
- * QEMU RISC-V lowRISC Ibex PLIC
- *
- * Copyright (c) 2020 Western Digital
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms and conditions of the GNU General Public License,
- * version 2 or later, as published by the Free Software Foundation.
- *
- * This program is distributed in the hope it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License along with
- * this program. If not, see <http://www.gnu.org/licenses/>.
- */
-
-#ifndef HW_IBEX_PLIC_H
-#define HW_IBEX_PLIC_H
-
-#include "hw/sysbus.h"
-#include "qom/object.h"
-
-#define TYPE_IBEX_PLIC "ibex-plic"
-OBJECT_DECLARE_SIMPLE_TYPE(IbexPlicState, IBEX_PLIC)
-
-struct IbexPlicState {
- /*< private >*/
- SysBusDevice parent_obj;
-
- /*< public >*/
- MemoryRegion mmio;
-
- uint32_t *pending;
- uint32_t *hidden_pending;
- uint32_t *claimed;
- uint32_t *source;
- uint32_t *priority;
- uint32_t *enable;
- uint32_t threshold;
- uint32_t claim;
-
- /* config */
- uint32_t num_cpus;
- uint32_t num_sources;
-
- uint32_t pending_base;
- uint32_t pending_num;
-
- uint32_t source_base;
- uint32_t source_num;
-
- uint32_t priority_base;
- uint32_t priority_num;
-
- uint32_t enable_base;
- uint32_t enable_num;
-
- uint32_t threshold_base;
-
- uint32_t claim_base;
-};
-
-#endif /* HW_IBEX_PLIC_H */
+++ /dev/null
-/*
- * i.MX31 Vectored Interrupt Controller
- *
- * Note this is NOT the PL192 provided by ARM, but
- * a custom implementation by Freescale.
- *
- * Copyright (c) 2008 OKL
- * Copyright (c) 2011 NICTA Pty Ltd
- * Originally written by Hans Jiang
- * Updated by Jean-Christophe Dubois <jcd@tribudubois.net>
- *
- * This code is licensed under the GPL version 2 or later. See
- * the COPYING file in the top-level directory.
- *
- * TODO: implement vectors.
- */
-#ifndef IMX_AVIC_H
-#define IMX_AVIC_H
-
-#include "hw/sysbus.h"
-#include "qom/object.h"
-
-#define TYPE_IMX_AVIC "imx.avic"
-OBJECT_DECLARE_SIMPLE_TYPE(IMXAVICState, IMX_AVIC)
-
-#define IMX_AVIC_NUM_IRQS 64
-
-/* Interrupt Control Bits */
-#define ABFLAG (1<<25)
-#define ABFEN (1<<24)
-#define NIDIS (1<<22) /* Normal Interrupt disable */
-#define FIDIS (1<<21) /* Fast interrupt disable */
-#define NIAD (1<<20) /* Normal Interrupt Arbiter Rise ARM level */
-#define FIAD (1<<19) /* Fast Interrupt Arbiter Rise ARM level */
-#define NM (1<<18) /* Normal interrupt mode */
-
-#define PRIO_PER_WORD (sizeof(uint32_t) * 8 / 4)
-#define PRIO_WORDS (IMX_AVIC_NUM_IRQS/PRIO_PER_WORD)
-
-struct IMXAVICState {
- /*< private >*/
- SysBusDevice parent_obj;
-
- /*< public >*/
- MemoryRegion iomem;
- uint64_t pending;
- uint64_t enabled;
- uint64_t is_fiq;
- uint32_t intcntl;
- uint32_t intmask;
- qemu_irq irq;
- qemu_irq fiq;
- uint32_t prio[PRIO_WORDS]; /* Priorities are 4-bits each */
-};
-
-#endif /* IMX_AVIC_H */
+++ /dev/null
-#ifndef IMX_GPCV2_H
-#define IMX_GPCV2_H
-
-#include "hw/sysbus.h"
-#include "qom/object.h"
-
-enum IMXGPCv2Registers {
- GPC_NUM = 0xE00 / sizeof(uint32_t),
-};
-
-struct IMXGPCv2State {
- /*< private >*/
- SysBusDevice parent_obj;
-
- /*< public >*/
- MemoryRegion iomem;
- uint32_t regs[GPC_NUM];
-};
-
-#define TYPE_IMX_GPCV2 "imx-gpcv2"
-OBJECT_DECLARE_SIMPLE_TYPE(IMXGPCv2State, IMX_GPCV2)
-
-#endif /* IMX_GPCV2_H */
+++ /dev/null
-#ifndef INTC_H
-#define INTC_H
-
-#include "qom/object.h"
-
-#define TYPE_INTERRUPT_STATS_PROVIDER "intctrl"
-
-typedef struct InterruptStatsProviderClass InterruptStatsProviderClass;
-DECLARE_CLASS_CHECKERS(InterruptStatsProviderClass, INTERRUPT_STATS_PROVIDER,
- TYPE_INTERRUPT_STATS_PROVIDER)
-#define INTERRUPT_STATS_PROVIDER(obj) \
- INTERFACE_CHECK(InterruptStatsProvider, (obj), \
- TYPE_INTERRUPT_STATS_PROVIDER)
-
-typedef struct InterruptStatsProvider InterruptStatsProvider;
-
-struct InterruptStatsProviderClass {
- InterfaceClass parent;
-
- /* The returned pointer and statistics must remain valid until
- * the BQL is next dropped.
- */
- bool (*get_statistics)(InterruptStatsProvider *obj, uint64_t **irq_counts,
- unsigned int *nb_irqs);
- void (*print_info)(InterruptStatsProvider *obj, Monitor *mon);
-};
-
-#endif
+++ /dev/null
-/*
- * This file is subject to the terms and conditions of the GNU General Public
- * License. See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * Copyright (C) 2000, 07 MIPS Technologies, Inc.
- * Copyright (C) 2016 Imagination Technologies
- *
- */
-
-#ifndef MIPS_GIC_H
-#define MIPS_GIC_H
-
-#include "qemu/units.h"
-#include "hw/timer/mips_gictimer.h"
-#include "hw/sysbus.h"
-#include "cpu.h"
-#include "qom/object.h"
-/*
- * GIC Specific definitions
- */
-
-/* The MIPS default location */
-#define GIC_BASE_ADDR 0x1bdc0000ULL
-#define GIC_ADDRSPACE_SZ (128 * KiB)
-
-/* Constants */
-#define GIC_POL_POS 1
-#define GIC_POL_NEG 0
-#define GIC_TRIG_EDGE 1
-#define GIC_TRIG_LEVEL 0
-
-#define MSK(n) ((1ULL << (n)) - 1)
-
-/* GIC Address Space */
-#define SHARED_SECTION_OFS 0x0000
-#define SHARED_SECTION_SIZE 0x8000
-#define VP_LOCAL_SECTION_OFS 0x8000
-#define VP_LOCAL_SECTION_SIZE 0x4000
-#define VP_OTHER_SECTION_OFS 0xc000
-#define VP_OTHER_SECTION_SIZE 0x4000
-#define USM_VISIBLE_SECTION_OFS 0x10000
-#define USM_VISIBLE_SECTION_SIZE 0x10000
-
-/* Register Map for Shared Section */
-
-#define GIC_SH_CONFIG_OFS 0x0000
-
-/* Shared Global Counter */
-#define GIC_SH_COUNTERLO_OFS 0x0010
-#define GIC_SH_COUNTERHI_OFS 0x0014
-#define GIC_SH_REVISIONID_OFS 0x0020
-
-/* Set/Clear corresponding bit in Edge Detect Register */
-#define GIC_SH_WEDGE_OFS 0x0280
-
-/* Reset Mask - Disables Interrupt */
-#define GIC_SH_RMASK_OFS 0x0300
-#define GIC_SH_RMASK_LAST_OFS 0x031c
-
-/* Set Mask (WO) - Enables Interrupt */
-#define GIC_SH_SMASK_OFS 0x0380
-#define GIC_SH_SMASK_LAST_OFS 0x039c
-
-/* Global Interrupt Mask Register (RO) - Bit Set == Interrupt enabled */
-#define GIC_SH_MASK_OFS 0x0400
-#define GIC_SH_MASK_LAST_OFS 0x041c
-
-/* Pending Global Interrupts (RO) */
-#define GIC_SH_PEND_OFS 0x0480
-#define GIC_SH_PEND_LAST_OFS 0x049c
-
-#define GIC_SH_MAP0_PIN_OFS 0x0500
-#define GIC_SH_MAP255_PIN_OFS 0x08fc
-
-#define GIC_SH_MAP0_VP_OFS 0x2000
-#define GIC_SH_MAP255_VP_LAST_OFS 0x3fe4
-
-/* Register Map for Local Section */
-#define GIC_VP_CTL_OFS 0x0000
-#define GIC_VP_PEND_OFS 0x0004
-#define GIC_VP_MASK_OFS 0x0008
-#define GIC_VP_RMASK_OFS 0x000c
-#define GIC_VP_SMASK_OFS 0x0010
-#define GIC_VP_WD_MAP_OFS 0x0040
-#define GIC_VP_COMPARE_MAP_OFS 0x0044
-#define GIC_VP_TIMER_MAP_OFS 0x0048
-#define GIC_VP_FDC_MAP_OFS 0x004c
-#define GIC_VP_PERFCTR_MAP_OFS 0x0050
-#define GIC_VP_SWINT0_MAP_OFS 0x0054
-#define GIC_VP_SWINT1_MAP_OFS 0x0058
-#define GIC_VP_OTHER_ADDR_OFS 0x0080
-#define GIC_VP_IDENT_OFS 0x0088
-#define GIC_VP_WD_CONFIG0_OFS 0x0090
-#define GIC_VP_WD_COUNT0_OFS 0x0094
-#define GIC_VP_WD_INITIAL0_OFS 0x0098
-#define GIC_VP_COMPARE_LO_OFS 0x00a0
-#define GIC_VP_COMPARE_HI_OFS 0x00a4
-#define GIC_VL_BRK_GROUP 0x3080
-
-/* User-Mode Visible Section Register */
-/* Read-only alias for GIC Shared CounterLo */
-#define GIC_USER_MODE_COUNTERLO 0x0000
-/* Read-only alias for GIC Shared CounterHi */
-#define GIC_USER_MODE_COUNTERHI 0x0004
-
-/* Masks */
-#define GIC_SH_CONFIG_COUNTSTOP_SHF 28
-#define GIC_SH_CONFIG_COUNTSTOP_MSK (MSK(1) << GIC_SH_CONFIG_COUNTSTOP_SHF)
-#define GIC_SH_CONFIG_COUNTBITS_SHF 24
-#define GIC_SH_CONFIG_COUNTBITS_MSK (MSK(4) << GIC_SH_CONFIG_COUNTBITS_SHF)
-#define GIC_SH_CONFIG_NUMINTRS_SHF 16
-#define GIC_SH_CONFIG_NUMINTRS_MSK (MSK(8) << GIC_SH_CONFIG_NUMINTRS_SHF)
-#define GIC_SH_CONFIG_PVPS_SHF 0
-#define GIC_SH_CONFIG_PVPS_MSK (MSK(8) << GIC_SH_CONFIG_NUMVPS_SHF)
-
-#define GIC_SH_WEDGE_RW_SHF 31
-#define GIC_SH_WEDGE_RW_MSK (MSK(1) << GIC_SH_WEDGE_RW_SHF)
-
-#define GIC_MAP_TO_PIN_SHF 31
-#define GIC_MAP_TO_PIN_MSK (MSK(1) << GIC_MAP_TO_PIN_SHF)
-#define GIC_MAP_TO_NMI_SHF 30
-#define GIC_MAP_TO_NMI_MSK (MSK(1) << GIC_MAP_TO_NMI_SHF)
-#define GIC_MAP_TO_YQ_SHF 29
-#define GIC_MAP_TO_YQ_MSK (MSK(1) << GIC_MAP_TO_YQ_SHF)
-#define GIC_MAP_SHF 0
-#define GIC_MAP_MSK (MSK(6) << GIC_MAP_SHF)
-#define GIC_MAP_TO_PIN_REG_MSK \
- (GIC_MAP_TO_PIN_MSK | GIC_MAP_TO_NMI_MSK | GIC_MAP_TO_YQ_MSK | GIC_MAP_MSK)
-
-/* GIC_VP_CTL Masks */
-#define GIC_VP_CTL_FDC_RTBL_SHF 4
-#define GIC_VP_CTL_FDC_RTBL_MSK (MSK(1) << GIC_VP_CTL_FDC_RTBL_SHF)
-#define GIC_VP_CTL_SWINT_RTBL_SHF 3
-#define GIC_VP_CTL_SWINT_RTBL_MSK (MSK(1) << GIC_VP_CTL_SWINT_RTBL_SHF)
-#define GIC_VP_CTL_PERFCNT_RTBL_SHF 2
-#define GIC_VP_CTL_PERFCNT_RTBL_MSK (MSK(1) << GIC_VP_CTL_PERFCNT_RTBL_SHF)
-#define GIC_VP_CTL_TIMER_RTBL_SHF 1
-#define GIC_VP_CTL_TIMER_RTBL_MSK (MSK(1) << GIC_VP_CTL_TIMER_RTBL_SHF)
-#define GIC_VP_CTL_EIC_MODE_SHF 0
-#define GIC_VP_CTL_EIC_MODE_MSK (MSK(1) << GIC_VP_CTL_EIC_MODE_SHF)
-
-/* GIC_VP_MASK Masks */
-#define GIC_VP_MASK_FDC_SHF 6
-#define GIC_VP_MASK_FDC_MSK (MSK(1) << GIC_VP_MASK_FDC_SHF)
-#define GIC_VP_MASK_SWINT1_SHF 5
-#define GIC_VP_MASK_SWINT1_MSK (MSK(1) << GIC_VP_MASK_SWINT1_SHF)
-#define GIC_VP_MASK_SWINT0_SHF 4
-#define GIC_VP_MASK_SWINT0_MSK (MSK(1) << GIC_VP_MASK_SWINT0_SHF)
-#define GIC_VP_MASK_PERFCNT_SHF 3
-#define GIC_VP_MASK_PERFCNT_MSK (MSK(1) << GIC_VP_MASK_PERFCNT_SHF)
-#define GIC_VP_MASK_TIMER_SHF 2
-#define GIC_VP_MASK_TIMER_MSK (MSK(1) << GIC_VP_MASK_TIMER_SHF)
-#define GIC_VP_MASK_CMP_SHF 1
-#define GIC_VP_MASK_CMP_MSK (MSK(1) << GIC_VP_MASK_CMP_SHF)
-#define GIC_VP_MASK_WD_SHF 0
-#define GIC_VP_MASK_WD_MSK (MSK(1) << GIC_VP_MASK_WD_SHF)
-#define GIC_VP_SET_RESET_MSK (MSK(7) << GIC_VP_MASK_WD_SHF)
-
-#define GIC_CPU_INT_MAX 5 /* Core Interrupt 7 */
-#define GIC_CPU_PIN_OFFSET 2
-
-/* Local GIC interrupts. */
-#define GIC_NUM_LOCAL_INTRS 7
-#define GIC_LOCAL_INT_FDC 6 /* CPU fast debug channel */
-#define GIC_LOCAL_INT_SWINT1 5 /* CPU software interrupt 1 */
-#define GIC_LOCAL_INT_SWINT0 4 /* CPU software interrupt 0 */
-#define GIC_LOCAL_INT_PERFCTR 3 /* CPU performance counter */
-#define GIC_LOCAL_INT_TIMER 2 /* CPU timer interrupt */
-#define GIC_LOCAL_INT_COMPARE 1 /* GIC count and compare timer */
-#define GIC_LOCAL_INT_WD 0 /* GIC watchdog */
-
-#define TYPE_MIPS_GIC "mips-gic"
-OBJECT_DECLARE_SIMPLE_TYPE(MIPSGICState, MIPS_GIC)
-
-/* Support up to 32 VPs and 256 IRQs */
-#define GIC_MAX_VPS 32
-#define GIC_MAX_INTRS 256
-
-typedef struct MIPSGICIRQState MIPSGICIRQState;
-typedef struct MIPSGICVPState MIPSGICVPState;
-
-struct MIPSGICIRQState {
- uint8_t enabled;
- uint8_t pending;
- uint32_t map_pin;
- int32_t map_vp;
- qemu_irq irq;
-};
-
-struct MIPSGICVPState {
- uint32_t ctl;
- uint32_t pend;
- uint32_t mask;
- uint32_t compare_map;
- uint32_t other_addr;
- CPUMIPSState *env;
-};
-
-struct MIPSGICState {
- SysBusDevice parent_obj;
- MemoryRegion mr;
-
- /* Shared Section Registers */
- uint32_t sh_config;
- MIPSGICIRQState *irq_state;
-
- /* VP Local/Other Section Registers */
- MIPSGICVPState *vps;
-
- /* GIC VP Timer */
- MIPSGICTimerState *gic_timer;
-
- int32_t num_vps;
- int32_t num_irq;
-};
-
-#endif /* MIPS_GIC_H */
+++ /dev/null
-/*
- * ARM RealView Emulation Baseboard Interrupt Controller
- *
- * Copyright (c) 2006-2007 CodeSourcery.
- * Written by Paul Brook
- *
- * This code is licensed under the GPL.
- */
-
-#ifndef HW_INTC_REALVIEW_GIC_H
-#define HW_INTC_REALVIEW_GIC_H
-
-#include "hw/sysbus.h"
-#include "hw/intc/arm_gic.h"
-#include "qom/object.h"
-
-#define TYPE_REALVIEW_GIC "realview_gic"
-OBJECT_DECLARE_SIMPLE_TYPE(RealViewGICState, REALVIEW_GIC)
-
-struct RealViewGICState {
- SysBusDevice parent_obj;
-
- MemoryRegion container;
-
- GICState gic;
-};
-
-#endif
+++ /dev/null
-/*
- * RX Interrupt Control Unit
- *
- * Copyright (c) 2019 Yoshinori Sato
- *
- * SPDX-License-Identifier: GPL-2.0-or-later
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms and conditions of the GNU General Public License,
- * version 2 or later, as published by the Free Software Foundation.
- *
- * This program is distributed in the hope it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License along with
- * this program. If not, see <http://www.gnu.org/licenses/>.
- */
-
-#ifndef HW_INTC_RX_ICU_H
-#define HW_INTC_RX_ICU_H
-
-#include "hw/sysbus.h"
-#include "qom/object.h"
-
-enum TRG_MODE {
- TRG_LEVEL = 0,
- TRG_NEDGE = 1, /* Falling */
- TRG_PEDGE = 2, /* Raising */
- TRG_BEDGE = 3, /* Both */
-};
-
-struct IRQSource {
- enum TRG_MODE sense;
- int level;
-};
-
-enum {
- /* Software interrupt request */
- SWI = 27,
- NR_IRQS = 256
-};
-
-struct RXICUState {
- /*< private >*/
- SysBusDevice parent_obj;
- /*< public >*/
-
- MemoryRegion memory;
- struct IRQSource src[NR_IRQS];
- uint32_t nr_irqs;
- uint8_t *map;
- uint32_t nr_sense;
- uint8_t *init_sense;
-
- uint8_t ir[NR_IRQS];
- uint8_t dtcer[NR_IRQS];
- uint8_t ier[NR_IRQS / 8];
- uint8_t ipr[142];
- uint8_t dmasr[4];
- uint16_t fir;
- uint8_t nmisr;
- uint8_t nmier;
- uint8_t nmiclr;
- uint8_t nmicr;
- int16_t req_irq;
- qemu_irq _irq;
- qemu_irq _fir;
- qemu_irq _swi;
-};
-
-#define TYPE_RX_ICU "rx-icu"
-OBJECT_DECLARE_SIMPLE_TYPE(RXICUState, RX_ICU)
-
-#endif /* RX_ICU_H */
+++ /dev/null
-/*
- * SiFive CLINT (Core Local Interruptor) interface
- *
- * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu
- * Copyright (c) 2017 SiFive, Inc.
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms and conditions of the GNU General Public License,
- * version 2 or later, as published by the Free Software Foundation.
- *
- * This program is distributed in the hope it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License along with
- * this program. If not, see <http://www.gnu.org/licenses/>.
- */
-
-#ifndef HW_SIFIVE_CLINT_H
-#define HW_SIFIVE_CLINT_H
-
-#include "hw/sysbus.h"
-
-#define TYPE_SIFIVE_CLINT "riscv.sifive.clint"
-
-#define SIFIVE_CLINT(obj) \
- OBJECT_CHECK(SiFiveCLINTState, (obj), TYPE_SIFIVE_CLINT)
-
-typedef struct SiFiveCLINTState {
- /*< private >*/
- SysBusDevice parent_obj;
-
- /*< public >*/
- MemoryRegion mmio;
- uint32_t hartid_base;
- uint32_t num_harts;
- uint32_t sip_base;
- uint32_t timecmp_base;
- uint32_t time_base;
- uint32_t aperture_size;
- uint32_t timebase_freq;
-} SiFiveCLINTState;
-
-DeviceState *sifive_clint_create(hwaddr addr, hwaddr size,
- uint32_t hartid_base, uint32_t num_harts, uint32_t sip_base,
- uint32_t timecmp_base, uint32_t time_base, uint32_t timebase_freq,
- bool provide_rdtime);
-
-enum {
- SIFIVE_SIP_BASE = 0x0,
- SIFIVE_TIMECMP_BASE = 0x4000,
- SIFIVE_TIME_BASE = 0xBFF8
-};
-
-enum {
- SIFIVE_CLINT_TIMEBASE_FREQ = 10000000
-};
-
-#endif
+++ /dev/null
-/*
- * SiFive PLIC (Platform Level Interrupt Controller) interface
- *
- * Copyright (c) 2017 SiFive, Inc.
- *
- * This provides a RISC-V PLIC device
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms and conditions of the GNU General Public License,
- * version 2 or later, as published by the Free Software Foundation.
- *
- * This program is distributed in the hope it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License along with
- * this program. If not, see <http://www.gnu.org/licenses/>.
- */
-
-#ifndef HW_SIFIVE_PLIC_H
-#define HW_SIFIVE_PLIC_H
-
-#include "hw/sysbus.h"
-#include "qom/object.h"
-
-#define TYPE_SIFIVE_PLIC "riscv.sifive.plic"
-
-typedef struct SiFivePLICState SiFivePLICState;
-DECLARE_INSTANCE_CHECKER(SiFivePLICState, SIFIVE_PLIC,
- TYPE_SIFIVE_PLIC)
-
-typedef enum PLICMode {
- PLICMode_U,
- PLICMode_S,
- PLICMode_H,
- PLICMode_M
-} PLICMode;
-
-typedef struct PLICAddr {
- uint32_t addrid;
- uint32_t hartid;
- PLICMode mode;
-} PLICAddr;
-
-struct SiFivePLICState {
- /*< private >*/
- SysBusDevice parent_obj;
-
- /*< public >*/
- MemoryRegion mmio;
- uint32_t num_addrs;
- uint32_t num_harts;
- uint32_t bitfield_words;
- uint32_t num_enables;
- PLICAddr *addr_config;
- uint32_t *source_priority;
- uint32_t *target_priority;
- uint32_t *pending;
- uint32_t *claimed;
- uint32_t *enable;
-
- /* config */
- char *hart_config;
- uint32_t hartid_base;
- uint32_t num_sources;
- uint32_t num_priorities;
- uint32_t priority_base;
- uint32_t pending_base;
- uint32_t enable_base;
- uint32_t enable_stride;
- uint32_t context_base;
- uint32_t context_stride;
- uint32_t aperture_size;
-};
-
-DeviceState *sifive_plic_create(hwaddr addr, char *hart_config,
- uint32_t hartid_base, uint32_t num_sources,
- uint32_t num_priorities, uint32_t priority_base,
- uint32_t pending_base, uint32_t enable_base,
- uint32_t enable_stride, uint32_t context_base,
- uint32_t context_stride, uint32_t aperture_size);
-
-#endif
+++ /dev/null
-/*
- * QEMU model of Xilinx I/O Module Interrupt Controller
- *
- * Copyright (c) 2014 Xilinx Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
- * furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
- * THE SOFTWARE.
- */
-
-#ifndef HW_INTC_XLNX_PMU_IOMOD_INTC_H
-#define HW_INTC_XLNX_PMU_IOMOD_INTC_H
-
-#include "hw/sysbus.h"
-#include "hw/register.h"
-#include "qom/object.h"
-
-#define TYPE_XLNX_PMU_IO_INTC "xlnx.pmu_io_intc"
-
-OBJECT_DECLARE_SIMPLE_TYPE(XlnxPMUIOIntc, XLNX_PMU_IO_INTC)
-
-/* This is R_PIT3_CONTROL + 1 */
-#define XLNXPMUIOINTC_R_MAX (0x78 + 1)
-
-struct XlnxPMUIOIntc {
- SysBusDevice parent_obj;
- MemoryRegion iomem;
-
- qemu_irq parent_irq;
-
- struct {
- uint32_t intr_size;
- uint32_t level_edge;
- uint32_t positive;
- } cfg;
-
- uint32_t irq_raw;
-
- uint32_t regs[XLNXPMUIOINTC_R_MAX];
- RegisterInfo regs_info[XLNXPMUIOINTC_R_MAX];
-};
-
-#endif /* HW_INTC_XLNX_PMU_IOMOD_INTC_H */
+++ /dev/null
-/*
- * QEMU model of the IPI Inter Processor Interrupt block
- *
- * Copyright (c) 2014 Xilinx Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
- * furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
- * THE SOFTWARE.
- */
-
-#ifndef XLNX_ZYNQMP_IPI_H
-#define XLNX_ZYNQMP_IPI_H
-
-#include "hw/sysbus.h"
-#include "hw/register.h"
-#include "qom/object.h"
-
-#define TYPE_XLNX_ZYNQMP_IPI "xlnx.zynqmp_ipi"
-
-OBJECT_DECLARE_SIMPLE_TYPE(XlnxZynqMPIPI, XLNX_ZYNQMP_IPI)
-
-/* This is R_IPI_IDR + 1 */
-#define R_XLNX_ZYNQMP_IPI_MAX ((0x1c / 4) + 1)
-
-#define NUM_IPIS 11
-
-struct XlnxZynqMPIPI {
- /* Private */
- SysBusDevice parent_obj;
-
- /* Public */
- MemoryRegion iomem;
- qemu_irq irq;
-
- qemu_irq irq_trig_out[NUM_IPIS];
- qemu_irq irq_obs_out[NUM_IPIS];
-
- uint32_t regs[R_XLNX_ZYNQMP_IPI_MAX];
- RegisterInfo regs_info[R_XLNX_ZYNQMP_IPI_MAX];
-};
-
-#endif /* XLNX_ZYNQMP_IPI_H */
+++ /dev/null
-/*
- * QEMU IndustryPack emulation
- *
- * Copyright (C) 2012 Igalia, S.L.
- * Author: Alberto Garcia <berto@igalia.com>
- *
- * This code is licensed under the GNU GPL v2 or (at your option) any
- * later version.
- */
-
-#ifndef QEMU_IPACK_H
-#define QEMU_IPACK_H
-
-#include "hw/qdev-core.h"
-#include "qom/object.h"
-
-
-#define TYPE_IPACK_BUS "IndustryPack"
-OBJECT_DECLARE_SIMPLE_TYPE(IPackBus, IPACK_BUS)
-
-struct IPackBus {
- /*< private >*/
- BusState parent_obj;
-
- /* All fields are private */
- uint8_t n_slots;
- uint8_t free_slot;
- qemu_irq_handler set_irq;
-};
-
-
-#define TYPE_IPACK_DEVICE "ipack-device"
-OBJECT_DECLARE_TYPE(IPackDevice, IPackDeviceClass,
- IPACK_DEVICE)
-
-struct IPackDeviceClass {
- /*< private >*/
- DeviceClass parent_class;
- /*< public >*/
-
- DeviceRealize realize;
- DeviceUnrealize unrealize;
-
- uint16_t (*io_read)(IPackDevice *dev, uint8_t addr);
- void (*io_write)(IPackDevice *dev, uint8_t addr, uint16_t val);
-
- uint16_t (*id_read)(IPackDevice *dev, uint8_t addr);
- void (*id_write)(IPackDevice *dev, uint8_t addr, uint16_t val);
-
- uint16_t (*int_read)(IPackDevice *dev, uint8_t addr);
- void (*int_write)(IPackDevice *dev, uint8_t addr, uint16_t val);
-
- uint16_t (*mem_read16)(IPackDevice *dev, uint32_t addr);
- void (*mem_write16)(IPackDevice *dev, uint32_t addr, uint16_t val);
-
- uint8_t (*mem_read8)(IPackDevice *dev, uint32_t addr);
- void (*mem_write8)(IPackDevice *dev, uint32_t addr, uint8_t val);
-};
-
-struct IPackDevice {
- /*< private >*/
- DeviceState parent_obj;
- /*< public >*/
-
- int32_t slot;
- /* IRQ objects for the IndustryPack INT0# and INT1# */
- qemu_irq *irq;
-};
-
-extern const VMStateDescription vmstate_ipack_device;
-
-#define VMSTATE_IPACK_DEVICE(_field, _state) \
- VMSTATE_STRUCT(_field, _state, 1, vmstate_ipack_device, IPackDevice)
-
-IPackDevice *ipack_device_find(IPackBus *bus, int32_t slot);
-void ipack_bus_new_inplace(IPackBus *bus, size_t bus_size,
- DeviceState *parent,
- const char *name, uint8_t n_slots,
- qemu_irq_handler handler);
-
-#endif
+++ /dev/null
-/*
- * IPMI base class
- *
- * Copyright (c) 2015 Corey Minyard, MontaVista Software, LLC
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
- * furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
- * THE SOFTWARE.
- */
-
-#ifndef HW_IPMI_H
-#define HW_IPMI_H
-
-#include "exec/memory.h"
-#include "hw/qdev-core.h"
-#include "qom/object.h"
-
-#define MAX_IPMI_MSG_SIZE 300
-
-enum ipmi_op {
- IPMI_RESET_CHASSIS,
- IPMI_POWEROFF_CHASSIS,
- IPMI_POWERON_CHASSIS,
- IPMI_POWERCYCLE_CHASSIS,
- IPMI_PULSE_DIAG_IRQ,
- IPMI_SHUTDOWN_VIA_ACPI_OVERTEMP,
- IPMI_SEND_NMI
-};
-
-#define IPMI_CC_INVALID_CMD 0xc1
-#define IPMI_CC_COMMAND_INVALID_FOR_LUN 0xc2
-#define IPMI_CC_TIMEOUT 0xc3
-#define IPMI_CC_OUT_OF_SPACE 0xc4
-#define IPMI_CC_INVALID_RESERVATION 0xc5
-#define IPMI_CC_REQUEST_DATA_TRUNCATED 0xc6
-#define IPMI_CC_REQUEST_DATA_LENGTH_INVALID 0xc7
-#define IPMI_CC_PARM_OUT_OF_RANGE 0xc9
-#define IPMI_CC_CANNOT_RETURN_REQ_NUM_BYTES 0xca
-#define IPMI_CC_REQ_ENTRY_NOT_PRESENT 0xcb
-#define IPMI_CC_INVALID_DATA_FIELD 0xcc
-#define IPMI_CC_BMC_INIT_IN_PROGRESS 0xd2
-#define IPMI_CC_COMMAND_NOT_SUPPORTED 0xd5
-#define IPMI_CC_UNSPECIFIED 0xff
-
-#define IPMI_NETFN_APP 0x06
-#define IPMI_NETFN_OEM 0x3a
-
-#define IPMI_DEBUG 1
-
-/* Specified in the SMBIOS spec. */
-#define IPMI_SMBIOS_KCS 0x01
-#define IPMI_SMBIOS_SMIC 0x02
-#define IPMI_SMBIOS_BT 0x03
-#define IPMI_SMBIOS_SSIF 0x04
-
-/*
- * Used for transferring information to interfaces that add
- * entries to firmware tables.
- */
-typedef struct IPMIFwInfo {
- const char *interface_name;
- int interface_type;
- uint8_t ipmi_spec_major_revision;
- uint8_t ipmi_spec_minor_revision;
- uint8_t i2c_slave_address;
- uint32_t uuid;
-
- uint64_t base_address;
- uint64_t register_length;
- uint8_t register_spacing;
- enum {
- IPMI_MEMSPACE_IO,
- IPMI_MEMSPACE_MEM32,
- IPMI_MEMSPACE_MEM64,
- IPMI_MEMSPACE_SMBUS
- } memspace;
-
- int interrupt_number;
- enum {
- IPMI_LEVEL_IRQ,
- IPMI_EDGE_IRQ
- } irq_type;
-} IPMIFwInfo;
-
-/*
- * Called by each instantiated IPMI interface device to get it's uuid.
- */
-uint32_t ipmi_next_uuid(void);
-
-/* IPMI Interface types (KCS, SMIC, BT) are prefixed with this */
-#define TYPE_IPMI_INTERFACE_PREFIX "ipmi-interface-"
-
-/*
- * An IPMI Interface, the interface for talking between the target
- * and the BMC.
- */
-#define TYPE_IPMI_INTERFACE "ipmi-interface"
-#define IPMI_INTERFACE(obj) \
- INTERFACE_CHECK(IPMIInterface, (obj), TYPE_IPMI_INTERFACE)
-typedef struct IPMIInterfaceClass IPMIInterfaceClass;
-DECLARE_CLASS_CHECKERS(IPMIInterfaceClass, IPMI_INTERFACE,
- TYPE_IPMI_INTERFACE)
-
-typedef struct IPMIInterface IPMIInterface;
-
-struct IPMIInterfaceClass {
- InterfaceClass parent;
-
- /*
- * min_size is the requested I/O size and must be a power of 2.
- * This is so PCI (or other busses) can request a bigger range.
- * Use 0 for the default.
- */
- void (*init)(struct IPMIInterface *s, unsigned int min_size, Error **errp);
-
- /*
- * Perform various operations on the hardware. If checkonly is
- * true, it will return if the operation can be performed, but it
- * will not do the operation.
- */
- int (*do_hw_op)(struct IPMIInterface *s, enum ipmi_op op, int checkonly);
-
- /*
- * Enable/disable irqs on the interface when the BMC requests this.
- */
- void (*set_irq_enable)(struct IPMIInterface *s, int val);
-
- /*
- * Handle an event that occurred on the interface, generally the.
- * target writing to a register.
- */
- void (*handle_if_event)(struct IPMIInterface *s);
-
- /*
- * The interfaces use this to perform certain ops
- */
- void (*set_atn)(struct IPMIInterface *s, int val, int irq);
-
- /*
- * Got an IPMI warm/cold reset.
- */
- void (*reset)(struct IPMIInterface *s, bool is_cold);
-
- /*
- * Handle a response from the bmc.
- */
- void (*handle_rsp)(struct IPMIInterface *s, uint8_t msg_id,
- unsigned char *rsp, unsigned int rsp_len);
-
- /*
- * Set by the owner to hold the backend data for the interface.
- */
- void *(*get_backend_data)(struct IPMIInterface *s);
-
- /*
- * Return the firmware info for a device.
- */
- void (*get_fwinfo)(struct IPMIInterface *s, IPMIFwInfo *info);
-};
-
-/*
- * Define a BMC simulator (or perhaps a connection to a real BMC)
- */
-#define TYPE_IPMI_BMC "ipmi-bmc"
-OBJECT_DECLARE_TYPE(IPMIBmc, IPMIBmcClass,
- IPMI_BMC)
-
-struct IPMIBmc {
- DeviceState parent;
-
- uint8_t slave_addr;
-
- IPMIInterface *intf;
-};
-
-struct IPMIBmcClass {
- DeviceClass parent;
-
- /* Called when the system resets to report to the bmc. */
- void (*handle_reset)(struct IPMIBmc *s);
-
- /*
- * Handle a command to the bmc.
- */
- void (*handle_command)(struct IPMIBmc *s,
- uint8_t *cmd, unsigned int cmd_len,
- unsigned int max_cmd_len,
- uint8_t msg_id);
-};
-
-/*
- * Add a link property to obj that points to a BMC.
- */
-void ipmi_bmc_find_and_link(Object *obj, Object **bmc);
-
-#ifdef IPMI_DEBUG
-#define ipmi_debug(fs, ...) \
- fprintf(stderr, "IPMI (%s): " fs, __func__, ##__VA_ARGS__)
-#else
-#define ipmi_debug(fs, ...)
-#endif
-
-struct ipmi_sdr_header {
- uint8_t rec_id[2];
- uint8_t sdr_version; /* 0x51 */
- uint8_t rec_type;
- uint8_t rec_length;
-};
-#define IPMI_SDR_HEADER_SIZE sizeof(struct ipmi_sdr_header)
-
-#define ipmi_sdr_recid(sdr) ((sdr)->rec_id[0] | ((sdr)->rec_id[1] << 8))
-#define ipmi_sdr_length(sdr) ((sdr)->rec_length + IPMI_SDR_HEADER_SIZE)
-
-/*
- * 43.2 SDR Type 02h. Compact Sensor Record
- */
-#define IPMI_SDR_COMPACT_TYPE 2
-
-struct ipmi_sdr_compact {
- struct ipmi_sdr_header header;
-
- uint8_t sensor_owner_id;
- uint8_t sensor_owner_lun;
- uint8_t sensor_owner_number; /* byte 8 */
- uint8_t entity_id;
- uint8_t entity_instance;
- uint8_t sensor_init;
- uint8_t sensor_caps;
- uint8_t sensor_type;
- uint8_t reading_type;
- uint8_t assert_mask[2]; /* byte 16 */
- uint8_t deassert_mask[2];
- uint8_t discrete_mask[2];
- uint8_t sensor_unit1;
- uint8_t sensor_unit2;
- uint8_t sensor_unit3;
- uint8_t sensor_direction[2]; /* byte 24 */
- uint8_t positive_threshold;
- uint8_t negative_threshold;
- uint8_t reserved[3];
- uint8_t oem;
- uint8_t id_str_len; /* byte 32 */
- uint8_t id_string[16];
-};
-
-typedef uint8_t ipmi_sdr_compact_buffer[sizeof(struct ipmi_sdr_compact)];
-
-int ipmi_bmc_sdr_find(IPMIBmc *b, uint16_t recid,
- const struct ipmi_sdr_compact **sdr, uint16_t *nextrec);
-void ipmi_bmc_gen_event(IPMIBmc *b, uint8_t *evt, bool log);
-
-#define TYPE_IPMI_BMC_SIMULATOR "ipmi-bmc-sim"
-OBJECT_DECLARE_SIMPLE_TYPE(IPMIBmcSim, IPMI_BMC_SIMULATOR)
-
-
-typedef struct RspBuffer {
- uint8_t buffer[MAX_IPMI_MSG_SIZE];
- unsigned int len;
-} RspBuffer;
-
-static inline void rsp_buffer_set_error(RspBuffer *rsp, uint8_t byte)
-{
- rsp->buffer[2] = byte;
-}
-
-/* Add a byte to the response. */
-static inline void rsp_buffer_push(RspBuffer *rsp, uint8_t byte)
-{
- if (rsp->len >= sizeof(rsp->buffer)) {
- rsp_buffer_set_error(rsp, IPMI_CC_REQUEST_DATA_TRUNCATED);
- return;
- }
- rsp->buffer[rsp->len++] = byte;
-}
-
-typedef struct IPMICmdHandler {
- void (*cmd_handler)(IPMIBmcSim *s,
- uint8_t *cmd, unsigned int cmd_len,
- RspBuffer *rsp);
- unsigned int cmd_len_min;
-} IPMICmdHandler;
-
-typedef struct IPMINetfn {
- unsigned int cmd_nums;
- const IPMICmdHandler *cmd_handlers;
-} IPMINetfn;
-
-int ipmi_sim_register_netfn(IPMIBmcSim *s, unsigned int netfn,
- const IPMINetfn *netfnd);
-
-#endif
+++ /dev/null
-/*
- * QEMU IPMI BT emulation
- *
- * Copyright (c) 2015 Corey Minyard, MontaVista Software, LLC
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
- * furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
- * THE SOFTWARE.
- */
-
-#ifndef HW_IPMI_BT_H
-#define HW_IPMI_BT_H
-
-#include "hw/ipmi/ipmi.h"
-
-typedef struct IPMIBT {
- IPMIBmc *bmc;
-
- bool do_wake;
-
- bool obf_irq_set;
- bool atn_irq_set;
- bool irqs_enabled;
-
- uint8_t outmsg[MAX_IPMI_MSG_SIZE];
- uint32_t outpos;
- uint32_t outlen;
-
- uint8_t inmsg[MAX_IPMI_MSG_SIZE];
- uint32_t inlen;
-
- uint8_t control_reg;
- uint8_t mask_reg;
-
- /*
- * This is a response number that we send with the command to make
- * sure that the response matches the command.
- */
- uint8_t waiting_rsp;
- uint8_t waiting_seq;
-
- uint32_t io_base;
- unsigned long io_length;
- MemoryRegion io;
- unsigned long size_mask;
-
- void (*raise_irq)(struct IPMIBT *ib);
- void (*lower_irq)(struct IPMIBT *ib);
- void *opaque;
-
- bool use_irq;
-} IPMIBT;
-
-void ipmi_bt_get_fwinfo(IPMIBT *ik, IPMIFwInfo *info);
-void ipmi_bt_class_init(IPMIInterfaceClass *iic);
-extern const VMStateDescription vmstate_IPMIBT;
-int ipmi_bt_vmstate_post_load(void *opaque, int version);
-
-#endif /* HW_IPMI_BT_H */
+++ /dev/null
-/*
- * QEMU IPMI KCS emulation
- *
- * Copyright (c) 2015,2017 Corey Minyard, MontaVista Software, LLC
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
- * furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
- * THE SOFTWARE.
- */
-
-#ifndef HW_IPMI_KCS_H
-#define HW_IPMI_KCS_H
-
-#include "hw/ipmi/ipmi.h"
-
-typedef struct IPMIKCS {
- IPMIBmc *bmc;
-
- bool do_wake;
-
- bool obf_irq_set;
- bool atn_irq_set;
- bool irqs_enabled;
-
- uint8_t outmsg[MAX_IPMI_MSG_SIZE];
- uint32_t outpos;
- uint32_t outlen;
-
- uint8_t inmsg[MAX_IPMI_MSG_SIZE];
- uint32_t inlen;
- bool write_end;
-
- uint8_t status_reg;
- uint8_t data_out_reg;
-
- int16_t data_in_reg; /* -1 means not written */
- int16_t cmd_reg;
-
- /*
- * This is a response number that we send with the command to make
- * sure that the response matches the command.
- */
- uint8_t waiting_rsp;
-
- uint32_t io_base;
- unsigned long io_length;
- MemoryRegion io;
- unsigned long size_mask;
-
- void (*raise_irq)(struct IPMIKCS *ik);
- void (*lower_irq)(struct IPMIKCS *ik);
- void *opaque;
-
- bool use_irq;
-} IPMIKCS;
-
-void ipmi_kcs_get_fwinfo(IPMIKCS *ik, IPMIFwInfo *info);
-void ipmi_kcs_class_init(IPMIInterfaceClass *iic);
-extern const VMStateDescription vmstate_IPMIKCS;
-int ipmi_kcs_vmstate_post_load(void *opaque, int version);
-
-#endif /* HW_IPMI_KCS_H */
+++ /dev/null
-/*
- * QEMU KVM support, paravirtual clock device
- *
- * Copyright (C) 2011 Siemens AG
- *
- * Authors:
- * Jan Kiszka <jan.kiszka@siemens.com>
- *
- * This work is licensed under the terms of the GNU GPL version 2.
- * See the COPYING file in the top-level directory.
- */
-
-#ifndef HW_KVM_CLOCK_H
-#define HW_KVM_CLOCK_H
-
-#ifdef CONFIG_KVM
-
-void kvmclock_create(bool create_always);
-
-#else /* CONFIG_KVM */
-
-static inline void kvmclock_create(bool create_always)
-{
-}
-
-#endif /* !CONFIG_KVM */
-
-#endif
+++ /dev/null
-#ifndef QEMU_HW_LM32_PIC_H
-#define QEMU_HW_LM32_PIC_H
-
-
-uint32_t lm32_pic_get_ip(DeviceState *d);
-uint32_t lm32_pic_get_im(DeviceState *d);
-void lm32_pic_set_ip(DeviceState *d, uint32_t ip);
-void lm32_pic_set_im(DeviceState *d, uint32_t im);
-
-#endif /* QEMU_HW_LM32_PIC_H */
+++ /dev/null
-#ifndef HW_MCF_H
-#define HW_MCF_H
-/* Motorola ColdFire device prototypes. */
-
-#include "target/m68k/cpu-qom.h"
-
-/* mcf_uart.c */
-uint64_t mcf_uart_read(void *opaque, hwaddr addr,
- unsigned size);
-void mcf_uart_write(void *opaque, hwaddr addr,
- uint64_t val, unsigned size);
-void *mcf_uart_init(qemu_irq irq, Chardev *chr);
-void mcf_uart_mm_init(hwaddr base, qemu_irq irq, Chardev *chr);
-
-/* mcf_intc.c */
-qemu_irq *mcf_intc_init(struct MemoryRegion *sysmem,
- hwaddr base,
- M68kCPU *cpu);
-
-/* mcf5206.c */
-#define TYPE_MCF5206_MBAR "mcf5206-mbar"
-
-#endif
+++ /dev/null
-/*
- * Definitions for the ColdFire Fast Ethernet Controller emulation.
- *
- * This code is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- */
-
-#ifndef HW_M68K_MCF_FEC_H
-#define HW_M68K_MCF_FEC_H
-#include "qom/object.h"
-
-#define TYPE_MCF_FEC_NET "mcf-fec"
-OBJECT_DECLARE_SIMPLE_TYPE(mcf_fec_state, MCF_FEC_NET)
-
-#define FEC_NUM_IRQ 13
-
-#endif
+++ /dev/null
-
-#ifndef NEXT_CUBE_H
-#define NEXT_CUBE_H
-
-#define TYPE_NEXTFB "next-fb"
-
-#define TYPE_NEXTKBD "next-kbd"
-
-enum next_dma_chan {
- NEXTDMA_FD,
- NEXTDMA_ENRX,
- NEXTDMA_ENTX,
- NEXTDMA_SCSI,
- NEXTDMA_SCC,
- NEXTDMA_SND
-};
-
-#define DMA_ENABLE 0x01000000
-#define DMA_SUPDATE 0x02000000
-#define DMA_COMPLETE 0x08000000
-
-#define DMA_M2DEV 0x0
-#define DMA_SETENABLE 0x00010000
-#define DMA_SETSUPDATE 0x00020000
-#define DMA_DEV2M 0x00040000
-#define DMA_CLRCOMPLETE 0x00080000
-#define DMA_RESET 0x00100000
-
-enum next_irqs {
- NEXT_FD_I,
- NEXT_KBD_I,
- NEXT_PWR_I,
- NEXT_ENRX_I,
- NEXT_ENTX_I,
- NEXT_SCSI_I,
- NEXT_CLK_I,
- NEXT_SCC_I,
- NEXT_ENTX_DMA_I,
- NEXT_ENRX_DMA_I,
- NEXT_SCSI_DMA_I,
- NEXT_SCC_DMA_I,
- NEXT_SND_I
-};
-
-void next_irq(void *opaque, int number, int level);
-
-#endif /* NEXT_CUBE_H */
+++ /dev/null
-#ifndef HW_MIPS_BIOS_H
-#define HW_MIPS_BIOS_H
-
-#include "qemu/units.h"
-#include "cpu.h"
-
-#define BIOS_SIZE (4 * MiB)
-#ifdef TARGET_WORDS_BIGENDIAN
-#define BIOS_FILENAME "mips_bios.bin"
-#else
-#define BIOS_FILENAME "mipsel_bios.bin"
-#endif
-
-#endif
+++ /dev/null
-/*
- * Coherent Processing System emulation.
- *
- * Copyright (c) 2016 Imagination Technologies
- *
- * This library is free software; you can redistribute it and/or
- * modify it under the terms of the GNU Lesser General Public
- * License as published by the Free Software Foundation; either
- * version 2.1 of the License, or (at your option) any later version.
- *
- * This library is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
- * Lesser General Public License for more details.
- *
- * You should have received a copy of the GNU Lesser General Public
- * License along with this library; if not, see <http://www.gnu.org/licenses/>.
- */
-
-#ifndef MIPS_CPS_H
-#define MIPS_CPS_H
-
-#include "hw/sysbus.h"
-#include "hw/clock.h"
-#include "hw/misc/mips_cmgcr.h"
-#include "hw/intc/mips_gic.h"
-#include "hw/misc/mips_cpc.h"
-#include "hw/misc/mips_itu.h"
-#include "target/mips/cpu.h"
-#include "qom/object.h"
-
-#define TYPE_MIPS_CPS "mips-cps"
-OBJECT_DECLARE_SIMPLE_TYPE(MIPSCPSState, MIPS_CPS)
-
-struct MIPSCPSState {
- SysBusDevice parent_obj;
-
- uint32_t num_vp;
- uint32_t num_irq;
- char *cpu_type;
-
- MemoryRegion container;
- MIPSGCRState gcr;
- MIPSGICState gic;
- MIPSCPCState cpc;
- MIPSITUState itu;
- Clock *clock;
-};
-
-qemu_irq get_cps_irq(MIPSCPSState *cps, int pin_number);
-
-#endif
+++ /dev/null
-#ifndef HW_MIPS_CPUDEVS_H
-#define HW_MIPS_CPUDEVS_H
-
-#include "target/mips/cpu-qom.h"
-
-/* Definitions for MIPS CPU internal devices. */
-
-/* addr.c */
-uint64_t cpu_mips_kseg0_to_phys(void *opaque, uint64_t addr);
-uint64_t cpu_mips_phys_to_kseg0(void *opaque, uint64_t addr);
-uint64_t cpu_mips_kvm_um_phys_to_kseg0(void *opaque, uint64_t addr);
-bool mips_um_ksegs_enabled(void);
-void mips_um_ksegs_enable(void);
-
-/* mips_int.c */
-void cpu_mips_irq_init_cpu(MIPSCPU *cpu);
-
-/* mips_timer.c */
-void cpu_mips_clock_init(MIPSCPU *cpu);
-
-#endif
+++ /dev/null
-#ifndef HW_MIPS_H
-#define HW_MIPS_H
-/* Definitions for mips board emulation. */
-
-#include "qemu/units.h"
-
-/* Kernels can be configured with 64KB pages */
-#define INITRD_PAGE_SIZE (64 * KiB)
-
-#include "exec/memory.h"
-
-/* gt64xxx.c */
-PCIBus *gt64120_register(qemu_irq *pic);
-
-/* bonito.c */
-PCIBus *bonito_init(qemu_irq *pic);
-
-/* rc4030.c */
-typedef struct rc4030DMAState *rc4030_dma;
-void rc4030_dma_read(void *dma, uint8_t *buf, int len);
-void rc4030_dma_write(void *dma, uint8_t *buf, int len);
-
-DeviceState *rc4030_init(rc4030_dma **dmas, IOMMUMemoryRegion **dma_mr);
-
-#endif
+++ /dev/null
-/*
- * Cortex-A9MPCore Snoop Control Unit (SCU) emulation.
- *
- * Copyright (c) 2009 CodeSourcery.
- * Copyright (c) 2011 Linaro Limited.
- * Written by Paul Brook, Peter Maydell.
- *
- * This code is licensed under the GPL.
- */
-#ifndef HW_MISC_A9SCU_H
-#define HW_MISC_A9SCU_H
-
-#include "hw/sysbus.h"
-#include "qom/object.h"
-
-/* A9MP private memory region. */
-
-struct A9SCUState {
- /*< private >*/
- SysBusDevice parent_obj;
- /*< public >*/
-
- MemoryRegion iomem;
- uint32_t control;
- uint32_t status;
- uint32_t num_cpu;
-};
-
-#define TYPE_A9_SCU "a9-scu"
-OBJECT_DECLARE_SIMPLE_TYPE(A9SCUState, A9_SCU)
-
-#endif
+++ /dev/null
-/*
- * Allwinner CPU Configuration Module emulation
- *
- * Copyright (C) 2019 Niek Linnenbank <nieklinnenbank@gmail.com>
- *
- * This program is free software: you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation, either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program. If not, see <http://www.gnu.org/licenses/>.
- */
-
-#ifndef HW_MISC_ALLWINNER_CPUCFG_H
-#define HW_MISC_ALLWINNER_CPUCFG_H
-
-#include "qom/object.h"
-#include "hw/sysbus.h"
-
-/**
- * Object model
- * @{
- */
-
-#define TYPE_AW_CPUCFG "allwinner-cpucfg"
-OBJECT_DECLARE_SIMPLE_TYPE(AwCpuCfgState, AW_CPUCFG)
-
-/** @} */
-
-/**
- * Allwinner CPU Configuration Module instance state
- */
-struct AwCpuCfgState {
- /*< private >*/
- SysBusDevice parent_obj;
- /*< public >*/
-
- MemoryRegion iomem;
- uint32_t gen_ctrl;
- uint32_t super_standby;
- uint32_t entry_addr;
-
-};
-
-#endif /* HW_MISC_ALLWINNER_CPUCFG_H */
+++ /dev/null
-/*
- * Allwinner H3 Clock Control Unit emulation
- *
- * Copyright (C) 2019 Niek Linnenbank <nieklinnenbank@gmail.com>
- *
- * This program is free software: you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation, either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program. If not, see <http://www.gnu.org/licenses/>.
- */
-
-#ifndef HW_MISC_ALLWINNER_H3_CCU_H
-#define HW_MISC_ALLWINNER_H3_CCU_H
-
-#include "qom/object.h"
-#include "hw/sysbus.h"
-
-/**
- * @name Constants
- * @{
- */
-
-/** Size of register I/O address space used by CCU device */
-#define AW_H3_CCU_IOSIZE (0x400)
-
-/** Total number of known registers */
-#define AW_H3_CCU_REGS_NUM (AW_H3_CCU_IOSIZE / sizeof(uint32_t))
-
-/** @} */
-
-/**
- * @name Object model
- * @{
- */
-
-#define TYPE_AW_H3_CCU "allwinner-h3-ccu"
-OBJECT_DECLARE_SIMPLE_TYPE(AwH3ClockCtlState, AW_H3_CCU)
-
-/** @} */
-
-/**
- * Allwinner H3 CCU object instance state.
- */
-struct AwH3ClockCtlState {
- /*< private >*/
- SysBusDevice parent_obj;
- /*< public >*/
-
- /** Maps I/O registers in physical memory */
- MemoryRegion iomem;
-
- /** Array of hardware registers */
- uint32_t regs[AW_H3_CCU_REGS_NUM];
-
-};
-
-#endif /* HW_MISC_ALLWINNER_H3_CCU_H */
+++ /dev/null
-/*
- * Allwinner H3 SDRAM Controller emulation
- *
- * Copyright (C) 2019 Niek Linnenbank <nieklinnenbank@gmail.com>
- *
- * This program is free software: you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation, either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program. If not, see <http://www.gnu.org/licenses/>.
- */
-
-#ifndef HW_MISC_ALLWINNER_H3_DRAMC_H
-#define HW_MISC_ALLWINNER_H3_DRAMC_H
-
-#include "qom/object.h"
-#include "hw/sysbus.h"
-#include "exec/hwaddr.h"
-
-/**
- * Constants
- * @{
- */
-
-/** Highest register address used by DRAMCOM module */
-#define AW_H3_DRAMCOM_REGS_MAXADDR (0x804)
-
-/** Total number of known DRAMCOM registers */
-#define AW_H3_DRAMCOM_REGS_NUM (AW_H3_DRAMCOM_REGS_MAXADDR / \
- sizeof(uint32_t))
-
-/** Highest register address used by DRAMCTL module */
-#define AW_H3_DRAMCTL_REGS_MAXADDR (0x88c)
-
-/** Total number of known DRAMCTL registers */
-#define AW_H3_DRAMCTL_REGS_NUM (AW_H3_DRAMCTL_REGS_MAXADDR / \
- sizeof(uint32_t))
-
-/** Highest register address used by DRAMPHY module */
-#define AW_H3_DRAMPHY_REGS_MAXADDR (0x4)
-
-/** Total number of known DRAMPHY registers */
-#define AW_H3_DRAMPHY_REGS_NUM (AW_H3_DRAMPHY_REGS_MAXADDR / \
- sizeof(uint32_t))
-
-/** @} */
-
-/**
- * Object model
- * @{
- */
-
-#define TYPE_AW_H3_DRAMC "allwinner-h3-dramc"
-OBJECT_DECLARE_SIMPLE_TYPE(AwH3DramCtlState, AW_H3_DRAMC)
-
-/** @} */
-
-/**
- * Allwinner H3 SDRAM Controller object instance state.
- */
-struct AwH3DramCtlState {
- /*< private >*/
- SysBusDevice parent_obj;
- /*< public >*/
-
- /** Physical base address for start of RAM */
- hwaddr ram_addr;
-
- /** Total RAM size in megabytes */
- uint32_t ram_size;
-
- /**
- * @name Memory Regions
- * @{
- */
-
- MemoryRegion row_mirror; /**< Simulates rows for RAM size detection */
- MemoryRegion row_mirror_alias; /**< Alias of the row which is mirrored */
- MemoryRegion dramcom_iomem; /**< DRAMCOM module I/O registers */
- MemoryRegion dramctl_iomem; /**< DRAMCTL module I/O registers */
- MemoryRegion dramphy_iomem; /**< DRAMPHY module I/O registers */
-
- /** @} */
-
- /**
- * @name Hardware Registers
- * @{
- */
-
- uint32_t dramcom[AW_H3_DRAMCOM_REGS_NUM]; /**< Array of DRAMCOM registers */
- uint32_t dramctl[AW_H3_DRAMCTL_REGS_NUM]; /**< Array of DRAMCTL registers */
- uint32_t dramphy[AW_H3_DRAMPHY_REGS_NUM] ;/**< Array of DRAMPHY registers */
-
- /** @} */
-
-};
-
-#endif /* HW_MISC_ALLWINNER_H3_DRAMC_H */
+++ /dev/null
-/*
- * Allwinner H3 System Control emulation
- *
- * Copyright (C) 2019 Niek Linnenbank <nieklinnenbank@gmail.com>
- *
- * This program is free software: you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation, either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program. If not, see <http://www.gnu.org/licenses/>.
- */
-
-#ifndef HW_MISC_ALLWINNER_H3_SYSCTRL_H
-#define HW_MISC_ALLWINNER_H3_SYSCTRL_H
-
-#include "qom/object.h"
-#include "hw/sysbus.h"
-
-/**
- * @name Constants
- * @{
- */
-
-/** Highest register address used by System Control device */
-#define AW_H3_SYSCTRL_REGS_MAXADDR (0x30)
-
-/** Total number of known registers */
-#define AW_H3_SYSCTRL_REGS_NUM ((AW_H3_SYSCTRL_REGS_MAXADDR / \
- sizeof(uint32_t)) + 1)
-
-/** @} */
-
-/**
- * @name Object model
- * @{
- */
-
-#define TYPE_AW_H3_SYSCTRL "allwinner-h3-sysctrl"
-OBJECT_DECLARE_SIMPLE_TYPE(AwH3SysCtrlState, AW_H3_SYSCTRL)
-
-/** @} */
-
-/**
- * Allwinner H3 System Control object instance state
- */
-struct AwH3SysCtrlState {
- /*< private >*/
- SysBusDevice parent_obj;
- /*< public >*/
-
- /** Maps I/O registers in physical memory */
- MemoryRegion iomem;
-
- /** Array of hardware registers */
- uint32_t regs[AW_H3_SYSCTRL_REGS_NUM];
-
-};
-
-#endif /* HW_MISC_ALLWINNER_H3_SYSCTRL_H */
+++ /dev/null
-/*
- * Allwinner Security ID emulation
- *
- * Copyright (C) 2019 Niek Linnenbank <nieklinnenbank@gmail.com>
- *
- * This program is free software: you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation, either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program. If not, see <http://www.gnu.org/licenses/>.
- */
-
-#ifndef HW_MISC_ALLWINNER_SID_H
-#define HW_MISC_ALLWINNER_SID_H
-
-#include "qom/object.h"
-#include "hw/sysbus.h"
-#include "qemu/uuid.h"
-
-/**
- * Object model
- * @{
- */
-
-#define TYPE_AW_SID "allwinner-sid"
-OBJECT_DECLARE_SIMPLE_TYPE(AwSidState, AW_SID)
-
-/** @} */
-
-/**
- * Allwinner Security ID object instance state
- */
-struct AwSidState {
- /*< private >*/
- SysBusDevice parent_obj;
- /*< public >*/
-
- /** Maps I/O registers in physical memory */
- MemoryRegion iomem;
-
- /** Control register defines how and what to read */
- uint32_t control;
-
- /** RdKey register contains the data retrieved by the device */
- uint32_t rdkey;
-
- /** Stores the emulated device identifier */
- QemuUUID identifier;
-
-};
-
-#endif /* HW_MISC_ALLWINNER_SID_H */
+++ /dev/null
-/*
- * ARM11MPCore Snoop Control Unit (SCU) emulation
- *
- * Copyright (c) 2006-2007 CodeSourcery.
- * Copyright (c) 2013 SUSE LINUX Products GmbH
- * Written by Paul Brook and Andreas Färber
- *
- * This code is licensed under the GPL.
- */
-
-#ifndef HW_MISC_ARM11SCU_H
-#define HW_MISC_ARM11SCU_H
-
-#include "hw/sysbus.h"
-#include "qom/object.h"
-
-#define TYPE_ARM11_SCU "arm11-scu"
-OBJECT_DECLARE_SIMPLE_TYPE(ARM11SCUState, ARM11_SCU)
-
-struct ARM11SCUState {
- /*< private >*/
- SysBusDevice parent_obj;
- /*< public >*/
-
- uint32_t control;
- uint32_t num_cpu;
- MemoryRegion iomem;
-};
-
-#endif
+++ /dev/null
-/*
- * ARM Integrator Board Debug, switch and LED section
- *
- * Browse the data sheet:
- *
- * http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.dui0159b/Babbfijf.html
- *
- * Copyright (c) 2013 Alex Bennée <alex@bennee.com>
- *
- * This work is licensed under the terms of the GNU GPL, version 2 or later.
- * See the COPYING file in the top-level directory.
- */
-
-#ifndef ARM_INTEGRATOR_DEBUG_H
-#define ARM_INTEGRATOR_DEBUG_H
-
-#define TYPE_INTEGRATOR_DEBUG "integrator_debug"
-
-#endif
+++ /dev/null
-/*
- * ARM SSE-200 CPU_IDENTITY register block
- *
- * Copyright (c) 2019 Linaro Limited
- * Written by Peter Maydell
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 or
- * (at your option) any later version.
- */
-
-/*
- * This is a model of the "CPU_IDENTITY" register block which is part of the
- * Arm SSE-200 and documented in
- * http://infocenter.arm.com/help/topic/com.arm.doc.101104_0100_00_en/corelink_sse200_subsystem_for_embedded_technical_reference_manual_101104_0100_00_en.pdf
- *
- * QEMU interface:
- * + QOM property "CPUID": the value to use for the CPUID register
- * + sysbus MMIO region 0: the system information register bank
- */
-
-#ifndef HW_MISC_ARMSSE_CPUID_H
-#define HW_MISC_ARMSSE_CPUID_H
-
-#include "hw/sysbus.h"
-#include "qom/object.h"
-
-#define TYPE_ARMSSE_CPUID "armsse-cpuid"
-OBJECT_DECLARE_SIMPLE_TYPE(ARMSSECPUID, ARMSSE_CPUID)
-
-struct ARMSSECPUID {
- /*< private >*/
- SysBusDevice parent_obj;
-
- /*< public >*/
- MemoryRegion iomem;
-
- /* Properties */
- uint32_t cpuid;
-};
-
-#endif
+++ /dev/null
-/*
- * ARM SSE-200 Message Handling Unit (MHU)
- *
- * Copyright (c) 2019 Linaro Limited
- * Written by Peter Maydell
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 or
- * (at your option) any later version.
- */
-
-/*
- * This is a model of the Message Handling Unit (MHU) which is part of the
- * Arm SSE-200 and documented in
- * http://infocenter.arm.com/help/topic/com.arm.doc.101104_0100_00_en/corelink_sse200_subsystem_for_embedded_technical_reference_manual_101104_0100_00_en.pdf
- *
- * QEMU interface:
- * + sysbus MMIO region 0: the system information register bank
- * + sysbus IRQ 0: interrupt for CPU 0
- * + sysbus IRQ 1: interrupt for CPU 1
- */
-
-#ifndef HW_MISC_ARMSSE_MHU_H
-#define HW_MISC_ARMSSE_MHU_H
-
-#include "hw/sysbus.h"
-#include "qom/object.h"
-
-#define TYPE_ARMSSE_MHU "armsse-mhu"
-OBJECT_DECLARE_SIMPLE_TYPE(ARMSSEMHU, ARMSSE_MHU)
-
-struct ARMSSEMHU {
- /*< private >*/
- SysBusDevice parent_obj;
-
- /*< public >*/
- MemoryRegion iomem;
- qemu_irq cpu0irq;
- qemu_irq cpu1irq;
-
- uint32_t cpu0intr;
- uint32_t cpu1intr;
-};
-
-#endif
+++ /dev/null
-/*
- * ASPEED System Control Unit
- *
- * Andrew Jeffery <andrew@aj.id.au>
- *
- * Copyright 2016 IBM Corp.
- *
- * This code is licensed under the GPL version 2 or later. See
- * the COPYING file in the top-level directory.
- */
-#ifndef ASPEED_SCU_H
-#define ASPEED_SCU_H
-
-#include "hw/sysbus.h"
-#include "qom/object.h"
-
-#define TYPE_ASPEED_SCU "aspeed.scu"
-OBJECT_DECLARE_TYPE(AspeedSCUState, AspeedSCUClass, ASPEED_SCU)
-#define TYPE_ASPEED_2400_SCU TYPE_ASPEED_SCU "-ast2400"
-#define TYPE_ASPEED_2500_SCU TYPE_ASPEED_SCU "-ast2500"
-#define TYPE_ASPEED_2600_SCU TYPE_ASPEED_SCU "-ast2600"
-
-#define ASPEED_SCU_NR_REGS (0x1A8 >> 2)
-#define ASPEED_AST2600_SCU_NR_REGS (0xE20 >> 2)
-
-struct AspeedSCUState {
- /*< private >*/
- SysBusDevice parent_obj;
-
- /*< public >*/
- MemoryRegion iomem;
-
- uint32_t regs[ASPEED_AST2600_SCU_NR_REGS];
- uint32_t silicon_rev;
- uint32_t hw_strap1;
- uint32_t hw_strap2;
- uint32_t hw_prot_key;
-};
-
-#define AST2400_A0_SILICON_REV 0x02000303U
-#define AST2400_A1_SILICON_REV 0x02010303U
-#define AST2500_A0_SILICON_REV 0x04000303U
-#define AST2500_A1_SILICON_REV 0x04010303U
-#define AST2600_A0_SILICON_REV 0x05000303U
-#define AST2600_A1_SILICON_REV 0x05010303U
-
-#define ASPEED_IS_AST2500(si_rev) ((((si_rev) >> 24) & 0xff) == 0x04)
-
-extern bool is_supported_silicon_rev(uint32_t silicon_rev);
-
-
-struct AspeedSCUClass {
- SysBusDeviceClass parent_class;
-
- const uint32_t *resets;
- uint32_t (*calc_hpll)(AspeedSCUState *s, uint32_t hpll_reg);
- uint32_t apb_divider;
- uint32_t nr_regs;
- const MemoryRegionOps *ops;
-};
-
-#define ASPEED_SCU_PROT_KEY 0x1688A8A8
-
-uint32_t aspeed_scu_get_apb_freq(AspeedSCUState *s);
-
-/*
- * Extracted from Aspeed SDK v00.03.21. Fixes and extra definitions
- * were added.
- *
- * Original header file :
- * arch/arm/mach-aspeed/include/mach/regs-scu.h
- *
- * Copyright (C) 2012-2020 ASPEED Technology Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * History :
- * 1. 2012/12/29 Ryan Chen Create
- */
-
-/* SCU08 Clock Selection Register
- *
- * 31 Enable Video Engine clock dynamic slow down
- * 30:28 Video Engine clock slow down setting
- * 27 2D Engine GCLK clock source selection
- * 26 2D Engine GCLK clock throttling enable
- * 25:23 APB PCLK divider selection
- * 22:20 LPC Host LHCLK divider selection
- * 19 LPC Host LHCLK clock generation/output enable control
- * 18:16 MAC AHB bus clock divider selection
- * 15 SD/SDIO clock running enable
- * 14:12 SD/SDIO divider selection
- * 11 Reserved
- * 10:8 Video port output clock delay control bit
- * 7 ARM CPU/AHB clock slow down enable
- * 6:4 ARM CPU/AHB clock slow down setting
- * 3:2 ECLK clock source selection
- * 1 CPU/AHB clock slow down idle timer
- * 0 CPU/AHB clock dynamic slow down enable (defined in bit[6:4])
- */
-#define SCU_CLK_GET_PCLK_DIV(x) (((x) >> 23) & 0x7)
-
-/* SCU24 H-PLL Parameter Register (for Aspeed AST2400 SOC)
- *
- * 18 H-PLL parameter selection
- * 0: Select H-PLL by strapping resistors
- * 1: Select H-PLL by the programmed registers (SCU24[17:0])
- * 17 Enable H-PLL bypass mode
- * 16 Turn off H-PLL
- * 10:5 H-PLL Numerator
- * 4 H-PLL Output Divider
- * 3:0 H-PLL Denumerator
- *
- * (Output frequency) = 24MHz * (2-OD) * [(Numerator+2) / (Denumerator+1)]
- */
-
-#define SCU_AST2400_H_PLL_PROGRAMMED (0x1 << 18)
-#define SCU_AST2400_H_PLL_BYPASS_EN (0x1 << 17)
-#define SCU_AST2400_H_PLL_OFF (0x1 << 16)
-
-/* SCU24 H-PLL Parameter Register (for Aspeed AST2500 SOC)
- *
- * 21 Enable H-PLL reset
- * 20 Enable H-PLL bypass mode
- * 19 Turn off H-PLL
- * 18:13 H-PLL Post Divider
- * 12:5 H-PLL Numerator (M)
- * 4:0 H-PLL Denumerator (N)
- *
- * (Output frequency) = CLKIN(24MHz) * [(M+1) / (N+1)] / (P+1)
- *
- * The default frequency is 792Mhz when CLKIN = 24MHz
- */
-
-#define SCU_H_PLL_BYPASS_EN (0x1 << 20)
-#define SCU_H_PLL_OFF (0x1 << 19)
-
-/* SCU70 Hardware Strapping Register definition (for Aspeed AST2400 SOC)
- *
- * 31:29 Software defined strapping registers
- * 28:27 DRAM size setting (for VGA driver use)
- * 26:24 DRAM configuration setting
- * 23 Enable 25 MHz reference clock input
- * 22 Enable GPIOE pass-through mode
- * 21 Enable GPIOD pass-through mode
- * 20 Disable LPC to decode SuperIO 0x2E/0x4E address
- * 19 Disable ACPI function
- * 23,18 Clock source selection
- * 17 Enable BMC 2nd boot watchdog timer
- * 16 SuperIO configuration address selection
- * 15 VGA Class Code selection
- * 14 Enable LPC dedicated reset pin function
- * 13:12 SPI mode selection
- * 11:10 CPU/AHB clock frequency ratio selection
- * 9:8 H-PLL default clock frequency selection
- * 7 Define MAC#2 interface
- * 6 Define MAC#1 interface
- * 5 Enable VGA BIOS ROM
- * 4 Boot flash memory extended option
- * 3:2 VGA memory size selection
- * 1:0 BMC CPU boot code selection
- */
-#define SCU_AST2400_HW_STRAP_SW_DEFINE(x) ((x) << 29)
-#define SCU_AST2400_HW_STRAP_SW_DEFINE_MASK (0x7 << 29)
-
-#define SCU_AST2400_HW_STRAP_DRAM_SIZE(x) ((x) << 27)
-#define SCU_AST2400_HW_STRAP_DRAM_SIZE_MASK (0x3 << 27)
-#define DRAM_SIZE_64MB 0
-#define DRAM_SIZE_128MB 1
-#define DRAM_SIZE_256MB 2
-#define DRAM_SIZE_512MB 3
-
-#define SCU_AST2400_HW_STRAP_DRAM_CONFIG(x) ((x) << 24)
-#define SCU_AST2400_HW_STRAP_DRAM_CONFIG_MASK (0x7 << 24)
-
-#define SCU_HW_STRAP_GPIOE_PT_EN (0x1 << 22)
-#define SCU_HW_STRAP_GPIOD_PT_EN (0x1 << 21)
-#define SCU_HW_STRAP_LPC_DEC_SUPER_IO (0x1 << 20)
-#define SCU_AST2400_HW_STRAP_ACPI_DIS (0x1 << 19)
-
-/* bit 23, 18 [1,0] */
-#define SCU_AST2400_HW_STRAP_SET_CLK_SOURCE(x) (((((x) & 0x3) >> 1) << 23) \
- | (((x) & 0x1) << 18))
-#define SCU_AST2400_HW_STRAP_GET_CLK_SOURCE(x) (((((x) >> 23) & 0x1) << 1) \
- | (((x) >> 18) & 0x1))
-#define SCU_AST2400_HW_STRAP_CLK_SOURCE_MASK ((0x1 << 23) | (0x1 << 18))
-#define SCU_HW_STRAP_CLK_25M_IN (0x1 << 23)
-#define AST2400_CLK_24M_IN 0
-#define AST2400_CLK_48M_IN 1
-#define AST2400_CLK_25M_IN_24M_USB_CKI 2
-#define AST2400_CLK_25M_IN_48M_USB_CKI 3
-
-#define SCU_HW_STRAP_CLK_48M_IN (0x1 << 18)
-#define SCU_HW_STRAP_2ND_BOOT_WDT (0x1 << 17)
-#define SCU_HW_STRAP_SUPER_IO_CONFIG (0x1 << 16)
-#define SCU_HW_STRAP_VGA_CLASS_CODE (0x1 << 15)
-#define SCU_HW_STRAP_LPC_RESET_PIN (0x1 << 14)
-
-#define SCU_HW_STRAP_SPI_MODE(x) ((x) << 12)
-#define SCU_HW_STRAP_SPI_MODE_MASK (0x3 << 12)
-#define SCU_HW_STRAP_SPI_DIS 0
-#define SCU_HW_STRAP_SPI_MASTER 1
-#define SCU_HW_STRAP_SPI_M_S_EN 2
-#define SCU_HW_STRAP_SPI_PASS_THROUGH 3
-
-#define SCU_AST2400_HW_STRAP_SET_CPU_AHB_RATIO(x) ((x) << 10)
-#define SCU_AST2400_HW_STRAP_GET_CPU_AHB_RATIO(x) (((x) >> 10) & 3)
-#define SCU_AST2400_HW_STRAP_CPU_AHB_RATIO_MASK (0x3 << 10)
-#define AST2400_CPU_AHB_RATIO_1_1 0
-#define AST2400_CPU_AHB_RATIO_2_1 1
-#define AST2400_CPU_AHB_RATIO_4_1 2
-#define AST2400_CPU_AHB_RATIO_3_1 3
-
-#define SCU_AST2400_HW_STRAP_GET_H_PLL_CLK(x) (((x) >> 8) & 0x3)
-#define SCU_AST2400_HW_STRAP_H_PLL_CLK_MASK (0x3 << 8)
-#define AST2400_CPU_384MHZ 0
-#define AST2400_CPU_360MHZ 1
-#define AST2400_CPU_336MHZ 2
-#define AST2400_CPU_408MHZ 3
-
-#define SCU_HW_STRAP_MAC1_RGMII (0x1 << 7)
-#define SCU_HW_STRAP_MAC0_RGMII (0x1 << 6)
-#define SCU_HW_STRAP_VGA_BIOS_ROM (0x1 << 5)
-#define SCU_HW_STRAP_SPI_WIDTH (0x1 << 4)
-
-#define SCU_HW_STRAP_VGA_SIZE_GET(x) (((x) >> 2) & 0x3)
-#define SCU_HW_STRAP_VGA_MASK (0x3 << 2)
-#define SCU_HW_STRAP_VGA_SIZE_SET(x) ((x) << 2)
-#define VGA_8M_DRAM 0
-#define VGA_16M_DRAM 1
-#define VGA_32M_DRAM 2
-#define VGA_64M_DRAM 3
-
-#define SCU_AST2400_HW_STRAP_BOOT_MODE(x) (x)
-#define AST2400_NOR_BOOT 0
-#define AST2400_NAND_BOOT 1
-#define AST2400_SPI_BOOT 2
-#define AST2400_DIS_BOOT 3
-
-/*
- * SCU70 Hardware strapping register definition (for Aspeed AST2500
- * SoC and higher)
- *
- * 31 Enable SPI Flash Strap Auto Fetch Mode
- * 30 Enable GPIO Strap Mode
- * 29 Select UART Debug Port
- * 28 Reserved (1)
- * 27 Enable fast reset mode for ARM ICE debugger
- * 26 Enable eSPI flash mode
- * 25 Enable eSPI mode
- * 24 Select DDR4 SDRAM
- * 23 Select 25 MHz reference clock input mode
- * 22 Enable GPIOE pass-through mode
- * 21 Enable GPIOD pass-through mode
- * 20 Disable LPC to decode SuperIO 0x2E/0x4E address
- * 19 Enable ACPI function
- * 18 Select USBCKI input frequency
- * 17 Enable BMC 2nd boot watchdog timer
- * 16 SuperIO configuration address selection
- * 15 VGA Class Code selection
- * 14 Select dedicated LPC reset input
- * 13:12 SPI mode selection
- * 11:9 AXI/AHB clock frequency ratio selection
- * 8 Reserved (0)
- * 7 Define MAC#2 interface
- * 6 Define MAC#1 interface
- * 5 Enable dedicated VGA BIOS ROM
- * 4 Reserved (0)
- * 3:2 VGA memory size selection
- * 1 Reserved (1)
- * 0 Disable CPU boot
- */
-#define SCU_AST2500_HW_STRAP_SPI_AUTOFETCH_ENABLE (0x1 << 31)
-#define SCU_AST2500_HW_STRAP_GPIO_STRAP_ENABLE (0x1 << 30)
-#define SCU_AST2500_HW_STRAP_UART_DEBUG (0x1 << 29)
-#define UART_DEBUG_UART1 0
-#define UART_DEBUG_UART5 1
-#define SCU_AST2500_HW_STRAP_RESERVED28 (0x1 << 28)
-
-#define SCU_AST2500_HW_STRAP_FAST_RESET_DBG (0x1 << 27)
-#define SCU_AST2500_HW_STRAP_ESPI_FLASH_ENABLE (0x1 << 26)
-#define SCU_AST2500_HW_STRAP_ESPI_ENABLE (0x1 << 25)
-#define SCU_AST2500_HW_STRAP_DDR4_ENABLE (0x1 << 24)
-#define SCU_AST2500_HW_STRAP_25HZ_CLOCK_MODE (0x1 << 23)
-
-#define SCU_AST2500_HW_STRAP_ACPI_ENABLE (0x1 << 19)
-#define SCU_AST2500_HW_STRAP_USBCKI_FREQ (0x1 << 18)
-#define USBCKI_FREQ_24MHZ 0
-#define USBCKI_FREQ_28MHZ 1
-
-#define SCU_AST2500_HW_STRAP_SET_AXI_AHB_RATIO(x) ((x) << 9)
-#define SCU_AST2500_HW_STRAP_GET_AXI_AHB_RATIO(x) (((x) >> 9) & 7)
-#define SCU_AST2500_HW_STRAP_CPU_AXI_RATIO_MASK (0x7 << 9)
-#define AXI_AHB_RATIO_UNDEFINED 0
-#define AXI_AHB_RATIO_2_1 1
-#define AXI_AHB_RATIO_3_1 2
-#define AXI_AHB_RATIO_4_1 3
-#define AXI_AHB_RATIO_5_1 4
-#define AXI_AHB_RATIO_6_1 5
-#define AXI_AHB_RATIO_7_1 6
-#define AXI_AHB_RATIO_8_1 7
-
-#define SCU_AST2500_HW_STRAP_RESERVED1 (0x1 << 1)
-#define SCU_AST2500_HW_STRAP_DIS_BOOT (0x1 << 0)
-
-#define AST2500_HW_STRAP1_DEFAULTS ( \
- SCU_AST2500_HW_STRAP_RESERVED28 | \
- SCU_HW_STRAP_2ND_BOOT_WDT | \
- SCU_HW_STRAP_VGA_CLASS_CODE | \
- SCU_HW_STRAP_LPC_RESET_PIN | \
- SCU_AST2500_HW_STRAP_SET_AXI_AHB_RATIO(AXI_AHB_RATIO_2_1) | \
- SCU_HW_STRAP_VGA_SIZE_SET(VGA_16M_DRAM) | \
- SCU_AST2500_HW_STRAP_RESERVED1)
-
-#endif /* ASPEED_SCU_H */
+++ /dev/null
-/*
- * ASPEED SDRAM Memory Controller
- *
- * Copyright (C) 2016 IBM Corp.
- *
- * This code is licensed under the GPL version 2 or later. See the
- * COPYING file in the top-level directory.
- */
-#ifndef ASPEED_SDMC_H
-#define ASPEED_SDMC_H
-
-#include "hw/sysbus.h"
-#include "qom/object.h"
-
-#define TYPE_ASPEED_SDMC "aspeed.sdmc"
-OBJECT_DECLARE_TYPE(AspeedSDMCState, AspeedSDMCClass, ASPEED_SDMC)
-#define TYPE_ASPEED_2400_SDMC TYPE_ASPEED_SDMC "-ast2400"
-#define TYPE_ASPEED_2500_SDMC TYPE_ASPEED_SDMC "-ast2500"
-#define TYPE_ASPEED_2600_SDMC TYPE_ASPEED_SDMC "-ast2600"
-
-/*
- * SDMC has 174 documented registers. In addition the u-boot device tree
- * describes the following regions:
- * - PHY status regs at offset 0x400, length 0x200
- * - PHY setting regs at offset 0x100, length 0x300
- *
- * There are two sets of MRS (Mode Registers) configuration in ast2600 memory
- * system: one is in the SDRAM MC (memory controller) which is used in run
- * time, and the other is in the DDR-PHY IP which is used during DDR-PHY
- * training.
- */
-#define ASPEED_SDMC_NR_REGS (0x500 >> 2)
-
-struct AspeedSDMCState {
- /*< private >*/
- SysBusDevice parent_obj;
-
- /*< public >*/
- MemoryRegion iomem;
-
- uint32_t regs[ASPEED_SDMC_NR_REGS];
- uint64_t ram_size;
- uint64_t max_ram_size;
-};
-
-
-struct AspeedSDMCClass {
- SysBusDeviceClass parent_class;
-
- uint64_t max_ram_size;
- const uint64_t *valid_ram_sizes;
- uint32_t (*compute_conf)(AspeedSDMCState *s, uint32_t data);
- void (*write)(AspeedSDMCState *s, uint32_t reg, uint32_t data);
-};
-
-#endif /* ASPEED_SDMC_H */
+++ /dev/null
-/*
- * ASPEED XDMA Controller
- * Eddie James <eajames@linux.ibm.com>
- *
- * Copyright (C) 2019 IBM Corp.
- * SPDX-License-Identifer: GPL-2.0-or-later
- */
-
-#ifndef ASPEED_XDMA_H
-#define ASPEED_XDMA_H
-
-#include "hw/sysbus.h"
-#include "qom/object.h"
-
-#define TYPE_ASPEED_XDMA "aspeed.xdma"
-OBJECT_DECLARE_SIMPLE_TYPE(AspeedXDMAState, ASPEED_XDMA)
-
-#define ASPEED_XDMA_NUM_REGS (ASPEED_XDMA_REG_SIZE / sizeof(uint32_t))
-#define ASPEED_XDMA_REG_SIZE 0x7C
-
-struct AspeedXDMAState {
- SysBusDevice parent;
-
- MemoryRegion iomem;
- qemu_irq irq;
-
- char bmc_cmdq_readp_set;
- uint32_t regs[ASPEED_XDMA_NUM_REGS];
-};
-
-#endif /* ASPEED_XDMA_H */
+++ /dev/null
-/*
- * auxbus.h
- *
- * Copyright (C)2014 : GreenSocs Ltd
- * http://www.greensocs.com/ , email: info@greensocs.com
- *
- * Developed by :
- * Frederic Konrad <fred.konrad@greensocs.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation, either version 2 of the License, or
- * (at your option)any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License along
- * with this program; if not, see <http://www.gnu.org/licenses/>.
- *
- */
-
-#ifndef HW_MISC_AUXBUS_H
-#define HW_MISC_AUXBUS_H
-
-#include "exec/memory.h"
-#include "hw/qdev-core.h"
-#include "qom/object.h"
-
-typedef struct AUXSlave AUXSlave;
-typedef enum AUXCommand AUXCommand;
-typedef enum AUXReply AUXReply;
-
-#define TYPE_AUXTOI2C "aux-to-i2c-bridge"
-OBJECT_DECLARE_SIMPLE_TYPE(AUXTOI2CState, AUXTOI2C)
-
-enum AUXCommand {
- WRITE_I2C = 0,
- READ_I2C = 1,
- WRITE_I2C_STATUS = 2,
- WRITE_I2C_MOT = 4,
- READ_I2C_MOT = 5,
- WRITE_AUX = 8,
- READ_AUX = 9
-};
-
-enum AUXReply {
- AUX_I2C_ACK = 0,
- AUX_NACK = 1,
- AUX_DEFER = 2,
- AUX_I2C_NACK = 4,
- AUX_I2C_DEFER = 8
-};
-
-#define TYPE_AUX_BUS "aux-bus"
-OBJECT_DECLARE_SIMPLE_TYPE(AUXBus, AUX_BUS)
-
-struct AUXBus {
- /* < private > */
- BusState qbus;
-
- /* < public > */
- AUXSlave *current_dev;
- AUXSlave *dev;
- uint32_t last_i2c_address;
- AUXCommand last_transaction;
-
- AUXTOI2CState *bridge;
-
- MemoryRegion *aux_io;
- AddressSpace aux_addr_space;
-};
-
-#define TYPE_AUX_SLAVE "aux-slave"
-OBJECT_DECLARE_SIMPLE_TYPE(AUXSlave, AUX_SLAVE)
-
-struct AUXSlave {
- /* < private > */
- DeviceState parent_obj;
-
- /* < public > */
- MemoryRegion *mmio;
-};
-
-/**
- * aux_bus_init: Initialize an AUX bus.
- *
- * Returns the new AUX bus created.
- *
- * @parent The device where this bus is located.
- * @name The name of the bus.
- */
-AUXBus *aux_bus_init(DeviceState *parent, const char *name);
-
-/**
- * aux_bus_realize: Realize an AUX bus.
- *
- * @bus: The AUX bus.
- */
-void aux_bus_realize(AUXBus *bus);
-
-/*
- * aux_request: Make a request on the bus.
- *
- * Returns the reply of the request.
- *
- * @bus Ths bus where the request happen.
- * @cmd The command requested.
- * @address The 20bits address of the slave.
- * @len The length of the read or write.
- * @data The data array which will be filled or read during transfer.
- */
-AUXReply aux_request(AUXBus *bus, AUXCommand cmd, uint32_t address,
- uint8_t len, uint8_t *data);
-
-/*
- * aux_get_i2c_bus: Get the i2c bus for I2C over AUX command.
- *
- * Returns the i2c bus associated to this AUX bus.
- *
- * @bus The AUX bus.
- */
-I2CBus *aux_get_i2c_bus(AUXBus *bus);
-
-/*
- * aux_init_mmio: Init an mmio for an AUX slave.
- *
- * @aux_slave The AUX slave.
- * @mmio The mmio to be registered.
- */
-void aux_init_mmio(AUXSlave *aux_slave, MemoryRegion *mmio);
-
-/* aux_map_slave: Map the mmio for an AUX slave on the bus.
- *
- * @dev The AUX slave.
- * @addr The address for the slave's mmio.
- */
-void aux_map_slave(AUXSlave *dev, hwaddr addr);
-
-#endif /* HW_MISC_AUXBUS_H */
+++ /dev/null
-/*
- * AVR Power Reduction Management
- *
- * Copyright (c) 2019-2020 Michael Rolnik
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
- * furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
- * THE SOFTWARE.
- */
-
-#ifndef HW_MISC_AVR_POWER_H
-#define HW_MISC_AVR_POWER_H
-
-#include "hw/sysbus.h"
-#include "hw/hw.h"
-#include "qom/object.h"
-
-
-#define TYPE_AVR_MASK "avr-power"
-OBJECT_DECLARE_SIMPLE_TYPE(AVRMaskState, AVR_MASK)
-
-struct AVRMaskState {
- /* <private> */
- SysBusDevice parent_obj;
-
- /* <public> */
- MemoryRegion iomem;
-
- uint8_t val;
- qemu_irq irq[8];
-};
-
-#endif /* HW_MISC_AVR_POWER_H */
+++ /dev/null
-/*
- * BCM2835 CPRMAN clock manager
- *
- * Copyright (c) 2020 Luc Michel <luc@lmichel.fr>
- *
- * SPDX-License-Identifier: GPL-2.0-or-later
- */
-
-#ifndef HW_MISC_CPRMAN_H
-#define HW_MISC_CPRMAN_H
-
-#include "hw/sysbus.h"
-#include "hw/qdev-clock.h"
-
-#define TYPE_BCM2835_CPRMAN "bcm2835-cprman"
-
-typedef struct BCM2835CprmanState BCM2835CprmanState;
-
-DECLARE_INSTANCE_CHECKER(BCM2835CprmanState, CPRMAN,
- TYPE_BCM2835_CPRMAN)
-
-#define CPRMAN_NUM_REGS (0x2000 / sizeof(uint32_t))
-
-typedef enum CprmanPll {
- CPRMAN_PLLA = 0,
- CPRMAN_PLLC,
- CPRMAN_PLLD,
- CPRMAN_PLLH,
- CPRMAN_PLLB,
-
- CPRMAN_NUM_PLL
-} CprmanPll;
-
-typedef enum CprmanPllChannel {
- CPRMAN_PLLA_CHANNEL_DSI0 = 0,
- CPRMAN_PLLA_CHANNEL_CORE,
- CPRMAN_PLLA_CHANNEL_PER,
- CPRMAN_PLLA_CHANNEL_CCP2,
-
- CPRMAN_PLLC_CHANNEL_CORE2,
- CPRMAN_PLLC_CHANNEL_CORE1,
- CPRMAN_PLLC_CHANNEL_PER,
- CPRMAN_PLLC_CHANNEL_CORE0,
-
- CPRMAN_PLLD_CHANNEL_DSI0,
- CPRMAN_PLLD_CHANNEL_CORE,
- CPRMAN_PLLD_CHANNEL_PER,
- CPRMAN_PLLD_CHANNEL_DSI1,
-
- CPRMAN_PLLH_CHANNEL_AUX,
- CPRMAN_PLLH_CHANNEL_RCAL,
- CPRMAN_PLLH_CHANNEL_PIX,
-
- CPRMAN_PLLB_CHANNEL_ARM,
-
- CPRMAN_NUM_PLL_CHANNEL,
-
- /* Special values used when connecting clock sources to clocks */
- CPRMAN_CLOCK_SRC_NORMAL = -1,
- CPRMAN_CLOCK_SRC_FORCE_GROUND = -2,
- CPRMAN_CLOCK_SRC_DSI0HSCK = -3,
-} CprmanPllChannel;
-
-typedef enum CprmanClockMux {
- CPRMAN_CLOCK_GNRIC,
- CPRMAN_CLOCK_VPU,
- CPRMAN_CLOCK_SYS,
- CPRMAN_CLOCK_PERIA,
- CPRMAN_CLOCK_PERII,
- CPRMAN_CLOCK_H264,
- CPRMAN_CLOCK_ISP,
- CPRMAN_CLOCK_V3D,
- CPRMAN_CLOCK_CAM0,
- CPRMAN_CLOCK_CAM1,
- CPRMAN_CLOCK_CCP2,
- CPRMAN_CLOCK_DSI0E,
- CPRMAN_CLOCK_DSI0P,
- CPRMAN_CLOCK_DPI,
- CPRMAN_CLOCK_GP0,
- CPRMAN_CLOCK_GP1,
- CPRMAN_CLOCK_GP2,
- CPRMAN_CLOCK_HSM,
- CPRMAN_CLOCK_OTP,
- CPRMAN_CLOCK_PCM,
- CPRMAN_CLOCK_PWM,
- CPRMAN_CLOCK_SLIM,
- CPRMAN_CLOCK_SMI,
- CPRMAN_CLOCK_TEC,
- CPRMAN_CLOCK_TD0,
- CPRMAN_CLOCK_TD1,
- CPRMAN_CLOCK_TSENS,
- CPRMAN_CLOCK_TIMER,
- CPRMAN_CLOCK_UART,
- CPRMAN_CLOCK_VEC,
- CPRMAN_CLOCK_PULSE,
- CPRMAN_CLOCK_SDC,
- CPRMAN_CLOCK_ARM,
- CPRMAN_CLOCK_AVEO,
- CPRMAN_CLOCK_EMMC,
- CPRMAN_CLOCK_EMMC2,
-
- CPRMAN_NUM_CLOCK_MUX
-} CprmanClockMux;
-
-typedef enum CprmanClockMuxSource {
- CPRMAN_CLOCK_SRC_GND = 0,
- CPRMAN_CLOCK_SRC_XOSC,
- CPRMAN_CLOCK_SRC_TD0,
- CPRMAN_CLOCK_SRC_TD1,
- CPRMAN_CLOCK_SRC_PLLA,
- CPRMAN_CLOCK_SRC_PLLC,
- CPRMAN_CLOCK_SRC_PLLD,
- CPRMAN_CLOCK_SRC_PLLH,
- CPRMAN_CLOCK_SRC_PLLC_CORE1,
- CPRMAN_CLOCK_SRC_PLLC_CORE2,
-
- CPRMAN_NUM_CLOCK_MUX_SRC
-} CprmanClockMuxSource;
-
-typedef struct CprmanPllState {
- /*< private >*/
- DeviceState parent_obj;
-
- /*< public >*/
- CprmanPll id;
-
- uint32_t *reg_cm;
- uint32_t *reg_a2w_ctrl;
- uint32_t *reg_a2w_ana; /* ANA[0] .. ANA[3] */
- uint32_t prediv_mask; /* prediv bit in ana[1] */
- uint32_t *reg_a2w_frac;
-
- Clock *xosc_in;
- Clock *out;
-} CprmanPllState;
-
-typedef struct CprmanPllChannelState {
- /*< private >*/
- DeviceState parent_obj;
-
- /*< public >*/
- CprmanPllChannel id;
- CprmanPll parent;
-
- uint32_t *reg_cm;
- uint32_t hold_mask;
- uint32_t load_mask;
- uint32_t *reg_a2w_ctrl;
- int fixed_divider;
-
- Clock *pll_in;
- Clock *out;
-} CprmanPllChannelState;
-
-typedef struct CprmanClockMuxState {
- /*< private >*/
- DeviceState parent_obj;
-
- /*< public >*/
- CprmanClockMux id;
-
- uint32_t *reg_ctl;
- uint32_t *reg_div;
- int int_bits;
- int frac_bits;
-
- Clock *srcs[CPRMAN_NUM_CLOCK_MUX_SRC];
- Clock *out;
-
- /*
- * Used by clock srcs update callback to retrieve both the clock and the
- * source number.
- */
- struct CprmanClockMuxState *backref[CPRMAN_NUM_CLOCK_MUX_SRC];
-} CprmanClockMuxState;
-
-typedef struct CprmanDsi0HsckMuxState {
- /*< private >*/
- DeviceState parent_obj;
-
- /*< public >*/
- CprmanClockMux id;
-
- uint32_t *reg_cm;
-
- Clock *plla_in;
- Clock *plld_in;
- Clock *out;
-} CprmanDsi0HsckMuxState;
-
-struct BCM2835CprmanState {
- /*< private >*/
- SysBusDevice parent_obj;
-
- /*< public >*/
- MemoryRegion iomem;
-
- CprmanPllState plls[CPRMAN_NUM_PLL];
- CprmanPllChannelState channels[CPRMAN_NUM_PLL_CHANNEL];
- CprmanClockMuxState clock_muxes[CPRMAN_NUM_CLOCK_MUX];
- CprmanDsi0HsckMuxState dsi0hsck_mux;
-
- uint32_t regs[CPRMAN_NUM_REGS];
- uint32_t xosc_freq;
-
- Clock *xosc;
- Clock *gnd;
-};
-
-#endif
+++ /dev/null
-/*
- * BCM2835 CPRMAN clock manager
- *
- * Copyright (c) 2020 Luc Michel <luc@lmichel.fr>
- *
- * SPDX-License-Identifier: GPL-2.0-or-later
- */
-
-#ifndef HW_MISC_CPRMAN_INTERNALS_H
-#define HW_MISC_CPRMAN_INTERNALS_H
-
-#include "hw/registerfields.h"
-#include "hw/misc/bcm2835_cprman.h"
-
-#define TYPE_CPRMAN_PLL "bcm2835-cprman-pll"
-#define TYPE_CPRMAN_PLL_CHANNEL "bcm2835-cprman-pll-channel"
-#define TYPE_CPRMAN_CLOCK_MUX "bcm2835-cprman-clock-mux"
-#define TYPE_CPRMAN_DSI0HSCK_MUX "bcm2835-cprman-dsi0hsck-mux"
-
-DECLARE_INSTANCE_CHECKER(CprmanPllState, CPRMAN_PLL,
- TYPE_CPRMAN_PLL)
-DECLARE_INSTANCE_CHECKER(CprmanPllChannelState, CPRMAN_PLL_CHANNEL,
- TYPE_CPRMAN_PLL_CHANNEL)
-DECLARE_INSTANCE_CHECKER(CprmanClockMuxState, CPRMAN_CLOCK_MUX,
- TYPE_CPRMAN_CLOCK_MUX)
-DECLARE_INSTANCE_CHECKER(CprmanDsi0HsckMuxState, CPRMAN_DSI0HSCK_MUX,
- TYPE_CPRMAN_DSI0HSCK_MUX)
-
-/* Register map */
-
-/* PLLs */
-REG32(CM_PLLA, 0x104)
- FIELD(CM_PLLA, LOADDSI0, 0, 1)
- FIELD(CM_PLLA, HOLDDSI0, 1, 1)
- FIELD(CM_PLLA, LOADCCP2, 2, 1)
- FIELD(CM_PLLA, HOLDCCP2, 3, 1)
- FIELD(CM_PLLA, LOADCORE, 4, 1)
- FIELD(CM_PLLA, HOLDCORE, 5, 1)
- FIELD(CM_PLLA, LOADPER, 6, 1)
- FIELD(CM_PLLA, HOLDPER, 7, 1)
- FIELD(CM_PLLx, ANARST, 8, 1)
-REG32(CM_PLLC, 0x108)
- FIELD(CM_PLLC, LOADCORE0, 0, 1)
- FIELD(CM_PLLC, HOLDCORE0, 1, 1)
- FIELD(CM_PLLC, LOADCORE1, 2, 1)
- FIELD(CM_PLLC, HOLDCORE1, 3, 1)
- FIELD(CM_PLLC, LOADCORE2, 4, 1)
- FIELD(CM_PLLC, HOLDCORE2, 5, 1)
- FIELD(CM_PLLC, LOADPER, 6, 1)
- FIELD(CM_PLLC, HOLDPER, 7, 1)
-REG32(CM_PLLD, 0x10c)
- FIELD(CM_PLLD, LOADDSI0, 0, 1)
- FIELD(CM_PLLD, HOLDDSI0, 1, 1)
- FIELD(CM_PLLD, LOADDSI1, 2, 1)
- FIELD(CM_PLLD, HOLDDSI1, 3, 1)
- FIELD(CM_PLLD, LOADCORE, 4, 1)
- FIELD(CM_PLLD, HOLDCORE, 5, 1)
- FIELD(CM_PLLD, LOADPER, 6, 1)
- FIELD(CM_PLLD, HOLDPER, 7, 1)
-REG32(CM_PLLH, 0x110)
- FIELD(CM_PLLH, LOADPIX, 0, 1)
- FIELD(CM_PLLH, LOADAUX, 1, 1)
- FIELD(CM_PLLH, LOADRCAL, 2, 1)
-REG32(CM_PLLB, 0x170)
- FIELD(CM_PLLB, LOADARM, 0, 1)
- FIELD(CM_PLLB, HOLDARM, 1, 1)
-
-REG32(A2W_PLLA_CTRL, 0x1100)
- FIELD(A2W_PLLx_CTRL, NDIV, 0, 10)
- FIELD(A2W_PLLx_CTRL, PDIV, 12, 3)
- FIELD(A2W_PLLx_CTRL, PWRDN, 16, 1)
- FIELD(A2W_PLLx_CTRL, PRST_DISABLE, 17, 1)
-REG32(A2W_PLLC_CTRL, 0x1120)
-REG32(A2W_PLLD_CTRL, 0x1140)
-REG32(A2W_PLLH_CTRL, 0x1160)
-REG32(A2W_PLLB_CTRL, 0x11e0)
-
-REG32(A2W_PLLA_ANA0, 0x1010)
-REG32(A2W_PLLA_ANA1, 0x1014)
- FIELD(A2W_PLLx_ANA1, FB_PREDIV, 14, 1)
-REG32(A2W_PLLA_ANA2, 0x1018)
-REG32(A2W_PLLA_ANA3, 0x101c)
-
-REG32(A2W_PLLC_ANA0, 0x1030)
-REG32(A2W_PLLC_ANA1, 0x1034)
-REG32(A2W_PLLC_ANA2, 0x1038)
-REG32(A2W_PLLC_ANA3, 0x103c)
-
-REG32(A2W_PLLD_ANA0, 0x1050)
-REG32(A2W_PLLD_ANA1, 0x1054)
-REG32(A2W_PLLD_ANA2, 0x1058)
-REG32(A2W_PLLD_ANA3, 0x105c)
-
-REG32(A2W_PLLH_ANA0, 0x1070)
-REG32(A2W_PLLH_ANA1, 0x1074)
- FIELD(A2W_PLLH_ANA1, FB_PREDIV, 11, 1)
-REG32(A2W_PLLH_ANA2, 0x1078)
-REG32(A2W_PLLH_ANA3, 0x107c)
-
-REG32(A2W_PLLB_ANA0, 0x10f0)
-REG32(A2W_PLLB_ANA1, 0x10f4)
-REG32(A2W_PLLB_ANA2, 0x10f8)
-REG32(A2W_PLLB_ANA3, 0x10fc)
-
-REG32(A2W_PLLA_FRAC, 0x1200)
- FIELD(A2W_PLLx_FRAC, FRAC, 0, 20)
-REG32(A2W_PLLC_FRAC, 0x1220)
-REG32(A2W_PLLD_FRAC, 0x1240)
-REG32(A2W_PLLH_FRAC, 0x1260)
-REG32(A2W_PLLB_FRAC, 0x12e0)
-
-/* PLL channels */
-REG32(A2W_PLLA_DSI0, 0x1300)
- FIELD(A2W_PLLx_CHANNELy, DIV, 0, 8)
- FIELD(A2W_PLLx_CHANNELy, DISABLE, 8, 1)
-REG32(A2W_PLLA_CORE, 0x1400)
-REG32(A2W_PLLA_PER, 0x1500)
-REG32(A2W_PLLA_CCP2, 0x1600)
-
-REG32(A2W_PLLC_CORE2, 0x1320)
-REG32(A2W_PLLC_CORE1, 0x1420)
-REG32(A2W_PLLC_PER, 0x1520)
-REG32(A2W_PLLC_CORE0, 0x1620)
-
-REG32(A2W_PLLD_DSI0, 0x1340)
-REG32(A2W_PLLD_CORE, 0x1440)
-REG32(A2W_PLLD_PER, 0x1540)
-REG32(A2W_PLLD_DSI1, 0x1640)
-
-REG32(A2W_PLLH_AUX, 0x1360)
-REG32(A2W_PLLH_RCAL, 0x1460)
-REG32(A2W_PLLH_PIX, 0x1560)
-REG32(A2W_PLLH_STS, 0x1660)
-
-REG32(A2W_PLLB_ARM, 0x13e0)
-
-/* Clock muxes */
-REG32(CM_GNRICCTL, 0x000)
- FIELD(CM_CLOCKx_CTL, SRC, 0, 4)
- FIELD(CM_CLOCKx_CTL, ENABLE, 4, 1)
- FIELD(CM_CLOCKx_CTL, KILL, 5, 1)
- FIELD(CM_CLOCKx_CTL, GATE, 6, 1)
- FIELD(CM_CLOCKx_CTL, BUSY, 7, 1)
- FIELD(CM_CLOCKx_CTL, BUSYD, 8, 1)
- FIELD(CM_CLOCKx_CTL, MASH, 9, 2)
- FIELD(CM_CLOCKx_CTL, FLIP, 11, 1)
-REG32(CM_GNRICDIV, 0x004)
- FIELD(CM_CLOCKx_DIV, FRAC, 0, 12)
-REG32(CM_VPUCTL, 0x008)
-REG32(CM_VPUDIV, 0x00c)
-REG32(CM_SYSCTL, 0x010)
-REG32(CM_SYSDIV, 0x014)
-REG32(CM_PERIACTL, 0x018)
-REG32(CM_PERIADIV, 0x01c)
-REG32(CM_PERIICTL, 0x020)
-REG32(CM_PERIIDIV, 0x024)
-REG32(CM_H264CTL, 0x028)
-REG32(CM_H264DIV, 0x02c)
-REG32(CM_ISPCTL, 0x030)
-REG32(CM_ISPDIV, 0x034)
-REG32(CM_V3DCTL, 0x038)
-REG32(CM_V3DDIV, 0x03c)
-REG32(CM_CAM0CTL, 0x040)
-REG32(CM_CAM0DIV, 0x044)
-REG32(CM_CAM1CTL, 0x048)
-REG32(CM_CAM1DIV, 0x04c)
-REG32(CM_CCP2CTL, 0x050)
-REG32(CM_CCP2DIV, 0x054)
-REG32(CM_DSI0ECTL, 0x058)
-REG32(CM_DSI0EDIV, 0x05c)
-REG32(CM_DSI0PCTL, 0x060)
-REG32(CM_DSI0PDIV, 0x064)
-REG32(CM_DPICTL, 0x068)
-REG32(CM_DPIDIV, 0x06c)
-REG32(CM_GP0CTL, 0x070)
-REG32(CM_GP0DIV, 0x074)
-REG32(CM_GP1CTL, 0x078)
-REG32(CM_GP1DIV, 0x07c)
-REG32(CM_GP2CTL, 0x080)
-REG32(CM_GP2DIV, 0x084)
-REG32(CM_HSMCTL, 0x088)
-REG32(CM_HSMDIV, 0x08c)
-REG32(CM_OTPCTL, 0x090)
-REG32(CM_OTPDIV, 0x094)
-REG32(CM_PCMCTL, 0x098)
-REG32(CM_PCMDIV, 0x09c)
-REG32(CM_PWMCTL, 0x0a0)
-REG32(CM_PWMDIV, 0x0a4)
-REG32(CM_SLIMCTL, 0x0a8)
-REG32(CM_SLIMDIV, 0x0ac)
-REG32(CM_SMICTL, 0x0b0)
-REG32(CM_SMIDIV, 0x0b4)
-REG32(CM_TCNTCTL, 0x0c0)
-REG32(CM_TCNTCNT, 0x0c4)
-REG32(CM_TECCTL, 0x0c8)
-REG32(CM_TECDIV, 0x0cc)
-REG32(CM_TD0CTL, 0x0d0)
-REG32(CM_TD0DIV, 0x0d4)
-REG32(CM_TD1CTL, 0x0d8)
-REG32(CM_TD1DIV, 0x0dc)
-REG32(CM_TSENSCTL, 0x0e0)
-REG32(CM_TSENSDIV, 0x0e4)
-REG32(CM_TIMERCTL, 0x0e8)
-REG32(CM_TIMERDIV, 0x0ec)
-REG32(CM_UARTCTL, 0x0f0)
-REG32(CM_UARTDIV, 0x0f4)
-REG32(CM_VECCTL, 0x0f8)
-REG32(CM_VECDIV, 0x0fc)
-REG32(CM_PULSECTL, 0x190)
-REG32(CM_PULSEDIV, 0x194)
-REG32(CM_SDCCTL, 0x1a8)
-REG32(CM_SDCDIV, 0x1ac)
-REG32(CM_ARMCTL, 0x1b0)
-REG32(CM_AVEOCTL, 0x1b8)
-REG32(CM_AVEODIV, 0x1bc)
-REG32(CM_EMMCCTL, 0x1c0)
-REG32(CM_EMMCDIV, 0x1c4)
-REG32(CM_EMMC2CTL, 0x1d0)
-REG32(CM_EMMC2DIV, 0x1d4)
-
-/* misc registers */
-REG32(CM_LOCK, 0x114)
- FIELD(CM_LOCK, FLOCKH, 12, 1)
- FIELD(CM_LOCK, FLOCKD, 11, 1)
- FIELD(CM_LOCK, FLOCKC, 10, 1)
- FIELD(CM_LOCK, FLOCKB, 9, 1)
- FIELD(CM_LOCK, FLOCKA, 8, 1)
-
-REG32(CM_DSI0HSCK, 0x120)
- FIELD(CM_DSI0HSCK, SELPLLD, 0, 1)
-
-/*
- * This field is common to all registers. Each register write value must match
- * the CPRMAN_PASSWORD magic value in its 8 MSB.
- */
-FIELD(CPRMAN, PASSWORD, 24, 8)
-#define CPRMAN_PASSWORD 0x5a
-
-/* PLL init info */
-typedef struct PLLInitInfo {
- const char *name;
- size_t cm_offset;
- size_t a2w_ctrl_offset;
- size_t a2w_ana_offset;
- uint32_t prediv_mask; /* Prediv bit in ana[1] */
- size_t a2w_frac_offset;
-} PLLInitInfo;
-
-#define FILL_PLL_INIT_INFO(pll_) \
- .cm_offset = R_CM_ ## pll_, \
- .a2w_ctrl_offset = R_A2W_ ## pll_ ## _CTRL, \
- .a2w_ana_offset = R_A2W_ ## pll_ ## _ANA0, \
- .a2w_frac_offset = R_A2W_ ## pll_ ## _FRAC
-
-static const PLLInitInfo PLL_INIT_INFO[] = {
- [CPRMAN_PLLA] = {
- .name = "plla",
- .prediv_mask = R_A2W_PLLx_ANA1_FB_PREDIV_MASK,
- FILL_PLL_INIT_INFO(PLLA),
- },
- [CPRMAN_PLLC] = {
- .name = "pllc",
- .prediv_mask = R_A2W_PLLx_ANA1_FB_PREDIV_MASK,
- FILL_PLL_INIT_INFO(PLLC),
- },
- [CPRMAN_PLLD] = {
- .name = "plld",
- .prediv_mask = R_A2W_PLLx_ANA1_FB_PREDIV_MASK,
- FILL_PLL_INIT_INFO(PLLD),
- },
- [CPRMAN_PLLH] = {
- .name = "pllh",
- .prediv_mask = R_A2W_PLLH_ANA1_FB_PREDIV_MASK,
- FILL_PLL_INIT_INFO(PLLH),
- },
- [CPRMAN_PLLB] = {
- .name = "pllb",
- .prediv_mask = R_A2W_PLLx_ANA1_FB_PREDIV_MASK,
- FILL_PLL_INIT_INFO(PLLB),
- },
-};
-
-#undef FILL_PLL_CHANNEL_INIT_INFO
-
-static inline void set_pll_init_info(BCM2835CprmanState *s,
- CprmanPllState *pll,
- CprmanPll id)
-{
- pll->id = id;
- pll->reg_cm = &s->regs[PLL_INIT_INFO[id].cm_offset];
- pll->reg_a2w_ctrl = &s->regs[PLL_INIT_INFO[id].a2w_ctrl_offset];
- pll->reg_a2w_ana = &s->regs[PLL_INIT_INFO[id].a2w_ana_offset];
- pll->prediv_mask = PLL_INIT_INFO[id].prediv_mask;
- pll->reg_a2w_frac = &s->regs[PLL_INIT_INFO[id].a2w_frac_offset];
-}
-
-
-/* PLL channel init info */
-typedef struct PLLChannelInitInfo {
- const char *name;
- CprmanPll parent;
- size_t cm_offset;
- uint32_t cm_hold_mask;
- uint32_t cm_load_mask;
- size_t a2w_ctrl_offset;
- unsigned int fixed_divider;
-} PLLChannelInitInfo;
-
-#define FILL_PLL_CHANNEL_INIT_INFO_common(pll_, channel_) \
- .parent = CPRMAN_ ## pll_, \
- .cm_offset = R_CM_ ## pll_, \
- .cm_load_mask = R_CM_ ## pll_ ## _ ## LOAD ## channel_ ## _MASK, \
- .a2w_ctrl_offset = R_A2W_ ## pll_ ## _ ## channel_
-
-#define FILL_PLL_CHANNEL_INIT_INFO(pll_, channel_) \
- FILL_PLL_CHANNEL_INIT_INFO_common(pll_, channel_), \
- .cm_hold_mask = R_CM_ ## pll_ ## _ ## HOLD ## channel_ ## _MASK, \
- .fixed_divider = 1
-
-#define FILL_PLL_CHANNEL_INIT_INFO_nohold(pll_, channel_) \
- FILL_PLL_CHANNEL_INIT_INFO_common(pll_, channel_), \
- .cm_hold_mask = 0
-
-static PLLChannelInitInfo PLL_CHANNEL_INIT_INFO[] = {
- [CPRMAN_PLLA_CHANNEL_DSI0] = {
- .name = "plla-dsi0",
- FILL_PLL_CHANNEL_INIT_INFO(PLLA, DSI0),
- },
- [CPRMAN_PLLA_CHANNEL_CORE] = {
- .name = "plla-core",
- FILL_PLL_CHANNEL_INIT_INFO(PLLA, CORE),
- },
- [CPRMAN_PLLA_CHANNEL_PER] = {
- .name = "plla-per",
- FILL_PLL_CHANNEL_INIT_INFO(PLLA, PER),
- },
- [CPRMAN_PLLA_CHANNEL_CCP2] = {
- .name = "plla-ccp2",
- FILL_PLL_CHANNEL_INIT_INFO(PLLA, CCP2),
- },
-
- [CPRMAN_PLLC_CHANNEL_CORE2] = {
- .name = "pllc-core2",
- FILL_PLL_CHANNEL_INIT_INFO(PLLC, CORE2),
- },
- [CPRMAN_PLLC_CHANNEL_CORE1] = {
- .name = "pllc-core1",
- FILL_PLL_CHANNEL_INIT_INFO(PLLC, CORE1),
- },
- [CPRMAN_PLLC_CHANNEL_PER] = {
- .name = "pllc-per",
- FILL_PLL_CHANNEL_INIT_INFO(PLLC, PER),
- },
- [CPRMAN_PLLC_CHANNEL_CORE0] = {
- .name = "pllc-core0",
- FILL_PLL_CHANNEL_INIT_INFO(PLLC, CORE0),
- },
-
- [CPRMAN_PLLD_CHANNEL_DSI0] = {
- .name = "plld-dsi0",
- FILL_PLL_CHANNEL_INIT_INFO(PLLD, DSI0),
- },
- [CPRMAN_PLLD_CHANNEL_CORE] = {
- .name = "plld-core",
- FILL_PLL_CHANNEL_INIT_INFO(PLLD, CORE),
- },
- [CPRMAN_PLLD_CHANNEL_PER] = {
- .name = "plld-per",
- FILL_PLL_CHANNEL_INIT_INFO(PLLD, PER),
- },
- [CPRMAN_PLLD_CHANNEL_DSI1] = {
- .name = "plld-dsi1",
- FILL_PLL_CHANNEL_INIT_INFO(PLLD, DSI1),
- },
-
- [CPRMAN_PLLH_CHANNEL_AUX] = {
- .name = "pllh-aux",
- .fixed_divider = 1,
- FILL_PLL_CHANNEL_INIT_INFO_nohold(PLLH, AUX),
- },
- [CPRMAN_PLLH_CHANNEL_RCAL] = {
- .name = "pllh-rcal",
- .fixed_divider = 10,
- FILL_PLL_CHANNEL_INIT_INFO_nohold(PLLH, RCAL),
- },
- [CPRMAN_PLLH_CHANNEL_PIX] = {
- .name = "pllh-pix",
- .fixed_divider = 10,
- FILL_PLL_CHANNEL_INIT_INFO_nohold(PLLH, PIX),
- },
-
- [CPRMAN_PLLB_CHANNEL_ARM] = {
- .name = "pllb-arm",
- FILL_PLL_CHANNEL_INIT_INFO(PLLB, ARM),
- },
-};
-
-#undef FILL_PLL_CHANNEL_INIT_INFO_nohold
-#undef FILL_PLL_CHANNEL_INIT_INFO
-#undef FILL_PLL_CHANNEL_INIT_INFO_common
-
-static inline void set_pll_channel_init_info(BCM2835CprmanState *s,
- CprmanPllChannelState *channel,
- CprmanPllChannel id)
-{
- channel->id = id;
- channel->parent = PLL_CHANNEL_INIT_INFO[id].parent;
- channel->reg_cm = &s->regs[PLL_CHANNEL_INIT_INFO[id].cm_offset];
- channel->hold_mask = PLL_CHANNEL_INIT_INFO[id].cm_hold_mask;
- channel->load_mask = PLL_CHANNEL_INIT_INFO[id].cm_load_mask;
- channel->reg_a2w_ctrl = &s->regs[PLL_CHANNEL_INIT_INFO[id].a2w_ctrl_offset];
- channel->fixed_divider = PLL_CHANNEL_INIT_INFO[id].fixed_divider;
-}
-
-/* Clock mux init info */
-typedef struct ClockMuxInitInfo {
- const char *name;
- size_t cm_offset; /* cm_offset[0]->CM_CTL, cm_offset[1]->CM_DIV */
- int int_bits;
- int frac_bits;
-
- CprmanPllChannel src_mapping[CPRMAN_NUM_CLOCK_MUX_SRC];
-} ClockMuxInitInfo;
-
-/*
- * Each clock mux can have up to 10 sources. Sources 0 to 3 are always the
- * same (ground, xosc, td0, td1). Sources 4 to 9 are mux specific, and are not
- * always populated. The following macros catch all those cases.
- */
-
-/* Unknown mapping. Connect everything to ground */
-#define SRC_MAPPING_INFO_unknown \
- .src_mapping = { \
- CPRMAN_CLOCK_SRC_FORCE_GROUND, /* gnd */ \
- CPRMAN_CLOCK_SRC_FORCE_GROUND, /* xosc */ \
- CPRMAN_CLOCK_SRC_FORCE_GROUND, /* test debug 0 */ \
- CPRMAN_CLOCK_SRC_FORCE_GROUND, /* test debug 1 */ \
- CPRMAN_CLOCK_SRC_FORCE_GROUND, /* pll a */ \
- CPRMAN_CLOCK_SRC_FORCE_GROUND, /* pll c */ \
- CPRMAN_CLOCK_SRC_FORCE_GROUND, /* pll d */ \
- CPRMAN_CLOCK_SRC_FORCE_GROUND, /* pll h */ \
- CPRMAN_CLOCK_SRC_FORCE_GROUND, /* pll c, core1 */ \
- CPRMAN_CLOCK_SRC_FORCE_GROUND, /* pll c, core2 */ \
- }
-
-/* Only the oscillator and the two test debug clocks */
-#define SRC_MAPPING_INFO_xosc \
- .src_mapping = { \
- CPRMAN_CLOCK_SRC_NORMAL, \
- CPRMAN_CLOCK_SRC_NORMAL, \
- CPRMAN_CLOCK_SRC_NORMAL, \
- CPRMAN_CLOCK_SRC_NORMAL, \
- CPRMAN_CLOCK_SRC_FORCE_GROUND, \
- CPRMAN_CLOCK_SRC_FORCE_GROUND, \
- CPRMAN_CLOCK_SRC_FORCE_GROUND, \
- CPRMAN_CLOCK_SRC_FORCE_GROUND, \
- CPRMAN_CLOCK_SRC_FORCE_GROUND, \
- CPRMAN_CLOCK_SRC_FORCE_GROUND, \
- }
-
-/* All the PLL "core" channels */
-#define SRC_MAPPING_INFO_core \
- .src_mapping = { \
- CPRMAN_CLOCK_SRC_NORMAL, \
- CPRMAN_CLOCK_SRC_NORMAL, \
- CPRMAN_CLOCK_SRC_NORMAL, \
- CPRMAN_CLOCK_SRC_NORMAL, \
- CPRMAN_PLLA_CHANNEL_CORE, \
- CPRMAN_PLLC_CHANNEL_CORE0, \
- CPRMAN_PLLD_CHANNEL_CORE, \
- CPRMAN_PLLH_CHANNEL_AUX, \
- CPRMAN_PLLC_CHANNEL_CORE1, \
- CPRMAN_PLLC_CHANNEL_CORE2, \
- }
-
-/* All the PLL "per" channels */
-#define SRC_MAPPING_INFO_periph \
- .src_mapping = { \
- CPRMAN_CLOCK_SRC_NORMAL, \
- CPRMAN_CLOCK_SRC_NORMAL, \
- CPRMAN_CLOCK_SRC_NORMAL, \
- CPRMAN_CLOCK_SRC_NORMAL, \
- CPRMAN_PLLA_CHANNEL_PER, \
- CPRMAN_PLLC_CHANNEL_PER, \
- CPRMAN_PLLD_CHANNEL_PER, \
- CPRMAN_CLOCK_SRC_FORCE_GROUND, \
- CPRMAN_CLOCK_SRC_FORCE_GROUND, \
- CPRMAN_CLOCK_SRC_FORCE_GROUND, \
- }
-
-/*
- * The DSI0 channels. This one got an intermediate mux between the PLL channels
- * and the clock input.
- */
-#define SRC_MAPPING_INFO_dsi0 \
- .src_mapping = { \
- CPRMAN_CLOCK_SRC_NORMAL, \
- CPRMAN_CLOCK_SRC_NORMAL, \
- CPRMAN_CLOCK_SRC_NORMAL, \
- CPRMAN_CLOCK_SRC_NORMAL, \
- CPRMAN_CLOCK_SRC_DSI0HSCK, \
- CPRMAN_CLOCK_SRC_FORCE_GROUND, \
- CPRMAN_CLOCK_SRC_FORCE_GROUND, \
- CPRMAN_CLOCK_SRC_FORCE_GROUND, \
- CPRMAN_CLOCK_SRC_FORCE_GROUND, \
- CPRMAN_CLOCK_SRC_FORCE_GROUND, \
- }
-
-/* The DSI1 channel */
-#define SRC_MAPPING_INFO_dsi1 \
- .src_mapping = { \
- CPRMAN_CLOCK_SRC_NORMAL, \
- CPRMAN_CLOCK_SRC_NORMAL, \
- CPRMAN_CLOCK_SRC_NORMAL, \
- CPRMAN_CLOCK_SRC_NORMAL, \
- CPRMAN_PLLD_CHANNEL_DSI1, \
- CPRMAN_CLOCK_SRC_FORCE_GROUND, \
- CPRMAN_CLOCK_SRC_FORCE_GROUND, \
- CPRMAN_CLOCK_SRC_FORCE_GROUND, \
- CPRMAN_CLOCK_SRC_FORCE_GROUND, \
- CPRMAN_CLOCK_SRC_FORCE_GROUND, \
- }
-
-#define FILL_CLOCK_MUX_SRC_MAPPING_INIT_INFO(kind_) \
- SRC_MAPPING_INFO_ ## kind_
-
-#define FILL_CLOCK_MUX_INIT_INFO(clock_, kind_) \
- .cm_offset = R_CM_ ## clock_ ## CTL, \
- FILL_CLOCK_MUX_SRC_MAPPING_INIT_INFO(kind_)
-
-static ClockMuxInitInfo CLOCK_MUX_INIT_INFO[] = {
- [CPRMAN_CLOCK_GNRIC] = {
- .name = "gnric",
- FILL_CLOCK_MUX_INIT_INFO(GNRIC, unknown),
- },
- [CPRMAN_CLOCK_VPU] = {
- .name = "vpu",
- .int_bits = 12,
- .frac_bits = 8,
- FILL_CLOCK_MUX_INIT_INFO(VPU, core),
- },
- [CPRMAN_CLOCK_SYS] = {
- .name = "sys",
- FILL_CLOCK_MUX_INIT_INFO(SYS, unknown),
- },
- [CPRMAN_CLOCK_PERIA] = {
- .name = "peria",
- FILL_CLOCK_MUX_INIT_INFO(PERIA, unknown),
- },
- [CPRMAN_CLOCK_PERII] = {
- .name = "perii",
- FILL_CLOCK_MUX_INIT_INFO(PERII, unknown),
- },
- [CPRMAN_CLOCK_H264] = {
- .name = "h264",
- .int_bits = 4,
- .frac_bits = 8,
- FILL_CLOCK_MUX_INIT_INFO(H264, core),
- },
- [CPRMAN_CLOCK_ISP] = {
- .name = "isp",
- .int_bits = 4,
- .frac_bits = 8,
- FILL_CLOCK_MUX_INIT_INFO(ISP, core),
- },
- [CPRMAN_CLOCK_V3D] = {
- .name = "v3d",
- FILL_CLOCK_MUX_INIT_INFO(V3D, core),
- },
- [CPRMAN_CLOCK_CAM0] = {
- .name = "cam0",
- .int_bits = 4,
- .frac_bits = 8,
- FILL_CLOCK_MUX_INIT_INFO(CAM0, periph),
- },
- [CPRMAN_CLOCK_CAM1] = {
- .name = "cam1",
- .int_bits = 4,
- .frac_bits = 8,
- FILL_CLOCK_MUX_INIT_INFO(CAM1, periph),
- },
- [CPRMAN_CLOCK_CCP2] = {
- .name = "ccp2",
- FILL_CLOCK_MUX_INIT_INFO(CCP2, unknown),
- },
- [CPRMAN_CLOCK_DSI0E] = {
- .name = "dsi0e",
- .int_bits = 4,
- .frac_bits = 8,
- FILL_CLOCK_MUX_INIT_INFO(DSI0E, dsi0),
- },
- [CPRMAN_CLOCK_DSI0P] = {
- .name = "dsi0p",
- .int_bits = 0,
- .frac_bits = 0,
- FILL_CLOCK_MUX_INIT_INFO(DSI0P, dsi0),
- },
- [CPRMAN_CLOCK_DPI] = {
- .name = "dpi",
- .int_bits = 4,
- .frac_bits = 8,
- FILL_CLOCK_MUX_INIT_INFO(DPI, periph),
- },
- [CPRMAN_CLOCK_GP0] = {
- .name = "gp0",
- .int_bits = 12,
- .frac_bits = 12,
- FILL_CLOCK_MUX_INIT_INFO(GP0, periph),
- },
- [CPRMAN_CLOCK_GP1] = {
- .name = "gp1",
- .int_bits = 12,
- .frac_bits = 12,
- FILL_CLOCK_MUX_INIT_INFO(GP1, periph),
- },
- [CPRMAN_CLOCK_GP2] = {
- .name = "gp2",
- .int_bits = 12,
- .frac_bits = 12,
- FILL_CLOCK_MUX_INIT_INFO(GP2, periph),
- },
- [CPRMAN_CLOCK_HSM] = {
- .name = "hsm",
- .int_bits = 4,
- .frac_bits = 8,
- FILL_CLOCK_MUX_INIT_INFO(HSM, periph),
- },
- [CPRMAN_CLOCK_OTP] = {
- .name = "otp",
- .int_bits = 4,
- .frac_bits = 0,
- FILL_CLOCK_MUX_INIT_INFO(OTP, xosc),
- },
- [CPRMAN_CLOCK_PCM] = {
- .name = "pcm",
- .int_bits = 12,
- .frac_bits = 12,
- FILL_CLOCK_MUX_INIT_INFO(PCM, periph),
- },
- [CPRMAN_CLOCK_PWM] = {
- .name = "pwm",
- .int_bits = 12,
- .frac_bits = 12,
- FILL_CLOCK_MUX_INIT_INFO(PWM, periph),
- },
- [CPRMAN_CLOCK_SLIM] = {
- .name = "slim",
- .int_bits = 12,
- .frac_bits = 12,
- FILL_CLOCK_MUX_INIT_INFO(SLIM, periph),
- },
- [CPRMAN_CLOCK_SMI] = {
- .name = "smi",
- .int_bits = 4,
- .frac_bits = 8,
- FILL_CLOCK_MUX_INIT_INFO(SMI, periph),
- },
- [CPRMAN_CLOCK_TEC] = {
- .name = "tec",
- .int_bits = 6,
- .frac_bits = 0,
- FILL_CLOCK_MUX_INIT_INFO(TEC, xosc),
- },
- [CPRMAN_CLOCK_TD0] = {
- .name = "td0",
- FILL_CLOCK_MUX_INIT_INFO(TD0, unknown),
- },
- [CPRMAN_CLOCK_TD1] = {
- .name = "td1",
- FILL_CLOCK_MUX_INIT_INFO(TD1, unknown),
- },
- [CPRMAN_CLOCK_TSENS] = {
- .name = "tsens",
- .int_bits = 5,
- .frac_bits = 0,
- FILL_CLOCK_MUX_INIT_INFO(TSENS, xosc),
- },
- [CPRMAN_CLOCK_TIMER] = {
- .name = "timer",
- .int_bits = 6,
- .frac_bits = 12,
- FILL_CLOCK_MUX_INIT_INFO(TIMER, xosc),
- },
- [CPRMAN_CLOCK_UART] = {
- .name = "uart",
- .int_bits = 10,
- .frac_bits = 12,
- FILL_CLOCK_MUX_INIT_INFO(UART, periph),
- },
- [CPRMAN_CLOCK_VEC] = {
- .name = "vec",
- .int_bits = 4,
- .frac_bits = 0,
- FILL_CLOCK_MUX_INIT_INFO(VEC, periph),
- },
- [CPRMAN_CLOCK_PULSE] = {
- .name = "pulse",
- FILL_CLOCK_MUX_INIT_INFO(PULSE, xosc),
- },
- [CPRMAN_CLOCK_SDC] = {
- .name = "sdram",
- .int_bits = 6,
- .frac_bits = 0,
- FILL_CLOCK_MUX_INIT_INFO(SDC, core),
- },
- [CPRMAN_CLOCK_ARM] = {
- .name = "arm",
- FILL_CLOCK_MUX_INIT_INFO(ARM, unknown),
- },
- [CPRMAN_CLOCK_AVEO] = {
- .name = "aveo",
- .int_bits = 4,
- .frac_bits = 0,
- FILL_CLOCK_MUX_INIT_INFO(AVEO, periph),
- },
- [CPRMAN_CLOCK_EMMC] = {
- .name = "emmc",
- .int_bits = 4,
- .frac_bits = 8,
- FILL_CLOCK_MUX_INIT_INFO(EMMC, periph),
- },
- [CPRMAN_CLOCK_EMMC2] = {
- .name = "emmc2",
- .int_bits = 4,
- .frac_bits = 8,
- FILL_CLOCK_MUX_INIT_INFO(EMMC2, unknown),
- },
-};
-
-#undef FILL_CLOCK_MUX_INIT_INFO
-#undef FILL_CLOCK_MUX_SRC_MAPPING_INIT_INFO
-#undef SRC_MAPPING_INFO_dsi1
-#undef SRC_MAPPING_INFO_dsi0
-#undef SRC_MAPPING_INFO_periph
-#undef SRC_MAPPING_INFO_core
-#undef SRC_MAPPING_INFO_xosc
-#undef SRC_MAPPING_INFO_unknown
-
-static inline void set_clock_mux_init_info(BCM2835CprmanState *s,
- CprmanClockMuxState *mux,
- CprmanClockMux id)
-{
- mux->id = id;
- mux->reg_ctl = &s->regs[CLOCK_MUX_INIT_INFO[id].cm_offset];
- mux->reg_div = &s->regs[CLOCK_MUX_INIT_INFO[id].cm_offset + 1];
- mux->int_bits = CLOCK_MUX_INIT_INFO[id].int_bits;
- mux->frac_bits = CLOCK_MUX_INIT_INFO[id].frac_bits;
-}
-
-
-/*
- * Object reset info
- * Those values have been dumped from a Raspberry Pi 3 Model B v1.2 using the
- * clk debugfs interface in Linux.
- */
-typedef struct PLLResetInfo {
- uint32_t cm;
- uint32_t a2w_ctrl;
- uint32_t a2w_ana[4];
- uint32_t a2w_frac;
-} PLLResetInfo;
-
-static const PLLResetInfo PLL_RESET_INFO[] = {
- [CPRMAN_PLLA] = {
- .cm = 0x0000008a,
- .a2w_ctrl = 0x0002103a,
- .a2w_frac = 0x00098000,
- .a2w_ana = { 0x00000000, 0x00144000, 0x00000000, 0x00000100 }
- },
-
- [CPRMAN_PLLC] = {
- .cm = 0x00000228,
- .a2w_ctrl = 0x0002103e,
- .a2w_frac = 0x00080000,
- .a2w_ana = { 0x00000000, 0x00144000, 0x00000000, 0x00000100 }
- },
-
- [CPRMAN_PLLD] = {
- .cm = 0x0000020a,
- .a2w_ctrl = 0x00021034,
- .a2w_frac = 0x00015556,
- .a2w_ana = { 0x00000000, 0x00144000, 0x00000000, 0x00000100 }
- },
-
- [CPRMAN_PLLH] = {
- .cm = 0x00000000,
- .a2w_ctrl = 0x0002102d,
- .a2w_frac = 0x00000000,
- .a2w_ana = { 0x00900000, 0x0000000c, 0x00000000, 0x00000000 }
- },
-
- [CPRMAN_PLLB] = {
- /* unknown */
- .cm = 0x00000000,
- .a2w_ctrl = 0x00000000,
- .a2w_frac = 0x00000000,
- .a2w_ana = { 0x00000000, 0x00000000, 0x00000000, 0x00000000 }
- }
-};
-
-typedef struct PLLChannelResetInfo {
- /*
- * Even though a PLL channel has a CM register, it shares it with its
- * parent PLL. The parent already takes care of the reset value.
- */
- uint32_t a2w_ctrl;
-} PLLChannelResetInfo;
-
-static const PLLChannelResetInfo PLL_CHANNEL_RESET_INFO[] = {
- [CPRMAN_PLLA_CHANNEL_DSI0] = { .a2w_ctrl = 0x00000100 },
- [CPRMAN_PLLA_CHANNEL_CORE] = { .a2w_ctrl = 0x00000003 },
- [CPRMAN_PLLA_CHANNEL_PER] = { .a2w_ctrl = 0x00000000 }, /* unknown */
- [CPRMAN_PLLA_CHANNEL_CCP2] = { .a2w_ctrl = 0x00000100 },
-
- [CPRMAN_PLLC_CHANNEL_CORE2] = { .a2w_ctrl = 0x00000100 },
- [CPRMAN_PLLC_CHANNEL_CORE1] = { .a2w_ctrl = 0x00000100 },
- [CPRMAN_PLLC_CHANNEL_PER] = { .a2w_ctrl = 0x00000002 },
- [CPRMAN_PLLC_CHANNEL_CORE0] = { .a2w_ctrl = 0x00000002 },
-
- [CPRMAN_PLLD_CHANNEL_DSI0] = { .a2w_ctrl = 0x00000100 },
- [CPRMAN_PLLD_CHANNEL_CORE] = { .a2w_ctrl = 0x00000004 },
- [CPRMAN_PLLD_CHANNEL_PER] = { .a2w_ctrl = 0x00000004 },
- [CPRMAN_PLLD_CHANNEL_DSI1] = { .a2w_ctrl = 0x00000100 },
-
- [CPRMAN_PLLH_CHANNEL_AUX] = { .a2w_ctrl = 0x00000004 },
- [CPRMAN_PLLH_CHANNEL_RCAL] = { .a2w_ctrl = 0x00000000 },
- [CPRMAN_PLLH_CHANNEL_PIX] = { .a2w_ctrl = 0x00000000 },
-
- [CPRMAN_PLLB_CHANNEL_ARM] = { .a2w_ctrl = 0x00000000 }, /* unknown */
-};
-
-typedef struct ClockMuxResetInfo {
- uint32_t cm_ctl;
- uint32_t cm_div;
-} ClockMuxResetInfo;
-
-static const ClockMuxResetInfo CLOCK_MUX_RESET_INFO[] = {
- [CPRMAN_CLOCK_GNRIC] = {
- .cm_ctl = 0, /* unknown */
- .cm_div = 0
- },
-
- [CPRMAN_CLOCK_VPU] = {
- .cm_ctl = 0x00000245,
- .cm_div = 0x00003000,
- },
-
- [CPRMAN_CLOCK_SYS] = {
- .cm_ctl = 0, /* unknown */
- .cm_div = 0
- },
-
- [CPRMAN_CLOCK_PERIA] = {
- .cm_ctl = 0, /* unknown */
- .cm_div = 0
- },
-
- [CPRMAN_CLOCK_PERII] = {
- .cm_ctl = 0, /* unknown */
- .cm_div = 0
- },
-
- [CPRMAN_CLOCK_H264] = {
- .cm_ctl = 0x00000244,
- .cm_div = 0x00003000,
- },
-
- [CPRMAN_CLOCK_ISP] = {
- .cm_ctl = 0x00000244,
- .cm_div = 0x00003000,
- },
-
- [CPRMAN_CLOCK_V3D] = {
- .cm_ctl = 0, /* unknown */
- .cm_div = 0
- },
-
- [CPRMAN_CLOCK_CAM0] = {
- .cm_ctl = 0x00000000,
- .cm_div = 0x00000000,
- },
-
- [CPRMAN_CLOCK_CAM1] = {
- .cm_ctl = 0x00000000,
- .cm_div = 0x00000000,
- },
-
- [CPRMAN_CLOCK_CCP2] = {
- .cm_ctl = 0, /* unknown */
- .cm_div = 0
- },
-
- [CPRMAN_CLOCK_DSI0E] = {
- .cm_ctl = 0x00000000,
- .cm_div = 0x00000000,
- },
-
- [CPRMAN_CLOCK_DSI0P] = {
- .cm_ctl = 0x00000000,
- .cm_div = 0x00000000,
- },
-
- [CPRMAN_CLOCK_DPI] = {
- .cm_ctl = 0x00000000,
- .cm_div = 0x00000000,
- },
-
- [CPRMAN_CLOCK_GP0] = {
- .cm_ctl = 0x00000200,
- .cm_div = 0x00000000,
- },
-
- [CPRMAN_CLOCK_GP1] = {
- .cm_ctl = 0x00000096,
- .cm_div = 0x00014000,
- },
-
- [CPRMAN_CLOCK_GP2] = {
- .cm_ctl = 0x00000291,
- .cm_div = 0x00249f00,
- },
-
- [CPRMAN_CLOCK_HSM] = {
- .cm_ctl = 0x00000000,
- .cm_div = 0x00000000,
- },
-
- [CPRMAN_CLOCK_OTP] = {
- .cm_ctl = 0x00000091,
- .cm_div = 0x00004000,
- },
-
- [CPRMAN_CLOCK_PCM] = {
- .cm_ctl = 0x00000200,
- .cm_div = 0x00000000,
- },
-
- [CPRMAN_CLOCK_PWM] = {
- .cm_ctl = 0x00000200,
- .cm_div = 0x00000000,
- },
-
- [CPRMAN_CLOCK_SLIM] = {
- .cm_ctl = 0x00000200,
- .cm_div = 0x00000000,
- },
-
- [CPRMAN_CLOCK_SMI] = {
- .cm_ctl = 0x00000000,
- .cm_div = 0x00000000,
- },
-
- [CPRMAN_CLOCK_TEC] = {
- .cm_ctl = 0x00000000,
- .cm_div = 0x00000000,
- },
-
- [CPRMAN_CLOCK_TD0] = {
- .cm_ctl = 0, /* unknown */
- .cm_div = 0
- },
-
- [CPRMAN_CLOCK_TD1] = {
- .cm_ctl = 0, /* unknown */
- .cm_div = 0
- },
-
- [CPRMAN_CLOCK_TSENS] = {
- .cm_ctl = 0x00000091,
- .cm_div = 0x0000a000,
- },
-
- [CPRMAN_CLOCK_TIMER] = {
- .cm_ctl = 0x00000291,
- .cm_div = 0x00013333,
- },
-
- [CPRMAN_CLOCK_UART] = {
- .cm_ctl = 0x00000296,
- .cm_div = 0x0000a6ab,
- },
-
- [CPRMAN_CLOCK_VEC] = {
- .cm_ctl = 0x00000097,
- .cm_div = 0x00002000,
- },
-
- [CPRMAN_CLOCK_PULSE] = {
- .cm_ctl = 0, /* unknown */
- .cm_div = 0
- },
-
- [CPRMAN_CLOCK_SDC] = {
- .cm_ctl = 0x00004006,
- .cm_div = 0x00003000,
- },
-
- [CPRMAN_CLOCK_ARM] = {
- .cm_ctl = 0, /* unknown */
- .cm_div = 0
- },
-
- [CPRMAN_CLOCK_AVEO] = {
- .cm_ctl = 0x00000000,
- .cm_div = 0x00000000,
- },
-
- [CPRMAN_CLOCK_EMMC] = {
- .cm_ctl = 0x00000295,
- .cm_div = 0x00006000,
- },
-
- [CPRMAN_CLOCK_EMMC2] = {
- .cm_ctl = 0, /* unknown */
- .cm_div = 0
- },
-};
-
-#endif
+++ /dev/null
-/*
- * Raspberry Pi emulation (c) 2012 Gregory Estrade
- *
- * This work is licensed under the terms of the GNU GPL, version 2 or later.
- * See the COPYING file in the top-level directory.
- */
-
-#ifndef BCM2835_MBOX_H
-#define BCM2835_MBOX_H
-
-#include "bcm2835_mbox_defs.h"
-#include "hw/sysbus.h"
-#include "qom/object.h"
-
-#define TYPE_BCM2835_MBOX "bcm2835-mbox"
-OBJECT_DECLARE_SIMPLE_TYPE(BCM2835MboxState, BCM2835_MBOX)
-
-typedef struct {
- uint32_t reg[MBOX_SIZE];
- uint32_t count;
- uint32_t status;
- uint32_t config;
-} BCM2835Mbox;
-
-struct BCM2835MboxState {
- /*< private >*/
- SysBusDevice busdev;
- /*< public >*/
- MemoryRegion *mbox_mr;
- AddressSpace mbox_as;
- MemoryRegion iomem;
- qemu_irq arm_irq;
-
- bool mbox_irq_disabled;
- bool available[MBOX_CHAN_COUNT];
- BCM2835Mbox mbox[2];
-};
-
-#endif
+++ /dev/null
-/*
- * Raspberry Pi emulation (c) 2012 Gregory Estrade
- *
- * This work is licensed under the terms of the GNU GPL, version 2 or later.
- * See the COPYING file in the top-level directory.
- */
-
-#ifndef BCM2835_MBOX_DEFS_H
-#define BCM2835_MBOX_DEFS_H
-
-/* Constants shared with the ARM identifying separate mailbox channels */
-#define MBOX_CHAN_POWER 0 /* for use by the power management interface */
-#define MBOX_CHAN_FB 1 /* for use by the frame buffer */
-#define MBOX_CHAN_VCHIQ 3 /* for use by the VCHIQ interface */
-#define MBOX_CHAN_PROPERTY 8 /* for use by the property channel */
-#define MBOX_CHAN_COUNT 9
-
-#define MBOX_SIZE 32
-#define MBOX_INVALID_DATA 0x0f
-
-/* Layout of the private address space used for communication between
- * the mbox device emulation, and child devices: each channel occupies
- * 16 bytes of address space, but only two registers are presently defined.
- */
-#define MBOX_AS_CHAN_SHIFT 4
-#define MBOX_AS_DATA 0 /* request / response data (RW at offset 0) */
-#define MBOX_AS_PENDING 4 /* pending response status (RO at offset 4) */
-
-#endif /* BCM2835_MBOX_DEFS_H */
+++ /dev/null
-/*
- * BCM2835 SOC MPHI state definitions
- *
- * Copyright (c) 2020 Paul Zimmerman <pauldzim@gmail.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#ifndef HW_MISC_BCM2835_MPHI_H
-#define HW_MISC_BCM2835_MPHI_H
-
-#include "hw/irq.h"
-#include "hw/sysbus.h"
-#include "qom/object.h"
-
-#define MPHI_MMIO_SIZE 0x1000
-
-typedef struct BCM2835MphiState BCM2835MphiState;
-
-struct BCM2835MphiState {
- SysBusDevice parent_obj;
- qemu_irq irq;
- MemoryRegion iomem;
-
- uint32_t outdda;
- uint32_t outddb;
- uint32_t ctrl;
- uint32_t intstat;
- uint32_t swirq;
-};
-
-#define TYPE_BCM2835_MPHI "bcm2835-mphi"
-
-OBJECT_DECLARE_SIMPLE_TYPE(BCM2835MphiState, BCM2835_MPHI)
-
-#endif
+++ /dev/null
-/*
- * Raspberry Pi emulation (c) 2012 Gregory Estrade
- *
- * This work is licensed under the terms of the GNU GPL, version 2 or later.
- * See the COPYING file in the top-level directory.
- */
-
-#ifndef BCM2835_PROPERTY_H
-#define BCM2835_PROPERTY_H
-
-#include "hw/sysbus.h"
-#include "net/net.h"
-#include "hw/display/bcm2835_fb.h"
-#include "qom/object.h"
-
-#define TYPE_BCM2835_PROPERTY "bcm2835-property"
-OBJECT_DECLARE_SIMPLE_TYPE(BCM2835PropertyState, BCM2835_PROPERTY)
-
-struct BCM2835PropertyState {
- /*< private >*/
- SysBusDevice busdev;
- /*< public >*/
-
- MemoryRegion *dma_mr;
- AddressSpace dma_as;
- MemoryRegion iomem;
- qemu_irq mbox_irq;
- BCM2835FBState *fbdev;
-
- MACAddr macaddr;
- uint32_t board_rev;
- uint32_t addr;
- bool pending;
-};
-
-#endif
+++ /dev/null
-/*
- * BCM2835 Random Number Generator emulation
- *
- * Copyright (C) 2017 Marcin Chojnacki <marcinch7@gmail.com>
- *
- * This work is licensed under the terms of the GNU GPL, version 2 or later.
- * See the COPYING file in the top-level directory.
- */
-
-#ifndef BCM2835_RNG_H
-#define BCM2835_RNG_H
-
-#include "hw/sysbus.h"
-#include "qom/object.h"
-
-#define TYPE_BCM2835_RNG "bcm2835-rng"
-OBJECT_DECLARE_SIMPLE_TYPE(BCM2835RngState, BCM2835_RNG)
-
-struct BCM2835RngState {
- SysBusDevice busdev;
- MemoryRegion iomem;
-
- uint32_t rng_ctrl;
- uint32_t rng_status;
-};
-
-#endif
+++ /dev/null
-/*
- * BCM2835 dummy thermal sensor
- *
- * Copyright (C) 2019 Philippe Mathieu-Daudé <f4bug@amsat.org>
- *
- * SPDX-License-Identifier: GPL-2.0-or-later
- */
-
-#ifndef HW_MISC_BCM2835_THERMAL_H
-#define HW_MISC_BCM2835_THERMAL_H
-
-#include "hw/sysbus.h"
-#include "qom/object.h"
-
-#define TYPE_BCM2835_THERMAL "bcm2835-thermal"
-
-OBJECT_DECLARE_SIMPLE_TYPE(Bcm2835ThermalState, BCM2835_THERMAL)
-
-struct Bcm2835ThermalState {
- /*< private >*/
- SysBusDevice parent_obj;
- /*< public >*/
- MemoryRegion iomem;
- uint32_t ctl;
-};
-
-#endif
+++ /dev/null
-/*
- * CBUS three-pin bus and the Retu / Betty / Tahvo / Vilma / Avilma /
- * Hinku / Vinku / Ahne / Pihi chips used in various Nokia platforms.
- * Based on reverse-engineering of a linux driver.
- *
- * Copyright (C) 2008 Nokia Corporation
- * Written by Andrzej Zaborowski
- *
- * This work is licensed under the terms of the GNU GPL, version 2 or later.
- * See the COPYING file in the top-level directory.
- */
-
-#ifndef HW_MISC_CBUS_H
-#define HW_MISC_CBUS_H
-
-
-typedef struct {
- qemu_irq clk;
- qemu_irq dat;
- qemu_irq sel;
-} CBus;
-
-CBus *cbus_init(qemu_irq dat_out);
-void cbus_attach(CBus *bus, void *slave_opaque);
-
-void *retu_init(qemu_irq irq, int vilma);
-void *tahvo_init(qemu_irq irq, int betty);
-
-void retu_key_event(void *retu, int state);
-
-#endif
+++ /dev/null
-/*
- * QEMU Empty Slot
- *
- * The empty_slot device emulates known to a bus but not connected devices.
- *
- * Copyright (c) 2010 Artyom Tarasenko
- *
- * This code is licensed under the GNU GPL v2 or (at your option) any later
- * version.
- */
-
-#ifndef HW_EMPTY_SLOT_H
-#define HW_EMPTY_SLOT_H
-
-#include "exec/hwaddr.h"
-
-void empty_slot_init(const char *name, hwaddr addr, uint64_t slot_size);
-
-#endif
+++ /dev/null
-/*
- * GRLIB AHB APB PNP
- *
- * Copyright (C) 2019 AdaCore
- *
- * Developed by :
- * Frederic Konrad <frederic.konrad@adacore.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation, either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License along
- * with this program; if not, see <http://www.gnu.org/licenses/>.
- *
- */
-
-#ifndef GRLIB_AHB_APB_PNP_H
-#define GRLIB_AHB_APB_PNP_H
-#include "qom/object.h"
-
-#define TYPE_GRLIB_AHB_PNP "grlib,ahbpnp"
-OBJECT_DECLARE_SIMPLE_TYPE(AHBPnp, GRLIB_AHB_PNP)
-
-#define TYPE_GRLIB_APB_PNP "grlib,apbpnp"
-OBJECT_DECLARE_SIMPLE_TYPE(APBPnp, GRLIB_APB_PNP)
-
-void grlib_ahb_pnp_add_entry(AHBPnp *dev, uint32_t address, uint32_t mask,
- uint8_t vendor, uint16_t device, int slave,
- int type);
-void grlib_apb_pnp_add_entry(APBPnp *dev, uint32_t address, uint32_t mask,
- uint8_t vendor, uint16_t device, uint8_t version,
- uint8_t irq, int type);
-
-/* VENDORS */
-#define GRLIB_VENDOR_GAISLER (0x01)
-/* DEVICES */
-#define GRLIB_LEON3_DEV (0x03)
-#define GRLIB_APBMST_DEV (0x06)
-#define GRLIB_APBUART_DEV (0x0C)
-#define GRLIB_IRQMP_DEV (0x0D)
-#define GRLIB_GPTIMER_DEV (0x11)
-/* TYPE */
-#define GRLIB_CPU_AREA (0x00)
-#define GRLIB_APBIO_AREA (0x01)
-#define GRLIB_AHBMEM_AREA (0x02)
-
-#define GRLIB_AHB_MASTER (0x00)
-#define GRLIB_AHB_SLAVE (0x01)
-
-#endif /* GRLIB_AHB_APB_PNP_H */
+++ /dev/null
-/*
- * IMX25 Clock Control Module
- *
- * Copyright (C) 2012 NICTA
- * Updated by Jean-Christophe Dubois <jcd@tribudubois.net>
- *
- * This work is licensed under the terms of the GNU GPL, version 2 or later.
- * See the COPYING file in the top-level directory.
- */
-
-#ifndef IMX25_CCM_H
-#define IMX25_CCM_H
-
-#include "hw/misc/imx_ccm.h"
-#include "qom/object.h"
-
-#define IMX25_CCM_MPCTL_REG 0
-#define IMX25_CCM_UPCTL_REG 1
-#define IMX25_CCM_CCTL_REG 2
-#define IMX25_CCM_CGCR0_REG 3
-#define IMX25_CCM_CGCR1_REG 4
-#define IMX25_CCM_CGCR2_REG 5
-#define IMX25_CCM_PCDR0_REG 6
-#define IMX25_CCM_PCDR1_REG 7
-#define IMX25_CCM_PCDR2_REG 8
-#define IMX25_CCM_PCDR3_REG 9
-#define IMX25_CCM_RCSR_REG 10
-#define IMX25_CCM_CRDR_REG 11
-#define IMX25_CCM_DCVR0_REG 12
-#define IMX25_CCM_DCVR1_REG 13
-#define IMX25_CCM_DCVR2_REG 14
-#define IMX25_CCM_DCVR3_REG 15
-#define IMX25_CCM_LTR0_REG 16
-#define IMX25_CCM_LTR1_REG 17
-#define IMX25_CCM_LTR2_REG 18
-#define IMX25_CCM_LTR3_REG 19
-#define IMX25_CCM_LTBR0_REG 20
-#define IMX25_CCM_LTBR1_REG 21
-#define IMX25_CCM_PMCR0_REG 22
-#define IMX25_CCM_PMCR1_REG 23
-#define IMX25_CCM_PMCR2_REG 24
-#define IMX25_CCM_MCR_REG 25
-#define IMX25_CCM_LPIMR0_REG 26
-#define IMX25_CCM_LPIMR1_REG 27
-#define IMX25_CCM_MAX_REG 28
-
-/* CCTL */
-#define CCTL_ARM_CLK_DIV_SHIFT (30)
-#define CCTL_ARM_CLK_DIV_MASK (0x3)
-#define CCTL_AHB_CLK_DIV_SHIFT (28)
-#define CCTL_AHB_CLK_DIV_MASK (0x3)
-#define CCTL_MPLL_BYPASS_SHIFT (22)
-#define CCTL_MPLL_BYPASS_MASK (0x1)
-#define CCTL_USB_DIV_SHIFT (16)
-#define CCTL_USB_DIV_MASK (0x3F)
-#define CCTL_ARM_SRC_SHIFT (13)
-#define CCTL_ARM_SRC_MASK (0x1)
-#define CCTL_UPLL_DIS_SHIFT (23)
-#define CCTL_UPLL_DIS_MASK (0x1)
-
-#define EXTRACT(value, name) (((value) >> CCTL_##name##_SHIFT) \
- & CCTL_##name##_MASK)
-#define INSERT(value, name) (((value) & CCTL_##name##_MASK) << \
- CCTL_##name##_SHIFT)
-
-#define TYPE_IMX25_CCM "imx25.ccm"
-OBJECT_DECLARE_SIMPLE_TYPE(IMX25CCMState, IMX25_CCM)
-
-struct IMX25CCMState {
- /* <private> */
- IMXCCMState parent_obj;
-
- /* <public> */
- MemoryRegion iomem;
-
- uint32_t reg[IMX25_CCM_MAX_REG];
-
-};
-
-#endif /* IMX25_CCM_H */
+++ /dev/null
-/*
- * IMX31 Clock Control Module
- *
- * Copyright (C) 2012 NICTA
- * Updated by Jean-Christophe Dubois <jcd@tribudubois.net>
- *
- * This work is licensed under the terms of the GNU GPL, version 2 or later.
- * See the COPYING file in the top-level directory.
- */
-
-#ifndef IMX31_CCM_H
-#define IMX31_CCM_H
-
-#include "hw/misc/imx_ccm.h"
-#include "qom/object.h"
-
-#define IMX31_CCM_CCMR_REG 0
-#define IMX31_CCM_PDR0_REG 1
-#define IMX31_CCM_PDR1_REG 2
-#define IMX31_CCM_RCSR_REG 3
-#define IMX31_CCM_MPCTL_REG 4
-#define IMX31_CCM_UPCTL_REG 5
-#define IMX31_CCM_SPCTL_REG 6
-#define IMX31_CCM_COSR_REG 7
-#define IMX31_CCM_CGR0_REG 8
-#define IMX31_CCM_CGR1_REG 9
-#define IMX31_CCM_CGR2_REG 10
-#define IMX31_CCM_WIMR_REG 11
-#define IMX31_CCM_LDC_REG 12
-#define IMX31_CCM_DCVR0_REG 13
-#define IMX31_CCM_DCVR1_REG 14
-#define IMX31_CCM_DCVR2_REG 15
-#define IMX31_CCM_DCVR3_REG 16
-#define IMX31_CCM_LTR0_REG 17
-#define IMX31_CCM_LTR1_REG 18
-#define IMX31_CCM_LTR2_REG 19
-#define IMX31_CCM_LTR3_REG 20
-#define IMX31_CCM_LTBR0_REG 21
-#define IMX31_CCM_LTBR1_REG 22
-#define IMX31_CCM_PMCR0_REG 23
-#define IMX31_CCM_PMCR1_REG 24
-#define IMX31_CCM_PDR2_REG 25
-#define IMX31_CCM_MAX_REG 26
-
-/* CCMR */
-#define CCMR_FPME (1<<0)
-#define CCMR_MPE (1<<3)
-#define CCMR_MDS (1<<7)
-#define CCMR_FPMF (1<<26)
-#define CCMR_PRCS (3<<1)
-
-#define PMCR0_DFSUP1 (1<<31)
-
-/* PDR0 */
-#define PDR0_MCU_PODF_SHIFT (0)
-#define PDR0_MCU_PODF_MASK (0x7)
-#define PDR0_MAX_PODF_SHIFT (3)
-#define PDR0_MAX_PODF_MASK (0x7)
-#define PDR0_IPG_PODF_SHIFT (6)
-#define PDR0_IPG_PODF_MASK (0x3)
-#define PDR0_NFC_PODF_SHIFT (8)
-#define PDR0_NFC_PODF_MASK (0x7)
-#define PDR0_HSP_PODF_SHIFT (11)
-#define PDR0_HSP_PODF_MASK (0x7)
-#define PDR0_PER_PODF_SHIFT (16)
-#define PDR0_PER_PODF_MASK (0x1f)
-#define PDR0_CSI_PODF_SHIFT (23)
-#define PDR0_CSI_PODF_MASK (0x1ff)
-
-#define EXTRACT(value, name) (((value) >> PDR0_##name##_PODF_SHIFT) \
- & PDR0_##name##_PODF_MASK)
-#define INSERT(value, name) (((value) & PDR0_##name##_PODF_MASK) << \
- PDR0_##name##_PODF_SHIFT)
-
-#define TYPE_IMX31_CCM "imx31.ccm"
-OBJECT_DECLARE_SIMPLE_TYPE(IMX31CCMState, IMX31_CCM)
-
-struct IMX31CCMState {
- /* <private> */
- IMXCCMState parent_obj;
-
- /* <public> */
- MemoryRegion iomem;
-
- uint32_t reg[IMX31_CCM_MAX_REG];
-
-};
-
-#endif /* IMX31_CCM_H */
+++ /dev/null
-/*
- * IMX6 Clock Control Module
- *
- * Copyright (C) 2012 NICTA
- * Updated by Jean-Christophe Dubois <jcd@tribudubois.net>
- *
- * This work is licensed under the terms of the GNU GPL, version 2 or later.
- * See the COPYING file in the top-level directory.
- */
-
-#ifndef IMX6_CCM_H
-#define IMX6_CCM_H
-
-#include "hw/misc/imx_ccm.h"
-#include "qemu/bitops.h"
-#include "qom/object.h"
-
-#define CCM_CCR 0
-#define CCM_CCDR 1
-#define CCM_CSR 2
-#define CCM_CCSR 3
-#define CCM_CACRR 4
-#define CCM_CBCDR 5
-#define CCM_CBCMR 6
-#define CCM_CSCMR1 7
-#define CCM_CSCMR2 8
-#define CCM_CSCDR1 9
-#define CCM_CS1CDR 10
-#define CCM_CS2CDR 11
-#define CCM_CDCDR 12
-#define CCM_CHSCCDR 13
-#define CCM_CSCDR2 14
-#define CCM_CSCDR3 15
-#define CCM_CDHIPR 18
-#define CCM_CTOR 20
-#define CCM_CLPCR 21
-#define CCM_CISR 22
-#define CCM_CIMR 23
-#define CCM_CCOSR 24
-#define CCM_CGPR 25
-#define CCM_CCGR0 26
-#define CCM_CCGR1 27
-#define CCM_CCGR2 28
-#define CCM_CCGR3 29
-#define CCM_CCGR4 30
-#define CCM_CCGR5 31
-#define CCM_CCGR6 32
-#define CCM_CMEOR 34
-#define CCM_MAX 35
-
-#define CCM_ANALOG_PLL_ARM 0
-#define CCM_ANALOG_PLL_ARM_SET 1
-#define CCM_ANALOG_PLL_ARM_CLR 2
-#define CCM_ANALOG_PLL_ARM_TOG 3
-#define CCM_ANALOG_PLL_USB1 4
-#define CCM_ANALOG_PLL_USB1_SET 5
-#define CCM_ANALOG_PLL_USB1_CLR 6
-#define CCM_ANALOG_PLL_USB1_TOG 7
-#define CCM_ANALOG_PLL_USB2 8
-#define CCM_ANALOG_PLL_USB2_SET 9
-#define CCM_ANALOG_PLL_USB2_CLR 10
-#define CCM_ANALOG_PLL_USB2_TOG 11
-#define CCM_ANALOG_PLL_SYS 12
-#define CCM_ANALOG_PLL_SYS_SET 13
-#define CCM_ANALOG_PLL_SYS_CLR 14
-#define CCM_ANALOG_PLL_SYS_TOG 15
-#define CCM_ANALOG_PLL_SYS_SS 16
-#define CCM_ANALOG_PLL_SYS_NUM 20
-#define CCM_ANALOG_PLL_SYS_DENOM 24
-#define CCM_ANALOG_PLL_AUDIO 28
-#define CCM_ANALOG_PLL_AUDIO_SET 29
-#define CCM_ANALOG_PLL_AUDIO_CLR 30
-#define CCM_ANALOG_PLL_AUDIO_TOG 31
-#define CCM_ANALOG_PLL_AUDIO_NUM 32
-#define CCM_ANALOG_PLL_AUDIO_DENOM 36
-#define CCM_ANALOG_PLL_VIDEO 40
-#define CCM_ANALOG_PLL_VIDEO_SET 41
-#define CCM_ANALOG_PLL_VIDEO_CLR 42
-#define CCM_ANALOG_PLL_VIDEO_TOG 44
-#define CCM_ANALOG_PLL_VIDEO_NUM 46
-#define CCM_ANALOG_PLL_VIDEO_DENOM 48
-#define CCM_ANALOG_PLL_MLB 52
-#define CCM_ANALOG_PLL_MLB_SET 53
-#define CCM_ANALOG_PLL_MLB_CLR 54
-#define CCM_ANALOG_PLL_MLB_TOG 55
-#define CCM_ANALOG_PLL_ENET 56
-#define CCM_ANALOG_PLL_ENET_SET 57
-#define CCM_ANALOG_PLL_ENET_CLR 58
-#define CCM_ANALOG_PLL_ENET_TOG 59
-#define CCM_ANALOG_PFD_480 60
-#define CCM_ANALOG_PFD_480_SET 61
-#define CCM_ANALOG_PFD_480_CLR 62
-#define CCM_ANALOG_PFD_480_TOG 63
-#define CCM_ANALOG_PFD_528 64
-#define CCM_ANALOG_PFD_528_SET 65
-#define CCM_ANALOG_PFD_528_CLR 66
-#define CCM_ANALOG_PFD_528_TOG 67
-
-/* PMU registers */
-#define PMU_REG_1P1 68
-#define PMU_REG_3P0 72
-#define PMU_REG_2P5 76
-#define PMU_REG_CORE 80
-
-#define CCM_ANALOG_MISC0 84
-#define PMU_MISC0 84
-#define CCM_ANALOG_MISC0_SET 85
-#define CCM_ANALOG_MISC0_CLR 86
-#define CCM_ANALOG_MISC0_TOG 87
-
-#define PMU_MISC1 88
-#define PMU_MISC1_SET 89
-#define PMU_MISC1_CLR 90
-#define PMU_MISC1_TOG 91
-
-#define CCM_ANALOG_MISC2 92
-#define PMU_MISC2 92
-#define CCM_ANALOG_MISC2_SET 93
-#define CCM_ANALOG_MISC2_CLR 94
-#define CCM_ANALOG_MISC2_TOG 95
-
-#define USB_ANALOG_USB1_VBUS_DETECT 104
-#define USB_ANALOG_USB1_VBUS_DETECT_SET 105
-#define USB_ANALOG_USB1_VBUS_DETECT_CLR 106
-#define USB_ANALOG_USB1_VBUS_DETECT_TOG 107
-#define USB_ANALOG_USB1_CHRG_DETECT 108
-#define USB_ANALOG_USB1_CHRG_DETECT_SET 109
-#define USB_ANALOG_USB1_CHRG_DETECT_CLR 110
-#define USB_ANALOG_USB1_CHRG_DETECT_TOG 111
-#define USB_ANALOG_USB1_VBUS_DETECT_STAT 112
-#define USB_ANALOG_USB1_CHRG_DETECT_STAT 116
-#define USB_ANALOG_USB1_MISC 124
-#define USB_ANALOG_USB1_MISC_SET 125
-#define USB_ANALOG_USB1_MISC_CLR 126
-#define USB_ANALOG_USB1_MISC_TOG 127
-#define USB_ANALOG_USB2_VBUS_DETECT 128
-#define USB_ANALOG_USB2_VBUS_DETECT_SET 129
-#define USB_ANALOG_USB2_VBUS_DETECT_CLR 130
-#define USB_ANALOG_USB2_VBUS_DETECT_TOG 131
-#define USB_ANALOG_USB2_CHRG_DETECT 132
-#define USB_ANALOG_USB2_CHRG_DETECT_SET 133
-#define USB_ANALOG_USB2_CHRG_DETECT_CLR 134
-#define USB_ANALOG_USB2_CHRG_DETECT_TOG 135
-#define USB_ANALOG_USB2_VBUS_DETECT_STAT 136
-#define USB_ANALOG_USB2_CHRG_DETECT_STAT 140
-#define USB_ANALOG_USB2_MISC 148
-#define USB_ANALOG_USB2_MISC_SET 149
-#define USB_ANALOG_USB2_MISC_CLR 150
-#define USB_ANALOG_USB2_MISC_TOG 151
-#define USB_ANALOG_DIGPROG 152
-#define CCM_ANALOG_MAX 153
-
-/* CCM_CBCMR */
-#define PRE_PERIPH_CLK_SEL_SHIFT (18)
-#define PRE_PERIPH_CLK_SEL_LENGTH (2)
-
-/* CCM_CBCDR */
-#define AHB_PODF_SHIFT (10)
-#define AHB_PODF_LENGTH (3)
-#define IPG_PODF_SHIFT (8)
-#define IPG_PODF_LENGTH (2)
-
-/* CCM_CSCMR1 */
-#define PERCLK_PODF_SHIFT (0)
-#define PERCLK_PODF_LENGTH (6)
-
-/* CCM_ANALOG_PFD_528 */
-#define PFD0_FRAC_SHIFT (0)
-#define PFD0_FRAC_LENGTH (6)
-#define PFD2_FRAC_SHIFT (16)
-#define PFD2_FRAC_LENGTH (6)
-
-/* CCM_ANALOG_PLL_SYS */
-#define DIV_SELECT_SHIFT (0)
-#define DIV_SELECT_LENGTH (1)
-
-#define CCM_ANALOG_PLL_LOCK (1 << 31);
-
-#define EXTRACT(value, name) extract32(value, name##_SHIFT, name##_LENGTH)
-
-#define TYPE_IMX6_CCM "imx6.ccm"
-OBJECT_DECLARE_SIMPLE_TYPE(IMX6CCMState, IMX6_CCM)
-
-struct IMX6CCMState {
- /* <private> */
- IMXCCMState parent_obj;
-
- /* <public> */
- MemoryRegion container;
- MemoryRegion ioccm;
- MemoryRegion ioanalog;
-
- uint32_t ccm[CCM_MAX];
- uint32_t analog[CCM_ANALOG_MAX];
-
-};
-
-#endif /* IMX6_CCM_H */
+++ /dev/null
-/*
- * IMX6 System Reset Controller
- *
- * Copyright (C) 2012 NICTA
- * Updated by Jean-Christophe Dubois <jcd@tribudubois.net>
- *
- * This work is licensed under the terms of the GNU GPL, version 2 or later.
- * See the COPYING file in the top-level directory.
- */
-
-#ifndef IMX6_SRC_H
-#define IMX6_SRC_H
-
-#include "hw/sysbus.h"
-#include "qemu/bitops.h"
-#include "qom/object.h"
-
-#define SRC_SCR 0
-#define SRC_SBMR1 1
-#define SRC_SRSR 2
-#define SRC_SISR 5
-#define SRC_SIMR 6
-#define SRC_SBMR2 7
-#define SRC_GPR1 8
-#define SRC_GPR2 9
-#define SRC_GPR3 10
-#define SRC_GPR4 11
-#define SRC_GPR5 12
-#define SRC_GPR6 13
-#define SRC_GPR7 14
-#define SRC_GPR8 15
-#define SRC_GPR9 16
-#define SRC_GPR10 17
-#define SRC_MAX 18
-
-/* SRC_SCR */
-#define CORE3_ENABLE_SHIFT 24
-#define CORE3_ENABLE_LENGTH 1
-#define CORE2_ENABLE_SHIFT 23
-#define CORE2_ENABLE_LENGTH 1
-#define CORE1_ENABLE_SHIFT 22
-#define CORE1_ENABLE_LENGTH 1
-#define CORE3_RST_SHIFT 16
-#define CORE3_RST_LENGTH 1
-#define CORE2_RST_SHIFT 15
-#define CORE2_RST_LENGTH 1
-#define CORE1_RST_SHIFT 14
-#define CORE1_RST_LENGTH 1
-#define CORE0_RST_SHIFT 13
-#define CORE0_RST_LENGTH 1
-#define SW_IPU1_RST_SHIFT 3
-#define SW_IPU1_RST_LENGTH 1
-#define SW_IPU2_RST_SHIFT 12
-#define SW_IPU2_RST_LENGTH 1
-#define WARM_RST_ENABLE_SHIFT 0
-#define WARM_RST_ENABLE_LENGTH 1
-
-#define EXTRACT(value, name) extract32(value, name##_SHIFT, name##_LENGTH)
-
-#define TYPE_IMX6_SRC "imx6.src"
-OBJECT_DECLARE_SIMPLE_TYPE(IMX6SRCState, IMX6_SRC)
-
-struct IMX6SRCState {
- /* <private> */
- SysBusDevice parent_obj;
-
- /* <public> */
- MemoryRegion iomem;
-
- uint32_t regs[SRC_MAX];
-
-};
-
-#endif /* IMX6_SRC_H */
+++ /dev/null
-/*
- * IMX6UL Clock Control Module
- *
- * Copyright (C) 2018 by Jean-Christophe Dubois <jcd@tribudubois.net>
- *
- * This work is licensed under the terms of the GNU GPL, version 2 or later.
- * See the COPYING file in the top-level directory.
- */
-
-#ifndef IMX6UL_CCM_H
-#define IMX6UL_CCM_H
-
-#include "hw/misc/imx_ccm.h"
-#include "qemu/bitops.h"
-#include "qom/object.h"
-
-#define CCM_CCR 0
-#define CCM_CCDR 1
-#define CCM_CSR 2
-#define CCM_CCSR 3
-#define CCM_CACRR 4
-#define CCM_CBCDR 5
-#define CCM_CBCMR 6
-#define CCM_CSCMR1 7
-#define CCM_CSCMR2 8
-#define CCM_CSCDR1 9
-#define CCM_CS1CDR 10
-#define CCM_CS2CDR 11
-#define CCM_CDCDR 12
-#define CCM_CHSCCDR 13
-#define CCM_CSCDR2 14
-#define CCM_CSCDR3 15
-#define CCM_CDHIPR 18
-#define CCM_CTOR 20
-#define CCM_CLPCR 21
-#define CCM_CISR 22
-#define CCM_CIMR 23
-#define CCM_CCOSR 24
-#define CCM_CGPR 25
-#define CCM_CCGR0 26
-#define CCM_CCGR1 27
-#define CCM_CCGR2 28
-#define CCM_CCGR3 29
-#define CCM_CCGR4 30
-#define CCM_CCGR5 31
-#define CCM_CCGR6 32
-#define CCM_CMEOR 34
-#define CCM_MAX 35
-
-#define CCM_ANALOG_PLL_ARM 0
-#define CCM_ANALOG_PLL_ARM_SET 1
-#define CCM_ANALOG_PLL_ARM_CLR 2
-#define CCM_ANALOG_PLL_ARM_TOG 3
-#define CCM_ANALOG_PLL_USB1 4
-#define CCM_ANALOG_PLL_USB1_SET 5
-#define CCM_ANALOG_PLL_USB1_CLR 6
-#define CCM_ANALOG_PLL_USB1_TOG 7
-#define CCM_ANALOG_PLL_USB2 8
-#define CCM_ANALOG_PLL_USB2_SET 9
-#define CCM_ANALOG_PLL_USB2_CLR 10
-#define CCM_ANALOG_PLL_USB2_TOG 11
-#define CCM_ANALOG_PLL_SYS 12
-#define CCM_ANALOG_PLL_SYS_SET 13
-#define CCM_ANALOG_PLL_SYS_CLR 14
-#define CCM_ANALOG_PLL_SYS_TOG 15
-#define CCM_ANALOG_PLL_SYS_SS 16
-#define CCM_ANALOG_PLL_SYS_NUM 20
-#define CCM_ANALOG_PLL_SYS_DENOM 24
-#define CCM_ANALOG_PLL_AUDIO 28
-#define CCM_ANALOG_PLL_AUDIO_SET 29
-#define CCM_ANALOG_PLL_AUDIO_CLR 30
-#define CCM_ANALOG_PLL_AUDIO_TOG 31
-#define CCM_ANALOG_PLL_AUDIO_NUM 32
-#define CCM_ANALOG_PLL_AUDIO_DENOM 36
-#define CCM_ANALOG_PLL_VIDEO 40
-#define CCM_ANALOG_PLL_VIDEO_SET 41
-#define CCM_ANALOG_PLL_VIDEO_CLR 42
-#define CCM_ANALOG_PLL_VIDEO_TOG 44
-#define CCM_ANALOG_PLL_VIDEO_NUM 46
-#define CCM_ANALOG_PLL_VIDEO_DENOM 48
-#define CCM_ANALOG_PLL_ENET 56
-#define CCM_ANALOG_PLL_ENET_SET 57
-#define CCM_ANALOG_PLL_ENET_CLR 58
-#define CCM_ANALOG_PLL_ENET_TOG 59
-#define CCM_ANALOG_PFD_480 60
-#define CCM_ANALOG_PFD_480_SET 61
-#define CCM_ANALOG_PFD_480_CLR 62
-#define CCM_ANALOG_PFD_480_TOG 63
-#define CCM_ANALOG_PFD_528 64
-#define CCM_ANALOG_PFD_528_SET 65
-#define CCM_ANALOG_PFD_528_CLR 66
-#define CCM_ANALOG_PFD_528_TOG 67
-
-/* PMU registers */
-#define PMU_REG_1P1 68
-#define PMU_REG_3P0 72
-#define PMU_REG_2P5 76
-#define PMU_REG_CORE 80
-
-#define CCM_ANALOG_MISC0 84
-#define PMU_MISC0 CCM_ANALOG_MISC0
-#define CCM_ANALOG_MISC0_SET 85
-#define PMU_MISC0_SET CCM_ANALOG_MISC0_SET
-#define CCM_ANALOG_MISC0_CLR 86
-#define PMU_MISC0_CLR CCM_ANALOG_MISC0_CLR
-#define CCM_ANALOG_MISC0_TOG 87
-#define PMU_MISC0_TOG CCM_ANALOG_MISC0_TOG
-
-#define CCM_ANALOG_MISC1 88
-#define PMU_MISC1 CCM_ANALOG_MISC1
-#define CCM_ANALOG_MISC1_SET 89
-#define PMU_MISC1_SET CCM_ANALOG_MISC1_SET
-#define CCM_ANALOG_MISC1_CLR 90
-#define PMU_MISC1_CLR CCM_ANALOG_MISC1_CLR
-#define CCM_ANALOG_MISC1_TOG 91
-#define PMU_MISC1_TOG CCM_ANALOG_MISC1_TOG
-
-#define CCM_ANALOG_MISC2 92
-#define PMU_MISC2 CCM_ANALOG_MISC2
-#define CCM_ANALOG_MISC2_SET 93
-#define PMU_MISC2_SET CCM_ANALOG_MISC2_SET
-#define CCM_ANALOG_MISC2_CLR 94
-#define PMU_MISC2_CLR CCM_ANALOG_MISC2_CLR
-#define CCM_ANALOG_MISC2_TOG 95
-#define PMU_MISC2_TOG CCM_ANALOG_MISC2_TOG
-
-#define TEMPMON_TEMPSENSE0 96
-#define TEMPMON_TEMPSENSE0_SET 97
-#define TEMPMON_TEMPSENSE0_CLR 98
-#define TEMPMON_TEMPSENSE0_TOG 99
-#define TEMPMON_TEMPSENSE1 100
-#define TEMPMON_TEMPSENSE1_SET 101
-#define TEMPMON_TEMPSENSE1_CLR 102
-#define TEMPMON_TEMPSENSE1_TOG 103
-#define TEMPMON_TEMPSENSE2 164
-#define TEMPMON_TEMPSENSE2_SET 165
-#define TEMPMON_TEMPSENSE2_CLR 166
-#define TEMPMON_TEMPSENSE2_TOG 167
-
-#define PMU_LOWPWR_CTRL 155
-#define PMU_LOWPWR_CTRL_SET 156
-#define PMU_LOWPWR_CTRL_CLR 157
-#define PMU_LOWPWR_CTRL_TOG 158
-
-#define USB_ANALOG_USB1_VBUS_DETECT 104
-#define USB_ANALOG_USB1_VBUS_DETECT_SET 105
-#define USB_ANALOG_USB1_VBUS_DETECT_CLR 106
-#define USB_ANALOG_USB1_VBUS_DETECT_TOG 107
-#define USB_ANALOG_USB1_CHRG_DETECT 108
-#define USB_ANALOG_USB1_CHRG_DETECT_SET 109
-#define USB_ANALOG_USB1_CHRG_DETECT_CLR 110
-#define USB_ANALOG_USB1_CHRG_DETECT_TOG 111
-#define USB_ANALOG_USB1_VBUS_DETECT_STAT 112
-#define USB_ANALOG_USB1_CHRG_DETECT_STAT 116
-#define USB_ANALOG_USB1_MISC 124
-#define USB_ANALOG_USB1_MISC_SET 125
-#define USB_ANALOG_USB1_MISC_CLR 126
-#define USB_ANALOG_USB1_MISC_TOG 127
-#define USB_ANALOG_USB2_VBUS_DETECT 128
-#define USB_ANALOG_USB2_VBUS_DETECT_SET 129
-#define USB_ANALOG_USB2_VBUS_DETECT_CLR 130
-#define USB_ANALOG_USB2_VBUS_DETECT_TOG 131
-#define USB_ANALOG_USB2_CHRG_DETECT 132
-#define USB_ANALOG_USB2_CHRG_DETECT_SET 133
-#define USB_ANALOG_USB2_CHRG_DETECT_CLR 134
-#define USB_ANALOG_USB2_CHRG_DETECT_TOG 135
-#define USB_ANALOG_USB2_VBUS_DETECT_STAT 136
-#define USB_ANALOG_USB2_CHRG_DETECT_STAT 140
-#define USB_ANALOG_USB2_MISC 148
-#define USB_ANALOG_USB2_MISC_SET 149
-#define USB_ANALOG_USB2_MISC_CLR 150
-#define USB_ANALOG_USB2_MISC_TOG 151
-#define USB_ANALOG_DIGPROG 152
-#define CCM_ANALOG_MAX 4096
-
-/* CCM_CBCMR */
-#define R_CBCMR_PRE_PERIPH_CLK_SEL_SHIFT (18)
-#define R_CBCMR_PRE_PERIPH_CLK_SEL_LENGTH (2)
-#define R_CBCMR_PERIPH_CLK2_SEL_SHIFT (12)
-#define R_CBCMR_PERIPH_CLK2_SEL_LENGTH (2)
-
-/* CCM_CBCDR */
-#define R_CBCDR_AHB_PODF_SHIFT (10)
-#define R_CBCDR_AHB_PODF_LENGTH (3)
-#define R_CBCDR_IPG_PODF_SHIFT (8)
-#define R_CBCDR_IPG_PODF_LENGTH (2)
-#define R_CBCDR_PERIPH_CLK_SEL_SHIFT (25)
-#define R_CBCDR_PERIPH_CLK_SEL_LENGTH (1)
-#define R_CBCDR_PERIPH_CLK2_PODF_SHIFT (27)
-#define R_CBCDR_PERIPH_CLK2_PODF_LENGTH (3)
-
-/* CCM_CSCMR1 */
-#define R_CSCMR1_PERCLK_PODF_SHIFT (0)
-#define R_CSCMR1_PERCLK_PODF_LENGTH (6)
-#define R_CSCMR1_PERCLK_CLK_SEL_SHIFT (6)
-#define R_CSCMR1_PERCLK_CLK_SEL_LENGTH (1)
-
-/* CCM_ANALOG_PFD_528 */
-#define R_ANALOG_PFD_528_PFD0_FRAC_SHIFT (0)
-#define R_ANALOG_PFD_528_PFD0_FRAC_LENGTH (6)
-#define R_ANALOG_PFD_528_PFD2_FRAC_SHIFT (16)
-#define R_ANALOG_PFD_528_PFD2_FRAC_LENGTH (6)
-
-/* CCM_ANALOG_PLL_SYS */
-#define R_ANALOG_PLL_SYS_DIV_SELECT_SHIFT (0)
-#define R_ANALOG_PLL_SYS_DIV_SELECT_LENGTH (1)
-
-#define CCM_ANALOG_PLL_LOCK (1 << 31);
-
-#define TYPE_IMX6UL_CCM "imx6ul.ccm"
-OBJECT_DECLARE_SIMPLE_TYPE(IMX6ULCCMState, IMX6UL_CCM)
-
-struct IMX6ULCCMState {
- /* <private> */
- IMXCCMState parent_obj;
-
- /* <public> */
- MemoryRegion container;
- MemoryRegion ioccm;
- MemoryRegion ioanalog;
-
- uint32_t ccm[CCM_MAX];
- uint32_t analog[CCM_ANALOG_MAX];
-
-};
-
-#endif /* IMX6UL_CCM_H */
+++ /dev/null
-/*
- * Copyright (c) 2017, Impinj, Inc.
- *
- * i.MX7 CCM, PMU and ANALOG IP blocks emulation code
- *
- * Author: Andrey Smirnov <andrew.smirnov@gmail.com>
- *
- * This work is licensed under the terms of the GNU GPL, version 2 or later.
- * See the COPYING file in the top-level directory.
- */
-
-#ifndef IMX7_CCM_H
-#define IMX7_CCM_H
-
-#include "hw/misc/imx_ccm.h"
-#include "qemu/bitops.h"
-#include "qom/object.h"
-
-enum IMX7AnalogRegisters {
- ANALOG_PLL_ARM,
- ANALOG_PLL_ARM_SET,
- ANALOG_PLL_ARM_CLR,
- ANALOG_PLL_ARM_TOG,
- ANALOG_PLL_DDR,
- ANALOG_PLL_DDR_SET,
- ANALOG_PLL_DDR_CLR,
- ANALOG_PLL_DDR_TOG,
- ANALOG_PLL_DDR_SS,
- ANALOG_PLL_DDR_SS_SET,
- ANALOG_PLL_DDR_SS_CLR,
- ANALOG_PLL_DDR_SS_TOG,
- ANALOG_PLL_DDR_NUM,
- ANALOG_PLL_DDR_NUM_SET,
- ANALOG_PLL_DDR_NUM_CLR,
- ANALOG_PLL_DDR_NUM_TOG,
- ANALOG_PLL_DDR_DENOM,
- ANALOG_PLL_DDR_DENOM_SET,
- ANALOG_PLL_DDR_DENOM_CLR,
- ANALOG_PLL_DDR_DENOM_TOG,
- ANALOG_PLL_480,
- ANALOG_PLL_480_SET,
- ANALOG_PLL_480_CLR,
- ANALOG_PLL_480_TOG,
- ANALOG_PLL_480A,
- ANALOG_PLL_480A_SET,
- ANALOG_PLL_480A_CLR,
- ANALOG_PLL_480A_TOG,
- ANALOG_PLL_480B,
- ANALOG_PLL_480B_SET,
- ANALOG_PLL_480B_CLR,
- ANALOG_PLL_480B_TOG,
- ANALOG_PLL_ENET,
- ANALOG_PLL_ENET_SET,
- ANALOG_PLL_ENET_CLR,
- ANALOG_PLL_ENET_TOG,
- ANALOG_PLL_AUDIO,
- ANALOG_PLL_AUDIO_SET,
- ANALOG_PLL_AUDIO_CLR,
- ANALOG_PLL_AUDIO_TOG,
- ANALOG_PLL_AUDIO_SS,
- ANALOG_PLL_AUDIO_SS_SET,
- ANALOG_PLL_AUDIO_SS_CLR,
- ANALOG_PLL_AUDIO_SS_TOG,
- ANALOG_PLL_AUDIO_NUM,
- ANALOG_PLL_AUDIO_NUM_SET,
- ANALOG_PLL_AUDIO_NUM_CLR,
- ANALOG_PLL_AUDIO_NUM_TOG,
- ANALOG_PLL_AUDIO_DENOM,
- ANALOG_PLL_AUDIO_DENOM_SET,
- ANALOG_PLL_AUDIO_DENOM_CLR,
- ANALOG_PLL_AUDIO_DENOM_TOG,
- ANALOG_PLL_VIDEO,
- ANALOG_PLL_VIDEO_SET,
- ANALOG_PLL_VIDEO_CLR,
- ANALOG_PLL_VIDEO_TOG,
- ANALOG_PLL_VIDEO_SS,
- ANALOG_PLL_VIDEO_SS_SET,
- ANALOG_PLL_VIDEO_SS_CLR,
- ANALOG_PLL_VIDEO_SS_TOG,
- ANALOG_PLL_VIDEO_NUM,
- ANALOG_PLL_VIDEO_NUM_SET,
- ANALOG_PLL_VIDEO_NUM_CLR,
- ANALOG_PLL_VIDEO_NUM_TOG,
- ANALOG_PLL_VIDEO_DENOM,
- ANALOG_PLL_VIDEO_DENOM_SET,
- ANALOG_PLL_VIDEO_DENOM_CLR,
- ANALOG_PLL_VIDEO_DENOM_TOG,
- ANALOG_PLL_MISC0,
- ANALOG_PLL_MISC0_SET,
- ANALOG_PLL_MISC0_CLR,
- ANALOG_PLL_MISC0_TOG,
-
- ANALOG_DIGPROG = 0x800 / sizeof(uint32_t),
- ANALOG_MAX,
-
- ANALOG_PLL_LOCK = BIT(31)
-};
-
-enum IMX7CCMRegisters {
- CCM_MAX = 0xBE00 / sizeof(uint32_t) + 1,
-};
-
-enum IMX7PMURegisters {
- PMU_MAX = 0x140 / sizeof(uint32_t),
-};
-
-#define TYPE_IMX7_CCM "imx7.ccm"
-OBJECT_DECLARE_SIMPLE_TYPE(IMX7CCMState, IMX7_CCM)
-
-struct IMX7CCMState {
- /* <private> */
- IMXCCMState parent_obj;
-
- /* <public> */
- MemoryRegion iomem;
-
- uint32_t ccm[CCM_MAX];
-};
-
-
-#define TYPE_IMX7_ANALOG "imx7.analog"
-OBJECT_DECLARE_SIMPLE_TYPE(IMX7AnalogState, IMX7_ANALOG)
-
-struct IMX7AnalogState {
- /* <private> */
- IMXCCMState parent_obj;
-
- /* <public> */
- struct {
- MemoryRegion container;
- MemoryRegion analog;
- MemoryRegion digprog;
- MemoryRegion pmu;
- } mmio;
-
- uint32_t analog[ANALOG_MAX];
- uint32_t pmu[PMU_MAX];
-};
-
-#endif /* IMX7_CCM_H */
+++ /dev/null
-/*
- * Copyright (c) 2017, Impinj, Inc.
- *
- * i.MX7 GPR IP block emulation code
- *
- * Author: Andrey Smirnov <andrew.smirnov@gmail.com>
- *
- * This work is licensed under the terms of the GNU GPL, version 2 or later.
- * See the COPYING file in the top-level directory.
- */
-
-#ifndef IMX7_GPR_H
-#define IMX7_GPR_H
-
-#include "qemu/bitops.h"
-#include "hw/sysbus.h"
-#include "qom/object.h"
-
-#define TYPE_IMX7_GPR "imx7.gpr"
-OBJECT_DECLARE_SIMPLE_TYPE(IMX7GPRState, IMX7_GPR)
-
-struct IMX7GPRState {
- /* <private> */
- SysBusDevice parent_obj;
-
- MemoryRegion mmio;
-};
-
-#endif /* IMX7_GPR_H */
+++ /dev/null
-/*
- * Copyright (c) 2017, Impinj, Inc.
- *
- * i.MX7 SNVS block emulation code
- *
- * Author: Andrey Smirnov <andrew.smirnov@gmail.com>
- *
- * This work is licensed under the terms of the GNU GPL, version 2 or later.
- * See the COPYING file in the top-level directory.
- */
-
-#ifndef IMX7_SNVS_H
-#define IMX7_SNVS_H
-
-#include "qemu/bitops.h"
-#include "hw/sysbus.h"
-#include "qom/object.h"
-
-
-enum IMX7SNVSRegisters {
- SNVS_LPCR = 0x38,
- SNVS_LPCR_TOP = BIT(6),
- SNVS_LPCR_DP_EN = BIT(5)
-};
-
-#define TYPE_IMX7_SNVS "imx7.snvs"
-OBJECT_DECLARE_SIMPLE_TYPE(IMX7SNVSState, IMX7_SNVS)
-
-struct IMX7SNVSState {
- /* <private> */
- SysBusDevice parent_obj;
-
- MemoryRegion mmio;
-};
-
-#endif /* IMX7_SNVS_H */
+++ /dev/null
-/*
- * IMX Clock Control Module base class
- *
- * Copyright (C) 2012 NICTA
- * Updated by Jean-Christophe Dubois <jcd@tribudubois.net>
- *
- * This work is licensed under the terms of the GNU GPL, version 2 or later.
- * See the COPYING file in the top-level directory.
- */
-
-#ifndef IMX_CCM_H
-#define IMX_CCM_H
-
-#include "hw/sysbus.h"
-#include "qom/object.h"
-
-#define CKIL_FREQ 32768 /* nominal 32khz clock */
-
-/* PLL control registers */
-#define PD(v) (((v) >> 26) & 0xf)
-#define MFD(v) (((v) >> 16) & 0x3ff)
-#define MFI(v) (((v) >> 10) & 0xf);
-#define MFN(v) ((v) & 0x3ff)
-
-#define PLL_PD(x) (((x) & 0xf) << 26)
-#define PLL_MFD(x) (((x) & 0x3ff) << 16)
-#define PLL_MFI(x) (((x) & 0xf) << 10)
-#define PLL_MFN(x) (((x) & 0x3ff) << 0)
-
-#define TYPE_IMX_CCM "imx.ccm"
-OBJECT_DECLARE_TYPE(IMXCCMState, IMXCCMClass, IMX_CCM)
-
-struct IMXCCMState {
- /* <private> */
- SysBusDevice parent_obj;
-
- /* <public> */
-
-};
-
-typedef enum {
- CLK_NONE,
- CLK_IPG,
- CLK_IPG_HIGH,
- CLK_32k,
- CLK_EXT,
- CLK_HIGH_DIV,
- CLK_HIGH,
-} IMXClk;
-
-struct IMXCCMClass {
- /* <private> */
- SysBusDeviceClass parent_class;
-
- /* <public> */
- uint32_t (*get_clock_frequency)(IMXCCMState *s, IMXClk clk);
-};
-
-uint32_t imx_ccm_calc_pll(uint32_t pllreg, uint32_t base_freq);
-
-uint32_t imx_ccm_get_clock_frequency(IMXCCMState *s, IMXClk clock);
-
-#endif /* IMX_CCM_H */
+++ /dev/null
-/*
- * Freescale i.MX RNGC emulation
- *
- * Copyright (C) 2020 Martin Kaiser <martin@kaiser.cx>
- *
- * This work is licensed under the terms of the GNU GPL, version 2 or later.
- * See the COPYING file in the top-level directory.
- */
-
-#ifndef IMX_RNGC_H
-#define IMX_RNGC_H
-
-#include "hw/sysbus.h"
-#include "qom/object.h"
-
-#define TYPE_IMX_RNGC "imx.rngc"
-OBJECT_DECLARE_SIMPLE_TYPE(IMXRNGCState, IMX_RNGC)
-
-struct IMXRNGCState {
- /*< private >*/
- SysBusDevice parent_obj;
-
- /*< public >*/
- MemoryRegion iomem;
-
- uint8_t op_self_test;
- uint8_t op_seed;
- uint8_t mask;
- bool auto_seed;
-
- QEMUBH *self_test_bh;
- QEMUBH *seed_bh;
- qemu_irq irq;
-};
-
-#endif /* IMX_RNGC_H */
+++ /dev/null
-/*
- * ARM IoT Kit security controller
- *
- * Copyright (c) 2018 Linaro Limited
- * Written by Peter Maydell
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 or
- * (at your option) any later version.
- */
-
-/* This is a model of the security controller which is part of the
- * Arm IoT Kit and documented in
- * http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ecm0601256/index.html
- *
- * QEMU interface:
- * + sysbus MMIO region 0 is the "secure privilege control block" registers
- * + sysbus MMIO region 1 is the "non-secure privilege control block" registers
- * + named GPIO output "sec_resp_cfg" indicating whether blocked accesses
- * should RAZ/WI or bus error
- * + named GPIO output "nsc_cfg" whose value tracks the NSCCFG register value
- * + named GPIO output "msc_irq" for the combined IRQ line from the MSCs
- * Controlling the 2 APB PPCs in the IoTKit:
- * + named GPIO outputs apb_ppc0_nonsec[0..2] and apb_ppc1_nonsec
- * + named GPIO outputs apb_ppc0_ap[0..2] and apb_ppc1_ap
- * + named GPIO outputs apb_ppc{0,1}_irq_enable
- * + named GPIO outputs apb_ppc{0,1}_irq_clear
- * + named GPIO inputs apb_ppc{0,1}_irq_status
- * Controlling each of the 4 expansion APB PPCs which a system using the IoTKit
- * might provide:
- * + named GPIO outputs apb_ppcexp{0,1,2,3}_nonsec[0..15]
- * + named GPIO outputs apb_ppcexp{0,1,2,3}_ap[0..15]
- * + named GPIO outputs apb_ppcexp{0,1,2,3}_irq_enable
- * + named GPIO outputs apb_ppcexp{0,1,2,3}_irq_clear
- * + named GPIO inputs apb_ppcexp{0,1,2,3}_irq_status
- * Controlling each of the 4 expansion AHB PPCs which a system using the IoTKit
- * might provide:
- * + named GPIO outputs ahb_ppcexp{0,1,2,3}_nonsec[0..15]
- * + named GPIO outputs ahb_ppcexp{0,1,2,3}_ap[0..15]
- * + named GPIO outputs ahb_ppcexp{0,1,2,3}_irq_enable
- * + named GPIO outputs ahb_ppcexp{0,1,2,3}_irq_clear
- * + named GPIO inputs ahb_ppcexp{0,1,2,3}_irq_status
- * Controlling the (up to) 4 MPCs in the IoTKit/SSE:
- * + named GPIO inputs mpc_status[0..3]
- * Controlling each of the 16 expansion MPCs which a system using the IoTKit
- * might provide:
- * + named GPIO inputs mpcexp_status[0..15]
- * Controlling each of the 16 expansion MSCs which a system using the IoTKit
- * might provide:
- * + named GPIO inputs mscexp_status[0..15]
- * + named GPIO outputs mscexp_clear[0..15]
- * + named GPIO outputs mscexp_ns[0..15]
- */
-
-#ifndef IOTKIT_SECCTL_H
-#define IOTKIT_SECCTL_H
-
-#include "hw/sysbus.h"
-#include "qom/object.h"
-
-#define TYPE_IOTKIT_SECCTL "iotkit-secctl"
-OBJECT_DECLARE_SIMPLE_TYPE(IoTKitSecCtl, IOTKIT_SECCTL)
-
-#define IOTS_APB_PPC0_NUM_PORTS 3
-#define IOTS_APB_PPC1_NUM_PORTS 1
-#define IOTS_PPC_NUM_PORTS 16
-#define IOTS_NUM_APB_PPC 2
-#define IOTS_NUM_APB_EXP_PPC 4
-#define IOTS_NUM_AHB_EXP_PPC 4
-#define IOTS_NUM_EXP_MPC 16
-#define IOTS_NUM_MPC 4
-#define IOTS_NUM_EXP_MSC 16
-
-
-/* State and IRQ lines relating to a PPC. For the
- * PPCs in the IoTKit not all the IRQ lines are used.
- */
-typedef struct IoTKitSecCtlPPC {
- qemu_irq nonsec[IOTS_PPC_NUM_PORTS];
- qemu_irq ap[IOTS_PPC_NUM_PORTS];
- qemu_irq irq_enable;
- qemu_irq irq_clear;
-
- uint32_t ns;
- uint32_t sp;
- uint32_t nsp;
-
- /* Number of ports actually present */
- int numports;
- /* Offset of this PPC's interrupt bits in SECPPCINTSTAT */
- int irq_bit_offset;
- IoTKitSecCtl *parent;
-} IoTKitSecCtlPPC;
-
-struct IoTKitSecCtl {
- /*< private >*/
- SysBusDevice parent_obj;
-
- /*< public >*/
- qemu_irq sec_resp_cfg;
- qemu_irq nsc_cfg_irq;
-
- MemoryRegion s_regs;
- MemoryRegion ns_regs;
-
- uint32_t secppcintstat;
- uint32_t secppcinten;
- uint32_t secrespcfg;
- uint32_t nsccfg;
- uint32_t brginten;
- uint32_t mpcintstatus;
-
- uint32_t secmscintstat;
- uint32_t secmscinten;
- uint32_t nsmscexp;
- qemu_irq mscexp_clear[IOTS_NUM_EXP_MSC];
- qemu_irq mscexp_ns[IOTS_NUM_EXP_MSC];
- qemu_irq msc_irq;
-
- IoTKitSecCtlPPC apb[IOTS_NUM_APB_PPC];
- IoTKitSecCtlPPC apbexp[IOTS_NUM_APB_EXP_PPC];
- IoTKitSecCtlPPC ahbexp[IOTS_NUM_APB_EXP_PPC];
-};
-
-#endif
+++ /dev/null
-/*
- * ARM IoTKit system control element
- *
- * Copyright (c) 2018 Linaro Limited
- * Written by Peter Maydell
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 or
- * (at your option) any later version.
- */
-
-/*
- * This is a model of the "system control element" which is part of the
- * Arm IoTKit and documented in
- * http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ecm0601256/index.html
- * Specifically, it implements the "system information block" and
- * "system control register" blocks.
- *
- * QEMU interface:
- * + QOM property "SYS_VERSION": value of the SYS_VERSION register of the
- * system information block of the SSE
- * (used to identify whether to provide SSE-200-only registers)
- * + sysbus MMIO region 0: the system information register bank
- * + sysbus MMIO region 1: the system control register bank
- */
-
-#ifndef HW_MISC_IOTKIT_SYSCTL_H
-#define HW_MISC_IOTKIT_SYSCTL_H
-
-#include "hw/sysbus.h"
-#include "qom/object.h"
-
-#define TYPE_IOTKIT_SYSCTL "iotkit-sysctl"
-OBJECT_DECLARE_SIMPLE_TYPE(IoTKitSysCtl, IOTKIT_SYSCTL)
-
-struct IoTKitSysCtl {
- /*< private >*/
- SysBusDevice parent_obj;
-
- /*< public >*/
- MemoryRegion iomem;
-
- uint32_t secure_debug;
- uint32_t reset_syndrome;
- uint32_t reset_mask;
- uint32_t gretreg;
- uint32_t initsvtor0;
- uint32_t cpuwait;
- uint32_t wicctrl;
- uint32_t scsecctrl;
- uint32_t fclk_div;
- uint32_t sysclk_div;
- uint32_t clock_force;
- uint32_t initsvtor1;
- uint32_t nmi_enable;
- uint32_t ewctrl;
- uint32_t pdcm_pd_sys_sense;
- uint32_t pdcm_pd_sram0_sense;
- uint32_t pdcm_pd_sram1_sense;
- uint32_t pdcm_pd_sram2_sense;
- uint32_t pdcm_pd_sram3_sense;
-
- /* Properties */
- uint32_t sys_version;
- uint32_t cpuwait_rst;
- uint32_t initsvtor0_rst;
- uint32_t initsvtor1_rst;
-
- bool is_sse200;
-};
-
-#endif
+++ /dev/null
-/*
- * ARM IoTKit system information block
- *
- * Copyright (c) 2018 Linaro Limited
- * Written by Peter Maydell
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 or
- * (at your option) any later version.
- */
-
-/*
- * This is a model of the "system information block" which is part of the
- * Arm IoTKit and documented in
- * http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ecm0601256/index.html
- * QEMU interface:
- * + QOM property "SYS_VERSION": value to use for SYS_VERSION register
- * + QOM property "SYS_CONFIG": value to use for SYS_CONFIG register
- * + sysbus MMIO region 0: the system information register bank
- */
-
-#ifndef HW_MISC_IOTKIT_SYSINFO_H
-#define HW_MISC_IOTKIT_SYSINFO_H
-
-#include "hw/sysbus.h"
-#include "qom/object.h"
-
-#define TYPE_IOTKIT_SYSINFO "iotkit-sysinfo"
-OBJECT_DECLARE_SIMPLE_TYPE(IoTKitSysInfo, IOTKIT_SYSINFO)
-
-struct IoTKitSysInfo {
- /*< private >*/
- SysBusDevice parent_obj;
-
- /*< public >*/
- MemoryRegion iomem;
-
- /* Properties */
- uint32_t sys_version;
- uint32_t sys_config;
-};
-
-#endif
+++ /dev/null
-
-/*
- * Inter-VM Shared Memory PCI device.
- *
- * Author:
- * Cam Macdonell <cam@cs.ualberta.ca>
- *
- * Based On: cirrus_vga.c
- * Copyright (c) 2004 Fabrice Bellard
- * Copyright (c) 2004 Makoto Suzuki (suzu)
- *
- * and rtl8139.c
- * Copyright (c) 2006 Igor Kovalenko
- *
- * This code is licensed under the GNU GPL v2.
- *
- * Contributions after 2012-01-13 are licensed under the terms of the
- * GNU GPL, version 2 or (at your option) any later version.
- */
-#ifndef IVSHMEM_H
-#define IVSHMEM_H
-
-#define IVSHMEM_PROTOCOL_VERSION 0
-
-#endif /* IVSHMEM_H */
+++ /dev/null
-/*
- * QEMU single LED device
- *
- * Copyright (C) 2020 Philippe Mathieu-Daudé <f4bug@amsat.org>
- *
- * SPDX-License-Identifier: GPL-2.0-or-later
- */
-#ifndef HW_MISC_LED_H
-#define HW_MISC_LED_H
-
-#include "qom/object.h"
-#include "hw/qdev-core.h"
-
-#define TYPE_LED "led"
-
-/**
- * LEDColor: Color of a LED
- *
- * This set is restricted to physically available LED colors.
- *
- * LED colors from 'Table 1. Product performance of LUXEON Rebel Color
- * Line' of the 'DS68 LUXEON Rebel Color Line' datasheet available at:
- * https://www.lumileds.com/products/color-leds/luxeon-rebel-color/
- */
-typedef enum { /* Coarse wavelength range */
- LED_COLOR_VIOLET, /* 425 nm */
- LED_COLOR_BLUE, /* 475 nm */
- LED_COLOR_CYAN, /* 500 nm */
- LED_COLOR_GREEN, /* 535 nm */
- LED_COLOR_AMBER, /* 590 nm */
- LED_COLOR_ORANGE, /* 615 nm */
- LED_COLOR_RED, /* 630 nm */
-} LEDColor;
-
-struct LEDState {
- /* Private */
- DeviceState parent_obj;
- /* Public */
-
- uint8_t intensity_percent;
- qemu_irq irq;
-
- /* Properties */
- char *description;
- char *color;
- /*
- * Determines whether a GPIO is using a positive (active-high)
- * logic (when used with GPIO, the intensity at reset is related
- * to the GPIO polarity).
- */
- bool gpio_active_high;
-};
-typedef struct LEDState LEDState;
-DECLARE_INSTANCE_CHECKER(LEDState, LED, TYPE_LED)
-
-/**
- * led_set_intensity: Set the intensity of a LED device
- * @s: the LED object
- * @intensity_percent: intensity as percentage in range 0 to 100.
- */
-void led_set_intensity(LEDState *s, unsigned intensity_percent);
-
-/**
- * led_get_intensity:
- * @s: the LED object
- *
- * Returns: The LED intensity as percentage in range 0 to 100.
- */
-unsigned led_get_intensity(LEDState *s);
-
-/**
- * led_set_state: Set the state of a LED device
- * @s: the LED object
- * @is_emitting: boolean indicating whether the LED is emitting
- *
- * This utility is meant for LED connected to GPIO.
- */
-void led_set_state(LEDState *s, bool is_emitting);
-
-/**
- * led_create_simple: Create and realize a LED device
- * @parentobj: the parent object
- * @gpio_polarity: GPIO polarity
- * @color: color of the LED
- * @description: description of the LED (optional)
- *
- * Create the device state structure, initialize it, and
- * drop the reference to it (the device is realized).
- *
- * Returns: The newly allocated and instantiated LED object.
- */
-LEDState *led_create_simple(Object *parentobj,
- GpioPolarity gpio_polarity,
- LEDColor color,
- const char *description);
-
-#endif /* HW_MISC_LED_H */
+++ /dev/null
-/*
- *
- * Copyright (c) 2011-2018 Laurent Vivier
- *
- * This work is licensed under the terms of the GNU GPL, version 2 or later.
- * See the COPYING file in the top-level directory.
- */
-
-#ifndef HW_MISC_MAC_VIA_H
-#define HW_MISC_MAC_VIA_H
-
-#include "exec/memory.h"
-#include "hw/sysbus.h"
-#include "hw/misc/mos6522.h"
-#include "qom/object.h"
-
-
-/* VIA 1 */
-#define VIA1_IRQ_ONE_SECOND_BIT 0
-#define VIA1_IRQ_VBLANK_BIT 1
-#define VIA1_IRQ_ADB_READY_BIT 2
-#define VIA1_IRQ_ADB_DATA_BIT 3
-#define VIA1_IRQ_ADB_CLOCK_BIT 4
-
-#define VIA1_IRQ_NB 8
-
-#define VIA1_IRQ_ONE_SECOND (1 << VIA1_IRQ_ONE_SECOND_BIT)
-#define VIA1_IRQ_VBLANK (1 << VIA1_IRQ_VBLANK_BIT)
-#define VIA1_IRQ_ADB_READY (1 << VIA1_IRQ_ADB_READY_BIT)
-#define VIA1_IRQ_ADB_DATA (1 << VIA1_IRQ_ADB_DATA_BIT)
-#define VIA1_IRQ_ADB_CLOCK (1 << VIA1_IRQ_ADB_CLOCK_BIT)
-
-
-#define TYPE_MOS6522_Q800_VIA1 "mos6522-q800-via1"
-OBJECT_DECLARE_SIMPLE_TYPE(MOS6522Q800VIA1State, MOS6522_Q800_VIA1)
-
-struct MOS6522Q800VIA1State {
- /*< private >*/
- MOS6522State parent_obj;
-
- qemu_irq irqs[VIA1_IRQ_NB];
- uint8_t last_b;
- uint8_t PRAM[256];
-
- /* external timers */
- QEMUTimer *one_second_timer;
- int64_t next_second;
- QEMUTimer *VBL_timer;
- int64_t next_VBL;
-};
-
-
-/* VIA 2 */
-#define VIA2_IRQ_SCSI_DATA_BIT 0
-#define VIA2_IRQ_SLOT_BIT 1
-#define VIA2_IRQ_UNUSED_BIT 2
-#define VIA2_IRQ_SCSI_BIT 3
-#define VIA2_IRQ_ASC_BIT 4
-
-#define VIA2_IRQ_NB 8
-
-#define VIA2_IRQ_SCSI_DATA (1 << VIA2_IRQ_SCSI_DATA_BIT)
-#define VIA2_IRQ_SLOT (1 << VIA2_IRQ_SLOT_BIT)
-#define VIA2_IRQ_UNUSED (1 << VIA2_IRQ_SCSI_BIT)
-#define VIA2_IRQ_SCSI (1 << VIA2_IRQ_UNUSED_BIT)
-#define VIA2_IRQ_ASC (1 << VIA2_IRQ_ASC_BIT)
-
-#define TYPE_MOS6522_Q800_VIA2 "mos6522-q800-via2"
-OBJECT_DECLARE_SIMPLE_TYPE(MOS6522Q800VIA2State, MOS6522_Q800_VIA2)
-
-struct MOS6522Q800VIA2State {
- /*< private >*/
- MOS6522State parent_obj;
-};
-
-
-#define TYPE_MAC_VIA "mac_via"
-OBJECT_DECLARE_SIMPLE_TYPE(MacVIAState, MAC_VIA)
-
-struct MacVIAState {
- SysBusDevice busdev;
-
- VMChangeStateEntry *vmstate;
-
- /* MMIO */
- MemoryRegion mmio;
- MemoryRegion via1mem;
- MemoryRegion via2mem;
-
- /* VIAs */
- MOS6522Q800VIA1State mos6522_via1;
- MOS6522Q800VIA2State mos6522_via2;
-
- /* RTC */
- uint32_t tick_offset;
-
- uint8_t data_out;
- int data_out_cnt;
- uint8_t data_in;
- uint8_t data_in_cnt;
- uint8_t cmd;
- int wprotect;
- int alt;
- BlockBackend *blk;
-
- /* ADB */
- ADBBusState adb_bus;
- qemu_irq adb_data_ready;
- int adb_data_in_size;
- int adb_data_in_index;
- int adb_data_out_index;
- uint8_t adb_data_in[128];
- uint8_t adb_data_out[16];
- uint8_t adb_autopoll_cmd;
-};
-
-#endif
+++ /dev/null
-/*
- * QEMU PowerMac CUDA device support
- *
- * Copyright (c) 2004-2007 Fabrice Bellard
- * Copyright (c) 2007 Jocelyn Mayer
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
- * furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
- * THE SOFTWARE.
- */
-
-#ifndef CUDA_H
-#define CUDA_H
-
-#include "hw/misc/mos6522.h"
-#include "qom/object.h"
-
-/* CUDA commands (2nd byte) */
-#define CUDA_WARM_START 0x0
-#define CUDA_AUTOPOLL 0x1
-#define CUDA_GET_6805_ADDR 0x2
-#define CUDA_GET_TIME 0x3
-#define CUDA_GET_PRAM 0x7
-#define CUDA_SET_6805_ADDR 0x8
-#define CUDA_SET_TIME 0x9
-#define CUDA_POWERDOWN 0xa
-#define CUDA_POWERUP_TIME 0xb
-#define CUDA_SET_PRAM 0xc
-#define CUDA_MS_RESET 0xd
-#define CUDA_SEND_DFAC 0xe
-#define CUDA_BATTERY_SWAP_SENSE 0x10
-#define CUDA_RESET_SYSTEM 0x11
-#define CUDA_SET_IPL 0x12
-#define CUDA_FILE_SERVER_FLAG 0x13
-#define CUDA_SET_AUTO_RATE 0x14
-#define CUDA_GET_AUTO_RATE 0x16
-#define CUDA_SET_DEVICE_LIST 0x19
-#define CUDA_GET_DEVICE_LIST 0x1a
-#define CUDA_SET_ONE_SECOND_MODE 0x1b
-#define CUDA_SET_POWER_MESSAGES 0x21
-#define CUDA_GET_SET_IIC 0x22
-#define CUDA_WAKEUP 0x23
-#define CUDA_TIMER_TICKLE 0x24
-#define CUDA_COMBINED_FORMAT_IIC 0x25
-
-
-/* MOS6522 CUDA */
-struct MOS6522CUDAState {
- /*< private >*/
- MOS6522State parent_obj;
-};
-
-#define TYPE_MOS6522_CUDA "mos6522-cuda"
-OBJECT_DECLARE_SIMPLE_TYPE(MOS6522CUDAState, MOS6522_CUDA)
-
-/* Cuda */
-#define TYPE_CUDA "cuda"
-OBJECT_DECLARE_SIMPLE_TYPE(CUDAState, CUDA)
-
-struct CUDAState {
- /*< private >*/
- SysBusDevice parent_obj;
- /*< public >*/
- MemoryRegion mem;
-
- ADBBusState adb_bus;
- MOS6522CUDAState mos6522_cuda;
-
- uint32_t tick_offset;
- uint64_t tb_frequency;
-
- uint8_t last_b;
- uint8_t last_acr;
-
- /* MacOS 9 is racy and requires a delay upon setting the SR_INT bit */
- uint64_t sr_delay_ns;
- QEMUTimer *sr_delay_timer;
-
- int data_in_size;
- int data_in_index;
- int data_out_index;
-
- qemu_irq irq;
- uint8_t data_in[128];
- uint8_t data_out[16];
-};
-
-#endif /* CUDA_H */
+++ /dev/null
-/*
- * PowerMac NewWorld MacIO GPIO emulation
- *
- * Copyright (c) 2016 Benjamin Herrenschmidt
- * Copyright (c) 2018 Mark Cave-Ayland
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
- * furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
- * THE SOFTWARE.
- */
-
-#ifndef MACIO_GPIO_H
-#define MACIO_GPIO_H
-
-#include "hw/ppc/openpic.h"
-#include "hw/sysbus.h"
-#include "qom/object.h"
-
-#define TYPE_MACIO_GPIO "macio-gpio"
-OBJECT_DECLARE_SIMPLE_TYPE(MacIOGPIOState, MACIO_GPIO)
-
-struct MacIOGPIOState {
- /*< private >*/
- SysBusDevice parent;
- /*< public >*/
-
- OpenPICState *pic;
-
- MemoryRegion gpiomem;
- qemu_irq gpio_extirqs[10];
- uint8_t gpio_levels[8];
- uint8_t gpio_regs[36]; /* XXX Check count */
-};
-
-void macio_set_gpio(MacIOGPIOState *s, uint32_t gpio, bool state);
-
-#endif
+++ /dev/null
-/*
- * PowerMac MacIO device emulation
- *
- * Copyright (c) 2005-2007 Fabrice Bellard
- * Copyright (c) 2007 Jocelyn Mayer
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
- * furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
- * THE SOFTWARE.
- */
-
-#ifndef MACIO_H
-#define MACIO_H
-
-#include "hw/char/escc.h"
-#include "hw/pci/pci.h"
-#include "hw/ide/internal.h"
-#include "hw/intc/heathrow_pic.h"
-#include "hw/misc/macio/cuda.h"
-#include "hw/misc/macio/gpio.h"
-#include "hw/misc/macio/pmu.h"
-#include "hw/ppc/mac.h"
-#include "hw/ppc/mac_dbdma.h"
-#include "hw/ppc/openpic.h"
-#include "qom/object.h"
-
-/* MacIO virtual bus */
-#define TYPE_MACIO_BUS "macio-bus"
-OBJECT_DECLARE_SIMPLE_TYPE(MacIOBusState, MACIO_BUS)
-
-struct MacIOBusState {
- /*< private >*/
- BusState parent_obj;
-};
-
-/* MacIO IDE */
-#define TYPE_MACIO_IDE "macio-ide"
-OBJECT_DECLARE_SIMPLE_TYPE(MACIOIDEState, MACIO_IDE)
-
-struct MACIOIDEState {
- /*< private >*/
- SysBusDevice parent_obj;
- /*< public >*/
- uint32_t addr;
- uint32_t channel;
- qemu_irq real_ide_irq;
- qemu_irq real_dma_irq;
- qemu_irq ide_irq;
- qemu_irq dma_irq;
-
- MemoryRegion mem;
- IDEBus bus;
- IDEDMA dma;
- void *dbdma;
- bool dma_active;
- uint32_t timing_reg;
- uint32_t irq_reg;
-};
-
-void macio_ide_init_drives(MACIOIDEState *ide, DriveInfo **hd_table);
-void macio_ide_register_dma(MACIOIDEState *ide);
-
-#define TYPE_MACIO "macio"
-OBJECT_DECLARE_SIMPLE_TYPE(MacIOState, MACIO)
-
-struct MacIOState {
- /*< private >*/
- PCIDevice parent;
- /*< public >*/
-
- MacIOBusState macio_bus;
- MemoryRegion bar;
- CUDAState cuda;
- PMUState pmu;
- DBDMAState dbdma;
- ESCCState escc;
- uint64_t frequency;
-};
-
-#define TYPE_OLDWORLD_MACIO "macio-oldworld"
-OBJECT_DECLARE_SIMPLE_TYPE(OldWorldMacIOState, OLDWORLD_MACIO)
-
-struct OldWorldMacIOState {
- /*< private >*/
- MacIOState parent_obj;
- /*< public >*/
-
- HeathrowState *pic;
-
- MacIONVRAMState nvram;
- MACIOIDEState ide[2];
-};
-
-#define TYPE_NEWWORLD_MACIO "macio-newworld"
-OBJECT_DECLARE_SIMPLE_TYPE(NewWorldMacIOState, NEWWORLD_MACIO)
-
-struct NewWorldMacIOState {
- /*< private >*/
- MacIOState parent_obj;
- /*< public >*/
-
- bool has_pmu;
- bool has_adb;
- OpenPICState *pic;
- MACIOIDEState ide[2];
- MacIOGPIOState gpio;
-};
-
-#endif /* MACIO_H */
+++ /dev/null
-/*
- * Definitions for talking to the PMU. The PMU is a microcontroller
- * which controls battery charging and system power on PowerBook 3400
- * and 2400 models as well as the RTC and various other things.
- *
- * Copyright (C) 1998 Paul Mackerras.
- * Copyright (C) 2016 Ben Herrenschmidt
- */
-
-#ifndef PMU_H
-#define PMU_H
-
-#include "hw/misc/mos6522.h"
-#include "hw/misc/macio/gpio.h"
-#include "qom/object.h"
-
-/*
- * PMU commands
- */
-
-#define PMU_POWER_CTRL0 0x10 /* control power of some devices */
-#define PMU_POWER_CTRL 0x11 /* control power of some devices */
-#define PMU_ADB_CMD 0x20 /* send ADB packet */
-#define PMU_ADB_POLL_OFF 0x21 /* disable ADB auto-poll */
-#define PMU_WRITE_NVRAM 0x33 /* write non-volatile RAM */
-#define PMU_READ_NVRAM 0x3b /* read non-volatile RAM */
-#define PMU_SET_RTC 0x30 /* set real-time clock */
-#define PMU_READ_RTC 0x38 /* read real-time clock */
-#define PMU_SET_VOLBUTTON 0x40 /* set volume up/down position */
-#define PMU_BACKLIGHT_BRIGHT 0x41 /* set backlight brightness */
-#define PMU_GET_VOLBUTTON 0x48 /* get volume up/down position */
-#define PMU_PCEJECT 0x4c /* eject PC-card from slot */
-#define PMU_BATTERY_STATE 0x6b /* report battery state etc. */
-#define PMU_SMART_BATTERY_STATE 0x6f /* report battery state (new way) */
-#define PMU_SET_INTR_MASK 0x70 /* set PMU interrupt mask */
-#define PMU_INT_ACK 0x78 /* read interrupt bits */
-#define PMU_SHUTDOWN 0x7e /* turn power off */
-#define PMU_CPU_SPEED 0x7d /* control CPU speed on some models */
-#define PMU_SLEEP 0x7f /* put CPU to sleep */
-#define PMU_POWER_EVENTS 0x8f /* Send power-event commands to PMU */
-#define PMU_I2C_CMD 0x9a /* I2C operations */
-#define PMU_RESET 0xd0 /* reset CPU */
-#define PMU_GET_BRIGHTBUTTON 0xd9 /* report brightness up/down pos */
-#define PMU_GET_COVER 0xdc /* report cover open/closed */
-#define PMU_SYSTEM_READY 0xdf /* tell PMU we are awake */
-#define PMU_DOWNLOAD_STATUS 0xe2 /* Called by MacOS during boot... */
-#define PMU_READ_PMU_RAM 0xe8 /* read the PMU RAM... ??? */
-#define PMU_GET_VERSION 0xea /* read the PMU version */
-
-/* Bits to use with the PMU_POWER_CTRL0 command */
-#define PMU_POW0_ON 0x80 /* OR this to power ON the device */
-#define PMU_POW0_OFF 0x00 /* leave bit 7 to 0 to power it OFF */
-#define PMU_POW0_HARD_DRIVE 0x04 /* Hard drive power
- * (on wallstreet/lombard ?) */
-
-/* Bits to use with the PMU_POWER_CTRL command */
-#define PMU_POW_ON 0x80 /* OR this to power ON the device */
-#define PMU_POW_OFF 0x00 /* leave bit 7 to 0 to power it OFF */
-#define PMU_POW_BACKLIGHT 0x01 /* backlight power */
-#define PMU_POW_CHARGER 0x02 /* battery charger power */
-#define PMU_POW_IRLED 0x04 /* IR led power (on wallstreet) */
-#define PMU_POW_MEDIABAY 0x08 /* media bay power
- * (wallstreet/lombard ?) */
-
-/* Bits in PMU interrupt and interrupt mask bytes */
-#define PMU_INT_PCEJECT 0x04 /* PC-card eject buttons */
-#define PMU_INT_SNDBRT 0x08 /* sound/brightness up/down buttons */
-#define PMU_INT_ADB 0x10 /* ADB autopoll or reply data */
-#define PMU_INT_BATTERY 0x20 /* Battery state change */
-#define PMU_INT_ENVIRONMENT 0x40 /* Environment interrupts */
-#define PMU_INT_TICK 0x80 /* 1-second tick interrupt */
-
-/* Other bits in PMU interrupt valid when PMU_INT_ADB is set */
-#define PMU_INT_ADB_AUTO 0x04 /* ADB autopoll, when PMU_INT_ADB */
-#define PMU_INT_WAITING_CHARGER 0x01 /* ??? */
-#define PMU_INT_AUTO_SRQ_POLL 0x02 /* ??? */
-
-/* Bits in the environement message (either obtained via PMU_GET_COVER,
- * or via PMU_INT_ENVIRONMENT on core99 */
-#define PMU_ENV_LID_CLOSED 0x01 /* The lid is closed */
-
-/* I2C related definitions */
-#define PMU_I2C_MODE_SIMPLE 0
-#define PMU_I2C_MODE_STDSUB 1
-#define PMU_I2C_MODE_COMBINED 2
-
-#define PMU_I2C_BUS_STATUS 0
-#define PMU_I2C_BUS_SYSCLK 1
-#define PMU_I2C_BUS_POWER 2
-
-#define PMU_I2C_STATUS_OK 0
-#define PMU_I2C_STATUS_DATAREAD 1
-#define PMU_I2C_STATUS_BUSY 0xfe
-
-/* Kind of PMU (model) */
-enum {
- PMU_UNKNOWN,
- PMU_OHARE_BASED, /* 2400, 3400, 3500 (old G3 powerbook) */
- PMU_HEATHROW_BASED, /* PowerBook G3 series */
- PMU_PADDINGTON_BASED, /* 1999 PowerBook G3 */
- PMU_KEYLARGO_BASED, /* Core99 motherboard (PMU99) */
- PMU_68K_V1, /* 68K PMU, version 1 */
- PMU_68K_V2, /* 68K PMU, version 2 */
-};
-
-/* PMU PMU_POWER_EVENTS commands */
-enum {
- PMU_PWR_GET_POWERUP_EVENTS = 0x00,
- PMU_PWR_SET_POWERUP_EVENTS = 0x01,
- PMU_PWR_CLR_POWERUP_EVENTS = 0x02,
- PMU_PWR_GET_WAKEUP_EVENTS = 0x03,
- PMU_PWR_SET_WAKEUP_EVENTS = 0x04,
- PMU_PWR_CLR_WAKEUP_EVENTS = 0x05,
-};
-
-/* Power events wakeup bits */
-enum {
- PMU_PWR_WAKEUP_KEY = 0x01, /* Wake on key press */
- PMU_PWR_WAKEUP_AC_INSERT = 0x02, /* Wake on AC adapter plug */
- PMU_PWR_WAKEUP_AC_CHANGE = 0x04,
- PMU_PWR_WAKEUP_LID_OPEN = 0x08,
- PMU_PWR_WAKEUP_RING = 0x10,
-};
-
-/*
- * This table indicates for each PMU opcode:
- * - the number of data bytes to be sent with the command, or -1
- * if a length byte should be sent,
- * - the number of response bytes which the PMU will return, or
- * -1 if it will send a length byte.
- */
-
-static const int8_t pmu_data_len[256][2] = {
-/* 0 1 2 3 4 5 6 7 */
- {-1, 0},{-1, 0},{-1, 0},{-1, 0},{-1, 0},{-1, 0},{-1, 0},{-1, 0},
- {-1, -1},{-1, -1},{-1, -1},{-1, -1},{-1, -1},{-1, -1},{-1, -1},{-1, -1},
- { 1, 0},{ 1, 0},{-1, 0},{-1, 0},{-1, 0},{-1, 0},{-1, 0},{-1, 0},
- { 0, 1},{ 0, 1},{-1, -1},{-1, -1},{-1, -1},{-1, -1},{-1, -1},{ 0, 0},
- {-1, 0},{ 0, 0},{ 2, 0},{ 1, 0},{ 1, 0},{-1, 0},{-1, 0},{-1, 0},
- { 0, -1},{ 0, -1},{-1, -1},{-1, -1},{-1, -1},{-1, -1},{-1, -1},{ 0, -1},
- { 4, 0},{20, 0},{-1, 0},{ 3, 0},{-1, 0},{-1, 0},{-1, 0},{-1, 0},
- { 0, 4},{ 0, 20},{ 2, -1},{ 2, 1},{ 3, -1},{-1, -1},{-1, -1},{ 4, 0},
- { 1, 0},{ 1, 0},{-1, 0},{-1, 0},{-1, 0},{-1, 0},{-1, 0},{-1, 0},
- { 0, 1},{ 0, 1},{-1, -1},{ 1, 0},{ 1, 0},{-1, -1},{-1, -1},{-1, -1},
- { 1, 0},{ 0, 0},{ 2, 0},{ 2, 0},{-1, 0},{ 1, 0},{ 3, 0},{ 1, 0},
- { 0, 1},{ 1, 0},{ 0, 2},{ 0, 2},{ 0, -1},{-1, -1},{-1, -1},{-1, -1},
- { 2, 0},{-1, 0},{-1, 0},{-1, 0},{-1, 0},{-1, 0},{-1, 0},{-1, 0},
- { 0, 3},{ 0, 3},{ 0, 2},{ 0, 8},{ 0, -1},{ 0, -1},{-1, -1},{-1, -1},
- { 1, 0},{ 1, 0},{ 1, 0},{-1, 0},{-1, 0},{-1, 0},{-1, 0},{-1, 0},
- { 0, -1},{ 0, -1},{-1, -1},{-1, -1},{-1, -1},{ 5, 1},{ 4, 1},{ 4, 1},
- { 4, 0},{-1, 0},{ 0, 0},{-1, 0},{-1, 0},{-1, 0},{-1, 0},{-1, 0},
- { 0, 5},{-1, -1},{-1, -1},{-1, -1},{-1, -1},{-1, -1},{-1, -1},{-1, -1},
- { 1, 0},{ 2, 0},{-1, 0},{-1, 0},{-1, 0},{-1, 0},{-1, 0},{-1, 0},
- { 0, 1},{ 0, 1},{-1, -1},{-1, -1},{-1, -1},{-1, -1},{-1, -1},{-1, -1},
- { 2, 0},{ 2, 0},{ 2, 0},{ 4, 0},{-1, 0},{ 0, 0},{-1, 0},{-1, 0},
- { 1, 1},{ 1, 0},{ 3, 0},{ 2, 0},{-1, -1},{-1, -1},{-1, -1},{-1, -1},
- {-1, 0},{-1, 0},{-1, 0},{-1, 0},{-1, 0},{-1, 0},{-1, 0},{-1, 0},
- {-1, -1},{-1, -1},{-1, -1},{-1, -1},{-1, -1},{-1, -1},{-1, -1},{-1, -1},
- {-1, 0},{-1, 0},{-1, 0},{-1, 0},{-1, 0},{-1, 0},{-1, 0},{-1, 0},
- {-1, -1},{-1, -1},{-1, -1},{-1, -1},{-1, -1},{-1, -1},{-1, -1},{-1, -1},
- { 0, 0},{-1, 0},{-1, 0},{-1, 0},{-1, 0},{-1, 0},{-1, 0},{-1, 0},
- { 1, 1},{ 1, 1},{-1, -1},{-1, -1},{ 0, 1},{ 0, -1},{-1, -1},{-1, -1},
- {-1, 0},{ 4, 0},{ 0, 1},{-1, 0},{-1, 0},{ 4, 0},{-1, 0},{-1, 0},
- { 3, -1},{-1, -1},{ 0, 1},{-1, -1},{ 0, -1},{-1, -1},{-1, -1},{ 0, 0},
- {-1, 0},{-1, 0},{-1, 0},{-1, 0},{-1, 0},{-1, 0},{-1, 0},{-1, 0},
- {-1, -1},{-1, -1},{-1, -1},{-1, -1},{-1, -1},{-1, -1},{-1, -1},{-1, -1},
-};
-
-/* Command protocol state machine */
-typedef enum {
- pmu_state_idle, /* Waiting for command */
- pmu_state_cmd, /* Receiving command */
- pmu_state_rsp, /* Responding to command */
-} PMUCmdState;
-
-/* MOS6522 PMU */
-struct MOS6522PMUState {
- /*< private >*/
- MOS6522State parent_obj;
-};
-
-#define TYPE_MOS6522_PMU "mos6522-pmu"
-OBJECT_DECLARE_SIMPLE_TYPE(MOS6522PMUState, MOS6522_PMU)
-/**
- * PMUState:
- * @last_b: last value of B register
- */
-
-struct PMUState {
- /*< private >*/
- SysBusDevice parent_obj;
- /*< public >*/
-
- MemoryRegion mem;
- uint64_t frequency;
- qemu_irq via_irq;
- bool via_irq_state;
-
- /* PMU state */
- MOS6522PMUState mos6522_pmu;
-
- /* PMU low level protocol state */
- PMUCmdState cmd_state;
- uint8_t last_b;
- uint8_t cmd;
- uint32_t cmdlen;
- uint32_t rsplen;
- uint8_t cmd_buf_pos;
- uint8_t cmd_buf[128];
- uint8_t cmd_rsp_pos;
- uint8_t cmd_rsp_sz;
- uint8_t cmd_rsp[128];
-
- /* PMU events/interrupts */
- uint8_t intbits;
- uint8_t intmask;
-
- /* ADB */
- bool has_adb;
- ADBBusState adb_bus;
- uint8_t adb_reply_size;
- uint8_t adb_reply[ADB_MAX_OUT_LEN];
-
- /* RTC */
- uint32_t tick_offset;
- QEMUTimer *one_sec_timer;
- int64_t one_sec_target;
-
- /* GPIO */
- MacIOGPIOState *gpio;
-};
-
-#define TYPE_VIA_PMU "via-pmu"
-OBJECT_DECLARE_SIMPLE_TYPE(PMUState, VIA_PMU)
-
-#endif /* PMU_H */
+++ /dev/null
-/*
- * Maxim MAX1110/1111 ADC chip emulation.
- *
- * Copyright (c) 2006 Openedhand Ltd.
- * Written by Andrzej Zaborowski <balrog@zabor.org>
- *
- * This code is licensed under the GNU GPLv2.
- *
- * Contributions after 2012-01-13 are licensed under the terms of the
- * GNU GPL, version 2 or (at your option) any later version.
- */
-
-#ifndef HW_MISC_MAX111X_H
-#define HW_MISC_MAX111X_H
-
-#include "hw/ssi/ssi.h"
-#include "qom/object.h"
-
-/*
- * This is a model of the Maxim MAX1110/1111 ADC chip, which for QEMU
- * is an SSI slave device. It has either 4 (max1110) or 8 (max1111)
- * 8-bit ADC channels.
- *
- * QEMU interface:
- * + GPIO inputs 0..3 (for max1110) or 0..7 (for max1111): set the value
- * of each ADC input, as an unsigned 8-bit value
- * + GPIO output 0: interrupt line
- * + Properties "input0" to "input3" (max1110) or "input0" to "input7"
- * (max1111): initial reset values for ADC inputs.
- *
- * Known bugs:
- * + the interrupt line is not correctly implemented, and will never
- * be lowered once it has been asserted.
- */
-struct MAX111xState {
- SSISlave parent_obj;
-
- qemu_irq interrupt;
- /* Values of inputs at system reset (settable by QOM property) */
- uint8_t reset_input[8];
-
- uint8_t tb1, rb2, rb3;
- int cycle;
-
- uint8_t input[8];
- int inputs, com;
-};
-
-#define TYPE_MAX_111X "max111x"
-
-OBJECT_DECLARE_SIMPLE_TYPE(MAX111xState, MAX_111X)
-
-#define TYPE_MAX_1110 "max1110"
-#define TYPE_MAX_1111 "max1111"
-
-#endif
+++ /dev/null
-/*
- * Microchip PolarFire SoC DDR Memory Controller module emulation
- *
- * Copyright (c) 2020 Wind River Systems, Inc.
- *
- * Author:
- * Bin Meng <bin.meng@windriver.com>
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 or
- * (at your option) version 3 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License along
- * with this program; if not, see <http://www.gnu.org/licenses/>.
- */
-
-#ifndef MCHP_PFSOC_DMC_H
-#define MCHP_PFSOC_DMC_H
-
-/* DDR SGMII PHY module */
-
-#define MCHP_PFSOC_DDR_SGMII_PHY_REG_SIZE 0x1000
-
-typedef struct MchpPfSoCDdrSgmiiPhyState {
- SysBusDevice parent;
- MemoryRegion sgmii_phy;
-} MchpPfSoCDdrSgmiiPhyState;
-
-#define TYPE_MCHP_PFSOC_DDR_SGMII_PHY "mchp.pfsoc.ddr_sgmii_phy"
-
-#define MCHP_PFSOC_DDR_SGMII_PHY(obj) \
- OBJECT_CHECK(MchpPfSoCDdrSgmiiPhyState, (obj), \
- TYPE_MCHP_PFSOC_DDR_SGMII_PHY)
-
-/* DDR CFG module */
-
-#define MCHP_PFSOC_DDR_CFG_REG_SIZE 0x40000
-
-typedef struct MchpPfSoCDdrCfgState {
- SysBusDevice parent;
- MemoryRegion cfg;
-} MchpPfSoCDdrCfgState;
-
-#define TYPE_MCHP_PFSOC_DDR_CFG "mchp.pfsoc.ddr_cfg"
-
-#define MCHP_PFSOC_DDR_CFG(obj) \
- OBJECT_CHECK(MchpPfSoCDdrCfgState, (obj), \
- TYPE_MCHP_PFSOC_DDR_CFG)
-
-#endif /* MCHP_PFSOC_DMC_H */
+++ /dev/null
-/*
- * Microchip PolarFire SoC IOSCB module emulation
- *
- * Copyright (c) 2020 Wind River Systems, Inc.
- *
- * Author:
- * Bin Meng <bin.meng@windriver.com>
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 or
- * (at your option) version 3 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License along
- * with this program; if not, see <http://www.gnu.org/licenses/>.
- */
-
-#ifndef MCHP_PFSOC_IOSCB_H
-#define MCHP_PFSOC_IOSCB_H
-
-typedef struct MchpPfSoCIoscbState {
- SysBusDevice parent;
- MemoryRegion container;
- MemoryRegion lane01;
- MemoryRegion lane23;
- MemoryRegion ctrl;
- MemoryRegion cfg;
- MemoryRegion pll_mss;
- MemoryRegion cfm_mss;
- MemoryRegion pll_ddr;
- MemoryRegion bc_ddr;
- MemoryRegion io_calib_ddr;
- MemoryRegion pll_sgmii;
- MemoryRegion dll_sgmii;
- MemoryRegion cfm_sgmii;
- MemoryRegion bc_sgmii;
- MemoryRegion io_calib_sgmii;
-} MchpPfSoCIoscbState;
-
-#define TYPE_MCHP_PFSOC_IOSCB "mchp.pfsoc.ioscb"
-
-#define MCHP_PFSOC_IOSCB(obj) \
- OBJECT_CHECK(MchpPfSoCIoscbState, (obj), TYPE_MCHP_PFSOC_IOSCB)
-
-#endif /* MCHP_PFSOC_IOSCB_H */
+++ /dev/null
-/*
- * Microchip PolarFire SoC SYSREG module emulation
- *
- * Copyright (c) 2020 Wind River Systems, Inc.
- *
- * Author:
- * Bin Meng <bin.meng@windriver.com>
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 or
- * (at your option) version 3 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License along
- * with this program; if not, see <http://www.gnu.org/licenses/>.
- */
-
-#ifndef MCHP_PFSOC_SYSREG_H
-#define MCHP_PFSOC_SYSREG_H
-
-#define MCHP_PFSOC_SYSREG_REG_SIZE 0x2000
-
-typedef struct MchpPfSoCSysregState {
- SysBusDevice parent;
- MemoryRegion sysreg;
-} MchpPfSoCSysregState;
-
-#define TYPE_MCHP_PFSOC_SYSREG "mchp.pfsoc.sysreg"
-
-#define MCHP_PFSOC_SYSREG(obj) \
- OBJECT_CHECK(MchpPfSoCSysregState, (obj), \
- TYPE_MCHP_PFSOC_SYSREG)
-
-#endif /* MCHP_PFSOC_SYSREG_H */
+++ /dev/null
-/*
- * This file is subject to the terms and conditions of the GNU General Public
- * License. See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * Copyright (C) 2015 Imagination Technologies
- *
- */
-
-#ifndef MIPS_CMGCR_H
-#define MIPS_CMGCR_H
-
-#include "hw/sysbus.h"
-#include "qom/object.h"
-
-#define TYPE_MIPS_GCR "mips-gcr"
-OBJECT_DECLARE_SIMPLE_TYPE(MIPSGCRState, MIPS_GCR)
-
-#define GCR_BASE_ADDR 0x1fbf8000ULL
-#define GCR_ADDRSPACE_SZ 0x8000
-
-/* Offsets to register blocks */
-#define MIPS_GCB_OFS 0x0000 /* Global Control Block */
-#define MIPS_CLCB_OFS 0x2000 /* Core Local Control Block */
-#define MIPS_COCB_OFS 0x4000 /* Core Other Control Block */
-#define MIPS_GDB_OFS 0x6000 /* Global Debug Block */
-
-/* Global Control Block Register Map */
-#define GCR_CONFIG_OFS 0x0000
-#define GCR_BASE_OFS 0x0008
-#define GCR_REV_OFS 0x0030
-#define GCR_GIC_BASE_OFS 0x0080
-#define GCR_CPC_BASE_OFS 0x0088
-#define GCR_GIC_STATUS_OFS 0x00D0
-#define GCR_CPC_STATUS_OFS 0x00F0
-#define GCR_L2_CONFIG_OFS 0x0130
-
-/* Core Local and Core Other Block Register Map */
-#define GCR_CL_CONFIG_OFS 0x0010
-#define GCR_CL_OTHER_OFS 0x0018
-#define GCR_CL_RESETBASE_OFS 0x0020
-
-/* GCR_L2_CONFIG register fields */
-#define GCR_L2_CONFIG_BYPASS_SHF 20
-#define GCR_L2_CONFIG_BYPASS_MSK ((0x1ULL) << GCR_L2_CONFIG_BYPASS_SHF)
-
-/* GCR_BASE register fields */
-#define GCR_BASE_GCRBASE_MSK 0xffffffff8000ULL
-
-/* GCR_GIC_BASE register fields */
-#define GCR_GIC_BASE_GICEN_MSK 1
-#define GCR_GIC_BASE_GICBASE_MSK 0xFFFFFFFE0000ULL
-#define GCR_GIC_BASE_MSK (GCR_GIC_BASE_GICEN_MSK | GCR_GIC_BASE_GICBASE_MSK)
-
-/* GCR_CPC_BASE register fields */
-#define GCR_CPC_BASE_CPCEN_MSK 1
-#define GCR_CPC_BASE_CPCBASE_MSK 0xFFFFFFFF8000ULL
-#define GCR_CPC_BASE_MSK (GCR_CPC_BASE_CPCEN_MSK | GCR_CPC_BASE_CPCBASE_MSK)
-
-/* GCR_CL_OTHER_OFS register fields */
-#define GCR_CL_OTHER_VPOTHER_MSK 0x7
-#define GCR_CL_OTHER_MSK GCR_CL_OTHER_VPOTHER_MSK
-
-/* GCR_CL_RESETBASE_OFS register fields */
-#define GCR_CL_RESET_BASE_RESETBASE_MSK 0xFFFFF000U
-#define GCR_CL_RESET_BASE_MSK GCR_CL_RESET_BASE_RESETBASE_MSK
-
-typedef struct MIPSGCRVPState MIPSGCRVPState;
-struct MIPSGCRVPState {
- uint32_t other;
- uint64_t reset_base;
-};
-
-struct MIPSGCRState {
- SysBusDevice parent_obj;
-
- int32_t gcr_rev;
- int32_t num_vps;
- hwaddr gcr_base;
- MemoryRegion iomem;
- MemoryRegion *cpc_mr;
- MemoryRegion *gic_mr;
-
- uint64_t cpc_base;
- uint64_t gic_base;
-
- /* VP Local/Other Registers */
- MIPSGCRVPState *vps;
-};
-
-#endif /* MIPS_CMGCR_H */
+++ /dev/null
-/*
- * Cluster Power Controller emulation
- *
- * Copyright (c) 2016 Imagination Technologies
- *
- * This library is free software; you can redistribute it and/or
- * modify it under the terms of the GNU Lesser General Public
- * License as published by the Free Software Foundation; either
- * version 2.1 of the License, or (at your option) any later version.
- *
- * This library is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
- * Lesser General Public License for more details.
- *
- * You should have received a copy of the GNU Lesser General Public
- * License along with this library; if not, see <http://www.gnu.org/licenses/>.
- */
-
-#ifndef MIPS_CPC_H
-#define MIPS_CPC_H
-
-#include "hw/sysbus.h"
-#include "qom/object.h"
-
-#define CPC_ADDRSPACE_SZ 0x6000
-
-/* CPC blocks offsets relative to base address */
-#define CPC_CL_BASE_OFS 0x2000
-#define CPC_CO_BASE_OFS 0x4000
-
-/* CPC register offsets relative to block offsets */
-#define CPC_VP_STOP_OFS 0x20
-#define CPC_VP_RUN_OFS 0x28
-#define CPC_VP_RUNNING_OFS 0x30
-
-#define TYPE_MIPS_CPC "mips-cpc"
-OBJECT_DECLARE_SIMPLE_TYPE(MIPSCPCState, MIPS_CPC)
-
-struct MIPSCPCState {
- SysBusDevice parent_obj;
-
- uint32_t num_vp;
- uint64_t vp_start_running; /* VPs running from restart */
-
- MemoryRegion mr;
- uint64_t vp_running; /* Indicates which VPs are in the run state */
-};
-
-#endif /* MIPS_CPC_H */
+++ /dev/null
-/*
- * Inter-Thread Communication Unit emulation.
- *
- * Copyright (c) 2016 Imagination Technologies
- *
- * This library is free software; you can redistribute it and/or
- * modify it under the terms of the GNU Lesser General Public
- * License as published by the Free Software Foundation; either
- * version 2.1 of the License, or (at your option) any later version.
- *
- * This library is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
- * Lesser General Public License for more details.
- *
- * You should have received a copy of the GNU Lesser General Public
- * License along with this library; if not, see <http://www.gnu.org/licenses/>.
- */
-
-#ifndef MIPS_ITU_H
-#define MIPS_ITU_H
-
-#include "hw/sysbus.h"
-#include "qom/object.h"
-
-#define TYPE_MIPS_ITU "mips-itu"
-OBJECT_DECLARE_SIMPLE_TYPE(MIPSITUState, MIPS_ITU)
-
-#define ITC_CELL_DEPTH_SHIFT 2
-#define ITC_CELL_DEPTH (1u << ITC_CELL_DEPTH_SHIFT)
-
-typedef struct ITCStorageCell {
- struct {
- uint8_t FIFODepth; /* Log2 of the cell depth */
- uint8_t FIFOPtr; /* Number of elements in a FIFO cell */
- uint8_t FIFO; /* 1 - FIFO cell, 0 - Semaphore cell */
- uint8_t T; /* Trap Bit */
- uint8_t F; /* Full Bit */
- uint8_t E; /* Empty Bit */
- } tag;
-
- /* Index of the oldest element in the queue */
- uint8_t fifo_out;
-
- /* Circular buffer for FIFO. Semaphore cells use index 0 only */
- uint64_t data[ITC_CELL_DEPTH];
-
- /* Bitmap tracking blocked threads on the cell.
- TODO: support >64 threads ? */
- uint64_t blocked_threads;
-} ITCStorageCell;
-
-#define ITC_ADDRESSMAP_NUM 2
-
-struct MIPSITUState {
- /*< private >*/
- SysBusDevice parent_obj;
- /*< public >*/
-
- int32_t num_fifo;
- int32_t num_semaphores;
-
- /* ITC Storage */
- ITCStorageCell *cell;
- MemoryRegion storage_io;
-
- /* ITC Configuration Tags */
- uint64_t ITCAddressMap[ITC_ADDRESSMAP_NUM];
- MemoryRegion tag_io;
-
- /* ITU Control Register */
- uint64_t icr0;
-
- /* SAAR */
- bool saar_present;
- void *saar;
-
-};
-
-/* Get ITC Configuration Tag memory region. */
-MemoryRegion *mips_itu_get_tag_region(MIPSITUState *itu);
-
-#endif /* MIPS_ITU_H */
+++ /dev/null
-/*
- * QEMU MOS6522 VIA emulation
- *
- * Copyright (c) 2004-2007 Fabrice Bellard
- * Copyright (c) 2007 Jocelyn Mayer
- * Copyright (c) 2018 Mark Cave-Ayland
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
- * furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
- * THE SOFTWARE.
- */
-
-#ifndef MOS6522_H
-#define MOS6522_H
-
-#include "exec/memory.h"
-#include "hw/sysbus.h"
-#include "hw/input/adb.h"
-#include "qom/object.h"
-
-/* Bits in ACR */
-#define SR_CTRL 0x1c /* Shift register control bits */
-#define SR_EXT 0x0c /* Shift on external clock */
-#define SR_OUT 0x10 /* Shift out if 1 */
-
-/* Bits in IFR and IER */
-#define IER_SET 0x80 /* set bits in IER */
-#define IER_CLR 0 /* clear bits in IER */
-
-#define CA2_INT 0x01
-#define CA1_INT 0x02
-#define SR_INT 0x04 /* Shift register full/empty */
-#define CB2_INT 0x08
-#define CB1_INT 0x10
-#define T2_INT 0x20 /* Timer 2 interrupt */
-#define T1_INT 0x40 /* Timer 1 interrupt */
-
-/* Bits in ACR */
-#define T1MODE 0xc0 /* Timer 1 mode */
-#define T1MODE_CONT 0x40 /* continuous interrupts */
-
-/* VIA registers */
-#define VIA_REG_B 0x00
-#define VIA_REG_A 0x01
-#define VIA_REG_DIRB 0x02
-#define VIA_REG_DIRA 0x03
-#define VIA_REG_T1CL 0x04
-#define VIA_REG_T1CH 0x05
-#define VIA_REG_T1LL 0x06
-#define VIA_REG_T1LH 0x07
-#define VIA_REG_T2CL 0x08
-#define VIA_REG_T2CH 0x09
-#define VIA_REG_SR 0x0a
-#define VIA_REG_ACR 0x0b
-#define VIA_REG_PCR 0x0c
-#define VIA_REG_IFR 0x0d
-#define VIA_REG_IER 0x0e
-#define VIA_REG_ANH 0x0f
-
-/**
- * MOS6522Timer:
- * @counter_value: counter value at load time
- */
-typedef struct MOS6522Timer {
- int index;
- uint16_t latch;
- uint16_t counter_value;
- int64_t load_time;
- int64_t next_irq_time;
- uint64_t frequency;
- QEMUTimer *timer;
-} MOS6522Timer;
-
-/**
- * MOS6522State:
- * @b: B-side data
- * @a: A-side data
- * @dirb: B-side direction (1=output)
- * @dira: A-side direction (1=output)
- * @sr: Shift register
- * @acr: Auxiliary control register
- * @pcr: Peripheral control register
- * @ifr: Interrupt flag register
- * @ier: Interrupt enable register
- * @anh: A-side data, no handshake
- * @last_b: last value of B register
- * @last_acr: last value of ACR register
- */
-struct MOS6522State {
- /*< private >*/
- SysBusDevice parent_obj;
- /*< public >*/
-
- MemoryRegion mem;
- /* VIA registers */
- uint8_t b;
- uint8_t a;
- uint8_t dirb;
- uint8_t dira;
- uint8_t sr;
- uint8_t acr;
- uint8_t pcr;
- uint8_t ifr;
- uint8_t ier;
-
- MOS6522Timer timers[2];
- uint64_t frequency;
-
- qemu_irq irq;
-};
-
-#define TYPE_MOS6522 "mos6522"
-OBJECT_DECLARE_TYPE(MOS6522State, MOS6522DeviceClass, MOS6522)
-
-struct MOS6522DeviceClass {
- DeviceClass parent_class;
-
- DeviceReset parent_reset;
- void (*set_sr_int)(MOS6522State *dev);
- void (*portB_write)(MOS6522State *dev);
- void (*portA_write)(MOS6522State *dev);
- void (*update_irq)(MOS6522State *dev);
- /* These are used to influence the CUDA MacOS timebase calibration */
- uint64_t (*get_timer1_counter_value)(MOS6522State *dev, MOS6522Timer *ti);
- uint64_t (*get_timer2_counter_value)(MOS6522State *dev, MOS6522Timer *ti);
- uint64_t (*get_timer1_load_time)(MOS6522State *dev, MOS6522Timer *ti);
- uint64_t (*get_timer2_load_time)(MOS6522State *dev, MOS6522Timer *ti);
-};
-
-
-extern const VMStateDescription vmstate_mos6522;
-
-uint64_t mos6522_read(void *opaque, hwaddr addr, unsigned size);
-void mos6522_write(void *opaque, hwaddr addr, uint64_t val, unsigned size);
-
-#endif /* MOS6522_H */
+++ /dev/null
-/*
- * ARM MPS2 FPGAIO emulation
- *
- * Copyright (c) 2018 Linaro Limited
- * Written by Peter Maydell
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 or
- * (at your option) any later version.
- */
-
-/* This is a model of the FPGAIO register block in the AN505
- * FPGA image for the MPS2 dev board; it is documented in the
- * application note:
- * http://infocenter.arm.com/help/topic/com.arm.doc.dai0505b/index.html
- *
- * QEMU interface:
- * + sysbus MMIO region 0: the register bank
- */
-
-#ifndef MPS2_FPGAIO_H
-#define MPS2_FPGAIO_H
-
-#include "hw/sysbus.h"
-#include "hw/misc/led.h"
-#include "qom/object.h"
-
-#define TYPE_MPS2_FPGAIO "mps2-fpgaio"
-OBJECT_DECLARE_SIMPLE_TYPE(MPS2FPGAIO, MPS2_FPGAIO)
-
-struct MPS2FPGAIO {
- /*< private >*/
- SysBusDevice parent_obj;
-
- /*< public >*/
- MemoryRegion iomem;
- LEDState *led[2];
-
- uint32_t led0;
- uint32_t prescale;
- uint32_t misc;
-
- /* QEMU_CLOCK_VIRTUAL time at which counter and pscntr were last synced */
- int64_t pscntr_sync_ticks;
- /* Values of COUNTER and PSCNTR at time pscntr_sync_ticks */
- uint32_t counter;
- uint32_t pscntr;
-
- uint32_t prescale_clk;
-
- /* These hold the CLOCK_VIRTUAL ns tick when the CLK1HZ/CLK100HZ was zero */
- int64_t clk1hz_tick_offset;
- int64_t clk100hz_tick_offset;
-};
-
-#endif
+++ /dev/null
-/*
- * ARM MPS2 SCC emulation
- *
- * Copyright (c) 2017 Linaro Limited
- * Written by Peter Maydell
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 or
- * (at your option) any later version.
- */
-
-#ifndef MPS2_SCC_H
-#define MPS2_SCC_H
-
-#include "hw/sysbus.h"
-#include "hw/misc/led.h"
-#include "qom/object.h"
-
-#define TYPE_MPS2_SCC "mps2-scc"
-OBJECT_DECLARE_SIMPLE_TYPE(MPS2SCC, MPS2_SCC)
-
-#define NUM_OSCCLK 3
-
-struct MPS2SCC {
- /*< private >*/
- SysBusDevice parent_obj;
-
- /*< public >*/
- MemoryRegion iomem;
- LEDState *led[8];
-
- uint32_t cfg0;
- uint32_t cfg1;
- uint32_t cfg4;
- uint32_t cfgdata_rtn;
- uint32_t cfgdata_out;
- uint32_t cfgctrl;
- uint32_t cfgstat;
- uint32_t dll;
- uint32_t aid;
- uint32_t id;
- uint32_t oscclk[NUM_OSCCLK];
- uint32_t oscclk_reset[NUM_OSCCLK];
-};
-
-#endif
+++ /dev/null
-/*
- * Microsemi SmartFusion2 SYSREG
- *
- * Copyright (c) 2017 Subbaraya Sundeep <sundeep.lkml@gmail.com>
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
- * furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
- * THE SOFTWARE.
- */
-
-#ifndef HW_MSF2_SYSREG_H
-#define HW_MSF2_SYSREG_H
-
-#include "hw/sysbus.h"
-#include "qom/object.h"
-
-enum {
- ESRAM_CR = 0x00 / 4,
- ESRAM_MAX_LAT,
- DDR_CR,
- ENVM_CR,
- ENVM_REMAP_BASE_CR,
- ENVM_REMAP_FAB_CR,
- CC_CR,
- CC_REGION_CR,
- CC_LOCK_BASE_ADDR_CR,
- CC_FLUSH_INDX_CR,
- DDRB_BUF_TIMER_CR,
- DDRB_NB_ADDR_CR,
- DDRB_NB_SIZE_CR,
- DDRB_CR,
-
- SOFT_RESET_CR = 0x48 / 4,
- M3_CR,
-
- GPIO_SYSRESET_SEL_CR = 0x58 / 4,
-
- MDDR_CR = 0x60 / 4,
-
- MSSDDR_PLL_STATUS_LOW_CR = 0x90 / 4,
- MSSDDR_PLL_STATUS_HIGH_CR,
- MSSDDR_FACC1_CR,
- MSSDDR_FACC2_CR,
-
- MSSDDR_PLL_STATUS = 0x150 / 4,
-};
-
-#define MSF2_SYSREG_MMIO_SIZE 0x300
-
-#define TYPE_MSF2_SYSREG "msf2-sysreg"
-OBJECT_DECLARE_SIMPLE_TYPE(MSF2SysregState, MSF2_SYSREG)
-
-struct MSF2SysregState {
- SysBusDevice parent_obj;
-
- MemoryRegion iomem;
-
- uint8_t apb0div;
- uint8_t apb1div;
-
- uint32_t regs[MSF2_SYSREG_MMIO_SIZE / 4];
-};
-
-#endif /* HW_MSF2_SYSREG_H */
+++ /dev/null
-/*
- * Nuvoton NPCM7xx Clock Control Registers.
- *
- * Copyright 2020 Google LLC
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License as published by the
- * Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
- * for more details.
- */
-#ifndef NPCM7XX_CLK_H
-#define NPCM7XX_CLK_H
-
-#include "exec/memory.h"
-#include "hw/sysbus.h"
-
-/*
- * The reference clock frequency for the timer modules, and the SECCNT and
- * CNTR25M registers in this module, is always 25 MHz.
- */
-#define NPCM7XX_TIMER_REF_HZ (25000000)
-
-/*
- * Number of registers in our device state structure. Don't change this without
- * incrementing the version_id in the vmstate.
- */
-#define NPCM7XX_CLK_NR_REGS (0x70 / sizeof(uint32_t))
-
-#define NPCM7XX_WATCHDOG_RESET_GPIO_IN "npcm7xx-clk-watchdog-reset-gpio-in"
-
-typedef struct NPCM7xxCLKState {
- SysBusDevice parent;
-
- MemoryRegion iomem;
-
- uint32_t regs[NPCM7XX_CLK_NR_REGS];
-
- /* Time reference for SECCNT and CNTR25M, initialized by power on reset */
- int64_t ref_ns;
-} NPCM7xxCLKState;
-
-#define TYPE_NPCM7XX_CLK "npcm7xx-clk"
-#define NPCM7XX_CLK(obj) OBJECT_CHECK(NPCM7xxCLKState, (obj), TYPE_NPCM7XX_CLK)
-
-#endif /* NPCM7XX_CLK_H */
+++ /dev/null
-/*
- * Nuvoton NPCM7xx System Global Control Registers.
- *
- * Copyright 2020 Google LLC
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License as published by the
- * Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
- * for more details.
- */
-#ifndef NPCM7XX_GCR_H
-#define NPCM7XX_GCR_H
-
-#include "exec/memory.h"
-#include "hw/sysbus.h"
-
-/*
- * Number of registers in our device state structure. Don't change this without
- * incrementing the version_id in the vmstate.
- */
-#define NPCM7XX_GCR_NR_REGS (0x148 / sizeof(uint32_t))
-
-typedef struct NPCM7xxGCRState {
- SysBusDevice parent;
-
- MemoryRegion iomem;
-
- uint32_t regs[NPCM7XX_GCR_NR_REGS];
-
- uint32_t reset_pwron;
- uint32_t reset_mdlr;
- uint32_t reset_intcr3;
-} NPCM7xxGCRState;
-
-#define TYPE_NPCM7XX_GCR "npcm7xx-gcr"
-#define NPCM7XX_GCR(obj) OBJECT_CHECK(NPCM7xxGCRState, (obj), TYPE_NPCM7XX_GCR)
-
-#endif /* NPCM7XX_GCR_H */
+++ /dev/null
-/*
- * Nuvoton NPCM7xx Random Number Generator.
- *
- * Copyright 2020 Google LLC
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License as published by the
- * Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
- * for more details.
- */
-#ifndef NPCM7XX_RNG_H
-#define NPCM7XX_RNG_H
-
-#include "hw/sysbus.h"
-
-typedef struct NPCM7xxRNGState {
- SysBusDevice parent;
-
- MemoryRegion iomem;
-
- uint8_t rngcs;
- uint8_t rngd;
- uint8_t rngmode;
-} NPCM7xxRNGState;
-
-#define TYPE_NPCM7XX_RNG "npcm7xx-rng"
-#define NPCM7XX_RNG(obj) OBJECT_CHECK(NPCM7xxRNGState, (obj), TYPE_NPCM7XX_RNG)
-
-#endif /* NPCM7XX_RNG_H */
+++ /dev/null
-/*
- * nRF51 Random Number Generator
- *
- * QEMU interface:
- * + Property "period_unfiltered_us": Time between two biased values in
- * microseconds.
- * + Property "period_filtered_us": Time between two unbiased values in
- * microseconds.
- * + sysbus MMIO regions 0: Memory Region with tasks, events and registers
- * to be mapped to the peripherals instance address by the SOC.
- * + Named GPIO output "irq": Interrupt line of the peripheral. Must be
- * connected to the associated peripheral interrupt line of the NVIC.
- * + Named GPIO output "eep_valrdy": Event set when new random value is ready
- * to be read.
- * + Named GPIO input "tep_start": Task that triggers start of continuous
- * generation of random values.
- * + Named GPIO input "tep_stop": Task that ends continuous generation of
- * random values.
- *
- * Accuracy of the peripheral model:
- * + Stochastic properties of different configurations of the random source
- * are not modeled.
- * + Generation of unfiltered and filtered random values take at least the
- * average generation time stated in the production specification;
- * non-deterministic generation times are not modeled.
- *
- * Copyright 2018 Steffen Görtz <contrib@steffen-goertz.de>
- *
- * This code is licensed under the GPL version 2 or later. See
- * the COPYING file in the top-level directory.
- *
- */
-
-#ifndef NRF51_RNG_H
-#define NRF51_RNG_H
-
-#include "hw/sysbus.h"
-#include "qemu/timer.h"
-#include "qom/object.h"
-#define TYPE_NRF51_RNG "nrf51_soc.rng"
-OBJECT_DECLARE_SIMPLE_TYPE(NRF51RNGState, NRF51_RNG)
-
-#define NRF51_RNG_SIZE 0x1000
-
-#define NRF51_RNG_TASK_START 0x000
-#define NRF51_RNG_TASK_STOP 0x004
-#define NRF51_RNG_EVENT_VALRDY 0x100
-#define NRF51_RNG_REG_SHORTS 0x200
-#define NRF51_RNG_REG_SHORTS_VALRDY_STOP 0
-#define NRF51_RNG_REG_INTEN 0x300
-#define NRF51_RNG_REG_INTEN_VALRDY 0
-#define NRF51_RNG_REG_INTENSET 0x304
-#define NRF51_RNG_REG_INTENCLR 0x308
-#define NRF51_RNG_REG_CONFIG 0x504
-#define NRF51_RNG_REG_CONFIG_DECEN 0
-#define NRF51_RNG_REG_VALUE 0x508
-
-struct NRF51RNGState {
- SysBusDevice parent_obj;
-
- MemoryRegion mmio;
- qemu_irq irq;
-
- /* Event End Points */
- qemu_irq eep_valrdy;
-
- QEMUTimer timer;
-
- /* Time between generation of successive unfiltered values in us */
- uint16_t period_unfiltered_us;
- /* Time between generation of successive filtered values in us */
- uint16_t period_filtered_us;
-
- uint8_t value;
-
- uint32_t active;
- uint32_t event_valrdy;
- uint32_t shortcut_stop_on_valrdy;
- uint32_t interrupt_enabled;
- uint32_t filter_enabled;
-
-};
-
-
-#endif /* NRF51_RNG_H */
+++ /dev/null
-/*
- * PCA9552 I2C LED blinker
- *
- * Copyright (c) 2017-2018, IBM Corporation.
- *
- * This work is licensed under the terms of the GNU GPL, version 2 or
- * later. See the COPYING file in the top-level directory.
- */
-#ifndef PCA9552_H
-#define PCA9552_H
-
-#include "hw/i2c/i2c.h"
-#include "qom/object.h"
-
-#define TYPE_PCA9552 "pca9552"
-#define TYPE_PCA955X "pca955x"
-typedef struct PCA955xState PCA955xState;
-DECLARE_INSTANCE_CHECKER(PCA955xState, PCA955X,
- TYPE_PCA955X)
-
-#define PCA955X_NR_REGS 10
-#define PCA955X_PIN_COUNT_MAX 16
-
-struct PCA955xState {
- /*< private >*/
- I2CSlave i2c;
- /*< public >*/
-
- uint8_t len;
- uint8_t pointer;
-
- uint8_t regs[PCA955X_NR_REGS];
- qemu_irq gpio[PCA955X_PIN_COUNT_MAX];
- char *description; /* For debugging purpose only */
-};
-
-#endif
+++ /dev/null
-/*
- * PCA9552 I2C LED blinker registers
- *
- * Copyright (c) 2017-2018, IBM Corporation.
- *
- * This work is licensed under the terms of the GNU GPL, version 2 or
- * later. See the COPYING file in the top-level directory.
- */
-#ifndef PCA9552_REGS_H
-#define PCA9552_REGS_H
-
-/*
- * Bits [0:3] are used to address a specific register.
- */
-#define PCA9552_INPUT0 0 /* read only input register 0 */
-#define PCA9552_INPUT1 1 /* read only input register 1 */
-#define PCA9552_PSC0 2 /* read/write frequency prescaler 0 */
-#define PCA9552_PWM0 3 /* read/write PWM register 0 */
-#define PCA9552_PSC1 4 /* read/write frequency prescaler 1 */
-#define PCA9552_PWM1 5 /* read/write PWM register 1 */
-#define PCA9552_LS0 6 /* read/write LED0 to LED3 selector */
-#define PCA9552_LS1 7 /* read/write LED4 to LED7 selector */
-#define PCA9552_LS2 8 /* read/write LED8 to LED11 selector */
-#define PCA9552_LS3 9 /* read/write LED12 to LED15 selector */
-
-/*
- * Bit [4] is used to activate the Auto-Increment option of the
- * register address
- */
-#define PCA9552_AUTOINC (1 << 4)
-
-#endif
+++ /dev/null
-/*
- * QEMU simulated pvpanic device.
- *
- * Copyright Fujitsu, Corp. 2013
- *
- * Authors:
- * Wen Congyang <wency@cn.fujitsu.com>
- * Hu Tao <hutao@cn.fujitsu.com>
- *
- * This work is licensed under the terms of the GNU GPL, version 2 or later.
- * See the COPYING file in the top-level directory.
- *
- */
-
-#ifndef HW_MISC_PVPANIC_H
-#define HW_MISC_PVPANIC_H
-
-#include "qom/object.h"
-
-#define TYPE_PVPANIC "pvpanic"
-
-#define PVPANIC_IOPORT_PROP "ioport"
-
-static inline uint16_t pvpanic_port(void)
-{
- Object *o = object_resolve_path_type("", TYPE_PVPANIC, NULL);
- if (!o) {
- return 0;
- }
- return object_property_get_uint(o, PVPANIC_IOPORT_PROP, NULL);
-}
-
-#endif
+++ /dev/null
-/*
- * QEMU SiFive E PRCI (Power, Reset, Clock, Interrupt) interface
- *
- * Copyright (c) 2017 SiFive, Inc.
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms and conditions of the GNU General Public License,
- * version 2 or later, as published by the Free Software Foundation.
- *
- * This program is distributed in the hope it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License along with
- * this program. If not, see <http://www.gnu.org/licenses/>.
- */
-
-#ifndef HW_SIFIVE_E_PRCI_H
-#define HW_SIFIVE_E_PRCI_H
-#include "qom/object.h"
-
-enum {
- SIFIVE_E_PRCI_HFROSCCFG = 0x0,
- SIFIVE_E_PRCI_HFXOSCCFG = 0x4,
- SIFIVE_E_PRCI_PLLCFG = 0x8,
- SIFIVE_E_PRCI_PLLOUTDIV = 0xC
-};
-
-enum {
- SIFIVE_E_PRCI_HFROSCCFG_RDY = (1 << 31),
- SIFIVE_E_PRCI_HFROSCCFG_EN = (1 << 30)
-};
-
-enum {
- SIFIVE_E_PRCI_HFXOSCCFG_RDY = (1 << 31),
- SIFIVE_E_PRCI_HFXOSCCFG_EN = (1 << 30)
-};
-
-enum {
- SIFIVE_E_PRCI_PLLCFG_PLLSEL = (1 << 16),
- SIFIVE_E_PRCI_PLLCFG_REFSEL = (1 << 17),
- SIFIVE_E_PRCI_PLLCFG_BYPASS = (1 << 18),
- SIFIVE_E_PRCI_PLLCFG_LOCK = (1 << 31)
-};
-
-enum {
- SIFIVE_E_PRCI_PLLOUTDIV_DIV1 = (1 << 8)
-};
-
-#define SIFIVE_E_PRCI_REG_SIZE 0x1000
-
-#define TYPE_SIFIVE_E_PRCI "riscv.sifive.e.prci"
-
-typedef struct SiFiveEPRCIState SiFiveEPRCIState;
-DECLARE_INSTANCE_CHECKER(SiFiveEPRCIState, SIFIVE_E_PRCI,
- TYPE_SIFIVE_E_PRCI)
-
-struct SiFiveEPRCIState {
- /*< private >*/
- SysBusDevice parent_obj;
-
- /*< public >*/
- MemoryRegion mmio;
- uint32_t hfrosccfg;
- uint32_t hfxosccfg;
- uint32_t pllcfg;
- uint32_t plloutdiv;
-};
-
-DeviceState *sifive_e_prci_create(hwaddr addr);
-
-#endif
+++ /dev/null
-/*
- * QEMU Test Finisher interface
- *
- * Copyright (c) 2018 SiFive, Inc.
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms and conditions of the GNU General Public License,
- * version 2 or later, as published by the Free Software Foundation.
- *
- * This program is distributed in the hope it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License along with
- * this program. If not, see <http://www.gnu.org/licenses/>.
- */
-
-#ifndef HW_SIFIVE_TEST_H
-#define HW_SIFIVE_TEST_H
-
-#include "hw/sysbus.h"
-#include "qom/object.h"
-
-#define TYPE_SIFIVE_TEST "riscv.sifive.test"
-
-typedef struct SiFiveTestState SiFiveTestState;
-DECLARE_INSTANCE_CHECKER(SiFiveTestState, SIFIVE_TEST,
- TYPE_SIFIVE_TEST)
-
-struct SiFiveTestState {
- /*< private >*/
- SysBusDevice parent_obj;
-
- /*< public >*/
- MemoryRegion mmio;
-};
-
-enum {
- FINISHER_FAIL = 0x3333,
- FINISHER_PASS = 0x5555,
- FINISHER_RESET = 0x7777
-};
-
-DeviceState *sifive_test_create(hwaddr addr);
-
-#endif
+++ /dev/null
-/*
- * QEMU SiFive U OTP (One-Time Programmable) Memory interface
- *
- * Copyright (c) 2019 Bin Meng <bmeng.cn@gmail.com>
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms and conditions of the GNU General Public License,
- * version 2 or later, as published by the Free Software Foundation.
- *
- * This program is distributed in the hope it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License along with
- * this program. If not, see <http://www.gnu.org/licenses/>.
- */
-
-#ifndef HW_SIFIVE_U_OTP_H
-#define HW_SIFIVE_U_OTP_H
-#include "qom/object.h"
-
-#define SIFIVE_U_OTP_PA 0x00
-#define SIFIVE_U_OTP_PAIO 0x04
-#define SIFIVE_U_OTP_PAS 0x08
-#define SIFIVE_U_OTP_PCE 0x0C
-#define SIFIVE_U_OTP_PCLK 0x10
-#define SIFIVE_U_OTP_PDIN 0x14
-#define SIFIVE_U_OTP_PDOUT 0x18
-#define SIFIVE_U_OTP_PDSTB 0x1C
-#define SIFIVE_U_OTP_PPROG 0x20
-#define SIFIVE_U_OTP_PTC 0x24
-#define SIFIVE_U_OTP_PTM 0x28
-#define SIFIVE_U_OTP_PTM_REP 0x2C
-#define SIFIVE_U_OTP_PTR 0x30
-#define SIFIVE_U_OTP_PTRIM 0x34
-#define SIFIVE_U_OTP_PWE 0x38
-
-#define SIFIVE_U_OTP_PWE_EN (1 << 0)
-
-#define SIFIVE_U_OTP_PCE_EN (1 << 0)
-
-#define SIFIVE_U_OTP_PDSTB_EN (1 << 0)
-
-#define SIFIVE_U_OTP_PTRIM_EN (1 << 0)
-
-#define SIFIVE_U_OTP_PA_MASK 0xfff
-#define SIFIVE_U_OTP_NUM_FUSES 0x1000
-#define SIFIVE_U_OTP_FUSE_WORD 4
-#define SIFIVE_U_OTP_SERIAL_ADDR 0xfc
-
-#define SIFIVE_U_OTP_REG_SIZE 0x1000
-
-#define TYPE_SIFIVE_U_OTP "riscv.sifive.u.otp"
-
-typedef struct SiFiveUOTPState SiFiveUOTPState;
-DECLARE_INSTANCE_CHECKER(SiFiveUOTPState, SIFIVE_U_OTP,
- TYPE_SIFIVE_U_OTP)
-
-struct SiFiveUOTPState {
- /*< private >*/
- SysBusDevice parent_obj;
-
- /*< public >*/
- MemoryRegion mmio;
- uint32_t pa;
- uint32_t paio;
- uint32_t pas;
- uint32_t pce;
- uint32_t pclk;
- uint32_t pdin;
- uint32_t pdstb;
- uint32_t pprog;
- uint32_t ptc;
- uint32_t ptm;
- uint32_t ptm_rep;
- uint32_t ptr;
- uint32_t ptrim;
- uint32_t pwe;
- uint32_t fuse[SIFIVE_U_OTP_NUM_FUSES];
- uint32_t fuse_wo[SIFIVE_U_OTP_NUM_FUSES];
- /* config */
- uint32_t serial;
- BlockBackend *blk;
-};
-
-#endif /* HW_SIFIVE_U_OTP_H */
+++ /dev/null
-/*
- * QEMU SiFive U PRCI (Power, Reset, Clock, Interrupt) interface
- *
- * Copyright (c) 2019 Bin Meng <bmeng.cn@gmail.com>
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms and conditions of the GNU General Public License,
- * version 2 or later, as published by the Free Software Foundation.
- *
- * This program is distributed in the hope it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License along with
- * this program. If not, see <http://www.gnu.org/licenses/>.
- */
-
-#ifndef HW_SIFIVE_U_PRCI_H
-#define HW_SIFIVE_U_PRCI_H
-#include "qom/object.h"
-
-#define SIFIVE_U_PRCI_HFXOSCCFG 0x00
-#define SIFIVE_U_PRCI_COREPLLCFG0 0x04
-#define SIFIVE_U_PRCI_DDRPLLCFG0 0x0C
-#define SIFIVE_U_PRCI_DDRPLLCFG1 0x10
-#define SIFIVE_U_PRCI_GEMGXLPLLCFG0 0x1C
-#define SIFIVE_U_PRCI_GEMGXLPLLCFG1 0x20
-#define SIFIVE_U_PRCI_CORECLKSEL 0x24
-#define SIFIVE_U_PRCI_DEVICESRESET 0x28
-#define SIFIVE_U_PRCI_CLKMUXSTATUS 0x2C
-
-/*
- * Current FU540-C000 manual says ready bit is at bit 29, but
- * freedom-u540-c000-bootloader codes (ux00prci.h) says it is at bit 31.
- * We have to trust the actual code that works.
- *
- * see https://github.com/sifive/freedom-u540-c000-bootloader
- */
-
-#define SIFIVE_U_PRCI_HFXOSCCFG_EN (1 << 30)
-#define SIFIVE_U_PRCI_HFXOSCCFG_RDY (1 << 31)
-
-/* xxxPLLCFG0 register bits */
-#define SIFIVE_U_PRCI_PLLCFG0_DIVR (1 << 0)
-#define SIFIVE_U_PRCI_PLLCFG0_DIVF (31 << 6)
-#define SIFIVE_U_PRCI_PLLCFG0_DIVQ (3 << 15)
-#define SIFIVE_U_PRCI_PLLCFG0_FSE (1 << 25)
-#define SIFIVE_U_PRCI_PLLCFG0_LOCK (1 << 31)
-
-/* xxxPLLCFG1 register bits */
-#define SIFIVE_U_PRCI_PLLCFG1_CKE (1 << 24)
-
-/* coreclksel register bits */
-#define SIFIVE_U_PRCI_CORECLKSEL_HFCLK (1 << 0)
-
-
-#define SIFIVE_U_PRCI_REG_SIZE 0x1000
-
-#define TYPE_SIFIVE_U_PRCI "riscv.sifive.u.prci"
-
-typedef struct SiFiveUPRCIState SiFiveUPRCIState;
-DECLARE_INSTANCE_CHECKER(SiFiveUPRCIState, SIFIVE_U_PRCI,
- TYPE_SIFIVE_U_PRCI)
-
-struct SiFiveUPRCIState {
- /*< private >*/
- SysBusDevice parent_obj;
-
- /*< public >*/
- MemoryRegion mmio;
- uint32_t hfxosccfg;
- uint32_t corepllcfg0;
- uint32_t ddrpllcfg0;
- uint32_t ddrpllcfg1;
- uint32_t gemgxlpllcfg0;
- uint32_t gemgxlpllcfg1;
- uint32_t coreclksel;
- uint32_t devicesreset;
- uint32_t clkmuxstatus;
-};
-
-/*
- * Clock indexes for use by Device Tree data and the PRCI driver.
- *
- * These values are from sifive-fu540-prci.h in the Linux kernel.
- */
-#define PRCI_CLK_COREPLL 0
-#define PRCI_CLK_DDRPLL 1
-#define PRCI_CLK_GEMGXLPLL 2
-#define PRCI_CLK_TLCLK 3
-
-#endif /* HW_SIFIVE_U_PRCI_H */
+++ /dev/null
-/*
- * STM32F2XX SYSCFG
- *
- * Copyright (c) 2014 Alistair Francis <alistair@alistair23.me>
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
- * furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
- * THE SOFTWARE.
- */
-
-#ifndef HW_STM32F2XX_SYSCFG_H
-#define HW_STM32F2XX_SYSCFG_H
-
-#include "hw/sysbus.h"
-#include "qom/object.h"
-
-#define SYSCFG_MEMRMP 0x00
-#define SYSCFG_PMC 0x04
-#define SYSCFG_EXTICR1 0x08
-#define SYSCFG_EXTICR2 0x0C
-#define SYSCFG_EXTICR3 0x10
-#define SYSCFG_EXTICR4 0x14
-#define SYSCFG_CMPCR 0x20
-
-#define TYPE_STM32F2XX_SYSCFG "stm32f2xx-syscfg"
-OBJECT_DECLARE_SIMPLE_TYPE(STM32F2XXSyscfgState, STM32F2XX_SYSCFG)
-
-struct STM32F2XXSyscfgState {
- /* <private> */
- SysBusDevice parent_obj;
-
- /* <public> */
- MemoryRegion mmio;
-
- uint32_t syscfg_memrmp;
- uint32_t syscfg_pmc;
- uint32_t syscfg_exticr1;
- uint32_t syscfg_exticr2;
- uint32_t syscfg_exticr3;
- uint32_t syscfg_exticr4;
- uint32_t syscfg_cmpcr;
-};
-
-#endif /* HW_STM32F2XX_SYSCFG_H */
+++ /dev/null
-/*
- * STM32F4XX EXTI
- *
- * Copyright (c) 2014 Alistair Francis <alistair@alistair23.me>
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
- * furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
- * THE SOFTWARE.
- */
-
-#ifndef HW_STM_EXTI_H
-#define HW_STM_EXTI_H
-
-#include "hw/sysbus.h"
-#include "hw/hw.h"
-#include "qom/object.h"
-
-#define EXTI_IMR 0x00
-#define EXTI_EMR 0x04
-#define EXTI_RTSR 0x08
-#define EXTI_FTSR 0x0C
-#define EXTI_SWIER 0x10
-#define EXTI_PR 0x14
-
-#define TYPE_STM32F4XX_EXTI "stm32f4xx-exti"
-OBJECT_DECLARE_SIMPLE_TYPE(STM32F4xxExtiState, STM32F4XX_EXTI)
-
-#define NUM_GPIO_EVENT_IN_LINES 16
-#define NUM_INTERRUPT_OUT_LINES 16
-
-struct STM32F4xxExtiState {
- SysBusDevice parent_obj;
-
- MemoryRegion mmio;
-
- uint32_t exti_imr;
- uint32_t exti_emr;
- uint32_t exti_rtsr;
- uint32_t exti_ftsr;
- uint32_t exti_swier;
- uint32_t exti_pr;
-
- qemu_irq irq[NUM_INTERRUPT_OUT_LINES];
-};
-
-#endif
+++ /dev/null
-/*
- * STM32F4xx SYSCFG
- *
- * Copyright (c) 2014 Alistair Francis <alistair@alistair23.me>
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
- * furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
- * THE SOFTWARE.
- */
-
-#ifndef HW_STM_SYSCFG_H
-#define HW_STM_SYSCFG_H
-
-#include "hw/sysbus.h"
-#include "hw/hw.h"
-#include "qom/object.h"
-
-#define SYSCFG_MEMRMP 0x00
-#define SYSCFG_PMC 0x04
-#define SYSCFG_EXTICR1 0x08
-#define SYSCFG_EXTICR2 0x0C
-#define SYSCFG_EXTICR3 0x10
-#define SYSCFG_EXTICR4 0x14
-#define SYSCFG_CMPCR 0x20
-
-#define TYPE_STM32F4XX_SYSCFG "stm32f4xx-syscfg"
-OBJECT_DECLARE_SIMPLE_TYPE(STM32F4xxSyscfgState, STM32F4XX_SYSCFG)
-
-#define SYSCFG_NUM_EXTICR 4
-
-struct STM32F4xxSyscfgState {
- /* <private> */
- SysBusDevice parent_obj;
-
- /* <public> */
- MemoryRegion mmio;
-
- uint32_t syscfg_memrmp;
- uint32_t syscfg_pmc;
- uint32_t syscfg_exticr[SYSCFG_NUM_EXTICR];
- uint32_t syscfg_cmpcr;
-
- qemu_irq irq;
- qemu_irq gpio_out[16];
-};
-
-#endif
+++ /dev/null
-/*
- * Texas Instruments TMP105 Temperature Sensor I2C messages
- *
- * Browse the data sheet:
- *
- * http://www.ti.com/lit/gpn/tmp105
- *
- * Copyright (C) 2012 Alex Horn <alex.horn@cs.ox.ac.uk>
- * Copyright (C) 2008-2012 Andrzej Zaborowski <balrogg@gmail.com>
- *
- * This work is licensed under the terms of the GNU GPL, version 2 or
- * later. See the COPYING file in the top-level directory.
- */
-
-#ifndef TMP105_REGS_H
-#define TMP105_REGS_H
-
-/**
- * TMP105Reg:
- * @TMP105_REG_TEMPERATURE: Temperature register
- * @TMP105_REG_CONFIG: Configuration register
- * @TMP105_REG_T_LOW: Low temperature register (also known as T_hyst)
- * @TMP105_REG_T_HIGH: High temperature register (also known as T_OS)
- *
- * The following temperature sensors are
- * compatible with the TMP105 registers:
- * - adt75
- * - ds1775
- * - ds75
- * - lm75
- * - lm75a
- * - max6625
- * - max6626
- * - mcp980x
- * - stds75
- * - tcn75
- * - tmp100
- * - tmp101
- * - tmp105
- * - tmp175
- * - tmp275
- * - tmp75
- **/
-typedef enum TMP105Reg {
- TMP105_REG_TEMPERATURE = 0,
- TMP105_REG_CONFIG,
- TMP105_REG_T_LOW,
- TMP105_REG_T_HIGH,
-} TMP105Reg;
-
-#endif
+++ /dev/null
-/*
- * ARM AHB5 TrustZone Memory Protection Controller emulation
- *
- * Copyright (c) 2018 Linaro Limited
- * Written by Peter Maydell
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 or
- * (at your option) any later version.
- */
-
-/* This is a model of the TrustZone memory protection controller (MPC).
- * It is documented in the ARM CoreLink SIE-200 System IP for Embedded TRM
- * (DDI 0571G):
- * https://developer.arm.com/products/architecture/m-profile/docs/ddi0571/g
- *
- * The MPC sits in front of memory and allows secure software to
- * configure it to either pass through or reject transactions.
- * Rejected transactions may be configured to either be aborted, or to
- * behave as RAZ/WI. An interrupt can be signalled for a rejected transaction.
- *
- * The MPC has a register interface which the guest uses to configure it.
- *
- * QEMU interface:
- * + sysbus MMIO region 0: MemoryRegion for the MPC's config registers
- * + sysbus MMIO region 1: MemoryRegion for the upstream end of the MPC
- * + Property "downstream": MemoryRegion defining the downstream memory
- * + Named GPIO output "irq": set for a transaction-failed interrupt
- */
-
-#ifndef TZ_MPC_H
-#define TZ_MPC_H
-
-#include "hw/sysbus.h"
-#include "qom/object.h"
-
-#define TYPE_TZ_MPC "tz-mpc"
-OBJECT_DECLARE_SIMPLE_TYPE(TZMPC, TZ_MPC)
-
-#define TZ_NUM_PORTS 16
-
-#define TYPE_TZ_MPC_IOMMU_MEMORY_REGION "tz-mpc-iommu-memory-region"
-
-
-struct TZMPC {
- /*< private >*/
- SysBusDevice parent_obj;
-
- /*< public >*/
-
- /* State */
- uint32_t ctrl;
- uint32_t blk_idx;
- uint32_t int_stat;
- uint32_t int_en;
- uint32_t int_info1;
- uint32_t int_info2;
-
- uint32_t *blk_lut;
-
- qemu_irq irq;
-
- /* Properties */
- MemoryRegion *downstream;
-
- hwaddr blocksize;
- uint32_t blk_max;
-
- /* MemoryRegions exposed to user */
- MemoryRegion regmr;
- IOMMUMemoryRegion upstream;
-
- /* MemoryRegion used internally */
- MemoryRegion blocked_io;
-
- AddressSpace downstream_as;
- AddressSpace blocked_io_as;
-};
-
-#endif
+++ /dev/null
-/*
- * ARM TrustZone master security controller emulation
- *
- * Copyright (c) 2018 Linaro Limited
- * Written by Peter Maydell
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 or
- * (at your option) any later version.
- */
-
-/*
- * This is a model of the TrustZone master security controller (MSC).
- * It is documented in the ARM CoreLink SIE-200 System IP for Embedded TRM
- * (DDI 0571G):
- * https://developer.arm.com/products/architecture/m-profile/docs/ddi0571/g
- *
- * The MSC sits in front of a device which can be a bus master (such as
- * a DMA controller) and allows secure software to configure it to either
- * pass through or reject transactions made by that bus master.
- * Rejected transactions may be configured to either be aborted, or to
- * behave as RAZ/WI. An interrupt can be signalled for a rejected transaction.
- *
- * The MSC has no register interface -- it is configured purely by a
- * collection of input signals from other hardware in the system. Typically
- * they are either hardwired or exposed in an ad-hoc register interface by
- * the SoC that uses the MSC.
- *
- * We don't currently implement the irq_enable GPIO input, because on
- * the MPS2 FPGA images it is always tied high, which is awkward to
- * implement in QEMU.
- *
- * QEMU interface:
- * + Named GPIO input "cfg_nonsec": set to 1 if the bus master should be
- * treated as nonsecure, or 0 for secure
- * + Named GPIO input "cfg_sec_resp": set to 1 if a rejected transaction should
- * result in a transaction error, or 0 for the transaction to RAZ/WI
- * + Named GPIO input "irq_clear": set to 1 to clear a pending interrupt
- * + Named GPIO output "irq": set for a transaction-failed interrupt
- * + Property "downstream": MemoryRegion defining where bus master transactions
- * are made if they are not blocked
- * + Property "idau": an object implementing IDAUInterface, which defines which
- * addresses should be treated as secure and which as non-secure.
- * This need not be the same IDAU as the one used by the CPU.
- * + sysbus MMIO region 0: MemoryRegion defining the upstream end of the MSC;
- * this should be passed to the bus master device as the region it should
- * make memory transactions to
- */
-
-#ifndef TZ_MSC_H
-#define TZ_MSC_H
-
-#include "hw/sysbus.h"
-#include "target/arm/idau.h"
-#include "qom/object.h"
-
-#define TYPE_TZ_MSC "tz-msc"
-OBJECT_DECLARE_SIMPLE_TYPE(TZMSC, TZ_MSC)
-
-struct TZMSC {
- /*< private >*/
- SysBusDevice parent_obj;
-
- /*< public >*/
-
- /* State: these just track the values of our input signals */
- bool cfg_nonsec;
- bool cfg_sec_resp;
- bool irq_clear;
- /* State: are we asserting irq ? */
- bool irq_status;
-
- qemu_irq irq;
- MemoryRegion *downstream;
- AddressSpace downstream_as;
- MemoryRegion upstream;
- IDAUInterface *idau;
-};
-
-#endif
+++ /dev/null
-/*
- * ARM TrustZone peripheral protection controller emulation
- *
- * Copyright (c) 2018 Linaro Limited
- * Written by Peter Maydell
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 or
- * (at your option) any later version.
- */
-
-/* This is a model of the TrustZone peripheral protection controller (PPC).
- * It is documented in the ARM CoreLink SIE-200 System IP for Embedded TRM
- * (DDI 0571G):
- * https://developer.arm.com/products/architecture/m-profile/docs/ddi0571/g
- *
- * The PPC sits in front of peripherals and allows secure software to
- * configure it to either pass through or reject transactions.
- * Rejected transactions may be configured to either be aborted, or to
- * behave as RAZ/WI. An interrupt can be signalled for a rejected transaction.
- *
- * The PPC has no register interface -- it is configured purely by a
- * collection of input signals from other hardware in the system. Typically
- * they are either hardwired or exposed in an ad-hoc register interface by
- * the SoC that uses the PPC.
- *
- * This QEMU model can be used to model either the AHB5 or APB4 TZ PPC,
- * since the only difference between them is that the AHB version has a
- * "default" port which has no security checks applied. In QEMU the default
- * port can be emulated simply by wiring its downstream devices directly
- * into the parent address space, since the PPC does not need to intercept
- * transactions there.
- *
- * In the hardware, selection of which downstream port to use is done by
- * the user's decode logic asserting one of the hsel[] signals. In QEMU,
- * we provide 16 MMIO regions, one per port, and the user maps these into
- * the desired addresses to implement the address decode.
- *
- * QEMU interface:
- * + sysbus MMIO regions 0..15: MemoryRegions defining the upstream end
- * of each of the 16 ports of the PPC. When a port is unused (i.e. no
- * downstream MemoryRegion is connected to it) at the end of the 0..15
- * range then no sysbus MMIO region is created for its upstream. When an
- * unused port lies in the middle of the range with other used ports at
- * higher port numbers, a dummy MMIO region is created to ensure that
- * port N's upstream is always sysbus MMIO region N. Dummy regions should
- * not be mapped, and will assert if any access is made to them.
- * + Property "port[0..15]": MemoryRegion defining the downstream device(s)
- * for each of the 16 ports of the PPC
- * + Named GPIO inputs "cfg_nonsec[0..15]": set to 1 if the port should be
- * accessible to NonSecure transactions
- * + Named GPIO inputs "cfg_ap[0..15]": set to 1 if the port should be
- * accessible to non-privileged transactions
- * + Named GPIO input "cfg_sec_resp": set to 1 if a rejected transaction should
- * result in a transaction error, or 0 for the transaction to RAZ/WI
- * + Named GPIO input "irq_enable": set to 1 to enable interrupts
- * + Named GPIO input "irq_clear": set to 1 to clear a pending interrupt
- * + Named GPIO output "irq": set for a transaction-failed interrupt
- * + Property "NONSEC_MASK": if a bit is set in this mask then accesses to
- * the associated port do not have the TZ security check performed. (This
- * corresponds to the hardware allowing this to be set as a Verilog
- * parameter.)
- */
-
-#ifndef TZ_PPC_H
-#define TZ_PPC_H
-
-#include "hw/sysbus.h"
-#include "qom/object.h"
-
-#define TYPE_TZ_PPC "tz-ppc"
-OBJECT_DECLARE_SIMPLE_TYPE(TZPPC, TZ_PPC)
-
-#define TZ_NUM_PORTS 16
-
-
-typedef struct TZPPCPort {
- TZPPC *ppc;
- MemoryRegion upstream;
- AddressSpace downstream_as;
- MemoryRegion *downstream;
-} TZPPCPort;
-
-struct TZPPC {
- /*< private >*/
- SysBusDevice parent_obj;
-
- /*< public >*/
-
- /* State: these just track the values of our input signals */
- bool cfg_nonsec[TZ_NUM_PORTS];
- bool cfg_ap[TZ_NUM_PORTS];
- bool cfg_sec_resp;
- bool irq_enable;
- bool irq_clear;
- /* State: are we asserting irq ? */
- bool irq_status;
-
- qemu_irq irq;
-
- /* Properties */
- uint32_t nonsec_mask;
-
- TZPPCPort port[TZ_NUM_PORTS];
-};
-
-#endif
+++ /dev/null
-/*
- * "Unimplemented" device
- *
- * Copyright Linaro Limited, 2017
- * Written by Peter Maydell
- */
-
-#ifndef HW_MISC_UNIMP_H
-#define HW_MISC_UNIMP_H
-
-#include "hw/qdev-properties.h"
-#include "hw/sysbus.h"
-#include "qapi/error.h"
-#include "qom/object.h"
-
-#define TYPE_UNIMPLEMENTED_DEVICE "unimplemented-device"
-
-OBJECT_DECLARE_SIMPLE_TYPE(UnimplementedDeviceState, UNIMPLEMENTED_DEVICE)
-
-struct UnimplementedDeviceState {
- SysBusDevice parent_obj;
- MemoryRegion iomem;
- unsigned offset_fmt_width;
- char *name;
- uint64_t size;
-};
-
-/**
- * create_unimplemented_device: create and map a dummy device
- * @name: name of the device for debug logging
- * @base: base address of the device's MMIO region
- * @size: size of the device's MMIO region
- *
- * This utility function creates and maps an instance of unimplemented-device,
- * which is a dummy device which simply logs all guest accesses to
- * it via the qemu_log LOG_UNIMP debug log.
- * The device is mapped at priority -1000, which means that you can
- * use it to cover a large region and then map other devices on top of it
- * if necessary.
- */
-static inline void create_unimplemented_device(const char *name,
- hwaddr base,
- hwaddr size)
-{
- DeviceState *dev = qdev_new(TYPE_UNIMPLEMENTED_DEVICE);
-
- qdev_prop_set_string(dev, "name", name);
- qdev_prop_set_uint64(dev, "size", size);
- sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
-
- sysbus_mmio_map_overlap(SYS_BUS_DEVICE(dev), 0, base, -1000);
-}
-
-#endif
+++ /dev/null
-/*
- * Virtual Machine coreinfo device
- *
- * Copyright (C) 2017 Red Hat, Inc.
- *
- * Authors: Marc-André Lureau <marcandre.lureau@redhat.com>
- *
- * This work is licensed under the terms of the GNU GPL, version 2 or later.
- * See the COPYING file in the top-level directory.
- *
- */
-#ifndef VMCOREINFO_H
-#define VMCOREINFO_H
-
-#include "hw/qdev-core.h"
-#include "standard-headers/linux/qemu_fw_cfg.h"
-#include "qom/object.h"
-
-#define VMCOREINFO_DEVICE "vmcoreinfo"
-typedef struct VMCoreInfoState VMCoreInfoState;
-DECLARE_INSTANCE_CHECKER(VMCoreInfoState, VMCOREINFO,
- VMCOREINFO_DEVICE)
-
-typedef struct fw_cfg_vmcoreinfo FWCfgVMCoreInfo;
-
-struct VMCoreInfoState {
- DeviceState parent_obj;
-
- bool has_vmcoreinfo;
- FWCfgVMCoreInfo vmcoreinfo;
-};
-
-/* returns NULL unless there is exactly one device */
-static inline VMCoreInfoState *vmcoreinfo_find(void)
-{
- Object *o = object_resolve_path_type("", VMCOREINFO_DEVICE, NULL);
-
- return o ? VMCOREINFO(o) : NULL;
-}
-
-#endif
+++ /dev/null
-/*
- * Device model for Zynq ADC controller
- *
- * Copyright (c) 2015 Guenter Roeck <linux@roeck-us.net>
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version
- * 2 of the License, or (at your option) any later version.
- *
- * You should have received a copy of the GNU General Public License along
- * with this program; if not, see <http://www.gnu.org/licenses/>.
- */
-
-#ifndef ZYNQ_XADC_H
-#define ZYNQ_XADC_H
-
-#include "hw/sysbus.h"
-#include "qom/object.h"
-
-#define ZYNQ_XADC_MMIO_SIZE 0x0020
-#define ZYNQ_XADC_NUM_IO_REGS (ZYNQ_XADC_MMIO_SIZE / 4)
-#define ZYNQ_XADC_NUM_ADC_REGS 128
-#define ZYNQ_XADC_FIFO_DEPTH 15
-
-#define TYPE_ZYNQ_XADC "xlnx,zynq-xadc"
-OBJECT_DECLARE_SIMPLE_TYPE(ZynqXADCState, ZYNQ_XADC)
-
-struct ZynqXADCState {
- /*< private >*/
- SysBusDevice parent_obj;
-
- /*< public >*/
- MemoryRegion iomem;
-
- uint32_t regs[ZYNQ_XADC_NUM_IO_REGS];
- uint16_t xadc_regs[ZYNQ_XADC_NUM_ADC_REGS];
- uint16_t xadc_read_reg_previous;
- uint16_t xadc_dfifo[ZYNQ_XADC_FIFO_DEPTH];
- uint16_t xadc_dfifo_entries;
-
- struct IRQState *qemu_irq;
-
-};
-
-#endif /* ZYNQ_XADC_H */
+++ /dev/null
-/*
- * Allwinner Sun8i Ethernet MAC emulation
- *
- * Copyright (C) 2019 Niek Linnenbank <nieklinnenbank@gmail.com>
- *
- * This program is free software: you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation, either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program. If not, see <http://www.gnu.org/licenses/>.
- */
-
-#ifndef HW_NET_ALLWINNER_SUN8I_EMAC_H
-#define HW_NET_ALLWINNER_SUN8I_EMAC_H
-
-#include "qom/object.h"
-#include "net/net.h"
-#include "hw/sysbus.h"
-
-/**
- * Object model
- * @{
- */
-
-#define TYPE_AW_SUN8I_EMAC "allwinner-sun8i-emac"
-OBJECT_DECLARE_SIMPLE_TYPE(AwSun8iEmacState, AW_SUN8I_EMAC)
-
-/** @} */
-
-/**
- * Allwinner Sun8i EMAC object instance state
- */
-struct AwSun8iEmacState {
- /*< private >*/
- SysBusDevice parent_obj;
- /*< public >*/
-
- /** Maps I/O registers in physical memory */
- MemoryRegion iomem;
-
- /** Interrupt output signal to notify CPU */
- qemu_irq irq;
-
- /** Memory region where DMA transfers are done */
- MemoryRegion *dma_mr;
-
- /** Address space used internally for DMA transfers */
- AddressSpace dma_as;
-
- /** Generic Network Interface Controller (NIC) for networking API */
- NICState *nic;
-
- /** Generic Network Interface Controller (NIC) configuration */
- NICConf conf;
-
- /**
- * @name Media Independent Interface (MII)
- * @{
- */
-
- uint8_t mii_phy_addr; /**< PHY address */
- uint32_t mii_cr; /**< Control */
- uint32_t mii_st; /**< Status */
- uint32_t mii_adv; /**< Advertised Abilities */
-
- /** @} */
-
- /**
- * @name Hardware Registers
- * @{
- */
-
- uint32_t basic_ctl0; /**< Basic Control 0 */
- uint32_t basic_ctl1; /**< Basic Control 1 */
- uint32_t int_en; /**< Interrupt Enable */
- uint32_t int_sta; /**< Interrupt Status */
- uint32_t frm_flt; /**< Receive Frame Filter */
-
- uint32_t rx_ctl0; /**< Receive Control 0 */
- uint32_t rx_ctl1; /**< Receive Control 1 */
- uint32_t rx_desc_head; /**< Receive Descriptor List Address */
- uint32_t rx_desc_curr; /**< Current Receive Descriptor Address */
-
- uint32_t tx_ctl0; /**< Transmit Control 0 */
- uint32_t tx_ctl1; /**< Transmit Control 1 */
- uint32_t tx_desc_head; /**< Transmit Descriptor List Address */
- uint32_t tx_desc_curr; /**< Current Transmit Descriptor Address */
- uint32_t tx_flowctl; /**< Transmit Flow Control */
-
- uint32_t mii_cmd; /**< Management Interface Command */
- uint32_t mii_data; /**< Management Interface Data */
-
- /** @} */
-
-};
-
-#endif /* HW_NET_ALLWINNER_SUN8I_H */
+++ /dev/null
-/*
- * Emulation of Allwinner EMAC Fast Ethernet controller and
- * Realtek RTL8201CP PHY
- *
- * Copyright (C) 2014 Beniamino Galvani <b.galvani@gmail.com>
- *
- * Allwinner EMAC register definitions from Linux kernel are:
- * Copyright 2012 Stefan Roese <sr@denx.de>
- * Copyright 2013 Maxime Ripard <maxime.ripard@free-electrons.com>
- * Copyright 1997 Sten Wang
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * version 2 as published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- */
-
-#ifndef ALLWINNER_EMAC_H
-#define ALLWINNER_EMAC_H
-
-#include "qemu/units.h"
-#include "net/net.h"
-#include "qemu/fifo8.h"
-#include "hw/net/mii.h"
-#include "hw/sysbus.h"
-#include "qom/object.h"
-
-#define TYPE_AW_EMAC "allwinner-emac"
-OBJECT_DECLARE_SIMPLE_TYPE(AwEmacState, AW_EMAC)
-
-/*
- * Allwinner EMAC register list
- */
-#define EMAC_CTL_REG 0x00
-
-#define EMAC_TX_MODE_REG 0x04
-#define EMAC_TX_FLOW_REG 0x08
-#define EMAC_TX_CTL0_REG 0x0C
-#define EMAC_TX_CTL1_REG 0x10
-#define EMAC_TX_INS_REG 0x14
-#define EMAC_TX_PL0_REG 0x18
-#define EMAC_TX_PL1_REG 0x1C
-#define EMAC_TX_STA_REG 0x20
-#define EMAC_TX_IO_DATA_REG 0x24
-#define EMAC_TX_IO_DATA1_REG 0x28
-#define EMAC_TX_TSVL0_REG 0x2C
-#define EMAC_TX_TSVH0_REG 0x30
-#define EMAC_TX_TSVL1_REG 0x34
-#define EMAC_TX_TSVH1_REG 0x38
-
-#define EMAC_RX_CTL_REG 0x3C
-#define EMAC_RX_HASH0_REG 0x40
-#define EMAC_RX_HASH1_REG 0x44
-#define EMAC_RX_STA_REG 0x48
-#define EMAC_RX_IO_DATA_REG 0x4C
-#define EMAC_RX_FBC_REG 0x50
-
-#define EMAC_INT_CTL_REG 0x54
-#define EMAC_INT_STA_REG 0x58
-
-#define EMAC_MAC_CTL0_REG 0x5C
-#define EMAC_MAC_CTL1_REG 0x60
-#define EMAC_MAC_IPGT_REG 0x64
-#define EMAC_MAC_IPGR_REG 0x68
-#define EMAC_MAC_CLRT_REG 0x6C
-#define EMAC_MAC_MAXF_REG 0x70
-#define EMAC_MAC_SUPP_REG 0x74
-#define EMAC_MAC_TEST_REG 0x78
-#define EMAC_MAC_MCFG_REG 0x7C
-#define EMAC_MAC_MCMD_REG 0x80
-#define EMAC_MAC_MADR_REG 0x84
-#define EMAC_MAC_MWTD_REG 0x88
-#define EMAC_MAC_MRDD_REG 0x8C
-#define EMAC_MAC_MIND_REG 0x90
-#define EMAC_MAC_SSRR_REG 0x94
-#define EMAC_MAC_A0_REG 0x98
-#define EMAC_MAC_A1_REG 0x9C
-#define EMAC_MAC_A2_REG 0xA0
-
-#define EMAC_SAFX_L_REG0 0xA4
-#define EMAC_SAFX_H_REG0 0xA8
-#define EMAC_SAFX_L_REG1 0xAC
-#define EMAC_SAFX_H_REG1 0xB0
-#define EMAC_SAFX_L_REG2 0xB4
-#define EMAC_SAFX_H_REG2 0xB8
-#define EMAC_SAFX_L_REG3 0xBC
-#define EMAC_SAFX_H_REG3 0xC0
-
-/* CTL register fields */
-#define EMAC_CTL_RESET (1 << 0)
-#define EMAC_CTL_TX_EN (1 << 1)
-#define EMAC_CTL_RX_EN (1 << 2)
-
-/* TX MODE register fields */
-#define EMAC_TX_MODE_ABORTED_FRAME_EN (1 << 0)
-#define EMAC_TX_MODE_DMA_EN (1 << 1)
-
-/* RX CTL register fields */
-#define EMAC_RX_CTL_AUTO_DRQ_EN (1 << 1)
-#define EMAC_RX_CTL_DMA_EN (1 << 2)
-#define EMAC_RX_CTL_PASS_ALL_EN (1 << 4)
-#define EMAC_RX_CTL_PASS_CTL_EN (1 << 5)
-#define EMAC_RX_CTL_PASS_CRC_ERR_EN (1 << 6)
-#define EMAC_RX_CTL_PASS_LEN_ERR_EN (1 << 7)
-#define EMAC_RX_CTL_PASS_LEN_OOR_EN (1 << 8)
-#define EMAC_RX_CTL_ACCEPT_UNICAST_EN (1 << 16)
-#define EMAC_RX_CTL_DA_FILTER_EN (1 << 17)
-#define EMAC_RX_CTL_ACCEPT_MULTICAST_EN (1 << 20)
-#define EMAC_RX_CTL_HASH_FILTER_EN (1 << 21)
-#define EMAC_RX_CTL_ACCEPT_BROADCAST_EN (1 << 22)
-#define EMAC_RX_CTL_SA_FILTER_EN (1 << 24)
-#define EMAC_RX_CTL_SA_FILTER_INVERT_EN (1 << 25)
-
-/* RX IO DATA register fields */
-#define EMAC_RX_HEADER(len, status) (((len) & 0xffff) | ((status) << 16))
-#define EMAC_RX_IO_DATA_STATUS_CRC_ERR (1 << 4)
-#define EMAC_RX_IO_DATA_STATUS_LEN_ERR (3 << 5)
-#define EMAC_RX_IO_DATA_STATUS_OK (1 << 7)
-#define EMAC_UNDOCUMENTED_MAGIC 0x0143414d /* header for RX frames */
-
-/* INT CTL and INT STA registers fields */
-#define EMAC_INT_TX_CHAN(x) (1 << (x))
-#define EMAC_INT_RX (1 << 8)
-
-/* Due to lack of specifications, size of fifos is chosen arbitrarily */
-#define TX_FIFO_SIZE (4 * KiB)
-#define RX_FIFO_SIZE (32 * KiB)
-
-#define NUM_TX_FIFOS 2
-#define RX_HDR_SIZE 8
-#define CRC_SIZE 4
-
-#define PHY_REG_SHIFT 0
-#define PHY_ADDR_SHIFT 8
-
-typedef struct RTL8201CPState {
- uint16_t bmcr;
- uint16_t bmsr;
- uint16_t anar;
- uint16_t anlpar;
-} RTL8201CPState;
-
-struct AwEmacState {
- /*< private >*/
- SysBusDevice parent_obj;
- /*< public >*/
-
- MemoryRegion iomem;
- qemu_irq irq;
- NICState *nic;
- NICConf conf;
- RTL8201CPState mii;
- uint8_t phy_addr;
-
- uint32_t ctl;
- uint32_t tx_mode;
- uint32_t rx_ctl;
- uint32_t int_ctl;
- uint32_t int_sta;
- uint32_t phy_target;
-
- Fifo8 rx_fifo;
- uint32_t rx_num_packets;
- uint32_t rx_packet_size;
- uint32_t rx_packet_pos;
-
- Fifo8 tx_fifo[NUM_TX_FIFOS];
- uint32_t tx_length[NUM_TX_FIFOS];
- uint32_t tx_channel;
-};
-
-#endif
+++ /dev/null
-/*
- * QEMU Cadence GEM emulation
- *
- * Copyright (c) 2011 Xilinx, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
- * furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
- * THE SOFTWARE.
- */
-
-#ifndef CADENCE_GEM_H
-#define CADENCE_GEM_H
-#include "qom/object.h"
-
-#define TYPE_CADENCE_GEM "cadence_gem"
-OBJECT_DECLARE_SIMPLE_TYPE(CadenceGEMState, CADENCE_GEM)
-
-#include "net/net.h"
-#include "hw/sysbus.h"
-
-#define CADENCE_GEM_MAXREG (0x00000800 / 4) /* Last valid GEM address */
-
-/* Max number of words in a DMA descriptor. */
-#define DESC_MAX_NUM_WORDS 6
-
-#define MAX_PRIORITY_QUEUES 8
-#define MAX_TYPE1_SCREENERS 16
-#define MAX_TYPE2_SCREENERS 16
-
-#define MAX_JUMBO_FRAME_SIZE_MASK 0x3FFF
-#define MAX_FRAME_SIZE MAX_JUMBO_FRAME_SIZE_MASK
-
-struct CadenceGEMState {
- /*< private >*/
- SysBusDevice parent_obj;
-
- /*< public >*/
- MemoryRegion iomem;
- MemoryRegion *dma_mr;
- AddressSpace dma_as;
- NICState *nic;
- NICConf conf;
- qemu_irq irq[MAX_PRIORITY_QUEUES];
-
- /* Static properties */
- uint8_t num_priority_queues;
- uint8_t num_type1_screeners;
- uint8_t num_type2_screeners;
- uint32_t revision;
- uint16_t jumbo_max_len;
-
- /* GEM registers backing store */
- uint32_t regs[CADENCE_GEM_MAXREG];
- /* Mask of register bits which are write only */
- uint32_t regs_wo[CADENCE_GEM_MAXREG];
- /* Mask of register bits which are read only */
- uint32_t regs_ro[CADENCE_GEM_MAXREG];
- /* Mask of register bits which are clear on read */
- uint32_t regs_rtc[CADENCE_GEM_MAXREG];
- /* Mask of register bits which are write 1 to clear */
- uint32_t regs_w1c[CADENCE_GEM_MAXREG];
-
- /* PHY address */
- uint8_t phy_addr;
- /* PHY registers backing store */
- uint16_t phy_regs[32];
-
- uint8_t phy_loop; /* Are we in phy loopback? */
-
- /* The current DMA descriptor pointers */
- uint32_t rx_desc_addr[MAX_PRIORITY_QUEUES];
- uint32_t tx_desc_addr[MAX_PRIORITY_QUEUES];
-
- uint8_t can_rx_state; /* Debug only */
-
- uint8_t tx_packet[MAX_FRAME_SIZE];
- uint8_t rx_packet[MAX_FRAME_SIZE];
- uint32_t rx_desc[MAX_PRIORITY_QUEUES][DESC_MAX_NUM_WORDS];
-
- bool sar_active[4];
-};
-
-#endif
+++ /dev/null
-/*
- * Faraday FTGMAC100 Gigabit Ethernet
- *
- * Copyright (C) 2016-2017, IBM Corporation.
- *
- * This code is licensed under the GPL version 2 or later. See the
- * COPYING file in the top-level directory.
- */
-
-#ifndef FTGMAC100_H
-#define FTGMAC100_H
-#include "qom/object.h"
-
-#define TYPE_FTGMAC100 "ftgmac100"
-OBJECT_DECLARE_SIMPLE_TYPE(FTGMAC100State, FTGMAC100)
-
-#include "hw/sysbus.h"
-#include "net/net.h"
-
-/*
- * Max frame size for the receiving buffer
- */
-#define FTGMAC100_MAX_FRAME_SIZE 9220
-
-struct FTGMAC100State {
- /*< private >*/
- SysBusDevice parent_obj;
-
- /*< public >*/
- NICState *nic;
- NICConf conf;
- qemu_irq irq;
- MemoryRegion iomem;
-
- uint8_t frame[FTGMAC100_MAX_FRAME_SIZE];
-
- uint32_t irq_state;
- uint32_t isr;
- uint32_t ier;
- uint32_t rx_enabled;
- uint32_t rx_ring;
- uint32_t rx_descriptor;
- uint32_t tx_ring;
- uint32_t tx_descriptor;
- uint32_t math[2];
- uint32_t rbsr;
- uint32_t itc;
- uint32_t aptcr;
- uint32_t dblac;
- uint32_t revr;
- uint32_t fear1;
- uint32_t tpafcr;
- uint32_t maccr;
- uint32_t phycr;
- uint32_t phydata;
- uint32_t fcr;
-
-
- uint32_t phy_status;
- uint32_t phy_control;
- uint32_t phy_advertise;
- uint32_t phy_int;
- uint32_t phy_int_mask;
-
- bool aspeed;
- uint32_t txdes0_edotr;
- uint32_t rxdes0_edorr;
-};
-
-#define TYPE_ASPEED_MII "aspeed-mmi"
-OBJECT_DECLARE_SIMPLE_TYPE(AspeedMiiState, ASPEED_MII)
-
-/*
- * AST2600 MII controller
- */
-struct AspeedMiiState {
- /*< private >*/
- SysBusDevice parent_obj;
-
- FTGMAC100State *nic;
-
- MemoryRegion iomem;
- uint32_t phycr;
- uint32_t phydata;
-};
-
-#endif
+++ /dev/null
-/*
- * i.MX FEC/ENET Ethernet Controller emulation.
- *
- * Copyright (c) 2013 Jean-Christophe Dubois. <jcd@tribudubois.net>
- *
- * Based on Coldfire Fast Ethernet Controller emulation.
- *
- * Copyright (c) 2007 CodeSourcery.
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License as published by the
- * Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
- * for more details.
- *
- * You should have received a copy of the GNU General Public License along
- * with this program; if not, see <http://www.gnu.org/licenses/>.
- */
-
-#ifndef IMX_FEC_H
-#define IMX_FEC_H
-#include "qom/object.h"
-
-#define TYPE_IMX_FEC "imx.fec"
-OBJECT_DECLARE_SIMPLE_TYPE(IMXFECState, IMX_FEC)
-
-#define TYPE_IMX_ENET "imx.enet"
-
-#include "hw/sysbus.h"
-#include "net/net.h"
-
-#define ENET_EIR 1
-#define ENET_EIMR 2
-#define ENET_RDAR 4
-#define ENET_TDAR 5
-#define ENET_ECR 9
-#define ENET_MMFR 16
-#define ENET_MSCR 17
-#define ENET_MIBC 25
-#define ENET_RCR 33
-#define ENET_TCR 49
-#define ENET_PALR 57
-#define ENET_PAUR 58
-#define ENET_OPD 59
-#define ENET_IAUR 70
-#define ENET_IALR 71
-#define ENET_GAUR 72
-#define ENET_GALR 73
-#define ENET_TFWR 81
-#define ENET_FRBR 83
-#define ENET_FRSR 84
-#define ENET_TDSR1 89
-#define ENET_TDSR2 92
-#define ENET_RDSR 96
-#define ENET_TDSR 97
-#define ENET_MRBR 98
-#define ENET_RSFL 100
-#define ENET_RSEM 101
-#define ENET_RAEM 102
-#define ENET_RAFL 103
-#define ENET_TSEM 104
-#define ENET_TAEM 105
-#define ENET_TAFL 106
-#define ENET_TIPG 107
-#define ENET_FTRL 108
-#define ENET_TACC 112
-#define ENET_RACC 113
-#define ENET_TDAR1 121
-#define ENET_TDAR2 123
-#define ENET_MIIGSK_CFGR 192
-#define ENET_MIIGSK_ENR 194
-#define ENET_ATCR 256
-#define ENET_ATVR 257
-#define ENET_ATOFF 258
-#define ENET_ATPER 259
-#define ENET_ATCOR 260
-#define ENET_ATINC 261
-#define ENET_ATSTMP 262
-#define ENET_TGSR 385
-#define ENET_TCSR0 386
-#define ENET_TCCR0 387
-#define ENET_TCSR1 388
-#define ENET_TCCR1 389
-#define ENET_TCSR2 390
-#define ENET_TCCR2 391
-#define ENET_TCSR3 392
-#define ENET_TCCR3 393
-#define ENET_MAX 400
-
-
-/* EIR and EIMR */
-#define ENET_INT_HB (1 << 31)
-#define ENET_INT_BABR (1 << 30)
-#define ENET_INT_BABT (1 << 29)
-#define ENET_INT_GRA (1 << 28)
-#define ENET_INT_TXF (1 << 27)
-#define ENET_INT_TXB (1 << 26)
-#define ENET_INT_RXF (1 << 25)
-#define ENET_INT_RXB (1 << 24)
-#define ENET_INT_MII (1 << 23)
-#define ENET_INT_EBERR (1 << 22)
-#define ENET_INT_LC (1 << 21)
-#define ENET_INT_RL (1 << 20)
-#define ENET_INT_UN (1 << 19)
-#define ENET_INT_PLR (1 << 18)
-#define ENET_INT_WAKEUP (1 << 17)
-#define ENET_INT_TS_AVAIL (1 << 16)
-#define ENET_INT_TS_TIMER (1 << 15)
-#define ENET_INT_TXF2 (1 << 7)
-#define ENET_INT_TXB2 (1 << 6)
-#define ENET_INT_TXF1 (1 << 3)
-#define ENET_INT_TXB1 (1 << 2)
-
-#define ENET_INT_MAC (ENET_INT_HB | ENET_INT_BABR | ENET_INT_BABT | \
- ENET_INT_GRA | ENET_INT_TXF | ENET_INT_TXB | \
- ENET_INT_RXF | ENET_INT_RXB | ENET_INT_MII | \
- ENET_INT_EBERR | ENET_INT_LC | ENET_INT_RL | \
- ENET_INT_UN | ENET_INT_PLR | ENET_INT_WAKEUP | \
- ENET_INT_TS_AVAIL | ENET_INT_TXF1 | \
- ENET_INT_TXB1 | ENET_INT_TXF2 | ENET_INT_TXB2)
-
-/* RDAR */
-#define ENET_RDAR_RDAR (1 << 24)
-
-/* TDAR */
-#define ENET_TDAR_TDAR (1 << 24)
-
-/* ECR */
-#define ENET_ECR_RESET (1 << 0)
-#define ENET_ECR_ETHEREN (1 << 1)
-#define ENET_ECR_MAGICEN (1 << 2)
-#define ENET_ECR_SLEEP (1 << 3)
-#define ENET_ECR_EN1588 (1 << 4)
-#define ENET_ECR_SPEED (1 << 5)
-#define ENET_ECR_DBGEN (1 << 6)
-#define ENET_ECR_STOPEN (1 << 7)
-#define ENET_ECR_DSBWP (1 << 8)
-
-/* MIBC */
-#define ENET_MIBC_MIB_DIS (1 << 31)
-#define ENET_MIBC_MIB_IDLE (1 << 30)
-#define ENET_MIBC_MIB_CLEAR (1 << 29)
-
-/* RCR */
-#define ENET_RCR_LOOP (1 << 0)
-#define ENET_RCR_DRT (1 << 1)
-#define ENET_RCR_MII_MODE (1 << 2)
-#define ENET_RCR_PROM (1 << 3)
-#define ENET_RCR_BC_REJ (1 << 4)
-#define ENET_RCR_FCE (1 << 5)
-#define ENET_RCR_RGMII_EN (1 << 6)
-#define ENET_RCR_RMII_MODE (1 << 8)
-#define ENET_RCR_RMII_10T (1 << 9)
-#define ENET_RCR_PADEN (1 << 12)
-#define ENET_RCR_PAUFWD (1 << 13)
-#define ENET_RCR_CRCFWD (1 << 14)
-#define ENET_RCR_CFEN (1 << 15)
-#define ENET_RCR_MAX_FL_SHIFT (16)
-#define ENET_RCR_MAX_FL_LENGTH (14)
-#define ENET_RCR_NLC (1 << 30)
-#define ENET_RCR_GRS (1 << 31)
-
-#define ENET_MAX_FRAME_SIZE (1 << ENET_RCR_MAX_FL_LENGTH)
-
-/* TCR */
-#define ENET_TCR_GTS (1 << 0)
-#define ENET_TCR_FDEN (1 << 2)
-#define ENET_TCR_TFC_PAUSE (1 << 3)
-#define ENET_TCR_RFC_PAUSE (1 << 4)
-#define ENET_TCR_ADDSEL_SHIFT (5)
-#define ENET_TCR_ADDSEL_LENGTH (3)
-#define ENET_TCR_CRCFWD (1 << 9)
-
-/* RDSR */
-#define ENET_TWFR_TFWR_SHIFT (0)
-#define ENET_TWFR_TFWR_LENGTH (6)
-#define ENET_TWFR_STRFWD (1 << 8)
-
-#define ENET_RACC_SHIFT16 BIT(7)
-
-/* Buffer Descriptor. */
-typedef struct {
- uint16_t length;
- uint16_t flags;
- uint32_t data;
-} IMXFECBufDesc;
-
-#define ENET_BD_R (1 << 15)
-#define ENET_BD_E (1 << 15)
-#define ENET_BD_O1 (1 << 14)
-#define ENET_BD_W (1 << 13)
-#define ENET_BD_O2 (1 << 12)
-#define ENET_BD_L (1 << 11)
-#define ENET_BD_TC (1 << 10)
-#define ENET_BD_ABC (1 << 9)
-#define ENET_BD_M (1 << 8)
-#define ENET_BD_BC (1 << 7)
-#define ENET_BD_MC (1 << 6)
-#define ENET_BD_LG (1 << 5)
-#define ENET_BD_NO (1 << 4)
-#define ENET_BD_CR (1 << 2)
-#define ENET_BD_OV (1 << 1)
-#define ENET_BD_TR (1 << 0)
-
-typedef struct {
- uint16_t length;
- uint16_t flags;
- uint32_t data;
- uint16_t status;
- uint16_t option;
- uint16_t checksum;
- uint16_t head_proto;
- uint32_t last_buffer;
- uint32_t timestamp;
- uint32_t reserved[2];
-} IMXENETBufDesc;
-
-#define ENET_BD_ME (1 << 15)
-#define ENET_BD_TX_INT (1 << 14)
-#define ENET_BD_TS (1 << 13)
-#define ENET_BD_PINS (1 << 12)
-#define ENET_BD_IINS (1 << 11)
-#define ENET_BD_PE (1 << 10)
-#define ENET_BD_CE (1 << 9)
-#define ENET_BD_UC (1 << 8)
-#define ENET_BD_RX_INT (1 << 7)
-
-#define ENET_BD_TXE (1 << 15)
-#define ENET_BD_UE (1 << 13)
-#define ENET_BD_EE (1 << 12)
-#define ENET_BD_FE (1 << 11)
-#define ENET_BD_LCE (1 << 10)
-#define ENET_BD_OE (1 << 9)
-#define ENET_BD_TSE (1 << 8)
-#define ENET_BD_ICE (1 << 5)
-#define ENET_BD_PCR (1 << 4)
-#define ENET_BD_VLAN (1 << 2)
-#define ENET_BD_IPV6 (1 << 1)
-#define ENET_BD_FRAG (1 << 0)
-
-#define ENET_BD_BDU (1 << 31)
-
-#define ENET_TX_RING_NUM 3
-
-#define FSL_IMX25_FEC_SIZE 0x4000
-
-struct IMXFECState {
- /*< private >*/
- SysBusDevice parent_obj;
-
- /*< public >*/
- NICState *nic;
- NICConf conf;
- qemu_irq irq[2];
- MemoryRegion iomem;
-
- uint32_t regs[ENET_MAX];
- uint32_t rx_descriptor;
-
- uint32_t tx_descriptor[ENET_TX_RING_NUM];
- uint32_t tx_ring_num;
-
- uint32_t phy_status;
- uint32_t phy_control;
- uint32_t phy_advertise;
- uint32_t phy_int;
- uint32_t phy_int_mask;
- uint32_t phy_num;
-
- bool is_fec;
-
- /* Buffer used to assemble a Tx frame */
- uint8_t frame[ENET_MAX_FRAME_SIZE];
-};
-
-#endif
+++ /dev/null
-/*
- * SMSC LAN9118 Ethernet interface emulation
- *
- * Copyright (c) 2009 CodeSourcery, LLC.
- * Written by Paul Brook
- *
- * This work is licensed under the terms of the GNU GPL, version 2 or later.
- * See the COPYING file in the top-level directory.
- */
-
-#ifndef HW_NET_LAN9118_H
-#define HW_NET_LAN9118_H
-
-#include "net/net.h"
-
-#define TYPE_LAN9118 "lan9118"
-
-void lan9118_init(NICInfo *, uint32_t, qemu_irq);
-
-#endif
+++ /dev/null
-/*
- * QEMU Lance (Am7990) device emulation
- *
- * Copyright (c) 2004 Antony T Curtis
- * Copyright (c) 2017 Mark Cave-Ayland
- *
- * This represents the Sparc32 lance (Am7990) ethernet device which is an
- * earlier register-compatible member of the AMD PC-Net II (Am79C970A) family.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
- * furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
- * THE SOFTWARE.
- */
-
-#ifndef LANCE_H
-#define LANCE_H
-
-#include "net/net.h"
-#include "hw/net/pcnet.h"
-#include "hw/sysbus.h"
-#include "qom/object.h"
-
-#define TYPE_LANCE "lance"
-typedef struct SysBusPCNetState SysBusPCNetState;
-DECLARE_INSTANCE_CHECKER(SysBusPCNetState, SYSBUS_PCNET,
- TYPE_LANCE)
-
-struct SysBusPCNetState {
- SysBusDevice parent_obj;
-
- PCNetState state;
-};
-
-#endif
+++ /dev/null
-/*
- * QEMU LASI i82596 device emulation
- *
- * Copyright (c) 201 Helge Deller <deller@gmx.de>
- *
- */
-
-#ifndef LASI_82596_H
-#define LASI_82596_H
-
-#include "net/net.h"
-#include "hw/net/i82596.h"
-#include "qom/object.h"
-
-#define TYPE_LASI_82596 "lasi_82596"
-typedef struct SysBusI82596State SysBusI82596State;
-DECLARE_INSTANCE_CHECKER(SysBusI82596State, SYSBUS_I82596,
- TYPE_LASI_82596)
-
-struct SysBusI82596State {
- SysBusDevice parent_obj;
-
- I82596State state;
- uint16_t last_val;
- int val_index:1;
-};
-
-SysBusI82596State *lasi_82596_init(MemoryRegion *addr_space,
- hwaddr hpa, qemu_irq irq);
-
-#endif
+++ /dev/null
-/*
- * Common network MII address and register definitions.
- *
- * Copyright (C) 2014 Beniamino Galvani <b.galvani@gmail.com>
- *
- * Allwinner EMAC register definitions from Linux kernel are:
- * Copyright 2012 Stefan Roese <sr@denx.de>
- * Copyright 2013 Maxime Ripard <maxime.ripard@free-electrons.com>
- * Copyright 1997 Sten Wang
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * version 2 as published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- */
-#ifndef MII_H
-#define MII_H
-
-/* PHY registers */
-#define MII_BMCR 0 /* Basic mode control register */
-#define MII_BMSR 1 /* Basic mode status register */
-#define MII_PHYID1 2 /* ID register 1 */
-#define MII_PHYID2 3 /* ID register 2 */
-#define MII_ANAR 4 /* Autonegotiation advertisement */
-#define MII_ANLPAR 5 /* Autonegotiation lnk partner abilities */
-#define MII_ANER 6 /* Autonegotiation expansion */
-#define MII_ANNP 7 /* Autonegotiation next page */
-#define MII_ANLPRNP 8 /* Autonegotiation link partner rx next page */
-#define MII_CTRL1000 9 /* 1000BASE-T control */
-#define MII_STAT1000 10 /* 1000BASE-T status */
-#define MII_MDDACR 13 /* MMD access control */
-#define MII_MDDAADR 14 /* MMD access address data */
-#define MII_EXTSTAT 15 /* Extended Status */
-#define MII_NSR 16
-#define MII_LBREMR 17
-#define MII_REC 18
-#define MII_SNRDR 19
-#define MII_TEST 25
-
-/* PHY registers fields */
-#define MII_BMCR_RESET (1 << 15)
-#define MII_BMCR_LOOPBACK (1 << 14)
-#define MII_BMCR_SPEED100 (1 << 13) /* LSB of Speed (100) */
-#define MII_BMCR_SPEED MII_BMCR_SPEED100
-#define MII_BMCR_AUTOEN (1 << 12) /* Autonegotiation enable */
-#define MII_BMCR_PDOWN (1 << 11) /* Enable low power state */
-#define MII_BMCR_ISOLATE (1 << 10) /* Isolate data paths from MII */
-#define MII_BMCR_ANRESTART (1 << 9) /* Auto negotiation restart */
-#define MII_BMCR_FD (1 << 8) /* Set duplex mode */
-#define MII_BMCR_CTST (1 << 7) /* Collision test */
-#define MII_BMCR_SPEED1000 (1 << 6) /* MSB of Speed (1000) */
-
-#define MII_BMSR_100TX_FD (1 << 14) /* Can do 100mbps, full-duplex */
-#define MII_BMSR_100TX_HD (1 << 13) /* Can do 100mbps, half-duplex */
-#define MII_BMSR_10T_FD (1 << 12) /* Can do 10mbps, full-duplex */
-#define MII_BMSR_10T_HD (1 << 11) /* Can do 10mbps, half-duplex */
-#define MII_BMSR_100T2_FD (1 << 10) /* Can do 100mbps T2, full-duplex */
-#define MII_BMSR_100T2_HD (1 << 9) /* Can do 100mbps T2, half-duplex */
-#define MII_BMSR_EXTSTAT (1 << 8) /* Extended status in register 15 */
-#define MII_BMSR_MFPS (1 << 6) /* MII Frame Preamble Suppression */
-#define MII_BMSR_AN_COMP (1 << 5) /* Auto-negotiation complete */
-#define MII_BMSR_RFAULT (1 << 4) /* Remote fault */
-#define MII_BMSR_AUTONEG (1 << 3) /* Able to do auto-negotiation */
-#define MII_BMSR_LINK_ST (1 << 2) /* Link status */
-#define MII_BMSR_JABBER (1 << 1) /* Jabber detected */
-#define MII_BMSR_EXTCAP (1 << 0) /* Ext-reg capability */
-
-#define MII_ANAR_PAUSE_ASYM (1 << 11) /* Try for asymetric pause */
-#define MII_ANAR_PAUSE (1 << 10) /* Try for pause */
-#define MII_ANAR_TXFD (1 << 8)
-#define MII_ANAR_TX (1 << 7)
-#define MII_ANAR_10FD (1 << 6)
-#define MII_ANAR_10 (1 << 5)
-#define MII_ANAR_CSMACD (1 << 0)
-
-#define MII_ANLPAR_ACK (1 << 14)
-#define MII_ANLPAR_PAUSEASY (1 << 11) /* can pause asymmetrically */
-#define MII_ANLPAR_PAUSE (1 << 10) /* can pause */
-#define MII_ANLPAR_TXFD (1 << 8)
-#define MII_ANLPAR_TX (1 << 7)
-#define MII_ANLPAR_10FD (1 << 6)
-#define MII_ANLPAR_10 (1 << 5)
-#define MII_ANLPAR_CSMACD (1 << 0)
-
-#define MII_ANER_NWAY (1 << 0) /* Can do N-way auto-nego */
-
-#define MII_CTRL1000_FULL (1 << 9) /* 1000BASE-T full duplex */
-#define MII_CTRL1000_HALF (1 << 8) /* 1000BASE-T half duplex */
-
-#define MII_STAT1000_FULL (1 << 11) /* 1000BASE-T full duplex */
-#define MII_STAT1000_HALF (1 << 10) /* 1000BASE-T half duplex */
-
-/* List of vendor identifiers */
-/* RealTek 8201 */
-#define RTL8201CP_PHYID1 0x0000
-#define RTL8201CP_PHYID2 0x8201
-
-/* RealTek 8211E */
-#define RTL8211E_PHYID1 0x001c
-#define RTL8211E_PHYID2 0xc915
-
-/* National Semiconductor DP83840 */
-#define DP83840_PHYID1 0x2000
-#define DP83840_PHYID2 0x5c01
-
-/* National Semiconductor DP83848 */
-#define DP83848_PHYID1 0x2000
-#define DP83848_PHYID2 0x5c90
-
-#endif /* MII_H */
+++ /dev/null
-/*
- * QEMU model of the Smartfusion2 Ethernet MAC.
- *
- * Copyright (c) 2020 Subbaraya Sundeep <sundeep.lkml@gmail.com>.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
- * furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
- * THE SOFTWARE.
- */
-
-#include "hw/sysbus.h"
-#include "exec/memory.h"
-#include "net/net.h"
-#include "net/eth.h"
-#include "qom/object.h"
-
-#define TYPE_MSS_EMAC "msf2-emac"
-OBJECT_DECLARE_SIMPLE_TYPE(MSF2EmacState, MSS_EMAC)
-
-#define R_MAX (0x1a0 / 4)
-#define PHY_MAX_REGS 32
-
-struct MSF2EmacState {
- SysBusDevice parent;
-
- MemoryRegion mmio;
- MemoryRegion *dma_mr;
- AddressSpace dma_as;
-
- qemu_irq irq;
- NICState *nic;
- NICConf conf;
-
- uint8_t mac_addr[ETH_ALEN];
- uint32_t rx_desc;
- uint16_t phy_regs[PHY_MAX_REGS];
-
- uint32_t regs[R_MAX];
-};
+++ /dev/null
-/*
- * QEMU NE2000 emulation -- isa bus windup
- *
- * Copyright (c) 2003-2004 Fabrice Bellard
- *
- * This work is licensed under the terms of the GNU GPL, version 2 or later.
- * See the COPYING file in the top-level directory.
- */
-
-#ifndef HW_NET_NE2000_ISA_H
-#define HW_NET_NE2000_ISA_H
-
-#include "hw/isa/isa.h"
-#include "hw/qdev-properties.h"
-#include "net/net.h"
-#include "qapi/error.h"
-
-#define TYPE_ISA_NE2000 "ne2k_isa"
-
-static inline ISADevice *isa_ne2000_init(ISABus *bus, int base, int irq,
- NICInfo *nd)
-{
- ISADevice *d;
-
- qemu_check_nic_model(nd, "ne2k_isa");
-
- d = isa_try_new(TYPE_ISA_NE2000);
- if (d) {
- DeviceState *dev = DEVICE(d);
-
- qdev_prop_set_uint32(dev, "iobase", base);
- qdev_prop_set_uint32(dev, "irq", irq);
- qdev_set_nic_properties(dev, nd);
- isa_realize_and_unref(d, bus, &error_fatal);
- }
- return d;
-}
-
-#endif
+++ /dev/null
-/*
- * SMSC 91C111 Ethernet interface emulation
- *
- * Copyright (c) 2005 CodeSourcery, LLC.
- * Written by Paul Brook
- *
- * This work is licensed under the terms of the GNU GPL, version 2 or later.
- * See the COPYING file in the top-level directory.
- */
-
-#ifndef HW_NET_SMC91C111_H
-#define HW_NET_SMC91C111_H
-
-#include "net/net.h"
-
-void smc91c111_init(NICInfo *, uint32_t, qemu_irq);
-
-#endif
+++ /dev/null
-/*
- * Copyright (c) 2013-2018 Laurent Vivier <laurent@vivier.eu>
- *
- * This work is licensed under the terms of the GNU GPL, version 2 or later.
- * See the COPYING file in the top-level directory.
- *
- */
-
-#ifndef HW_NUBUS_MAC_H
-#define HW_NUBUS_MAC_H
-
-#include "hw/nubus/nubus.h"
-#include "qom/object.h"
-
-#define TYPE_MAC_NUBUS_BRIDGE "mac-nubus-bridge"
-OBJECT_DECLARE_SIMPLE_TYPE(MacNubusState, MAC_NUBUS_BRIDGE)
-
-struct MacNubusState {
- SysBusDevice sysbus_dev;
-
- NubusBus *bus;
-};
-
-#endif
+++ /dev/null
-/*
- * Copyright (c) 2013-2018 Laurent Vivier <laurent@vivier.eu>
- *
- * This work is licensed under the terms of the GNU GPL, version 2 or later.
- * See the COPYING file in the top-level directory.
- *
- */
-
-#ifndef HW_NUBUS_NUBUS_H
-#define HW_NUBUS_NUBUS_H
-
-#include "hw/qdev-properties.h"
-#include "exec/address-spaces.h"
-#include "qom/object.h"
-
-#define NUBUS_SUPER_SLOT_SIZE 0x10000000U
-#define NUBUS_SUPER_SLOT_NB 0x9
-
-#define NUBUS_SLOT_SIZE 0x01000000
-#define NUBUS_SLOT_NB 0xF
-
-#define NUBUS_FIRST_SLOT 0x9
-#define NUBUS_LAST_SLOT 0xF
-
-#define TYPE_NUBUS_DEVICE "nubus-device"
-OBJECT_DECLARE_SIMPLE_TYPE(NubusDevice, NUBUS_DEVICE)
-
-#define TYPE_NUBUS_BUS "nubus-bus"
-OBJECT_DECLARE_SIMPLE_TYPE(NubusBus, NUBUS_BUS)
-
-#define TYPE_NUBUS_BRIDGE "nubus-bridge"
-
-struct NubusBus {
- BusState qbus;
-
- MemoryRegion super_slot_io;
- MemoryRegion slot_io;
-
- int current_slot;
-};
-
-struct NubusDevice {
- DeviceState qdev;
-
- int slot_nb;
- MemoryRegion slot_mem;
-
- /* Format Block */
-
- MemoryRegion fblock_io;
-
- uint32_t rom_length;
- uint32_t rom_crc;
- uint8_t rom_rev;
- uint8_t rom_format;
- uint8_t byte_lanes;
- int32_t directory_offset;
-
- /* ROM */
-
- MemoryRegion rom_io;
- const uint8_t *rom;
-};
-
-void nubus_register_rom(NubusDevice *dev, const uint8_t *rom, uint32_t size,
- int revision, int format, uint8_t byte_lanes);
-
-#endif
+++ /dev/null
-/*
- * QEMU Simba PCI bridge
- *
- * Copyright (c) 2006 Fabrice Bellard
- * Copyright (c) 2012,2013 Artyom Tarasenko
- * Copyright (c) 2017 Mark Cave-Ayland
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
- * furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
- * THE SOFTWARE.
- */
-
-#ifndef HW_PCI_BRIDGE_SIMBA_H
-#define HW_PCI_BRIDGE_SIMBA_H
-
-#include "hw/pci/pci_bridge.h"
-#include "qom/object.h"
-
-
-struct SimbaPCIBridge {
- /*< private >*/
- PCIBridge parent_obj;
-};
-
-#define TYPE_SIMBA_PCI_BRIDGE "pbm-bridge"
-OBJECT_DECLARE_SIMPLE_TYPE(SimbaPCIBridge, SIMBA_PCI_BRIDGE)
-
-#endif
+++ /dev/null
-/*
- * QEMU PowerPC helper routines for the device tree.
- *
- * Copyright (C) 2016 IBM Corp.
- *
- * This code is licensed under the GPL version 2 or later. See the
- * COPYING file in the top-level directory.
- */
-
-#ifndef PPC_FDT_H
-#define PPC_FDT_H
-
-#include "qemu/error-report.h"
-#include "target/ppc/cpu-qom.h"
-
-#define _FDT(exp) \
- do { \
- int ret = (exp); \
- if (ret < 0) { \
- error_report("error creating device tree: %s: %s", \
- #exp, fdt_strerror(ret)); \
- exit(1); \
- } \
- } while (0)
-
-size_t ppc_create_page_sizes_prop(PowerPCCPU *cpu, uint32_t *prop,
- size_t maxsize);
-
-#endif /* PPC_FDT_H */
+++ /dev/null
-/*
- * Copyright (c) 2009 Laurent Vivier
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
- * furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
- * THE SOFTWARE.
- */
-
-#ifndef HW_MAC_DBDMA_H
-#define HW_MAC_DBDMA_H
-
-#include "exec/memory.h"
-#include "qemu/iov.h"
-#include "sysemu/dma.h"
-#include "hw/sysbus.h"
-#include "qom/object.h"
-
-typedef struct DBDMA_io DBDMA_io;
-
-typedef void (*DBDMA_flush)(DBDMA_io *io);
-typedef void (*DBDMA_rw)(DBDMA_io *io);
-typedef void (*DBDMA_end)(DBDMA_io *io);
-struct DBDMA_io {
- void *opaque;
- void *channel;
- hwaddr addr;
- int len;
- int is_last;
- int is_dma_out;
- DBDMA_end dma_end;
- /* DMA is in progress, don't start another one */
- bool processing;
- /* DMA request */
- void *dma_mem;
- dma_addr_t dma_len;
- DMADirection dir;
-};
-
-/*
- * DBDMA control/status registers. All little-endian.
- */
-
-#define DBDMA_CONTROL 0x00
-#define DBDMA_STATUS 0x01
-#define DBDMA_CMDPTR_HI 0x02
-#define DBDMA_CMDPTR_LO 0x03
-#define DBDMA_INTR_SEL 0x04
-#define DBDMA_BRANCH_SEL 0x05
-#define DBDMA_WAIT_SEL 0x06
-#define DBDMA_XFER_MODE 0x07
-#define DBDMA_DATA2PTR_HI 0x08
-#define DBDMA_DATA2PTR_LO 0x09
-#define DBDMA_RES1 0x0A
-#define DBDMA_ADDRESS_HI 0x0B
-#define DBDMA_BRANCH_ADDR_HI 0x0C
-#define DBDMA_RES2 0x0D
-#define DBDMA_RES3 0x0E
-#define DBDMA_RES4 0x0F
-
-#define DBDMA_REGS 16
-#define DBDMA_SIZE (DBDMA_REGS * sizeof(uint32_t))
-
-#define DBDMA_CHANNEL_SHIFT 7
-#define DBDMA_CHANNEL_SIZE (1 << DBDMA_CHANNEL_SHIFT)
-
-#define DBDMA_CHANNELS (0x1000 >> DBDMA_CHANNEL_SHIFT)
-
-/* Bits in control and status registers */
-
-#define RUN 0x8000
-#define PAUSE 0x4000
-#define FLUSH 0x2000
-#define WAKE 0x1000
-#define DEAD 0x0800
-#define ACTIVE 0x0400
-#define BT 0x0100
-#define DEVSTAT 0x00ff
-
-/*
- * DBDMA command structure. These fields are all little-endian!
- */
-
-typedef struct dbdma_cmd {
- uint16_t req_count; /* requested byte transfer count */
- uint16_t command; /* command word (has bit-fields) */
- uint32_t phy_addr; /* physical data address */
- uint32_t cmd_dep; /* command-dependent field */
- uint16_t res_count; /* residual count after completion */
- uint16_t xfer_status; /* transfer status */
-} dbdma_cmd;
-
-/* DBDMA command values in command field */
-
-#define COMMAND_MASK 0xf000
-#define OUTPUT_MORE 0x0000 /* transfer memory data to stream */
-#define OUTPUT_LAST 0x1000 /* ditto followed by end marker */
-#define INPUT_MORE 0x2000 /* transfer stream data to memory */
-#define INPUT_LAST 0x3000 /* ditto, expect end marker */
-#define STORE_WORD 0x4000 /* write word (4 bytes) to device reg */
-#define LOAD_WORD 0x5000 /* read word (4 bytes) from device reg */
-#define DBDMA_NOP 0x6000 /* do nothing */
-#define DBDMA_STOP 0x7000 /* suspend processing */
-
-/* Key values in command field */
-
-#define KEY_MASK 0x0700
-#define KEY_STREAM0 0x0000 /* usual data stream */
-#define KEY_STREAM1 0x0100 /* control/status stream */
-#define KEY_STREAM2 0x0200 /* device-dependent stream */
-#define KEY_STREAM3 0x0300 /* device-dependent stream */
-#define KEY_STREAM4 0x0400 /* reserved */
-#define KEY_REGS 0x0500 /* device register space */
-#define KEY_SYSTEM 0x0600 /* system memory-mapped space */
-#define KEY_DEVICE 0x0700 /* device memory-mapped space */
-
-/* Interrupt control values in command field */
-
-#define INTR_MASK 0x0030
-#define INTR_NEVER 0x0000 /* don't interrupt */
-#define INTR_IFSET 0x0010 /* intr if condition bit is 1 */
-#define INTR_IFCLR 0x0020 /* intr if condition bit is 0 */
-#define INTR_ALWAYS 0x0030 /* always interrupt */
-
-/* Branch control values in command field */
-
-#define BR_MASK 0x000c
-#define BR_NEVER 0x0000 /* don't branch */
-#define BR_IFSET 0x0004 /* branch if condition bit is 1 */
-#define BR_IFCLR 0x0008 /* branch if condition bit is 0 */
-#define BR_ALWAYS 0x000c /* always branch */
-
-/* Wait control values in command field */
-
-#define WAIT_MASK 0x0003
-#define WAIT_NEVER 0x0000 /* don't wait */
-#define WAIT_IFSET 0x0001 /* wait if condition bit is 1 */
-#define WAIT_IFCLR 0x0002 /* wait if condition bit is 0 */
-#define WAIT_ALWAYS 0x0003 /* always wait */
-
-typedef struct DBDMA_channel {
- int channel;
- uint32_t regs[DBDMA_REGS];
- qemu_irq irq;
- DBDMA_io io;
- DBDMA_rw rw;
- DBDMA_flush flush;
- dbdma_cmd current;
-} DBDMA_channel;
-
-struct DBDMAState {
- SysBusDevice parent_obj;
-
- MemoryRegion mem;
- DBDMA_channel channels[DBDMA_CHANNELS];
- QEMUBH *bh;
-};
-typedef struct DBDMAState DBDMAState;
-
-/* Externally callable functions */
-
-void DBDMA_register_channel(void *dbdma, int nchan, qemu_irq irq,
- DBDMA_rw rw, DBDMA_flush flush,
- void *opaque);
-void DBDMA_kick(DBDMAState *dbdma);
-
-#define TYPE_MAC_DBDMA "mac-dbdma"
-OBJECT_DECLARE_SIMPLE_TYPE(DBDMAState, MAC_DBDMA)
-
-#endif
+++ /dev/null
-#ifndef OPENPIC_H
-#define OPENPIC_H
-
-#include "hw/sysbus.h"
-#include "hw/core/cpu.h"
-#include "qom/object.h"
-
-#define MAX_CPU 32
-#define MAX_MSI 8
-#define VID 0x03 /* MPIC version ID */
-
-/* OpenPIC have 5 outputs per CPU connected and one IRQ out single output */
-enum {
- OPENPIC_OUTPUT_INT = 0, /* IRQ */
- OPENPIC_OUTPUT_CINT, /* critical IRQ */
- OPENPIC_OUTPUT_MCK, /* Machine check event */
- OPENPIC_OUTPUT_DEBUG, /* Inconditional debug event */
- OPENPIC_OUTPUT_RESET, /* Core reset event */
- OPENPIC_OUTPUT_NB,
-};
-
-typedef struct IrqLines { qemu_irq irq[OPENPIC_OUTPUT_NB]; } IrqLines;
-
-#define OPENPIC_MODEL_RAVEN 0
-#define OPENPIC_MODEL_FSL_MPIC_20 1
-#define OPENPIC_MODEL_FSL_MPIC_42 2
-#define OPENPIC_MODEL_KEYLARGO 3
-
-#define OPENPIC_MAX_SRC 256
-#define OPENPIC_MAX_TMR 4
-#define OPENPIC_MAX_IPI 4
-#define OPENPIC_MAX_IRQ (OPENPIC_MAX_SRC + OPENPIC_MAX_IPI + \
- OPENPIC_MAX_TMR)
-
-/* Raven */
-#define RAVEN_MAX_CPU 2
-#define RAVEN_MAX_EXT 48
-#define RAVEN_MAX_IRQ 64
-#define RAVEN_MAX_TMR OPENPIC_MAX_TMR
-#define RAVEN_MAX_IPI OPENPIC_MAX_IPI
-
-/* KeyLargo */
-#define KEYLARGO_MAX_CPU 4
-#define KEYLARGO_MAX_EXT 64
-#define KEYLARGO_MAX_IPI 4
-#define KEYLARGO_MAX_IRQ (64 + KEYLARGO_MAX_IPI)
-#define KEYLARGO_MAX_TMR 0
-#define KEYLARGO_IPI_IRQ (KEYLARGO_MAX_EXT) /* First IPI IRQ */
-/* Timers don't exist but this makes the code happy... */
-#define KEYLARGO_TMR_IRQ (KEYLARGO_IPI_IRQ + KEYLARGO_MAX_IPI)
-
-/* Interrupt definitions */
-#define RAVEN_FE_IRQ (RAVEN_MAX_EXT) /* Internal functional IRQ */
-#define RAVEN_ERR_IRQ (RAVEN_MAX_EXT + 1) /* Error IRQ */
-#define RAVEN_TMR_IRQ (RAVEN_MAX_EXT + 2) /* First timer IRQ */
-#define RAVEN_IPI_IRQ (RAVEN_TMR_IRQ + RAVEN_MAX_TMR) /* First IPI IRQ */
-/* First doorbell IRQ */
-#define RAVEN_DBL_IRQ (RAVEN_IPI_IRQ + (RAVEN_MAX_CPU * RAVEN_MAX_IPI))
-
-typedef struct FslMpicInfo {
- int max_ext;
-} FslMpicInfo;
-
-typedef enum IRQType {
- IRQ_TYPE_NORMAL = 0,
- IRQ_TYPE_FSLINT, /* FSL internal interrupt -- level only */
- IRQ_TYPE_FSLSPECIAL, /* FSL timer/IPI interrupt, edge, no polarity */
-} IRQType;
-
-/* Round up to the nearest 64 IRQs so that the queue length
- * won't change when moving between 32 and 64 bit hosts.
- */
-#define IRQQUEUE_SIZE_BITS ((OPENPIC_MAX_IRQ + 63) & ~63)
-
-typedef struct IRQQueue {
- unsigned long *queue;
- int32_t queue_size; /* Only used for VMSTATE_BITMAP */
- int next;
- int priority;
-} IRQQueue;
-
-typedef struct IRQSource {
- uint32_t ivpr; /* IRQ vector/priority register */
- uint32_t idr; /* IRQ destination register */
- uint32_t destmask; /* bitmap of CPU destinations */
- int last_cpu;
- int output; /* IRQ level, e.g. OPENPIC_OUTPUT_INT */
- int pending; /* TRUE if IRQ is pending */
- IRQType type;
- bool level:1; /* level-triggered */
- bool nomask:1; /* critical interrupts ignore mask on some FSL MPICs */
-} IRQSource;
-
-#define IVPR_MASK_SHIFT 31
-#define IVPR_MASK_MASK (1U << IVPR_MASK_SHIFT)
-#define IVPR_ACTIVITY_SHIFT 30
-#define IVPR_ACTIVITY_MASK (1U << IVPR_ACTIVITY_SHIFT)
-#define IVPR_MODE_SHIFT 29
-#define IVPR_MODE_MASK (1U << IVPR_MODE_SHIFT)
-#define IVPR_POLARITY_SHIFT 23
-#define IVPR_POLARITY_MASK (1U << IVPR_POLARITY_SHIFT)
-#define IVPR_SENSE_SHIFT 22
-#define IVPR_SENSE_MASK (1U << IVPR_SENSE_SHIFT)
-
-#define IVPR_PRIORITY_MASK (0xFU << 16)
-#define IVPR_PRIORITY(_ivprr_) ((int)(((_ivprr_) & IVPR_PRIORITY_MASK) >> 16))
-#define IVPR_VECTOR(opp, _ivprr_) ((_ivprr_) & (opp)->vector_mask)
-
-/* IDR[EP/CI] are only for FSL MPIC prior to v4.0 */
-#define IDR_EP 0x80000000 /* external pin */
-#define IDR_CI 0x40000000 /* critical interrupt */
-
-typedef struct OpenPICTimer {
- uint32_t tccr; /* Global timer current count register */
- uint32_t tbcr; /* Global timer base count register */
- int n_IRQ;
- bool qemu_timer_active; /* Is the qemu_timer is running? */
- struct QEMUTimer *qemu_timer;
- struct OpenPICState *opp; /* Device timer is part of. */
- /* The QEMU_CLOCK_VIRTUAL time (in ns) corresponding to the last
- current_count written or read, only defined if qemu_timer_active. */
- uint64_t origin_time;
-} OpenPICTimer;
-
-typedef struct OpenPICMSI {
- uint32_t msir; /* Shared Message Signaled Interrupt Register */
-} OpenPICMSI;
-
-typedef struct IRQDest {
- int32_t ctpr; /* CPU current task priority */
- IRQQueue raised;
- IRQQueue servicing;
- qemu_irq *irqs;
-
- /* Count of IRQ sources asserting on non-INT outputs */
- uint32_t outputs_active[OPENPIC_OUTPUT_NB];
-} IRQDest;
-
-#define TYPE_OPENPIC "openpic"
-OBJECT_DECLARE_SIMPLE_TYPE(OpenPICState, OPENPIC)
-
-struct OpenPICState {
- /*< private >*/
- SysBusDevice parent_obj;
- /*< public >*/
-
- MemoryRegion mem;
-
- /* Behavior control */
- FslMpicInfo *fsl;
- uint32_t model;
- uint32_t flags;
- uint32_t nb_irqs;
- uint32_t vid;
- uint32_t vir; /* Vendor identification register */
- uint32_t vector_mask;
- uint32_t tfrr_reset;
- uint32_t ivpr_reset;
- uint32_t idr_reset;
- uint32_t brr1;
- uint32_t mpic_mode_mask;
-
- /* Sub-regions */
- MemoryRegion sub_io_mem[6];
-
- /* Global registers */
- uint32_t frr; /* Feature reporting register */
- uint32_t gcr; /* Global configuration register */
- uint32_t pir; /* Processor initialization register */
- uint32_t spve; /* Spurious vector register */
- uint32_t tfrr; /* Timer frequency reporting register */
- /* Source registers */
- IRQSource src[OPENPIC_MAX_IRQ];
- /* Local registers per output pin */
- IRQDest dst[MAX_CPU];
- uint32_t nb_cpus;
- /* Timer registers */
- OpenPICTimer timers[OPENPIC_MAX_TMR];
- uint32_t max_tmr;
-
- /* Shared MSI registers */
- OpenPICMSI msi[MAX_MSI];
- uint32_t max_irq;
- uint32_t irq_ipi0;
- uint32_t irq_tim0;
- uint32_t irq_msi;
-};
-
-#endif /* OPENPIC_H */
+++ /dev/null
-#ifndef OPENPIC_KVM_H
-#define OPENPIC_KVM_H
-
-#define TYPE_KVM_OPENPIC "kvm-openpic"
-int kvm_openpic_connect_vcpu(DeviceState *d, CPUState *cs);
-
-#endif /* OPENPIC_KVM_H */
+++ /dev/null
-/*
- * QEMU PowerPC PowerNV various definitions
- *
- * Copyright (c) 2014-2016 BenH, IBM Corporation.
- *
- * This library is free software; you can redistribute it and/or
- * modify it under the terms of the GNU Lesser General Public
- * License as published by the Free Software Foundation; either
- * version 2.1 of the License, or (at your option) any later version.
- *
- * This library is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
- * Lesser General Public License for more details.
- *
- * You should have received a copy of the GNU Lesser General Public
- * License along with this library; if not, see <http://www.gnu.org/licenses/>.
- */
-
-#ifndef PPC_PNV_H
-#define PPC_PNV_H
-
-#include "hw/boards.h"
-#include "hw/sysbus.h"
-#include "hw/ipmi/ipmi.h"
-#include "hw/ppc/pnv_lpc.h"
-#include "hw/ppc/pnv_pnor.h"
-#include "hw/ppc/pnv_psi.h"
-#include "hw/ppc/pnv_occ.h"
-#include "hw/ppc/pnv_homer.h"
-#include "hw/ppc/pnv_xive.h"
-#include "hw/ppc/pnv_core.h"
-#include "hw/pci-host/pnv_phb3.h"
-#include "hw/pci-host/pnv_phb4.h"
-#include "qom/object.h"
-
-#define TYPE_PNV_CHIP "pnv-chip"
-OBJECT_DECLARE_TYPE(PnvChip, PnvChipClass,
- PNV_CHIP)
-
-struct PnvChip {
- /*< private >*/
- SysBusDevice parent_obj;
-
- /*< public >*/
- uint32_t chip_id;
- uint64_t ram_start;
- uint64_t ram_size;
-
- uint32_t nr_cores;
- uint32_t nr_threads;
- uint64_t cores_mask;
- PnvCore **cores;
-
- uint32_t num_phbs;
-
- MemoryRegion xscom_mmio;
- MemoryRegion xscom;
- AddressSpace xscom_as;
-
- gchar *dt_isa_nodename;
-};
-
-#define TYPE_PNV8_CHIP "pnv8-chip"
-typedef struct Pnv8Chip Pnv8Chip;
-DECLARE_INSTANCE_CHECKER(Pnv8Chip, PNV8_CHIP,
- TYPE_PNV8_CHIP)
-
-struct Pnv8Chip {
- /*< private >*/
- PnvChip parent_obj;
-
- /*< public >*/
- MemoryRegion icp_mmio;
-
- PnvLpcController lpc;
- Pnv8Psi psi;
- PnvOCC occ;
- PnvHomer homer;
-
-#define PNV8_CHIP_PHB3_MAX 4
- PnvPHB3 phbs[PNV8_CHIP_PHB3_MAX];
-
- XICSFabric *xics;
-};
-
-#define TYPE_PNV9_CHIP "pnv9-chip"
-typedef struct Pnv9Chip Pnv9Chip;
-DECLARE_INSTANCE_CHECKER(Pnv9Chip, PNV9_CHIP,
- TYPE_PNV9_CHIP)
-
-struct Pnv9Chip {
- /*< private >*/
- PnvChip parent_obj;
-
- /*< public >*/
- PnvXive xive;
- Pnv9Psi psi;
- PnvLpcController lpc;
- PnvOCC occ;
- PnvHomer homer;
-
- uint32_t nr_quads;
- PnvQuad *quads;
-
-#define PNV9_CHIP_MAX_PEC 3
- PnvPhb4PecState pecs[PNV9_CHIP_MAX_PEC];
-};
-
-/*
- * A SMT8 fused core is a pair of SMT4 cores.
- */
-#define PNV9_PIR2FUSEDCORE(pir) (((pir) >> 3) & 0xf)
-#define PNV9_PIR2CHIP(pir) (((pir) >> 8) & 0x7f)
-
-#define TYPE_PNV10_CHIP "pnv10-chip"
-typedef struct Pnv10Chip Pnv10Chip;
-DECLARE_INSTANCE_CHECKER(Pnv10Chip, PNV10_CHIP,
- TYPE_PNV10_CHIP)
-
-struct Pnv10Chip {
- /*< private >*/
- PnvChip parent_obj;
-
- /*< public >*/
- Pnv9Psi psi;
- PnvLpcController lpc;
-};
-
-struct PnvChipClass {
- /*< private >*/
- SysBusDeviceClass parent_class;
-
- /*< public >*/
- uint64_t chip_cfam_id;
- uint64_t cores_mask;
- uint32_t num_phbs;
-
- DeviceRealize parent_realize;
-
- uint32_t (*core_pir)(PnvChip *chip, uint32_t core_id);
- void (*intc_create)(PnvChip *chip, PowerPCCPU *cpu, Error **errp);
- void (*intc_reset)(PnvChip *chip, PowerPCCPU *cpu);
- void (*intc_destroy)(PnvChip *chip, PowerPCCPU *cpu);
- void (*intc_print_info)(PnvChip *chip, PowerPCCPU *cpu, Monitor *mon);
- ISABus *(*isa_create)(PnvChip *chip, Error **errp);
- void (*dt_populate)(PnvChip *chip, void *fdt);
- void (*pic_print_info)(PnvChip *chip, Monitor *mon);
- uint64_t (*xscom_core_base)(PnvChip *chip, uint32_t core_id);
- uint32_t (*xscom_pcba)(PnvChip *chip, uint64_t addr);
-};
-
-#define PNV_CHIP_TYPE_SUFFIX "-" TYPE_PNV_CHIP
-#define PNV_CHIP_TYPE_NAME(cpu_model) cpu_model PNV_CHIP_TYPE_SUFFIX
-
-#define TYPE_PNV_CHIP_POWER8E PNV_CHIP_TYPE_NAME("power8e_v2.1")
-DECLARE_INSTANCE_CHECKER(PnvChip, PNV_CHIP_POWER8E,
- TYPE_PNV_CHIP_POWER8E)
-
-#define TYPE_PNV_CHIP_POWER8 PNV_CHIP_TYPE_NAME("power8_v2.0")
-DECLARE_INSTANCE_CHECKER(PnvChip, PNV_CHIP_POWER8,
- TYPE_PNV_CHIP_POWER8)
-
-#define TYPE_PNV_CHIP_POWER8NVL PNV_CHIP_TYPE_NAME("power8nvl_v1.0")
-DECLARE_INSTANCE_CHECKER(PnvChip, PNV_CHIP_POWER8NVL,
- TYPE_PNV_CHIP_POWER8NVL)
-
-#define TYPE_PNV_CHIP_POWER9 PNV_CHIP_TYPE_NAME("power9_v2.0")
-DECLARE_INSTANCE_CHECKER(PnvChip, PNV_CHIP_POWER9,
- TYPE_PNV_CHIP_POWER9)
-
-#define TYPE_PNV_CHIP_POWER10 PNV_CHIP_TYPE_NAME("power10_v1.0")
-DECLARE_INSTANCE_CHECKER(PnvChip, PNV_CHIP_POWER10,
- TYPE_PNV_CHIP_POWER10)
-
-/*
- * This generates a HW chip id depending on an index, as found on a
- * two socket system with dual chip modules :
- *
- * 0x0, 0x1, 0x10, 0x11
- *
- * 4 chips should be the maximum
- *
- * TODO: use a machine property to define the chip ids
- */
-#define PNV_CHIP_HWID(i) ((((i) & 0x3e) << 3) | ((i) & 0x1))
-
-/*
- * Converts back a HW chip id to an index. This is useful to calculate
- * the MMIO addresses of some controllers which depend on the chip id.
- */
-#define PNV_CHIP_INDEX(chip) \
- (((chip)->chip_id >> 2) * 2 + ((chip)->chip_id & 0x3))
-
-PowerPCCPU *pnv_chip_find_cpu(PnvChip *chip, uint32_t pir);
-
-#define TYPE_PNV_MACHINE MACHINE_TYPE_NAME("powernv")
-typedef struct PnvMachineClass PnvMachineClass;
-typedef struct PnvMachineState PnvMachineState;
-DECLARE_OBJ_CHECKERS(PnvMachineState, PnvMachineClass,
- PNV_MACHINE, TYPE_PNV_MACHINE)
-
-
-struct PnvMachineClass {
- /*< private >*/
- MachineClass parent_class;
-
- /*< public >*/
- const char *compat;
- int compat_size;
-
- void (*dt_power_mgt)(PnvMachineState *pnv, void *fdt);
-};
-
-struct PnvMachineState {
- /*< private >*/
- MachineState parent_obj;
-
- uint32_t initrd_base;
- long initrd_size;
-
- uint32_t num_chips;
- PnvChip **chips;
-
- ISABus *isa_bus;
- uint32_t cpld_irqstate;
-
- IPMIBmc *bmc;
- Notifier powerdown_notifier;
-
- PnvPnor *pnor;
-
- hwaddr fw_load_addr;
-};
-
-#define PNV_FDT_ADDR 0x01000000
-#define PNV_TIMEBASE_FREQ 512000000ULL
-
-/*
- * BMC helpers
- */
-void pnv_dt_bmc_sensors(IPMIBmc *bmc, void *fdt);
-void pnv_bmc_powerdown(IPMIBmc *bmc);
-IPMIBmc *pnv_bmc_create(PnvPnor *pnor);
-IPMIBmc *pnv_bmc_find(Error **errp);
-void pnv_bmc_set_pnor(IPMIBmc *bmc, PnvPnor *pnor);
-
-/*
- * POWER8 MMIO base addresses
- */
-#define PNV_XSCOM_SIZE 0x800000000ull
-#define PNV_XSCOM_BASE(chip) \
- (0x0003fc0000000000ull + ((uint64_t)(chip)->chip_id) * PNV_XSCOM_SIZE)
-
-#define PNV_OCC_COMMON_AREA_SIZE 0x0000000000800000ull
-#define PNV_OCC_COMMON_AREA_BASE 0x7fff800000ull
-#define PNV_OCC_SENSOR_BASE(chip) (PNV_OCC_COMMON_AREA_BASE + \
- PNV_OCC_SENSOR_DATA_BLOCK_BASE(PNV_CHIP_INDEX(chip)))
-
-#define PNV_HOMER_SIZE 0x0000000000400000ull
-#define PNV_HOMER_BASE(chip) \
- (0x7ffd800000ull + ((uint64_t)PNV_CHIP_INDEX(chip)) * PNV_HOMER_SIZE)
-
-
-/*
- * XSCOM 0x20109CA defines the ICP BAR:
- *
- * 0:29 : bits 14 to 43 of address to define 1 MB region.
- * 30 : 1 to enable ICP to receive loads/stores against its BAR region
- * 31:63 : Constant 0
- *
- * Usually defined as :
- *
- * 0xffffe00200000000 -> 0x0003ffff80000000
- * 0xffffe00600000000 -> 0x0003ffff80100000
- * 0xffffe02200000000 -> 0x0003ffff80800000
- * 0xffffe02600000000 -> 0x0003ffff80900000
- */
-#define PNV_ICP_SIZE 0x0000000000100000ull
-#define PNV_ICP_BASE(chip) \
- (0x0003ffff80000000ull + (uint64_t) PNV_CHIP_INDEX(chip) * PNV_ICP_SIZE)
-
-
-#define PNV_PSIHB_SIZE 0x0000000000100000ull
-#define PNV_PSIHB_BASE(chip) \
- (0x0003fffe80000000ull + (uint64_t)PNV_CHIP_INDEX(chip) * PNV_PSIHB_SIZE)
-
-#define PNV_PSIHB_FSP_SIZE 0x0000000100000000ull
-#define PNV_PSIHB_FSP_BASE(chip) \
- (0x0003ffe000000000ull + (uint64_t)PNV_CHIP_INDEX(chip) * \
- PNV_PSIHB_FSP_SIZE)
-
-/*
- * POWER9 MMIO base addresses
- */
-#define PNV9_CHIP_BASE(chip, base) \
- ((base) + ((uint64_t) (chip)->chip_id << 42))
-
-#define PNV9_XIVE_VC_SIZE 0x0000008000000000ull
-#define PNV9_XIVE_VC_BASE(chip) PNV9_CHIP_BASE(chip, 0x0006010000000000ull)
-
-#define PNV9_XIVE_PC_SIZE 0x0000001000000000ull
-#define PNV9_XIVE_PC_BASE(chip) PNV9_CHIP_BASE(chip, 0x0006018000000000ull)
-
-#define PNV9_LPCM_SIZE 0x0000000100000000ull
-#define PNV9_LPCM_BASE(chip) PNV9_CHIP_BASE(chip, 0x0006030000000000ull)
-
-#define PNV9_PSIHB_SIZE 0x0000000000100000ull
-#define PNV9_PSIHB_BASE(chip) PNV9_CHIP_BASE(chip, 0x0006030203000000ull)
-
-#define PNV9_XIVE_IC_SIZE 0x0000000000080000ull
-#define PNV9_XIVE_IC_BASE(chip) PNV9_CHIP_BASE(chip, 0x0006030203100000ull)
-
-#define PNV9_XIVE_TM_SIZE 0x0000000000040000ull
-#define PNV9_XIVE_TM_BASE(chip) PNV9_CHIP_BASE(chip, 0x0006030203180000ull)
-
-#define PNV9_PSIHB_ESB_SIZE 0x0000000000010000ull
-#define PNV9_PSIHB_ESB_BASE(chip) PNV9_CHIP_BASE(chip, 0x00060302031c0000ull)
-
-#define PNV9_XSCOM_SIZE 0x0000000400000000ull
-#define PNV9_XSCOM_BASE(chip) PNV9_CHIP_BASE(chip, 0x00603fc00000000ull)
-
-#define PNV9_OCC_COMMON_AREA_SIZE 0x0000000000800000ull
-#define PNV9_OCC_COMMON_AREA_BASE 0x203fff800000ull
-#define PNV9_OCC_SENSOR_BASE(chip) (PNV9_OCC_COMMON_AREA_BASE + \
- PNV_OCC_SENSOR_DATA_BLOCK_BASE(PNV_CHIP_INDEX(chip)))
-
-#define PNV9_HOMER_SIZE 0x0000000000400000ull
-#define PNV9_HOMER_BASE(chip) \
- (0x203ffd800000ull + ((uint64_t)PNV_CHIP_INDEX(chip)) * PNV9_HOMER_SIZE)
-
-/*
- * POWER10 MMIO base addresses - 16TB stride per chip
- */
-#define PNV10_CHIP_BASE(chip, base) \
- ((base) + ((uint64_t) (chip)->chip_id << 44))
-
-#define PNV10_XSCOM_SIZE 0x0000000400000000ull
-#define PNV10_XSCOM_BASE(chip) PNV10_CHIP_BASE(chip, 0x00603fc00000000ull)
-
-#define PNV10_LPCM_SIZE 0x0000000100000000ull
-#define PNV10_LPCM_BASE(chip) PNV10_CHIP_BASE(chip, 0x0006030000000000ull)
-
-#define PNV10_PSIHB_ESB_SIZE 0x0000000000100000ull
-#define PNV10_PSIHB_ESB_BASE(chip) PNV10_CHIP_BASE(chip, 0x0006030202000000ull)
-
-#define PNV10_PSIHB_SIZE 0x0000000000100000ull
-#define PNV10_PSIHB_BASE(chip) PNV10_CHIP_BASE(chip, 0x0006030203000000ull)
-
-#endif /* PPC_PNV_H */
+++ /dev/null
-/*
- * QEMU PowerPC PowerNV CPU Core model
- *
- * Copyright (c) 2016, IBM Corporation.
- *
- * This library is free software; you can redistribute it and/or
- * modify it under the terms of the GNU Lesser General Public License
- * as published by the Free Software Foundation; either version 2.1 of
- * the License, or (at your option) any later version.
- *
- * This library is distributed in the hope that it will be useful, but
- * WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
- * Lesser General Public License for more details.
- *
- * You should have received a copy of the GNU Lesser General Public
- * License along with this library; if not, see <http://www.gnu.org/licenses/>.
- */
-
-#ifndef PPC_PNV_CORE_H
-#define PPC_PNV_CORE_H
-
-#include "hw/cpu/core.h"
-#include "target/ppc/cpu.h"
-#include "qom/object.h"
-
-#define TYPE_PNV_CORE "powernv-cpu-core"
-OBJECT_DECLARE_TYPE(PnvCore, PnvCoreClass,
- PNV_CORE)
-
-typedef struct PnvChip PnvChip;
-
-struct PnvCore {
- /*< private >*/
- CPUCore parent_obj;
-
- /*< public >*/
- PowerPCCPU **threads;
- uint32_t pir;
- uint64_t hrmor;
- PnvChip *chip;
-
- MemoryRegion xscom_regs;
-};
-
-struct PnvCoreClass {
- DeviceClass parent_class;
-
- const MemoryRegionOps *xscom_ops;
-};
-
-#define PNV_CORE_TYPE_SUFFIX "-" TYPE_PNV_CORE
-#define PNV_CORE_TYPE_NAME(cpu_model) cpu_model PNV_CORE_TYPE_SUFFIX
-
-typedef struct PnvCPUState {
- Object *intc;
-} PnvCPUState;
-
-static inline PnvCPUState *pnv_cpu_state(PowerPCCPU *cpu)
-{
- return (PnvCPUState *)cpu->machine_data;
-}
-
-#define TYPE_PNV_QUAD "powernv-cpu-quad"
-OBJECT_DECLARE_SIMPLE_TYPE(PnvQuad, PNV_QUAD)
-
-struct PnvQuad {
- DeviceState parent_obj;
-
- uint32_t id;
- MemoryRegion xscom_regs;
-};
-#endif /* PPC_PNV_CORE_H */
+++ /dev/null
-/*
- * QEMU PowerPC PowerNV Emulation of a few HOMER related registers
- *
- * Copyright (c) 2019, IBM Corporation.
- *
- * This library is free software; you can redistribute it and/or
- * modify it under the terms of the GNU Lesser General Public
- * License as published by the Free Software Foundation; either
- * version 2.1 of the License, or (at your option) any later version.
- *
- * This library is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
- * Lesser General Public License for more details.
- *
- * You should have received a copy of the GNU Lesser General Public
- * License along with this library; if not, see <http://www.gnu.org/licenses/>.
- */
-
-#ifndef PPC_PNV_HOMER_H
-#define PPC_PNV_HOMER_H
-
-#include "hw/ppc/pnv.h"
-#include "qom/object.h"
-
-#define TYPE_PNV_HOMER "pnv-homer"
-OBJECT_DECLARE_TYPE(PnvHomer, PnvHomerClass,
- PNV_HOMER)
-#define TYPE_PNV8_HOMER TYPE_PNV_HOMER "-POWER8"
-DECLARE_INSTANCE_CHECKER(PnvHomer, PNV8_HOMER,
- TYPE_PNV8_HOMER)
-#define TYPE_PNV9_HOMER TYPE_PNV_HOMER "-POWER9"
-DECLARE_INSTANCE_CHECKER(PnvHomer, PNV9_HOMER,
- TYPE_PNV9_HOMER)
-
-struct PnvHomer {
- DeviceState parent;
-
- struct PnvChip *chip;
- MemoryRegion pba_regs;
- MemoryRegion regs;
-};
-
-
-struct PnvHomerClass {
- DeviceClass parent_class;
-
- int pba_size;
- const MemoryRegionOps *pba_ops;
- int homer_size;
- const MemoryRegionOps *homer_ops;
-
- hwaddr core_max_base;
-};
-
-#endif /* PPC_PNV_HOMER_H */
+++ /dev/null
-/*
- * QEMU PowerPC PowerNV LPC controller
- *
- * Copyright (c) 2016, IBM Corporation.
- *
- * This library is free software; you can redistribute it and/or
- * modify it under the terms of the GNU Lesser General Public
- * License as published by the Free Software Foundation; either
- * version 2.1 of the License, or (at your option) any later version.
- *
- * This library is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
- * Lesser General Public License for more details.
- *
- * You should have received a copy of the GNU Lesser General Public
- * License along with this library; if not, see <http://www.gnu.org/licenses/>.
- */
-
-#ifndef PPC_PNV_LPC_H
-#define PPC_PNV_LPC_H
-
-#include "hw/ppc/pnv_psi.h"
-#include "qom/object.h"
-
-#define TYPE_PNV_LPC "pnv-lpc"
-typedef struct PnvLpcClass PnvLpcClass;
-typedef struct PnvLpcController PnvLpcController;
-DECLARE_OBJ_CHECKERS(PnvLpcController, PnvLpcClass,
- PNV_LPC, TYPE_PNV_LPC)
-#define TYPE_PNV8_LPC TYPE_PNV_LPC "-POWER8"
-DECLARE_INSTANCE_CHECKER(PnvLpcController, PNV8_LPC,
- TYPE_PNV8_LPC)
-
-#define TYPE_PNV9_LPC TYPE_PNV_LPC "-POWER9"
-DECLARE_INSTANCE_CHECKER(PnvLpcController, PNV9_LPC,
- TYPE_PNV9_LPC)
-
-#define TYPE_PNV10_LPC TYPE_PNV_LPC "-POWER10"
-DECLARE_INSTANCE_CHECKER(PnvLpcController, PNV10_LPC,
- TYPE_PNV10_LPC)
-
-struct PnvLpcController {
- DeviceState parent;
-
- uint64_t eccb_stat_reg;
- uint32_t eccb_data_reg;
-
- /* OPB bus */
- MemoryRegion opb_mr;
- AddressSpace opb_as;
-
- /* ISA IO and Memory space */
- MemoryRegion isa_io;
- MemoryRegion isa_mem;
- MemoryRegion isa_fw;
-
- /* Windows from OPB to ISA (aliases) */
- MemoryRegion opb_isa_io;
- MemoryRegion opb_isa_mem;
- MemoryRegion opb_isa_fw;
-
- /* Registers */
- MemoryRegion lpc_hc_regs;
- MemoryRegion opb_master_regs;
-
- /* OPB Master LS registers */
- uint32_t opb_irq_route0;
- uint32_t opb_irq_route1;
- uint32_t opb_irq_stat;
- uint32_t opb_irq_mask;
- uint32_t opb_irq_pol;
- uint32_t opb_irq_input;
-
- /* LPC HC registers */
- uint32_t lpc_hc_fw_seg_idsel;
- uint32_t lpc_hc_fw_rd_acc_size;
- uint32_t lpc_hc_irqser_ctrl;
- uint32_t lpc_hc_irqmask;
- uint32_t lpc_hc_irqstat;
- uint32_t lpc_hc_error_addr;
-
- /* XSCOM registers */
- MemoryRegion xscom_regs;
-
- /* PSI to generate interrupts */
- PnvPsi *psi;
-};
-
-
-struct PnvLpcClass {
- DeviceClass parent_class;
-
- int psi_irq;
-
- DeviceRealize parent_realize;
-};
-
-/*
- * Old compilers error on typdef forward declarations. Keep them happy.
- */
-struct PnvChip;
-
-ISABus *pnv_lpc_isa_create(PnvLpcController *lpc, bool use_cpld, Error **errp);
-int pnv_dt_lpc(struct PnvChip *chip, void *fdt, int root_offset,
- uint64_t lpcm_addr, uint64_t lpcm_size);
-
-#endif /* PPC_PNV_LPC_H */
+++ /dev/null
-/*
- * QEMU PowerPC PowerNV Emulation of a few OCC related registers
- *
- * Copyright (c) 2015-2017, IBM Corporation.
- *
- * This library is free software; you can redistribute it and/or
- * modify it under the terms of the GNU Lesser General Public
- * License as published by the Free Software Foundation; either
- * version 2.1 of the License, or (at your option) any later version.
- *
- * This library is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
- * Lesser General Public License for more details.
- *
- * You should have received a copy of the GNU Lesser General Public
- * License along with this library; if not, see <http://www.gnu.org/licenses/>.
- */
-
-#ifndef PPC_PNV_OCC_H
-#define PPC_PNV_OCC_H
-
-#include "hw/ppc/pnv_psi.h"
-#include "qom/object.h"
-
-#define TYPE_PNV_OCC "pnv-occ"
-OBJECT_DECLARE_TYPE(PnvOCC, PnvOCCClass,
- PNV_OCC)
-#define TYPE_PNV8_OCC TYPE_PNV_OCC "-POWER8"
-DECLARE_INSTANCE_CHECKER(PnvOCC, PNV8_OCC,
- TYPE_PNV8_OCC)
-#define TYPE_PNV9_OCC TYPE_PNV_OCC "-POWER9"
-DECLARE_INSTANCE_CHECKER(PnvOCC, PNV9_OCC,
- TYPE_PNV9_OCC)
-
-#define PNV_OCC_SENSOR_DATA_BLOCK_OFFSET 0x00580000
-#define PNV_OCC_SENSOR_DATA_BLOCK_SIZE 0x00025800
-
-struct PnvOCC {
- DeviceState xd;
-
- /* OCC Misc interrupt */
- uint64_t occmisc;
-
- PnvPsi *psi;
-
- MemoryRegion xscom_regs;
- MemoryRegion sram_regs;
-};
-
-
-struct PnvOCCClass {
- DeviceClass parent_class;
-
- int xscom_size;
- const MemoryRegionOps *xscom_ops;
- int psi_irq;
-};
-
-#define PNV_OCC_SENSOR_DATA_BLOCK_BASE(i) \
- (PNV_OCC_SENSOR_DATA_BLOCK_OFFSET + (i) * PNV_OCC_SENSOR_DATA_BLOCK_SIZE)
-
-#endif /* PPC_PNV_OCC_H */
+++ /dev/null
-/*
- * QEMU PowerNV PNOR simple model
- *
- * Copyright (c) 2019, IBM Corporation.
- *
- * This code is licensed under the GPL version 2 or later. See the
- * COPYING file in the top-level directory.
- */
-#ifndef _PPC_PNV_PNOR_H
-#define _PPC_PNV_PNOR_H
-#include "qom/object.h"
-
-/*
- * PNOR offset on the LPC FW address space
- */
-#define PNOR_SPI_OFFSET 0x0c000000UL
-
-#define TYPE_PNV_PNOR "pnv-pnor"
-OBJECT_DECLARE_SIMPLE_TYPE(PnvPnor, PNV_PNOR)
-
-struct PnvPnor {
- SysBusDevice parent_obj;
-
- BlockBackend *blk;
-
- uint8_t *storage;
- int64_t size;
- MemoryRegion mmio;
-};
-
-#endif /* _PPC_PNV_PNOR_H */
+++ /dev/null
-/*
- * QEMU PowerPC PowerNV Processor Service Interface (PSI) model
- *
- * Copyright (c) 2015-2017, IBM Corporation.
- *
- * This library is free software; you can redistribute it and/or
- * modify it under the terms of the GNU Lesser General Public
- * License as published by the Free Software Foundation; either
- * version 2.1 of the License, or (at your option) any later version.
- *
- * This library is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
- * Lesser General Public License for more details.
- *
- * You should have received a copy of the GNU Lesser General Public
- * License along with this library; if not, see <http://www.gnu.org/licenses/>.
- */
-
-#ifndef PPC_PNV_PSI_H
-#define PPC_PNV_PSI_H
-
-#include "hw/sysbus.h"
-#include "hw/ppc/xics.h"
-#include "hw/ppc/xive.h"
-#include "qom/object.h"
-
-#define TYPE_PNV_PSI "pnv-psi"
-OBJECT_DECLARE_TYPE(PnvPsi, PnvPsiClass,
- PNV_PSI)
-
-#define PSIHB_XSCOM_MAX 0x20
-
-struct PnvPsi {
- DeviceState parent;
-
- MemoryRegion regs_mr;
- uint64_t bar;
-
- /* FSP region not supported */
- /* MemoryRegion fsp_mr; */
- uint64_t fsp_bar;
-
- /* Interrupt generation */
- qemu_irq *qirqs;
-
- /* Registers */
- uint64_t regs[PSIHB_XSCOM_MAX];
-
- MemoryRegion xscom_regs;
-};
-
-#define TYPE_PNV8_PSI TYPE_PNV_PSI "-POWER8"
-OBJECT_DECLARE_SIMPLE_TYPE(Pnv8Psi, PNV8_PSI)
-
-struct Pnv8Psi {
- PnvPsi parent;
-
- ICSState ics;
-};
-
-#define TYPE_PNV9_PSI TYPE_PNV_PSI "-POWER9"
-OBJECT_DECLARE_SIMPLE_TYPE(Pnv9Psi, PNV9_PSI)
-
-struct Pnv9Psi {
- PnvPsi parent;
-
- XiveSource source;
-};
-
-#define TYPE_PNV10_PSI TYPE_PNV_PSI "-POWER10"
-
-
-struct PnvPsiClass {
- SysBusDeviceClass parent_class;
-
- uint32_t xscom_pcba;
- uint32_t xscom_size;
- uint64_t bar_mask;
- const char *compat;
- int compat_size;
-
- void (*irq_set)(PnvPsi *psi, int, bool state);
-};
-
-/* The PSI and FSP interrupts are muxed on the same IRQ number */
-typedef enum PnvPsiIrq {
- PSIHB_IRQ_PSI, /* internal use only */
- PSIHB_IRQ_FSP, /* internal use only */
- PSIHB_IRQ_OCC,
- PSIHB_IRQ_FSI,
- PSIHB_IRQ_LPC_I2C,
- PSIHB_IRQ_LOCAL_ERR,
- PSIHB_IRQ_EXTERNAL,
-} PnvPsiIrq;
-
-#define PSI_NUM_INTERRUPTS 6
-
-void pnv_psi_irq_set(PnvPsi *psi, int irq, bool state);
-
-/* P9 PSI Interrupts */
-#define PSIHB9_IRQ_PSI 0
-#define PSIHB9_IRQ_OCC 1
-#define PSIHB9_IRQ_FSI 2
-#define PSIHB9_IRQ_LPCHC 3
-#define PSIHB9_IRQ_LOCAL_ERR 4
-#define PSIHB9_IRQ_GLOBAL_ERR 5
-#define PSIHB9_IRQ_TPM 6
-#define PSIHB9_IRQ_LPC_SIRQ0 7
-#define PSIHB9_IRQ_LPC_SIRQ1 8
-#define PSIHB9_IRQ_LPC_SIRQ2 9
-#define PSIHB9_IRQ_LPC_SIRQ3 10
-#define PSIHB9_IRQ_SBE_I2C 11
-#define PSIHB9_IRQ_DIO 12
-#define PSIHB9_IRQ_PSU 13
-#define PSIHB9_NUM_IRQS 14
-
-void pnv_psi_pic_print_info(Pnv9Psi *psi, Monitor *mon);
-
-#endif /* PPC_PNV_PSI_H */
+++ /dev/null
-/*
- * QEMU PowerPC XIVE interrupt controller model
- *
- * Copyright (c) 2017-2019, IBM Corporation.
- *
- * This code is licensed under the GPL version 2 or later. See the
- * COPYING file in the top-level directory.
- */
-
-#ifndef PPC_PNV_XIVE_H
-#define PPC_PNV_XIVE_H
-
-#include "hw/ppc/xive.h"
-#include "qom/object.h"
-
-struct PnvChip;
-
-#define TYPE_PNV_XIVE "pnv-xive"
-OBJECT_DECLARE_TYPE(PnvXive, PnvXiveClass,
- PNV_XIVE)
-
-#define XIVE_BLOCK_MAX 16
-
-#define XIVE_TABLE_BLK_MAX 16 /* Block Scope Table (0-15) */
-#define XIVE_TABLE_MIG_MAX 16 /* Migration Register Table (1-15) */
-#define XIVE_TABLE_VDT_MAX 16 /* VDT Domain Table (0-15) */
-#define XIVE_TABLE_EDT_MAX 64 /* EDT Domain Table (0-63) */
-
-struct PnvXive {
- XiveRouter parent_obj;
-
- /* Owning chip */
- struct PnvChip *chip;
-
- /* XSCOM addresses giving access to the controller registers */
- MemoryRegion xscom_regs;
-
- /* Main MMIO regions that can be configured by FW */
- MemoryRegion ic_mmio;
- MemoryRegion ic_reg_mmio;
- MemoryRegion ic_notify_mmio;
- MemoryRegion ic_lsi_mmio;
- MemoryRegion tm_indirect_mmio;
- MemoryRegion vc_mmio;
- MemoryRegion pc_mmio;
- MemoryRegion tm_mmio;
-
- /*
- * IPI and END address spaces modeling the EDT segmentation in the
- * VC region
- */
- AddressSpace ipi_as;
- MemoryRegion ipi_mmio;
- MemoryRegion ipi_edt_mmio;
-
- AddressSpace end_as;
- MemoryRegion end_mmio;
- MemoryRegion end_edt_mmio;
-
- /* Shortcut values for the Main MMIO regions */
- hwaddr ic_base;
- uint32_t ic_shift;
- hwaddr vc_base;
- uint32_t vc_shift;
- hwaddr pc_base;
- uint32_t pc_shift;
- hwaddr tm_base;
- uint32_t tm_shift;
-
- /* Our XIVE source objects for IPIs and ENDs */
- XiveSource ipi_source;
- XiveENDSource end_source;
-
- /* Interrupt controller registers */
- uint64_t regs[0x300];
-
- /*
- * Virtual Structure Descriptor tables : EAT, SBE, ENDT, NVTT, IRQ
- * These are in a SRAM protected by ECC.
- */
- uint64_t vsds[5][XIVE_BLOCK_MAX];
-
- /* Translation tables */
- uint64_t blk[XIVE_TABLE_BLK_MAX];
- uint64_t mig[XIVE_TABLE_MIG_MAX];
- uint64_t vdt[XIVE_TABLE_VDT_MAX];
- uint64_t edt[XIVE_TABLE_EDT_MAX];
-};
-
-struct PnvXiveClass {
- XiveRouterClass parent_class;
-
- DeviceRealize parent_realize;
-};
-
-void pnv_xive_pic_print_info(PnvXive *xive, Monitor *mon);
-
-#endif /* PPC_PNV_XIVE_H */
+++ /dev/null
-/*
- * QEMU PowerPC PowerNV XSCOM bus definitions
- *
- * Copyright (c) 2016, IBM Corporation.
- *
- * This library is free software; you can redistribute it and/or
- * modify it under the terms of the GNU Lesser General Public
- * License as published by the Free Software Foundation; either
- * version 2.1 of the License, or (at your option) any later version.
- *
- * This library is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
- * Lesser General Public License for more details.
- *
- * You should have received a copy of the GNU Lesser General Public
- * License along with this library; if not, see <http://www.gnu.org/licenses/>.
- */
-
-#ifndef PPC_PNV_XSCOM_H
-#define PPC_PNV_XSCOM_H
-
-#include "qom/object.h"
-
-typedef struct PnvXScomInterface PnvXScomInterface;
-
-#define TYPE_PNV_XSCOM_INTERFACE "pnv-xscom-interface"
-#define PNV_XSCOM_INTERFACE(obj) \
- INTERFACE_CHECK(PnvXScomInterface, (obj), TYPE_PNV_XSCOM_INTERFACE)
-typedef struct PnvXScomInterfaceClass PnvXScomInterfaceClass;
-DECLARE_CLASS_CHECKERS(PnvXScomInterfaceClass, PNV_XSCOM_INTERFACE,
- TYPE_PNV_XSCOM_INTERFACE)
-
-struct PnvXScomInterfaceClass {
- InterfaceClass parent;
- int (*dt_xscom)(PnvXScomInterface *dev, void *fdt, int offset);
-};
-
-/*
- * Layout of the XSCOM PCB addresses of EX core 1 (POWER 8)
- *
- * GPIO 0x1100xxxx
- * SCOM 0x1101xxxx
- * OHA 0x1102xxxx
- * CLOCK CTL 0x1103xxxx
- * FIR 0x1104xxxx
- * THERM 0x1105xxxx
- * <reserved> 0x1106xxxx
- * ..
- * 0x110Exxxx
- * PCB SLAVE 0x110Fxxxx
- */
-
-#define PNV_XSCOM_EX_CORE_BASE 0x10000000ull
-
-#define PNV_XSCOM_EX_BASE(core) \
- (PNV_XSCOM_EX_CORE_BASE | ((uint64_t)(core) << 24))
-#define PNV_XSCOM_EX_SIZE 0x100000
-
-#define PNV_XSCOM_LPC_BASE 0xb0020
-#define PNV_XSCOM_LPC_SIZE 0x4
-
-#define PNV_XSCOM_PSIHB_BASE 0x2010900
-#define PNV_XSCOM_PSIHB_SIZE 0x20
-
-#define PNV_XSCOM_OCC_BASE 0x0066000
-#define PNV_XSCOM_OCC_SIZE 0x6000
-
-#define PNV_XSCOM_PBA_BASE 0x2013f00
-#define PNV_XSCOM_PBA_SIZE 0x40
-
-#define PNV_XSCOM_PBCQ_NEST_BASE 0x2012000
-#define PNV_XSCOM_PBCQ_NEST_SIZE 0x46
-
-#define PNV_XSCOM_PBCQ_PCI_BASE 0x9012000
-#define PNV_XSCOM_PBCQ_PCI_SIZE 0x15
-
-#define PNV_XSCOM_PBCQ_SPCI_BASE 0x9013c00
-#define PNV_XSCOM_PBCQ_SPCI_SIZE 0x5
-
-/*
- * Layout of the XSCOM PCB addresses (POWER 9)
- */
-#define PNV9_XSCOM_EC_BASE(core) \
- ((uint64_t)(((core) & 0x1F) + 0x20) << 24)
-#define PNV9_XSCOM_EC_SIZE 0x100000
-
-#define PNV9_XSCOM_EQ_BASE(core) \
- ((uint64_t)(((core) & 0x1C) + 0x40) << 22)
-#define PNV9_XSCOM_EQ_SIZE 0x100000
-
-#define PNV9_XSCOM_OCC_BASE PNV_XSCOM_OCC_BASE
-#define PNV9_XSCOM_OCC_SIZE 0x8000
-
-#define PNV9_XSCOM_PBA_BASE 0x5012b00
-#define PNV9_XSCOM_PBA_SIZE 0x40
-
-#define PNV9_XSCOM_PSIHB_BASE 0x5012900
-#define PNV9_XSCOM_PSIHB_SIZE 0x100
-
-#define PNV9_XSCOM_XIVE_BASE 0x5013000
-#define PNV9_XSCOM_XIVE_SIZE 0x300
-
-#define PNV9_XSCOM_PEC_NEST_BASE 0x4010c00
-#define PNV9_XSCOM_PEC_NEST_SIZE 0x100
-
-#define PNV9_XSCOM_PEC_PCI_BASE 0xd010800
-#define PNV9_XSCOM_PEC_PCI_SIZE 0x200
-
-/* XSCOM PCI "pass-through" window to PHB SCOM */
-#define PNV9_XSCOM_PEC_PCI_STK0 0x100
-#define PNV9_XSCOM_PEC_PCI_STK1 0x140
-#define PNV9_XSCOM_PEC_PCI_STK2 0x180
-
-/*
- * Layout of the XSCOM PCB addresses (POWER 10)
- */
-#define PNV10_XSCOM_EQ_CHIPLET(core) (0x20 + ((core) >> 2))
-#define PNV10_XSCOM_EQ(chiplet) ((chiplet) << 24)
-#define PNV10_XSCOM_EC(proc) \
- ((0x2 << 16) | ((1 << (3 - (proc))) << 12))
-
-#define PNV10_XSCOM_EQ_BASE(core) \
- ((uint64_t) PNV10_XSCOM_EQ(PNV10_XSCOM_EQ_CHIPLET(core)))
-#define PNV10_XSCOM_EQ_SIZE 0x100000
-
-#define PNV10_XSCOM_EC_BASE(core) \
- ((uint64_t) PNV10_XSCOM_EQ_BASE(core) | PNV10_XSCOM_EC(core & 0x3))
-#define PNV10_XSCOM_EC_SIZE 0x100000
-
-#define PNV10_XSCOM_PSIHB_BASE 0x3011D00
-#define PNV10_XSCOM_PSIHB_SIZE 0x100
-
-void pnv_xscom_realize(PnvChip *chip, uint64_t size, Error **errp);
-int pnv_dt_xscom(PnvChip *chip, void *fdt, int root_offset,
- uint64_t xscom_base, uint64_t xscom_size,
- const char *compat, int compat_size);
-
-void pnv_xscom_add_subregion(PnvChip *chip, hwaddr offset,
- MemoryRegion *mr);
-void pnv_xscom_region_init(MemoryRegion *mr,
- struct Object *owner,
- const MemoryRegionOps *ops,
- void *opaque,
- const char *name,
- uint64_t size);
-
-#endif /* PPC_PNV_XSCOM_H */
+++ /dev/null
-#ifndef HW_PPC_H
-#define HW_PPC_H
-
-#include "target/ppc/cpu-qom.h"
-
-void ppc_set_irq(PowerPCCPU *cpu, int n_IRQ, int level);
-PowerPCCPU *ppc_get_vcpu_by_pir(int pir);
-int ppc_cpu_pir(PowerPCCPU *cpu);
-
-/* PowerPC hardware exceptions management helpers */
-typedef void (*clk_setup_cb)(void *opaque, uint32_t freq);
-typedef struct clk_setup_t clk_setup_t;
-struct clk_setup_t {
- clk_setup_cb cb;
- void *opaque;
-};
-static inline void clk_setup (clk_setup_t *clk, uint32_t freq)
-{
- if (clk->cb != NULL)
- (*clk->cb)(clk->opaque, freq);
-}
-
-struct ppc_tb_t {
- /* Time base management */
- int64_t tb_offset; /* Compensation */
- int64_t atb_offset; /* Compensation */
- int64_t vtb_offset;
- uint32_t tb_freq; /* TB frequency */
- /* Decrementer management */
- uint64_t decr_next; /* Tick for next decr interrupt */
- uint32_t decr_freq; /* decrementer frequency */
- QEMUTimer *decr_timer;
- /* Hypervisor decrementer management */
- uint64_t hdecr_next; /* Tick for next hdecr interrupt */
- QEMUTimer *hdecr_timer;
- int64_t purr_offset;
- void *opaque;
- uint32_t flags;
-};
-
-/* PPC Timers flags */
-#define PPC_TIMER_BOOKE (1 << 0) /* Enable Booke support */
-#define PPC_TIMER_E500 (1 << 1) /* Enable e500 support */
-#define PPC_DECR_UNDERFLOW_TRIGGERED (1 << 2) /* Decr interrupt triggered when
- * the most significant bit
- * changes from 0 to 1.
- */
-#define PPC_DECR_ZERO_TRIGGERED (1 << 3) /* Decr interrupt triggered when
- * the decrementer reaches zero.
- */
-#define PPC_DECR_UNDERFLOW_LEVEL (1 << 4) /* Decr interrupt active when
- * the most significant bit is 1.
- */
-
-uint64_t cpu_ppc_get_tb(ppc_tb_t *tb_env, uint64_t vmclk, int64_t tb_offset);
-clk_setup_cb cpu_ppc_tb_init (CPUPPCState *env, uint32_t freq);
-/* Embedded PowerPC DCR management */
-typedef uint32_t (*dcr_read_cb)(void *opaque, int dcrn);
-typedef void (*dcr_write_cb)(void *opaque, int dcrn, uint32_t val);
-int ppc_dcr_init (CPUPPCState *env, int (*dcr_read_error)(int dcrn),
- int (*dcr_write_error)(int dcrn));
-int ppc_dcr_register (CPUPPCState *env, int dcrn, void *opaque,
- dcr_read_cb drc_read, dcr_write_cb dcr_write);
-clk_setup_cb ppc_40x_timers_init (CPUPPCState *env, uint32_t freq,
- unsigned int decr_excp);
-
-/* Embedded PowerPC reset */
-void ppc40x_core_reset(PowerPCCPU *cpu);
-void ppc40x_chip_reset(PowerPCCPU *cpu);
-void ppc40x_system_reset(PowerPCCPU *cpu);
-
-#if defined(CONFIG_USER_ONLY)
-static inline void ppc40x_irq_init(PowerPCCPU *cpu) {}
-static inline void ppc6xx_irq_init(PowerPCCPU *cpu) {}
-static inline void ppc970_irq_init(PowerPCCPU *cpu) {}
-static inline void ppcPOWER7_irq_init(PowerPCCPU *cpu) {}
-static inline void ppcPOWER9_irq_init(PowerPCCPU *cpu) {}
-static inline void ppce500_irq_init(PowerPCCPU *cpu) {}
-static inline void ppc_irq_reset(PowerPCCPU *cpu) {}
-#else
-void ppc40x_irq_init(PowerPCCPU *cpu);
-void ppce500_irq_init(PowerPCCPU *cpu);
-void ppc6xx_irq_init(PowerPCCPU *cpu);
-void ppc970_irq_init(PowerPCCPU *cpu);
-void ppcPOWER7_irq_init(PowerPCCPU *cpu);
-void ppcPOWER9_irq_init(PowerPCCPU *cpu);
-void ppc_irq_reset(PowerPCCPU *cpu);
-#endif
-
-/* PPC machines for OpenBIOS */
-enum {
- ARCH_PREP = 0,
- ARCH_MAC99,
- ARCH_HEATHROW,
- ARCH_MAC99_U3,
-};
-
-#define FW_CFG_PPC_WIDTH (FW_CFG_ARCH_LOCAL + 0x00)
-#define FW_CFG_PPC_HEIGHT (FW_CFG_ARCH_LOCAL + 0x01)
-#define FW_CFG_PPC_DEPTH (FW_CFG_ARCH_LOCAL + 0x02)
-#define FW_CFG_PPC_TBFREQ (FW_CFG_ARCH_LOCAL + 0x03)
-#define FW_CFG_PPC_CLOCKFREQ (FW_CFG_ARCH_LOCAL + 0x04)
-#define FW_CFG_PPC_IS_KVM (FW_CFG_ARCH_LOCAL + 0x05)
-#define FW_CFG_PPC_KVM_HC (FW_CFG_ARCH_LOCAL + 0x06)
-#define FW_CFG_PPC_KVM_PID (FW_CFG_ARCH_LOCAL + 0x07)
-#define FW_CFG_PPC_NVRAM_ADDR (FW_CFG_ARCH_LOCAL + 0x08)
-#define FW_CFG_PPC_BUSFREQ (FW_CFG_ARCH_LOCAL + 0x09)
-#define FW_CFG_PPC_NVRAM_FLAT (FW_CFG_ARCH_LOCAL + 0x0a)
-#define FW_CFG_PPC_VIACONFIG (FW_CFG_ARCH_LOCAL + 0x0b)
-
-#define PPC_SERIAL_MM_BAUDBASE 399193
-
-/* ppc_booke.c */
-void ppc_booke_timers_init(PowerPCCPU *cpu, uint32_t freq, uint32_t flags);
-#endif
+++ /dev/null
-/*
- * QEMU PowerPC 4xx emulation shared definitions
- *
- * Copyright (c) 2007 Jocelyn Mayer
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
- * furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
- * THE SOFTWARE.
- */
-
-#ifndef PPC4XX_H
-#define PPC4XX_H
-
-#include "hw/ppc/ppc.h"
-#include "exec/memory.h"
-
-/* PowerPC 4xx core initialization */
-PowerPCCPU *ppc4xx_init(const char *cpu_model,
- clk_setup_t *cpu_clk, clk_setup_t *tb_clk,
- uint32_t sysclk);
-
-/* PowerPC 4xx universal interrupt controller */
-enum {
- PPCUIC_OUTPUT_INT = 0,
- PPCUIC_OUTPUT_CINT = 1,
- PPCUIC_OUTPUT_NB,
-};
-qemu_irq *ppcuic_init (CPUPPCState *env, qemu_irq *irqs,
- uint32_t dcr_base, int has_ssr, int has_vr);
-
-void ppc4xx_sdram_banks(MemoryRegion *ram, int nr_banks,
- MemoryRegion ram_memories[],
- hwaddr ram_bases[], hwaddr ram_sizes[],
- const ram_addr_t sdram_bank_sizes[]);
-
-void ppc4xx_sdram_init (CPUPPCState *env, qemu_irq irq, int nbanks,
- MemoryRegion ram_memories[],
- hwaddr *ram_bases,
- hwaddr *ram_sizes,
- int do_init);
-
-void ppc4xx_mal_init(CPUPPCState *env, uint8_t txcnum, uint8_t rxcnum,
- qemu_irq irqs[4]);
-
-#define TYPE_PPC4xx_PCI_HOST_BRIDGE "ppc4xx-pcihost"
-
-#endif /* PPC4XX_H */
+++ /dev/null
-#ifndef HW_PPC_E500_H
-#define HW_PPC_E500_H
-
-void ppce500_set_mpic_proxy(bool enabled);
-
-#endif
+++ /dev/null
-#ifndef HW_SPAPR_H
-#define HW_SPAPR_H
-
-#include "qemu/units.h"
-#include "sysemu/dma.h"
-#include "hw/boards.h"
-#include "hw/ppc/spapr_drc.h"
-#include "hw/mem/pc-dimm.h"
-#include "hw/ppc/spapr_ovec.h"
-#include "hw/ppc/spapr_irq.h"
-#include "qom/object.h"
-#include "hw/ppc/spapr_xive.h" /* For SpaprXive */
-#include "hw/ppc/xics.h" /* For ICSState */
-#include "hw/ppc/spapr_tpm_proxy.h"
-
-struct SpaprVioBus;
-struct SpaprPhbState;
-struct SpaprNvram;
-
-typedef struct SpaprEventLogEntry SpaprEventLogEntry;
-typedef struct SpaprEventSource SpaprEventSource;
-typedef struct SpaprPendingHpt SpaprPendingHpt;
-
-#define HPTE64_V_HPTE_DIRTY 0x0000000000000040ULL
-#define SPAPR_ENTRY_POINT 0x100
-
-#define SPAPR_TIMEBASE_FREQ 512000000ULL
-
-#define TYPE_SPAPR_RTC "spapr-rtc"
-
-OBJECT_DECLARE_SIMPLE_TYPE(SpaprRtcState, SPAPR_RTC)
-
-struct SpaprRtcState {
- /*< private >*/
- DeviceState parent_obj;
- int64_t ns_offset;
-};
-
-typedef struct SpaprDimmState SpaprDimmState;
-
-#define TYPE_SPAPR_MACHINE "spapr-machine"
-OBJECT_DECLARE_TYPE(SpaprMachineState, SpaprMachineClass, SPAPR_MACHINE)
-
-typedef enum {
- SPAPR_RESIZE_HPT_DEFAULT = 0,
- SPAPR_RESIZE_HPT_DISABLED,
- SPAPR_RESIZE_HPT_ENABLED,
- SPAPR_RESIZE_HPT_REQUIRED,
-} SpaprResizeHpt;
-
-/**
- * Capabilities
- */
-
-/* Hardware Transactional Memory */
-#define SPAPR_CAP_HTM 0x00
-/* Vector Scalar Extensions */
-#define SPAPR_CAP_VSX 0x01
-/* Decimal Floating Point */
-#define SPAPR_CAP_DFP 0x02
-/* Cache Flush on Privilege Change */
-#define SPAPR_CAP_CFPC 0x03
-/* Speculation Barrier Bounds Checking */
-#define SPAPR_CAP_SBBC 0x04
-/* Indirect Branch Serialisation */
-#define SPAPR_CAP_IBS 0x05
-/* HPT Maximum Page Size (encoded as a shift) */
-#define SPAPR_CAP_HPT_MAXPAGESIZE 0x06
-/* Nested KVM-HV */
-#define SPAPR_CAP_NESTED_KVM_HV 0x07
-/* Large Decrementer */
-#define SPAPR_CAP_LARGE_DECREMENTER 0x08
-/* Count Cache Flush Assist HW Instruction */
-#define SPAPR_CAP_CCF_ASSIST 0x09
-/* Implements PAPR FWNMI option */
-#define SPAPR_CAP_FWNMI 0x0A
-/* Num Caps */
-#define SPAPR_CAP_NUM (SPAPR_CAP_FWNMI + 1)
-
-/*
- * Capability Values
- */
-/* Bool Caps */
-#define SPAPR_CAP_OFF 0x00
-#define SPAPR_CAP_ON 0x01
-
-/* Custom Caps */
-
-/* Generic */
-#define SPAPR_CAP_BROKEN 0x00
-#define SPAPR_CAP_WORKAROUND 0x01
-#define SPAPR_CAP_FIXED 0x02
-/* SPAPR_CAP_IBS (cap-ibs) */
-#define SPAPR_CAP_FIXED_IBS 0x02
-#define SPAPR_CAP_FIXED_CCD 0x03
-#define SPAPR_CAP_FIXED_NA 0x10 /* Lets leave a bit of a gap... */
-
-#define FDT_MAX_SIZE 0x100000
-
-/*
- * NUMA related macros. MAX_DISTANCE_REF_POINTS was taken
- * from Linux kernel arch/powerpc/mm/numa.h. It represents the
- * amount of associativity domains for non-CPU resources.
- *
- * NUMA_ASSOC_SIZE is the base array size of an ibm,associativity
- * array for any non-CPU resource.
- *
- * VCPU_ASSOC_SIZE represents the size of ibm,associativity array
- * for CPUs, which has an extra element (vcpu_id) in the end.
- */
-#define MAX_DISTANCE_REF_POINTS 4
-#define NUMA_ASSOC_SIZE (MAX_DISTANCE_REF_POINTS + 1)
-#define VCPU_ASSOC_SIZE (NUMA_ASSOC_SIZE + 1)
-
-typedef struct SpaprCapabilities SpaprCapabilities;
-struct SpaprCapabilities {
- uint8_t caps[SPAPR_CAP_NUM];
-};
-
-/**
- * SpaprMachineClass:
- */
-struct SpaprMachineClass {
- /*< private >*/
- MachineClass parent_class;
-
- /*< public >*/
- bool dr_lmb_enabled; /* enable dynamic-reconfig/hotplug of LMBs */
- bool dr_phb_enabled; /* enable dynamic-reconfig/hotplug of PHBs */
- bool update_dt_enabled; /* enable KVMPPC_H_UPDATE_DT */
- bool use_ohci_by_default; /* use USB-OHCI instead of XHCI */
- bool pre_2_10_has_unused_icps;
- bool legacy_irq_allocation;
- uint32_t nr_xirqs;
- bool broken_host_serial_model; /* present real host info to the guest */
- bool pre_4_1_migration; /* don't migrate hpt-max-page-size */
- bool linux_pci_probe;
- bool smp_threads_vsmt; /* set VSMT to smp_threads by default */
- hwaddr rma_limit; /* clamp the RMA to this size */
- bool pre_5_1_assoc_refpoints;
- bool pre_5_2_numa_associativity;
-
- void (*phb_placement)(SpaprMachineState *spapr, uint32_t index,
- uint64_t *buid, hwaddr *pio,
- hwaddr *mmio32, hwaddr *mmio64,
- unsigned n_dma, uint32_t *liobns, hwaddr *nv2gpa,
- hwaddr *nv2atsd, Error **errp);
- SpaprResizeHpt resize_hpt_default;
- SpaprCapabilities default_caps;
- SpaprIrq *irq;
-};
-
-/**
- * SpaprMachineState:
- */
-struct SpaprMachineState {
- /*< private >*/
- MachineState parent_obj;
-
- struct SpaprVioBus *vio_bus;
- QLIST_HEAD(, SpaprPhbState) phbs;
- struct SpaprNvram *nvram;
- SpaprRtcState rtc;
-
- SpaprResizeHpt resize_hpt;
- void *htab;
- uint32_t htab_shift;
- uint64_t patb_entry; /* Process tbl registed in H_REGISTER_PROCESS_TABLE */
- SpaprPendingHpt *pending_hpt; /* in-progress resize */
-
- hwaddr rma_size;
- uint32_t fdt_size;
- uint32_t fdt_initial_size;
- void *fdt_blob;
- long kernel_size;
- bool kernel_le;
- uint64_t kernel_addr;
- uint32_t initrd_base;
- long initrd_size;
- uint64_t rtc_offset; /* Now used only during incoming migration */
- struct PPCTimebase tb;
- bool has_graphics;
- uint32_t vsmt; /* Virtual SMT mode (KVM's "core stride") */
-
- Notifier epow_notifier;
- QTAILQ_HEAD(, SpaprEventLogEntry) pending_events;
- bool use_hotplug_event_source;
- SpaprEventSource *event_sources;
-
- /* ibm,client-architecture-support option negotiation */
- bool cas_pre_isa3_guest;
- SpaprOptionVector *ov5; /* QEMU-supported option vectors */
- SpaprOptionVector *ov5_cas; /* negotiated (via CAS) option vectors */
- uint32_t max_compat_pvr;
-
- /* Migration state */
- int htab_save_index;
- bool htab_first_pass;
- int htab_fd;
-
- /* Pending DIMM unplug cache. It is populated when a LMB
- * unplug starts. It can be regenerated if a migration
- * occurs during the unplug process. */
- QTAILQ_HEAD(, SpaprDimmState) pending_dimm_unplugs;
-
- /* State related to FWNMI option */
-
- /* System Reset and Machine Check Notification Routine addresses
- * registered by "ibm,nmi-register" RTAS call.
- */
- target_ulong fwnmi_system_reset_addr;
- target_ulong fwnmi_machine_check_addr;
-
- /* Machine Check FWNMI synchronization, fwnmi_machine_check_interlock is
- * set to -1 if a FWNMI machine check is not in progress, else is set to
- * the CPU that was delivered the machine check, and is set back to -1
- * when that CPU makes an "ibm,nmi-interlock" RTAS call. The cond is used
- * to synchronize other CPUs.
- */
- int fwnmi_machine_check_interlock;
- QemuCond fwnmi_machine_check_interlock_cond;
-
- /*< public >*/
- char *kvm_type;
- char *host_model;
- char *host_serial;
-
- int32_t irq_map_nr;
- unsigned long *irq_map;
- SpaprIrq *irq;
- qemu_irq *qirqs;
- SpaprInterruptController *active_intc;
- ICSState *ics;
- SpaprXive *xive;
-
- bool cmd_line_caps[SPAPR_CAP_NUM];
- SpaprCapabilities def, eff, mig;
-
- unsigned gpu_numa_id;
- SpaprTpmProxy *tpm_proxy;
-
- uint32_t numa_assoc_array[MAX_NODES][NUMA_ASSOC_SIZE];
-
- Error *fwnmi_migration_blocker;
-};
-
-#define H_SUCCESS 0
-#define H_BUSY 1 /* Hardware busy -- retry later */
-#define H_CLOSED 2 /* Resource closed */
-#define H_NOT_AVAILABLE 3
-#define H_CONSTRAINED 4 /* Resource request constrained to max allowed */
-#define H_PARTIAL 5
-#define H_IN_PROGRESS 14 /* Kind of like busy */
-#define H_PAGE_REGISTERED 15
-#define H_PARTIAL_STORE 16
-#define H_PENDING 17 /* returned from H_POLL_PENDING */
-#define H_CONTINUE 18 /* Returned from H_Join on success */
-#define H_LONG_BUSY_START_RANGE 9900 /* Start of long busy range */
-#define H_LONG_BUSY_ORDER_1_MSEC 9900 /* Long busy, hint that 1msec \
- is a good time to retry */
-#define H_LONG_BUSY_ORDER_10_MSEC 9901 /* Long busy, hint that 10msec \
- is a good time to retry */
-#define H_LONG_BUSY_ORDER_100_MSEC 9902 /* Long busy, hint that 100msec \
- is a good time to retry */
-#define H_LONG_BUSY_ORDER_1_SEC 9903 /* Long busy, hint that 1sec \
- is a good time to retry */
-#define H_LONG_BUSY_ORDER_10_SEC 9904 /* Long busy, hint that 10sec \
- is a good time to retry */
-#define H_LONG_BUSY_ORDER_100_SEC 9905 /* Long busy, hint that 100sec \
- is a good time to retry */
-#define H_LONG_BUSY_END_RANGE 9905 /* End of long busy range */
-#define H_HARDWARE -1 /* Hardware error */
-#define H_FUNCTION -2 /* Function not supported */
-#define H_PRIVILEGE -3 /* Caller not privileged */
-#define H_PARAMETER -4 /* Parameter invalid, out-of-range or conflicting */
-#define H_BAD_MODE -5 /* Illegal msr value */
-#define H_PTEG_FULL -6 /* PTEG is full */
-#define H_NOT_FOUND -7 /* PTE was not found" */
-#define H_RESERVED_DABR -8 /* DABR address is reserved by the hypervisor on this processor" */
-#define H_NO_MEM -9
-#define H_AUTHORITY -10
-#define H_PERMISSION -11
-#define H_DROPPED -12
-#define H_SOURCE_PARM -13
-#define H_DEST_PARM -14
-#define H_REMOTE_PARM -15
-#define H_RESOURCE -16
-#define H_ADAPTER_PARM -17
-#define H_RH_PARM -18
-#define H_RCQ_PARM -19
-#define H_SCQ_PARM -20
-#define H_EQ_PARM -21
-#define H_RT_PARM -22
-#define H_ST_PARM -23
-#define H_SIGT_PARM -24
-#define H_TOKEN_PARM -25
-#define H_MLENGTH_PARM -27
-#define H_MEM_PARM -28
-#define H_MEM_ACCESS_PARM -29
-#define H_ATTR_PARM -30
-#define H_PORT_PARM -31
-#define H_MCG_PARM -32
-#define H_VL_PARM -33
-#define H_TSIZE_PARM -34
-#define H_TRACE_PARM -35
-
-#define H_MASK_PARM -37
-#define H_MCG_FULL -38
-#define H_ALIAS_EXIST -39
-#define H_P_COUNTER -40
-#define H_TABLE_FULL -41
-#define H_ALT_TABLE -42
-#define H_MR_CONDITION -43
-#define H_NOT_ENOUGH_RESOURCES -44
-#define H_R_STATE -45
-#define H_RESCINDEND -46
-#define H_P2 -55
-#define H_P3 -56
-#define H_P4 -57
-#define H_P5 -58
-#define H_P6 -59
-#define H_P7 -60
-#define H_P8 -61
-#define H_P9 -62
-#define H_OVERLAP -68
-#define H_UNSUPPORTED_FLAG -256
-#define H_MULTI_THREADS_ACTIVE -9005
-
-
-/* Long Busy is a condition that can be returned by the firmware
- * when a call cannot be completed now, but the identical call
- * should be retried later. This prevents calls blocking in the
- * firmware for long periods of time. Annoyingly the firmware can return
- * a range of return codes, hinting at how long we should wait before
- * retrying. If you don't care for the hint, the macro below is a good
- * way to check for the long_busy return codes
- */
-#define H_IS_LONG_BUSY(x) ((x >= H_LONG_BUSY_START_RANGE) \
- && (x <= H_LONG_BUSY_END_RANGE))
-
-/* Flags */
-#define H_LARGE_PAGE (1ULL<<(63-16))
-#define H_EXACT (1ULL<<(63-24)) /* Use exact PTE or return H_PTEG_FULL */
-#define H_R_XLATE (1ULL<<(63-25)) /* include a valid logical page num in the pte if the valid bit is set */
-#define H_READ_4 (1ULL<<(63-26)) /* Return 4 PTEs */
-#define H_PAGE_STATE_CHANGE (1ULL<<(63-28))
-#define H_PAGE_UNUSED ((1ULL<<(63-29)) | (1ULL<<(63-30)))
-#define H_PAGE_SET_UNUSED (H_PAGE_STATE_CHANGE | H_PAGE_UNUSED)
-#define H_PAGE_SET_LOANED (H_PAGE_SET_UNUSED | (1ULL<<(63-31)))
-#define H_PAGE_SET_ACTIVE H_PAGE_STATE_CHANGE
-#define H_AVPN (1ULL<<(63-32)) /* An avpn is provided as a sanity test */
-#define H_ANDCOND (1ULL<<(63-33))
-#define H_ICACHE_INVALIDATE (1ULL<<(63-40)) /* icbi, etc. (ignored for IO pages) */
-#define H_ICACHE_SYNCHRONIZE (1ULL<<(63-41)) /* dcbst, icbi, etc (ignored for IO pages */
-#define H_ZERO_PAGE (1ULL<<(63-48)) /* zero the page before mapping (ignored for IO pages) */
-#define H_COPY_PAGE (1ULL<<(63-49))
-#define H_N (1ULL<<(63-61))
-#define H_PP1 (1ULL<<(63-62))
-#define H_PP2 (1ULL<<(63-63))
-
-/* Values for 2nd argument to H_SET_MODE */
-#define H_SET_MODE_RESOURCE_SET_CIABR 1
-#define H_SET_MODE_RESOURCE_SET_DAWR 2
-#define H_SET_MODE_RESOURCE_ADDR_TRANS_MODE 3
-#define H_SET_MODE_RESOURCE_LE 4
-
-/* Flags for H_SET_MODE_RESOURCE_LE */
-#define H_SET_MODE_ENDIAN_BIG 0
-#define H_SET_MODE_ENDIAN_LITTLE 1
-
-/* VASI States */
-#define H_VASI_INVALID 0
-#define H_VASI_ENABLED 1
-#define H_VASI_ABORTED 2
-#define H_VASI_SUSPENDING 3
-#define H_VASI_SUSPENDED 4
-#define H_VASI_RESUMED 5
-#define H_VASI_COMPLETED 6
-
-/* DABRX flags */
-#define H_DABRX_HYPERVISOR (1ULL<<(63-61))
-#define H_DABRX_KERNEL (1ULL<<(63-62))
-#define H_DABRX_USER (1ULL<<(63-63))
-
-/* Values for KVM_PPC_GET_CPU_CHAR & H_GET_CPU_CHARACTERISTICS */
-#define H_CPU_CHAR_SPEC_BAR_ORI31 PPC_BIT(0)
-#define H_CPU_CHAR_BCCTRL_SERIALISED PPC_BIT(1)
-#define H_CPU_CHAR_L1D_FLUSH_ORI30 PPC_BIT(2)
-#define H_CPU_CHAR_L1D_FLUSH_TRIG2 PPC_BIT(3)
-#define H_CPU_CHAR_L1D_THREAD_PRIV PPC_BIT(4)
-#define H_CPU_CHAR_HON_BRANCH_HINTS PPC_BIT(5)
-#define H_CPU_CHAR_THR_RECONF_TRIG PPC_BIT(6)
-#define H_CPU_CHAR_CACHE_COUNT_DIS PPC_BIT(7)
-#define H_CPU_CHAR_BCCTR_FLUSH_ASSIST PPC_BIT(9)
-#define H_CPU_BEHAV_FAVOUR_SECURITY PPC_BIT(0)
-#define H_CPU_BEHAV_L1D_FLUSH_PR PPC_BIT(1)
-#define H_CPU_BEHAV_BNDS_CHK_SPEC_BAR PPC_BIT(2)
-#define H_CPU_BEHAV_FLUSH_COUNT_CACHE PPC_BIT(5)
-
-/* Each control block has to be on a 4K boundary */
-#define H_CB_ALIGNMENT 4096
-
-/* pSeries hypervisor opcodes */
-#define H_REMOVE 0x04
-#define H_ENTER 0x08
-#define H_READ 0x0c
-#define H_CLEAR_MOD 0x10
-#define H_CLEAR_REF 0x14
-#define H_PROTECT 0x18
-#define H_GET_TCE 0x1c
-#define H_PUT_TCE 0x20
-#define H_SET_SPRG0 0x24
-#define H_SET_DABR 0x28
-#define H_PAGE_INIT 0x2c
-#define H_SET_ASR 0x30
-#define H_ASR_ON 0x34
-#define H_ASR_OFF 0x38
-#define H_LOGICAL_CI_LOAD 0x3c
-#define H_LOGICAL_CI_STORE 0x40
-#define H_LOGICAL_CACHE_LOAD 0x44
-#define H_LOGICAL_CACHE_STORE 0x48
-#define H_LOGICAL_ICBI 0x4c
-#define H_LOGICAL_DCBF 0x50
-#define H_GET_TERM_CHAR 0x54
-#define H_PUT_TERM_CHAR 0x58
-#define H_REAL_TO_LOGICAL 0x5c
-#define H_HYPERVISOR_DATA 0x60
-#define H_EOI 0x64
-#define H_CPPR 0x68
-#define H_IPI 0x6c
-#define H_IPOLL 0x70
-#define H_XIRR 0x74
-#define H_PERFMON 0x7c
-#define H_MIGRATE_DMA 0x78
-#define H_REGISTER_VPA 0xDC
-#define H_CEDE 0xE0
-#define H_CONFER 0xE4
-#define H_PROD 0xE8
-#define H_GET_PPP 0xEC
-#define H_SET_PPP 0xF0
-#define H_PURR 0xF4
-#define H_PIC 0xF8
-#define H_REG_CRQ 0xFC
-#define H_FREE_CRQ 0x100
-#define H_VIO_SIGNAL 0x104
-#define H_SEND_CRQ 0x108
-#define H_COPY_RDMA 0x110
-#define H_REGISTER_LOGICAL_LAN 0x114
-#define H_FREE_LOGICAL_LAN 0x118
-#define H_ADD_LOGICAL_LAN_BUFFER 0x11C
-#define H_SEND_LOGICAL_LAN 0x120
-#define H_BULK_REMOVE 0x124
-#define H_MULTICAST_CTRL 0x130
-#define H_SET_XDABR 0x134
-#define H_STUFF_TCE 0x138
-#define H_PUT_TCE_INDIRECT 0x13C
-#define H_CHANGE_LOGICAL_LAN_MAC 0x14C
-#define H_VTERM_PARTNER_INFO 0x150
-#define H_REGISTER_VTERM 0x154
-#define H_FREE_VTERM 0x158
-#define H_RESET_EVENTS 0x15C
-#define H_ALLOC_RESOURCE 0x160
-#define H_FREE_RESOURCE 0x164
-#define H_MODIFY_QP 0x168
-#define H_QUERY_QP 0x16C
-#define H_REREGISTER_PMR 0x170
-#define H_REGISTER_SMR 0x174
-#define H_QUERY_MR 0x178
-#define H_QUERY_MW 0x17C
-#define H_QUERY_HCA 0x180
-#define H_QUERY_PORT 0x184
-#define H_MODIFY_PORT 0x188
-#define H_DEFINE_AQP1 0x18C
-#define H_GET_TRACE_BUFFER 0x190
-#define H_DEFINE_AQP0 0x194
-#define H_RESIZE_MR 0x198
-#define H_ATTACH_MCQP 0x19C
-#define H_DETACH_MCQP 0x1A0
-#define H_CREATE_RPT 0x1A4
-#define H_REMOVE_RPT 0x1A8
-#define H_REGISTER_RPAGES 0x1AC
-#define H_DISABLE_AND_GETC 0x1B0
-#define H_ERROR_DATA 0x1B4
-#define H_GET_HCA_INFO 0x1B8
-#define H_GET_PERF_COUNT 0x1BC
-#define H_MANAGE_TRACE 0x1C0
-#define H_GET_CPU_CHARACTERISTICS 0x1C8
-#define H_FREE_LOGICAL_LAN_BUFFER 0x1D4
-#define H_QUERY_INT_STATE 0x1E4
-#define H_POLL_PENDING 0x1D8
-#define H_ILLAN_ATTRIBUTES 0x244
-#define H_MODIFY_HEA_QP 0x250
-#define H_QUERY_HEA_QP 0x254
-#define H_QUERY_HEA 0x258
-#define H_QUERY_HEA_PORT 0x25C
-#define H_MODIFY_HEA_PORT 0x260
-#define H_REG_BCMC 0x264
-#define H_DEREG_BCMC 0x268
-#define H_REGISTER_HEA_RPAGES 0x26C
-#define H_DISABLE_AND_GET_HEA 0x270
-#define H_GET_HEA_INFO 0x274
-#define H_ALLOC_HEA_RESOURCE 0x278
-#define H_ADD_CONN 0x284
-#define H_DEL_CONN 0x288
-#define H_JOIN 0x298
-#define H_VASI_STATE 0x2A4
-#define H_ENABLE_CRQ 0x2B0
-#define H_GET_EM_PARMS 0x2B8
-#define H_SET_MPP 0x2D0
-#define H_GET_MPP 0x2D4
-#define H_HOME_NODE_ASSOCIATIVITY 0x2EC
-#define H_XIRR_X 0x2FC
-#define H_RANDOM 0x300
-#define H_SET_MODE 0x31C
-#define H_RESIZE_HPT_PREPARE 0x36C
-#define H_RESIZE_HPT_COMMIT 0x370
-#define H_CLEAN_SLB 0x374
-#define H_INVALIDATE_PID 0x378
-#define H_REGISTER_PROC_TBL 0x37C
-#define H_SIGNAL_SYS_RESET 0x380
-
-#define H_INT_GET_SOURCE_INFO 0x3A8
-#define H_INT_SET_SOURCE_CONFIG 0x3AC
-#define H_INT_GET_SOURCE_CONFIG 0x3B0
-#define H_INT_GET_QUEUE_INFO 0x3B4
-#define H_INT_SET_QUEUE_CONFIG 0x3B8
-#define H_INT_GET_QUEUE_CONFIG 0x3BC
-#define H_INT_SET_OS_REPORTING_LINE 0x3C0
-#define H_INT_GET_OS_REPORTING_LINE 0x3C4
-#define H_INT_ESB 0x3C8
-#define H_INT_SYNC 0x3CC
-#define H_INT_RESET 0x3D0
-#define H_SCM_READ_METADATA 0x3E4
-#define H_SCM_WRITE_METADATA 0x3E8
-#define H_SCM_BIND_MEM 0x3EC
-#define H_SCM_UNBIND_MEM 0x3F0
-#define H_SCM_UNBIND_ALL 0x3FC
-
-#define MAX_HCALL_OPCODE H_SCM_UNBIND_ALL
-
-/* The hcalls above are standardized in PAPR and implemented by pHyp
- * as well.
- *
- * We also need some hcalls which are specific to qemu / KVM-on-POWER.
- * We put those into the 0xf000-0xfffc range which is reserved by PAPR
- * for "platform-specific" hcalls.
- */
-#define KVMPPC_HCALL_BASE 0xf000
-#define KVMPPC_H_RTAS (KVMPPC_HCALL_BASE + 0x0)
-#define KVMPPC_H_LOGICAL_MEMOP (KVMPPC_HCALL_BASE + 0x1)
-/* Client Architecture support */
-#define KVMPPC_H_CAS (KVMPPC_HCALL_BASE + 0x2)
-#define KVMPPC_H_UPDATE_DT (KVMPPC_HCALL_BASE + 0x3)
-#define KVMPPC_HCALL_MAX KVMPPC_H_UPDATE_DT
-
-/*
- * The hcall range 0xEF00 to 0xEF80 is reserved for use in facilitating
- * Secure VM mode via an Ultravisor / Protected Execution Facility
- */
-#define SVM_HCALL_BASE 0xEF00
-#define SVM_H_TPM_COMM 0xEF10
-#define SVM_HCALL_MAX SVM_H_TPM_COMM
-
-
-typedef struct SpaprDeviceTreeUpdateHeader {
- uint32_t version_id;
-} SpaprDeviceTreeUpdateHeader;
-
-#define hcall_dprintf(fmt, ...) \
- do { \
- qemu_log_mask(LOG_GUEST_ERROR, "%s: " fmt, __func__, ## __VA_ARGS__); \
- } while (0)
-
-typedef target_ulong (*spapr_hcall_fn)(PowerPCCPU *cpu, SpaprMachineState *sm,
- target_ulong opcode,
- target_ulong *args);
-
-void spapr_register_hypercall(target_ulong opcode, spapr_hcall_fn fn);
-target_ulong spapr_hypercall(PowerPCCPU *cpu, target_ulong opcode,
- target_ulong *args);
-
-target_ulong do_client_architecture_support(PowerPCCPU *cpu,
- SpaprMachineState *spapr,
- target_ulong addr,
- target_ulong fdt_bufsize);
-
-/* Virtual Processor Area structure constants */
-#define VPA_MIN_SIZE 640
-#define VPA_SIZE_OFFSET 0x4
-#define VPA_SHARED_PROC_OFFSET 0x9
-#define VPA_SHARED_PROC_VAL 0x2
-#define VPA_DISPATCH_COUNTER 0x100
-
-/* ibm,set-eeh-option */
-#define RTAS_EEH_DISABLE 0
-#define RTAS_EEH_ENABLE 1
-#define RTAS_EEH_THAW_IO 2
-#define RTAS_EEH_THAW_DMA 3
-
-/* ibm,get-config-addr-info2 */
-#define RTAS_GET_PE_ADDR 0
-#define RTAS_GET_PE_MODE 1
-#define RTAS_PE_MODE_NONE 0
-#define RTAS_PE_MODE_NOT_SHARED 1
-#define RTAS_PE_MODE_SHARED 2
-
-/* ibm,read-slot-reset-state2 */
-#define RTAS_EEH_PE_STATE_NORMAL 0
-#define RTAS_EEH_PE_STATE_RESET 1
-#define RTAS_EEH_PE_STATE_STOPPED_IO_DMA 2
-#define RTAS_EEH_PE_STATE_STOPPED_DMA 4
-#define RTAS_EEH_PE_STATE_UNAVAIL 5
-#define RTAS_EEH_NOT_SUPPORT 0
-#define RTAS_EEH_SUPPORT 1
-#define RTAS_EEH_PE_UNAVAIL_INFO 1000
-#define RTAS_EEH_PE_RECOVER_INFO 0
-
-/* ibm,set-slot-reset */
-#define RTAS_SLOT_RESET_DEACTIVATE 0
-#define RTAS_SLOT_RESET_HOT 1
-#define RTAS_SLOT_RESET_FUNDAMENTAL 3
-
-/* ibm,slot-error-detail */
-#define RTAS_SLOT_TEMP_ERR_LOG 1
-#define RTAS_SLOT_PERM_ERR_LOG 2
-
-/* RTAS return codes */
-#define RTAS_OUT_SUCCESS 0
-#define RTAS_OUT_NO_ERRORS_FOUND 1
-#define RTAS_OUT_HW_ERROR -1
-#define RTAS_OUT_BUSY -2
-#define RTAS_OUT_PARAM_ERROR -3
-#define RTAS_OUT_NOT_SUPPORTED -3
-#define RTAS_OUT_NO_SUCH_INDICATOR -3
-#define RTAS_OUT_NOT_AUTHORIZED -9002
-#define RTAS_OUT_SYSPARM_PARAM_ERROR -9999
-
-/* DDW pagesize mask values from ibm,query-pe-dma-window */
-#define RTAS_DDW_PGSIZE_4K 0x01
-#define RTAS_DDW_PGSIZE_64K 0x02
-#define RTAS_DDW_PGSIZE_16M 0x04
-#define RTAS_DDW_PGSIZE_32M 0x08
-#define RTAS_DDW_PGSIZE_64M 0x10
-#define RTAS_DDW_PGSIZE_128M 0x20
-#define RTAS_DDW_PGSIZE_256M 0x40
-#define RTAS_DDW_PGSIZE_16G 0x80
-
-/* RTAS tokens */
-#define RTAS_TOKEN_BASE 0x2000
-
-#define RTAS_DISPLAY_CHARACTER (RTAS_TOKEN_BASE + 0x00)
-#define RTAS_GET_TIME_OF_DAY (RTAS_TOKEN_BASE + 0x01)
-#define RTAS_SET_TIME_OF_DAY (RTAS_TOKEN_BASE + 0x02)
-#define RTAS_POWER_OFF (RTAS_TOKEN_BASE + 0x03)
-#define RTAS_SYSTEM_REBOOT (RTAS_TOKEN_BASE + 0x04)
-#define RTAS_QUERY_CPU_STOPPED_STATE (RTAS_TOKEN_BASE + 0x05)
-#define RTAS_START_CPU (RTAS_TOKEN_BASE + 0x06)
-#define RTAS_STOP_SELF (RTAS_TOKEN_BASE + 0x07)
-#define RTAS_IBM_GET_SYSTEM_PARAMETER (RTAS_TOKEN_BASE + 0x08)
-#define RTAS_IBM_SET_SYSTEM_PARAMETER (RTAS_TOKEN_BASE + 0x09)
-#define RTAS_IBM_SET_XIVE (RTAS_TOKEN_BASE + 0x0A)
-#define RTAS_IBM_GET_XIVE (RTAS_TOKEN_BASE + 0x0B)
-#define RTAS_IBM_INT_OFF (RTAS_TOKEN_BASE + 0x0C)
-#define RTAS_IBM_INT_ON (RTAS_TOKEN_BASE + 0x0D)
-#define RTAS_CHECK_EXCEPTION (RTAS_TOKEN_BASE + 0x0E)
-#define RTAS_EVENT_SCAN (RTAS_TOKEN_BASE + 0x0F)
-#define RTAS_IBM_SET_TCE_BYPASS (RTAS_TOKEN_BASE + 0x10)
-#define RTAS_QUIESCE (RTAS_TOKEN_BASE + 0x11)
-#define RTAS_NVRAM_FETCH (RTAS_TOKEN_BASE + 0x12)
-#define RTAS_NVRAM_STORE (RTAS_TOKEN_BASE + 0x13)
-#define RTAS_READ_PCI_CONFIG (RTAS_TOKEN_BASE + 0x14)
-#define RTAS_WRITE_PCI_CONFIG (RTAS_TOKEN_BASE + 0x15)
-#define RTAS_IBM_READ_PCI_CONFIG (RTAS_TOKEN_BASE + 0x16)
-#define RTAS_IBM_WRITE_PCI_CONFIG (RTAS_TOKEN_BASE + 0x17)
-#define RTAS_IBM_QUERY_INTERRUPT_SOURCE_NUMBER (RTAS_TOKEN_BASE + 0x18)
-#define RTAS_IBM_CHANGE_MSI (RTAS_TOKEN_BASE + 0x19)
-#define RTAS_SET_INDICATOR (RTAS_TOKEN_BASE + 0x1A)
-#define RTAS_SET_POWER_LEVEL (RTAS_TOKEN_BASE + 0x1B)
-#define RTAS_GET_POWER_LEVEL (RTAS_TOKEN_BASE + 0x1C)
-#define RTAS_GET_SENSOR_STATE (RTAS_TOKEN_BASE + 0x1D)
-#define RTAS_IBM_CONFIGURE_CONNECTOR (RTAS_TOKEN_BASE + 0x1E)
-#define RTAS_IBM_OS_TERM (RTAS_TOKEN_BASE + 0x1F)
-#define RTAS_IBM_SET_EEH_OPTION (RTAS_TOKEN_BASE + 0x20)
-#define RTAS_IBM_GET_CONFIG_ADDR_INFO2 (RTAS_TOKEN_BASE + 0x21)
-#define RTAS_IBM_READ_SLOT_RESET_STATE2 (RTAS_TOKEN_BASE + 0x22)
-#define RTAS_IBM_SET_SLOT_RESET (RTAS_TOKEN_BASE + 0x23)
-#define RTAS_IBM_CONFIGURE_PE (RTAS_TOKEN_BASE + 0x24)
-#define RTAS_IBM_SLOT_ERROR_DETAIL (RTAS_TOKEN_BASE + 0x25)
-#define RTAS_IBM_QUERY_PE_DMA_WINDOW (RTAS_TOKEN_BASE + 0x26)
-#define RTAS_IBM_CREATE_PE_DMA_WINDOW (RTAS_TOKEN_BASE + 0x27)
-#define RTAS_IBM_REMOVE_PE_DMA_WINDOW (RTAS_TOKEN_BASE + 0x28)
-#define RTAS_IBM_RESET_PE_DMA_WINDOW (RTAS_TOKEN_BASE + 0x29)
-#define RTAS_IBM_SUSPEND_ME (RTAS_TOKEN_BASE + 0x2A)
-#define RTAS_IBM_NMI_REGISTER (RTAS_TOKEN_BASE + 0x2B)
-#define RTAS_IBM_NMI_INTERLOCK (RTAS_TOKEN_BASE + 0x2C)
-
-#define RTAS_TOKEN_MAX (RTAS_TOKEN_BASE + 0x2D)
-
-/* RTAS ibm,get-system-parameter token values */
-#define RTAS_SYSPARM_SPLPAR_CHARACTERISTICS 20
-#define RTAS_SYSPARM_DIAGNOSTICS_RUN_MODE 42
-#define RTAS_SYSPARM_UUID 48
-
-/* RTAS indicator/sensor types
- *
- * as defined by PAPR+ 2.7 7.3.5.4, Table 41
- *
- * NOTE: currently only DR-related sensors are implemented here
- */
-#define RTAS_SENSOR_TYPE_ISOLATION_STATE 9001
-#define RTAS_SENSOR_TYPE_DR 9002
-#define RTAS_SENSOR_TYPE_ALLOCATION_STATE 9003
-#define RTAS_SENSOR_TYPE_ENTITY_SENSE RTAS_SENSOR_TYPE_ALLOCATION_STATE
-
-/* Possible values for the platform-processor-diagnostics-run-mode parameter
- * of the RTAS ibm,get-system-parameter call.
- */
-#define DIAGNOSTICS_RUN_MODE_DISABLED 0
-#define DIAGNOSTICS_RUN_MODE_STAGGERED 1
-#define DIAGNOSTICS_RUN_MODE_IMMEDIATE 2
-#define DIAGNOSTICS_RUN_MODE_PERIODIC 3
-
-static inline uint64_t ppc64_phys_to_real(uint64_t addr)
-{
- return addr & ~0xF000000000000000ULL;
-}
-
-static inline uint32_t rtas_ld(target_ulong phys, int n)
-{
- return ldl_be_phys(&address_space_memory, ppc64_phys_to_real(phys + 4*n));
-}
-
-static inline uint64_t rtas_ldq(target_ulong phys, int n)
-{
- return (uint64_t)rtas_ld(phys, n) << 32 | rtas_ld(phys, n + 1);
-}
-
-static inline void rtas_st(target_ulong phys, int n, uint32_t val)
-{
- stl_be_phys(&address_space_memory, ppc64_phys_to_real(phys + 4*n), val);
-}
-
-typedef void (*spapr_rtas_fn)(PowerPCCPU *cpu, SpaprMachineState *sm,
- uint32_t token,
- uint32_t nargs, target_ulong args,
- uint32_t nret, target_ulong rets);
-void spapr_rtas_register(int token, const char *name, spapr_rtas_fn fn);
-target_ulong spapr_rtas_call(PowerPCCPU *cpu, SpaprMachineState *sm,
- uint32_t token, uint32_t nargs, target_ulong args,
- uint32_t nret, target_ulong rets);
-void spapr_dt_rtas_tokens(void *fdt, int rtas);
-void spapr_load_rtas(SpaprMachineState *spapr, void *fdt, hwaddr addr);
-
-#define SPAPR_TCE_PAGE_SHIFT 12
-#define SPAPR_TCE_PAGE_SIZE (1ULL << SPAPR_TCE_PAGE_SHIFT)
-#define SPAPR_TCE_PAGE_MASK (SPAPR_TCE_PAGE_SIZE - 1)
-
-#define SPAPR_VIO_BASE_LIOBN 0x00000000
-#define SPAPR_VIO_LIOBN(reg) (0x00000000 | (reg))
-#define SPAPR_PCI_LIOBN(phb_index, window_num) \
- (0x80000000 | ((phb_index) << 8) | (window_num))
-#define SPAPR_IS_PCI_LIOBN(liobn) (!!((liobn) & 0x80000000))
-#define SPAPR_PCI_DMA_WINDOW_NUM(liobn) ((liobn) & 0xff)
-
-#define RTAS_SIZE 2048
-#define RTAS_ERROR_LOG_MAX 2048
-
-/* Offset from rtas-base where error log is placed */
-#define RTAS_ERROR_LOG_OFFSET 0x30
-
-#define RTAS_EVENT_SCAN_RATE 1
-
-/* This helper should be used to encode interrupt specifiers when the related
- * "interrupt-controller" node has its "#interrupt-cells" property set to 2 (ie,
- * VIO devices, RTAS event sources and PHBs).
- */
-static inline void spapr_dt_irq(uint32_t *intspec, int irq, bool is_lsi)
-{
- intspec[0] = cpu_to_be32(irq);
- intspec[1] = is_lsi ? cpu_to_be32(1) : 0;
-}
-
-
-#define TYPE_SPAPR_TCE_TABLE "spapr-tce-table"
-OBJECT_DECLARE_SIMPLE_TYPE(SpaprTceTable, SPAPR_TCE_TABLE)
-
-#define TYPE_SPAPR_IOMMU_MEMORY_REGION "spapr-iommu-memory-region"
-DECLARE_INSTANCE_CHECKER(IOMMUMemoryRegion, SPAPR_IOMMU_MEMORY_REGION,
- TYPE_SPAPR_IOMMU_MEMORY_REGION)
-
-struct SpaprTceTable {
- DeviceState parent;
- uint32_t liobn;
- uint32_t nb_table;
- uint64_t bus_offset;
- uint32_t page_shift;
- uint64_t *table;
- uint32_t mig_nb_table;
- uint64_t *mig_table;
- bool bypass;
- bool need_vfio;
- bool skipping_replay;
- int fd;
- MemoryRegion root;
- IOMMUMemoryRegion iommu;
- struct SpaprVioDevice *vdev; /* for @bypass migration compatibility only */
- QLIST_ENTRY(SpaprTceTable) list;
-};
-
-SpaprTceTable *spapr_tce_find_by_liobn(target_ulong liobn);
-
-struct SpaprEventLogEntry {
- uint32_t summary;
- uint32_t extended_length;
- void *extended_log;
- QTAILQ_ENTRY(SpaprEventLogEntry) next;
-};
-
-void *spapr_build_fdt(SpaprMachineState *spapr, bool reset, size_t space);
-void spapr_events_init(SpaprMachineState *sm);
-void spapr_dt_events(SpaprMachineState *sm, void *fdt);
-void close_htab_fd(SpaprMachineState *spapr);
-void spapr_setup_hpt(SpaprMachineState *spapr);
-void spapr_free_hpt(SpaprMachineState *spapr);
-SpaprTceTable *spapr_tce_new_table(DeviceState *owner, uint32_t liobn);
-void spapr_tce_table_enable(SpaprTceTable *tcet,
- uint32_t page_shift, uint64_t bus_offset,
- uint32_t nb_table);
-void spapr_tce_table_disable(SpaprTceTable *tcet);
-void spapr_tce_set_need_vfio(SpaprTceTable *tcet, bool need_vfio);
-
-MemoryRegion *spapr_tce_get_iommu(SpaprTceTable *tcet);
-int spapr_dma_dt(void *fdt, int node_off, const char *propname,
- uint32_t liobn, uint64_t window, uint32_t size);
-int spapr_tcet_dma_dt(void *fdt, int node_off, const char *propname,
- SpaprTceTable *tcet);
-void spapr_pci_switch_vga(bool big_endian);
-void spapr_hotplug_req_add_by_index(SpaprDrc *drc);
-void spapr_hotplug_req_remove_by_index(SpaprDrc *drc);
-void spapr_hotplug_req_add_by_count(SpaprDrcType drc_type,
- uint32_t count);
-void spapr_hotplug_req_remove_by_count(SpaprDrcType drc_type,
- uint32_t count);
-void spapr_hotplug_req_add_by_count_indexed(SpaprDrcType drc_type,
- uint32_t count, uint32_t index);
-void spapr_hotplug_req_remove_by_count_indexed(SpaprDrcType drc_type,
- uint32_t count, uint32_t index);
-int spapr_hpt_shift_for_ramsize(uint64_t ramsize);
-int spapr_reallocate_hpt(SpaprMachineState *spapr, int shift, Error **errp);
-void spapr_clear_pending_events(SpaprMachineState *spapr);
-void spapr_clear_pending_hotplug_events(SpaprMachineState *spapr);
-int spapr_max_server_number(SpaprMachineState *spapr);
-void spapr_store_hpte(PowerPCCPU *cpu, hwaddr ptex,
- uint64_t pte0, uint64_t pte1);
-void spapr_mce_req_event(PowerPCCPU *cpu, bool recovered);
-bool spapr_machine_using_legacy_numa(SpaprMachineState *spapr);
-
-/* DRC callbacks. */
-void spapr_core_release(DeviceState *dev);
-int spapr_core_dt_populate(SpaprDrc *drc, SpaprMachineState *spapr,
- void *fdt, int *fdt_start_offset, Error **errp);
-void spapr_lmb_release(DeviceState *dev);
-int spapr_lmb_dt_populate(SpaprDrc *drc, SpaprMachineState *spapr,
- void *fdt, int *fdt_start_offset, Error **errp);
-void spapr_phb_release(DeviceState *dev);
-int spapr_phb_dt_populate(SpaprDrc *drc, SpaprMachineState *spapr,
- void *fdt, int *fdt_start_offset, Error **errp);
-
-void spapr_rtc_read(SpaprRtcState *rtc, struct tm *tm, uint32_t *ns);
-int spapr_rtc_import_offset(SpaprRtcState *rtc, int64_t legacy_offset);
-
-#define TYPE_SPAPR_RNG "spapr-rng"
-
-#define SPAPR_MEMORY_BLOCK_SIZE ((hwaddr)1 << 28) /* 256MB */
-
-/*
- * This defines the maximum number of DIMM slots we can have for sPAPR
- * guest. This is not defined by sPAPR but we are defining it to 32 slots
- * based on default number of slots provided by PowerPC kernel.
- */
-#define SPAPR_MAX_RAM_SLOTS 32
-
-/* 1GB alignment for hotplug memory region */
-#define SPAPR_DEVICE_MEM_ALIGN (1 * GiB)
-
-/*
- * Number of 32 bit words in each LMB list entry in ibm,dynamic-memory
- * property under ibm,dynamic-reconfiguration-memory node.
- */
-#define SPAPR_DR_LMB_LIST_ENTRY_SIZE 6
-
-/*
- * Defines for flag value in ibm,dynamic-memory property under
- * ibm,dynamic-reconfiguration-memory node.
- */
-#define SPAPR_LMB_FLAGS_ASSIGNED 0x00000008
-#define SPAPR_LMB_FLAGS_DRC_INVALID 0x00000020
-#define SPAPR_LMB_FLAGS_RESERVED 0x00000080
-#define SPAPR_LMB_FLAGS_HOTREMOVABLE 0x00000100
-
-void spapr_do_system_reset_on_cpu(CPUState *cs, run_on_cpu_data arg);
-
-#define HTAB_SIZE(spapr) (1ULL << ((spapr)->htab_shift))
-
-int spapr_get_vcpu_id(PowerPCCPU *cpu);
-bool spapr_set_vcpu_id(PowerPCCPU *cpu, int cpu_index, Error **errp);
-PowerPCCPU *spapr_find_cpu(int vcpu_id);
-
-int spapr_caps_pre_load(void *opaque);
-int spapr_caps_pre_save(void *opaque);
-
-/*
- * Handling of optional capabilities
- */
-extern const VMStateDescription vmstate_spapr_cap_htm;
-extern const VMStateDescription vmstate_spapr_cap_vsx;
-extern const VMStateDescription vmstate_spapr_cap_dfp;
-extern const VMStateDescription vmstate_spapr_cap_cfpc;
-extern const VMStateDescription vmstate_spapr_cap_sbbc;
-extern const VMStateDescription vmstate_spapr_cap_ibs;
-extern const VMStateDescription vmstate_spapr_cap_hpt_maxpagesize;
-extern const VMStateDescription vmstate_spapr_cap_nested_kvm_hv;
-extern const VMStateDescription vmstate_spapr_cap_large_decr;
-extern const VMStateDescription vmstate_spapr_cap_ccf_assist;
-extern const VMStateDescription vmstate_spapr_cap_fwnmi;
-
-static inline uint8_t spapr_get_cap(SpaprMachineState *spapr, int cap)
-{
- return spapr->eff.caps[cap];
-}
-
-void spapr_caps_init(SpaprMachineState *spapr);
-void spapr_caps_apply(SpaprMachineState *spapr);
-void spapr_caps_cpu_apply(SpaprMachineState *spapr, PowerPCCPU *cpu);
-void spapr_caps_add_properties(SpaprMachineClass *smc);
-int spapr_caps_post_migration(SpaprMachineState *spapr);
-
-bool spapr_check_pagesize(SpaprMachineState *spapr, hwaddr pagesize,
- Error **errp);
-/*
- * XIVE definitions
- */
-#define SPAPR_OV5_XIVE_LEGACY 0x0
-#define SPAPR_OV5_XIVE_EXPLOIT 0x40
-#define SPAPR_OV5_XIVE_BOTH 0x80 /* Only to advertise on the platform */
-
-void spapr_set_all_lpcrs(target_ulong value, target_ulong mask);
-hwaddr spapr_get_rtas_addr(void);
-#endif /* HW_SPAPR_H */
+++ /dev/null
-/*
- * sPAPR CPU core device.
- *
- * Copyright (C) 2016 Bharata B Rao <bharata@linux.vnet.ibm.com>
- *
- * This work is licensed under the terms of the GNU GPL, version 2 or later.
- * See the COPYING file in the top-level directory.
- */
-#ifndef HW_SPAPR_CPU_CORE_H
-#define HW_SPAPR_CPU_CORE_H
-
-#include "hw/cpu/core.h"
-#include "hw/qdev-core.h"
-#include "target/ppc/cpu-qom.h"
-#include "target/ppc/cpu.h"
-#include "qom/object.h"
-
-#define TYPE_SPAPR_CPU_CORE "spapr-cpu-core"
-OBJECT_DECLARE_TYPE(SpaprCpuCore, SpaprCpuCoreClass,
- SPAPR_CPU_CORE)
-
-#define SPAPR_CPU_CORE_TYPE_NAME(model) model "-" TYPE_SPAPR_CPU_CORE
-
-struct SpaprCpuCore {
- /*< private >*/
- CPUCore parent_obj;
-
- /*< public >*/
- PowerPCCPU **threads;
- int node_id;
- bool pre_3_0_migration; /* older machine don't know about SpaprCpuState */
-};
-
-struct SpaprCpuCoreClass {
- DeviceClass parent_class;
- const char *cpu_type;
-};
-
-const char *spapr_get_cpu_core_type(const char *cpu_type);
-void spapr_cpu_set_entry_state(PowerPCCPU *cpu, target_ulong nip,
- target_ulong r1, target_ulong r3,
- target_ulong r4);
-
-typedef struct SpaprCpuState {
- uint64_t vpa_addr;
- uint64_t slb_shadow_addr, slb_shadow_size;
- uint64_t dtl_addr, dtl_size;
- bool prod; /* not migrated, only used to improve dispatch latencies */
- struct ICPState *icp;
- struct XiveTCTX *tctx;
-} SpaprCpuState;
-
-static inline SpaprCpuState *spapr_cpu_state(PowerPCCPU *cpu)
-{
- return (SpaprCpuState *)cpu->machine_data;
-}
-
-#endif
+++ /dev/null
-/*
- * QEMU SPAPR Dynamic Reconfiguration Connector Implementation
- *
- * Copyright IBM Corp. 2014
- *
- * Authors:
- * Michael Roth <mdroth@linux.vnet.ibm.com>
- *
- * This work is licensed under the terms of the GNU GPL, version 2 or later.
- * See the COPYING file in the top-level directory.
- */
-
-#ifndef HW_SPAPR_DRC_H
-#define HW_SPAPR_DRC_H
-
-#include <libfdt.h>
-#include "qom/object.h"
-#include "sysemu/runstate.h"
-#include "hw/qdev-core.h"
-#include "qapi/error.h"
-
-#define TYPE_SPAPR_DR_CONNECTOR "spapr-dr-connector"
-#define SPAPR_DR_CONNECTOR_GET_CLASS(obj) \
- OBJECT_GET_CLASS(SpaprDrcClass, obj, TYPE_SPAPR_DR_CONNECTOR)
-#define SPAPR_DR_CONNECTOR_CLASS(klass) \
- OBJECT_CLASS_CHECK(SpaprDrcClass, klass, \
- TYPE_SPAPR_DR_CONNECTOR)
-#define SPAPR_DR_CONNECTOR(obj) OBJECT_CHECK(SpaprDrc, (obj), \
- TYPE_SPAPR_DR_CONNECTOR)
-
-#define TYPE_SPAPR_DRC_PHYSICAL "spapr-drc-physical"
-#define SPAPR_DRC_PHYSICAL(obj) OBJECT_CHECK(SpaprDrcPhysical, (obj), \
- TYPE_SPAPR_DRC_PHYSICAL)
-
-#define TYPE_SPAPR_DRC_LOGICAL "spapr-drc-logical"
-
-#define TYPE_SPAPR_DRC_CPU "spapr-drc-cpu"
-
-#define TYPE_SPAPR_DRC_PCI "spapr-drc-pci"
-
-#define TYPE_SPAPR_DRC_LMB "spapr-drc-lmb"
-
-#define TYPE_SPAPR_DRC_PHB "spapr-drc-phb"
-
-#define TYPE_SPAPR_DRC_PMEM "spapr-drc-pmem"
-
-/*
- * Various hotplug types managed by SpaprDrc
- *
- * these are somewhat arbitrary, but to make things easier
- * when generating DRC indexes later we've aligned the bit
- * positions with the values used to assign DRC indexes on
- * pSeries. we use those values as bit shifts to allow for
- * the OR'ing of these values in various QEMU routines, but
- * for values exposed to the guest (via DRC indexes for
- * instance) we will use the shift amounts.
- */
-typedef enum {
- SPAPR_DR_CONNECTOR_TYPE_SHIFT_CPU = 1,
- SPAPR_DR_CONNECTOR_TYPE_SHIFT_PHB = 2,
- SPAPR_DR_CONNECTOR_TYPE_SHIFT_VIO = 3,
- SPAPR_DR_CONNECTOR_TYPE_SHIFT_PCI = 4,
- SPAPR_DR_CONNECTOR_TYPE_SHIFT_LMB = 8,
- SPAPR_DR_CONNECTOR_TYPE_SHIFT_PMEM = 9,
-} SpaprDrcTypeShift;
-
-typedef enum {
- SPAPR_DR_CONNECTOR_TYPE_ANY = ~0,
- SPAPR_DR_CONNECTOR_TYPE_CPU = 1 << SPAPR_DR_CONNECTOR_TYPE_SHIFT_CPU,
- SPAPR_DR_CONNECTOR_TYPE_PHB = 1 << SPAPR_DR_CONNECTOR_TYPE_SHIFT_PHB,
- SPAPR_DR_CONNECTOR_TYPE_VIO = 1 << SPAPR_DR_CONNECTOR_TYPE_SHIFT_VIO,
- SPAPR_DR_CONNECTOR_TYPE_PCI = 1 << SPAPR_DR_CONNECTOR_TYPE_SHIFT_PCI,
- SPAPR_DR_CONNECTOR_TYPE_LMB = 1 << SPAPR_DR_CONNECTOR_TYPE_SHIFT_LMB,
- SPAPR_DR_CONNECTOR_TYPE_PMEM = 1 << SPAPR_DR_CONNECTOR_TYPE_SHIFT_PMEM,
-} SpaprDrcType;
-
-/*
- * set via set-indicator RTAS calls
- * as documented by PAPR+ 2.7 13.5.3.4, Table 177
- *
- * isolated: put device under firmware control
- * unisolated: claim OS control of device (may or may not be in use)
- */
-typedef enum {
- SPAPR_DR_ISOLATION_STATE_ISOLATED = 0,
- SPAPR_DR_ISOLATION_STATE_UNISOLATED = 1
-} SpaprDRIsolationState;
-
-/*
- * set via set-indicator RTAS calls
- * as documented by PAPR+ 2.7 13.5.3.4, Table 177
- *
- * unusable: mark device as unavailable to OS
- * usable: mark device as available to OS
- * exchange: (currently unused)
- * recover: (currently unused)
- */
-typedef enum {
- SPAPR_DR_ALLOCATION_STATE_UNUSABLE = 0,
- SPAPR_DR_ALLOCATION_STATE_USABLE = 1,
- SPAPR_DR_ALLOCATION_STATE_EXCHANGE = 2,
- SPAPR_DR_ALLOCATION_STATE_RECOVER = 3
-} SpaprDRAllocationState;
-
-/*
- * DR-indicator (LED/visual indicator)
- *
- * set via set-indicator RTAS calls
- * as documented by PAPR+ 2.7 13.5.3.4, Table 177,
- * and PAPR+ 2.7 13.5.4.1, Table 180
- *
- * inactive: hotpluggable entity inactive and safely removable
- * active: hotpluggable entity in use and not safely removable
- * identify: (currently unused)
- * action: (currently unused)
- */
-typedef enum {
- SPAPR_DR_INDICATOR_INACTIVE = 0,
- SPAPR_DR_INDICATOR_ACTIVE = 1,
- SPAPR_DR_INDICATOR_IDENTIFY = 2,
- SPAPR_DR_INDICATOR_ACTION = 3,
-} SpaprDRIndicatorState;
-
-/*
- * returned via get-sensor-state RTAS calls
- * as documented by PAPR+ 2.7 13.5.3.3, Table 175:
- *
- * empty: connector slot empty (e.g. empty hotpluggable PCI slot)
- * present: connector slot populated and device available to OS
- * unusable: device not currently available to OS
- * exchange: (currently unused)
- * recover: (currently unused)
- */
-typedef enum {
- SPAPR_DR_ENTITY_SENSE_EMPTY = 0,
- SPAPR_DR_ENTITY_SENSE_PRESENT = 1,
- SPAPR_DR_ENTITY_SENSE_UNUSABLE = 2,
- SPAPR_DR_ENTITY_SENSE_EXCHANGE = 3,
- SPAPR_DR_ENTITY_SENSE_RECOVER = 4,
-} SpaprDREntitySense;
-
-typedef enum {
- SPAPR_DR_CC_RESPONSE_NEXT_SIB = 1, /* currently unused */
- SPAPR_DR_CC_RESPONSE_NEXT_CHILD = 2,
- SPAPR_DR_CC_RESPONSE_NEXT_PROPERTY = 3,
- SPAPR_DR_CC_RESPONSE_PREV_PARENT = 4,
- SPAPR_DR_CC_RESPONSE_SUCCESS = 0,
- SPAPR_DR_CC_RESPONSE_ERROR = -1,
- SPAPR_DR_CC_RESPONSE_CONTINUE = -2,
- SPAPR_DR_CC_RESPONSE_NOT_CONFIGURABLE = -9003,
-} SpaprDRCCResponse;
-
-typedef enum {
- /*
- * Values come from Fig. 12 in LoPAPR section 13.4
- *
- * These are exposed in the migration stream, so don't change
- * them.
- */
- SPAPR_DRC_STATE_INVALID = 0,
- SPAPR_DRC_STATE_LOGICAL_UNUSABLE = 1,
- SPAPR_DRC_STATE_LOGICAL_AVAILABLE = 2,
- SPAPR_DRC_STATE_LOGICAL_UNISOLATE = 3,
- SPAPR_DRC_STATE_LOGICAL_CONFIGURED = 4,
- SPAPR_DRC_STATE_PHYSICAL_AVAILABLE = 5,
- SPAPR_DRC_STATE_PHYSICAL_POWERON = 6,
- SPAPR_DRC_STATE_PHYSICAL_UNISOLATE = 7,
- SPAPR_DRC_STATE_PHYSICAL_CONFIGURED = 8,
-} SpaprDrcState;
-
-typedef struct SpaprDrc {
- /*< private >*/
- DeviceState parent;
-
- uint32_t id;
- Object *owner;
-
- uint32_t state;
-
- /* RTAS ibm,configure-connector state */
- /* (only valid in UNISOLATE state) */
- int ccs_offset;
- int ccs_depth;
-
- /* device pointer, via link property */
- DeviceState *dev;
- bool unplug_requested;
- void *fdt;
- int fdt_start_offset;
-} SpaprDrc;
-
-struct SpaprMachineState;
-
-typedef struct SpaprDrcClass {
- /*< private >*/
- DeviceClass parent;
- SpaprDrcState empty_state;
- SpaprDrcState ready_state;
-
- /*< public >*/
- SpaprDrcTypeShift typeshift;
- const char *typename; /* used in device tree, PAPR 13.5.2.6 & C.6.1 */
- const char *drc_name_prefix; /* used other places in device tree */
-
- SpaprDREntitySense (*dr_entity_sense)(SpaprDrc *drc);
- uint32_t (*isolate)(SpaprDrc *drc);
- uint32_t (*unisolate)(SpaprDrc *drc);
- void (*release)(DeviceState *dev);
-
- int (*dt_populate)(SpaprDrc *drc, struct SpaprMachineState *spapr,
- void *fdt, int *fdt_start_offset, Error **errp);
-} SpaprDrcClass;
-
-typedef struct SpaprDrcPhysical {
- /*< private >*/
- SpaprDrc parent;
-
- /* DR-indicator */
- uint32_t dr_indicator;
-} SpaprDrcPhysical;
-
-static inline bool spapr_drc_hotplugged(DeviceState *dev)
-{
- return dev->hotplugged && !runstate_check(RUN_STATE_INMIGRATE);
-}
-
-void spapr_drc_reset(SpaprDrc *drc);
-
-uint32_t spapr_drc_index(SpaprDrc *drc);
-SpaprDrcType spapr_drc_type(SpaprDrc *drc);
-
-SpaprDrc *spapr_dr_connector_new(Object *owner, const char *type,
- uint32_t id);
-SpaprDrc *spapr_drc_by_index(uint32_t index);
-SpaprDrc *spapr_drc_by_id(const char *type, uint32_t id);
-int spapr_dt_drc(void *fdt, int offset, Object *owner, uint32_t drc_type_mask);
-
-bool spapr_drc_attach(SpaprDrc *drc, DeviceState *d, Error **errp);
-void spapr_drc_detach(SpaprDrc *drc);
-
-/* Returns true if a hot plug/unplug request is pending */
-bool spapr_drc_transient(SpaprDrc *drc);
-
-static inline bool spapr_drc_unplug_requested(SpaprDrc *drc)
-{
- return drc->unplug_requested;
-}
-
-#endif /* HW_SPAPR_DRC_H */
+++ /dev/null
-/*
- * QEMU PowerPC sPAPR IRQ backend definitions
- *
- * Copyright (c) 2018, IBM Corporation.
- *
- * This code is licensed under the GPL version 2 or later. See the
- * COPYING file in the top-level directory.
- */
-
-#ifndef HW_SPAPR_IRQ_H
-#define HW_SPAPR_IRQ_H
-
-#include "target/ppc/cpu-qom.h"
-#include "qom/object.h"
-
-/*
- * IRQ range offsets per device type
- */
-#define SPAPR_IRQ_IPI 0x0
-
-#define SPAPR_XIRQ_BASE XICS_IRQ_BASE /* 0x1000 */
-#define SPAPR_IRQ_EPOW (SPAPR_XIRQ_BASE + 0x0000)
-#define SPAPR_IRQ_HOTPLUG (SPAPR_XIRQ_BASE + 0x0001)
-#define SPAPR_IRQ_VIO (SPAPR_XIRQ_BASE + 0x0100) /* 256 VIO devices */
-#define SPAPR_IRQ_PCI_LSI (SPAPR_XIRQ_BASE + 0x0200) /* 32+ PHBs devices */
-
-/* Offset of the dynamic range covered by the bitmap allocator */
-#define SPAPR_IRQ_MSI (SPAPR_XIRQ_BASE + 0x0300)
-
-#define SPAPR_NR_XIRQS 0x1000
-
-struct SpaprMachineState;
-
-typedef struct SpaprInterruptController SpaprInterruptController;
-
-#define TYPE_SPAPR_INTC "spapr-interrupt-controller"
-#define SPAPR_INTC(obj) \
- INTERFACE_CHECK(SpaprInterruptController, (obj), TYPE_SPAPR_INTC)
-typedef struct SpaprInterruptControllerClass SpaprInterruptControllerClass;
-DECLARE_CLASS_CHECKERS(SpaprInterruptControllerClass, SPAPR_INTC,
- TYPE_SPAPR_INTC)
-
-struct SpaprInterruptControllerClass {
- InterfaceClass parent;
-
- int (*activate)(SpaprInterruptController *intc, uint32_t nr_servers,
- Error **errp);
- void (*deactivate)(SpaprInterruptController *intc);
-
- /*
- * These methods will typically be called on all intcs, active and
- * inactive
- */
- int (*cpu_intc_create)(SpaprInterruptController *intc,
- PowerPCCPU *cpu, Error **errp);
- void (*cpu_intc_reset)(SpaprInterruptController *intc, PowerPCCPU *cpu);
- void (*cpu_intc_destroy)(SpaprInterruptController *intc, PowerPCCPU *cpu);
- int (*claim_irq)(SpaprInterruptController *intc, int irq, bool lsi,
- Error **errp);
- void (*free_irq)(SpaprInterruptController *intc, int irq);
-
- /* These methods should only be called on the active intc */
- void (*set_irq)(SpaprInterruptController *intc, int irq, int val);
- void (*print_info)(SpaprInterruptController *intc, Monitor *mon);
- void (*dt)(SpaprInterruptController *intc, uint32_t nr_servers,
- void *fdt, uint32_t phandle);
- int (*post_load)(SpaprInterruptController *intc, int version_id);
-};
-
-void spapr_irq_update_active_intc(struct SpaprMachineState *spapr);
-
-int spapr_irq_cpu_intc_create(struct SpaprMachineState *spapr,
- PowerPCCPU *cpu, Error **errp);
-void spapr_irq_cpu_intc_reset(struct SpaprMachineState *spapr, PowerPCCPU *cpu);
-void spapr_irq_cpu_intc_destroy(struct SpaprMachineState *spapr, PowerPCCPU *cpu);
-void spapr_irq_print_info(struct SpaprMachineState *spapr, Monitor *mon);
-void spapr_irq_dt(struct SpaprMachineState *spapr, uint32_t nr_servers,
- void *fdt, uint32_t phandle);
-
-uint32_t spapr_irq_nr_msis(struct SpaprMachineState *spapr);
-int spapr_irq_msi_alloc(struct SpaprMachineState *spapr, uint32_t num, bool align,
- Error **errp);
-void spapr_irq_msi_free(struct SpaprMachineState *spapr, int irq, uint32_t num);
-
-typedef struct SpaprIrq {
- bool xics;
- bool xive;
-} SpaprIrq;
-
-extern SpaprIrq spapr_irq_xics;
-extern SpaprIrq spapr_irq_xics_legacy;
-extern SpaprIrq spapr_irq_xive;
-extern SpaprIrq spapr_irq_dual;
-
-void spapr_irq_init(struct SpaprMachineState *spapr, Error **errp);
-int spapr_irq_claim(struct SpaprMachineState *spapr, int irq, bool lsi, Error **errp);
-void spapr_irq_free(struct SpaprMachineState *spapr, int irq, int num);
-qemu_irq spapr_qirq(struct SpaprMachineState *spapr, int irq);
-int spapr_irq_post_load(struct SpaprMachineState *spapr, int version_id);
-void spapr_irq_reset(struct SpaprMachineState *spapr, Error **errp);
-int spapr_irq_get_phandle(struct SpaprMachineState *spapr, void *fdt, Error **errp);
-
-typedef int (*SpaprInterruptControllerInitKvm)(SpaprInterruptController *,
- uint32_t, Error **);
-
-int spapr_irq_init_kvm(SpaprInterruptControllerInitKvm fn,
- SpaprInterruptController *intc,
- uint32_t nr_servers,
- Error **errp);
-
-/*
- * XICS legacy routines
- */
-int spapr_irq_find(struct SpaprMachineState *spapr, int num, bool align, Error **errp);
-#define spapr_irq_findone(spapr, errp) spapr_irq_find(spapr, 1, false, errp)
-
-#endif
+++ /dev/null
-/*
- * QEMU PowerPC pSeries Logical Partition NUMA associativity handling
- *
- * Copyright IBM Corp. 2020
- *
- * Authors:
- * Daniel Henrique Barboza <danielhb413@gmail.com>
- *
- * This work is licensed under the terms of the GNU GPL, version 2 or later.
- * See the COPYING file in the top-level directory.
- */
-
-#ifndef HW_SPAPR_NUMA_H
-#define HW_SPAPR_NUMA_H
-
-#include "hw/boards.h"
-#include "hw/ppc/spapr.h"
-
-/*
- * Having both SpaprMachineState and MachineState as arguments
- * feels odd, but it will spare a MACHINE() call inside the
- * function. spapr_machine_init() is the only caller for it, and
- * it has both pointers resolved already.
- */
-void spapr_numa_associativity_init(SpaprMachineState *spapr,
- MachineState *machine);
-void spapr_numa_write_rtas_dt(SpaprMachineState *spapr, void *fdt, int rtas);
-void spapr_numa_write_associativity_dt(SpaprMachineState *spapr, void *fdt,
- int offset, int nodeid);
-int spapr_numa_fixup_cpu_dt(SpaprMachineState *spapr, void *fdt,
- int offset, PowerPCCPU *cpu);
-int spapr_numa_write_assoc_lookup_arrays(SpaprMachineState *spapr, void *fdt,
- int offset);
-
-#endif /* HW_SPAPR_NUMA_H */
+++ /dev/null
-/*
- * QEMU PowerPC PAPR SCM backend definitions
- *
- * Copyright (c) 2020, IBM Corporation.
- *
- * This code is licensed under the GPL version 2 or later. See the
- * COPYING file in the top-level directory.
- */
-
-#ifndef HW_SPAPR_NVDIMM_H
-#define HW_SPAPR_NVDIMM_H
-
-#include "hw/mem/nvdimm.h"
-#include "hw/ppc/spapr.h"
-
-/*
- * The nvdimm size should be aligned to SCM block size.
- * The SCM block size should be aligned to SPAPR_MEMORY_BLOCK_SIZE
- * inorder to have SCM regions not to overlap with dimm memory regions.
- * The SCM devices can have variable block sizes. For now, fixing the
- * block size to the minimum value.
- */
-#define SPAPR_MINIMUM_SCM_BLOCK_SIZE SPAPR_MEMORY_BLOCK_SIZE
-
-/* Have an explicit check for alignment */
-QEMU_BUILD_BUG_ON(SPAPR_MINIMUM_SCM_BLOCK_SIZE % SPAPR_MEMORY_BLOCK_SIZE);
-
-int spapr_pmem_dt_populate(SpaprDrc *drc, SpaprMachineState *spapr,
- void *fdt, int *fdt_start_offset, Error **errp);
-void spapr_dt_persistent_memory(SpaprMachineState *spapr, void *fdt);
-bool spapr_nvdimm_validate(HotplugHandler *hotplug_dev, NVDIMMDevice *nvdimm,
- uint64_t size, Error **errp);
-bool spapr_add_nvdimm(DeviceState *dev, uint64_t slot, Error **errp);
-
-#endif
+++ /dev/null
-/*
- * QEMU SPAPR Option/Architecture Vector Definitions
- *
- * Each architecture option is organized/documented by the following
- * in LoPAPR 1.1, Table 244:
- *
- * <vector number>: the bit-vector in which the option is located
- * <vector byte>: the byte offset of the vector entry
- * <vector bit>: the bit offset within the vector entry
- *
- * where each vector entry can be one or more bytes.
- *
- * Firmware expects a somewhat literal encoding of this bit-vector
- * structure, where each entry is stored in little-endian so that the
- * byte ordering reflects that of the documentation, but where each bit
- * offset is from "left-to-right" in the traditional representation of
- * a byte value where the MSB is the left-most bit. Thus, each
- * individual byte encodes the option bits in reverse order of the
- * documented bit.
- *
- * These definitions/helpers attempt to abstract away this internal
- * representation so that we can define/set/test for individual option
- * bits using only the documented values. This is done mainly by relying
- * on a bitmap to approximate the documented "bit-vector" structure and
- * handling conversations to-from the internal representation under the
- * covers.
- *
- * Copyright IBM Corp. 2016
- *
- * Authors:
- * Michael Roth <mdroth@linux.vnet.ibm.com>
- *
- * This work is licensed under the terms of the GNU GPL, version 2 or later.
- * See the COPYING file in the top-level directory.
- */
-
-#ifndef SPAPR_OVEC_H
-#define SPAPR_OVEC_H
-
-#include "cpu.h"
-
-typedef struct SpaprOptionVector SpaprOptionVector;
-
-#define OV_BIT(byte, bit) ((byte - 1) * BITS_PER_BYTE + bit)
-
-/* option vector 1 */
-#define OV1_PPC_3_00 OV_BIT(3, 0) /* guest supports PowerPC 3.00? */
-
-/* option vector 5 */
-#define OV5_DRCONF_MEMORY OV_BIT(2, 2)
-#define OV5_FORM1_AFFINITY OV_BIT(5, 0)
-#define OV5_HP_EVT OV_BIT(6, 5)
-#define OV5_HPT_RESIZE OV_BIT(6, 7)
-#define OV5_DRMEM_V2 OV_BIT(22, 0)
-#define OV5_XIVE_BOTH OV_BIT(23, 0)
-#define OV5_XIVE_EXPLOIT OV_BIT(23, 1) /* 1=exploitation 0=legacy */
-
-/* ISA 3.00 MMU features: */
-#define OV5_MMU_BOTH OV_BIT(24, 0) /* Radix and hash */
-#define OV5_MMU_RADIX_300 OV_BIT(24, 1) /* 1=Radix only, 0=Hash only */
-#define OV5_MMU_RADIX_GTSE OV_BIT(26, 1) /* Radix GTSE */
-
-/* interfaces */
-SpaprOptionVector *spapr_ovec_new(void);
-SpaprOptionVector *spapr_ovec_clone(SpaprOptionVector *ov_orig);
-void spapr_ovec_intersect(SpaprOptionVector *ov,
- SpaprOptionVector *ov1,
- SpaprOptionVector *ov2);
-bool spapr_ovec_subset(SpaprOptionVector *ov1, SpaprOptionVector *ov2);
-void spapr_ovec_cleanup(SpaprOptionVector *ov);
-void spapr_ovec_set(SpaprOptionVector *ov, long bitnr);
-void spapr_ovec_clear(SpaprOptionVector *ov, long bitnr);
-bool spapr_ovec_test(SpaprOptionVector *ov, long bitnr);
-SpaprOptionVector *spapr_ovec_parse_vector(target_ulong table_addr, int vector);
-int spapr_dt_ovec(void *fdt, int fdt_offset,
- SpaprOptionVector *ov, const char *name);
-
-/* migration */
-extern const VMStateDescription vmstate_spapr_ovec;
-
-#endif /* SPAPR_OVEC_H */
+++ /dev/null
-#ifndef HW_SPAPR_RTAS_H
-#define HW_SPAPR_RTAS_H
-/*
- * This work is licensed under the terms of the GNU GPL, version 2 or later.
- * See the COPYING file in the top-level directory.
- */
-
-uint64_t qtest_rtas_call(char *cmd, uint32_t nargs, uint64_t args,
- uint32_t nret, uint64_t rets);
-#endif /* HW_SPAPR_RTAS_H */
+++ /dev/null
-/*
- * SPAPR TPM Proxy/Hypercall
- *
- * Copyright IBM Corp. 2019
- *
- * Authors:
- * Michael Roth <mdroth@linux.vnet.ibm.com>
- *
- * This work is licensed under the terms of the GNU GPL, version 2 or later.
- * See the COPYING file in the top-level directory.
- */
-
-#ifndef HW_SPAPR_TPM_PROXY_H
-#define HW_SPAPR_TPM_PROXY_H
-
-#include "qom/object.h"
-#include "hw/qdev-core.h"
-
-#define TYPE_SPAPR_TPM_PROXY "spapr-tpm-proxy"
-OBJECT_DECLARE_SIMPLE_TYPE(SpaprTpmProxy, SPAPR_TPM_PROXY)
-
-struct SpaprTpmProxy {
- /*< private >*/
- DeviceState parent;
-
- char *host_path;
- int host_fd;
-};
-
-#endif /* HW_SPAPR_TPM_PROXY_H */
+++ /dev/null
-#ifndef HW_SPAPR_VIO_H
-#define HW_SPAPR_VIO_H
-
-/*
- * QEMU sPAPR VIO bus definitions
- *
- * Copyright (c) 2010 David Gibson, IBM Corporation <david@gibson.dropbear.id.au>
- * Based on the s390 virtio bus definitions:
- * Copyright (c) 2009 Alexander Graf <agraf@suse.de>
- *
- * This library is free software; you can redistribute it and/or
- * modify it under the terms of the GNU Lesser General Public
- * License as published by the Free Software Foundation; either
- * version 2.1 of the License, or (at your option) any later version.
- *
- * This library is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
- * Lesser General Public License for more details.
- *
- * You should have received a copy of the GNU Lesser General Public
- * License along with this library; if not, see <http://www.gnu.org/licenses/>.
- */
-
-#include "hw/ppc/spapr.h"
-#include "sysemu/dma.h"
-#include "hw/irq.h"
-#include "qom/object.h"
-
-#define TYPE_VIO_SPAPR_DEVICE "vio-spapr-device"
-OBJECT_DECLARE_TYPE(SpaprVioDevice, SpaprVioDeviceClass,
- VIO_SPAPR_DEVICE)
-
-#define TYPE_SPAPR_VIO_BUS "spapr-vio-bus"
-OBJECT_DECLARE_SIMPLE_TYPE(SpaprVioBus, SPAPR_VIO_BUS)
-
-#define TYPE_SPAPR_VIO_BRIDGE "spapr-vio-bridge"
-
-typedef struct SpaprVioCrq {
- uint64_t qladdr;
- uint32_t qsize;
- uint32_t qnext;
- int(*SendFunc)(struct SpaprVioDevice *vdev, uint8_t *crq);
-} SpaprVioCrq;
-
-
-struct SpaprVioDeviceClass {
- DeviceClass parent_class;
-
- const char *dt_name, *dt_type, *dt_compatible;
- target_ulong signal_mask;
- uint32_t rtce_window_size;
- void (*realize)(SpaprVioDevice *dev, Error **errp);
- void (*reset)(SpaprVioDevice *dev);
- int (*devnode)(SpaprVioDevice *dev, void *fdt, int node_off);
- const char *(*get_dt_compatible)(SpaprVioDevice *dev);
-};
-
-struct SpaprVioDevice {
- DeviceState qdev;
- uint32_t reg;
- uint32_t irq;
- uint64_t signal_state;
- SpaprVioCrq crq;
- AddressSpace as;
- MemoryRegion mrroot;
- MemoryRegion mrbypass;
- SpaprTceTable *tcet;
-};
-
-#define DEFINE_SPAPR_PROPERTIES(type, field) \
- DEFINE_PROP_UINT32("reg", type, field.reg, -1)
-
-struct SpaprVioBus {
- BusState bus;
- uint32_t next_reg;
-};
-
-SpaprVioBus *spapr_vio_bus_init(void);
-SpaprVioDevice *spapr_vio_find_by_reg(SpaprVioBus *bus, uint32_t reg);
-void spapr_dt_vdevice(SpaprVioBus *bus, void *fdt);
-gchar *spapr_vio_stdout_path(SpaprVioBus *bus);
-
-static inline void spapr_vio_irq_pulse(SpaprVioDevice *dev)
-{
- SpaprMachineState *spapr = SPAPR_MACHINE(qdev_get_machine());
-
- qemu_irq_pulse(spapr_qirq(spapr, dev->irq));
-}
-
-static inline bool spapr_vio_dma_valid(SpaprVioDevice *dev, uint64_t taddr,
- uint32_t size, DMADirection dir)
-{
- return dma_memory_valid(&dev->as, taddr, size, dir);
-}
-
-static inline int spapr_vio_dma_read(SpaprVioDevice *dev, uint64_t taddr,
- void *buf, uint32_t size)
-{
- return (dma_memory_read(&dev->as, taddr, buf, size) != 0) ?
- H_DEST_PARM : H_SUCCESS;
-}
-
-static inline int spapr_vio_dma_write(SpaprVioDevice *dev, uint64_t taddr,
- const void *buf, uint32_t size)
-{
- return (dma_memory_write(&dev->as, taddr, buf, size) != 0) ?
- H_DEST_PARM : H_SUCCESS;
-}
-
-static inline int spapr_vio_dma_set(SpaprVioDevice *dev, uint64_t taddr,
- uint8_t c, uint32_t size)
-{
- return (dma_memory_set(&dev->as, taddr, c, size) != 0) ?
- H_DEST_PARM : H_SUCCESS;
-}
-
-#define vio_stb(_dev, _addr, _val) (stb_dma(&(_dev)->as, (_addr), (_val)))
-#define vio_sth(_dev, _addr, _val) (stw_be_dma(&(_dev)->as, (_addr), (_val)))
-#define vio_stl(_dev, _addr, _val) (stl_be_dma(&(_dev)->as, (_addr), (_val)))
-#define vio_stq(_dev, _addr, _val) (stq_be_dma(&(_dev)->as, (_addr), (_val)))
-#define vio_ldq(_dev, _addr) (ldq_be_dma(&(_dev)->as, (_addr)))
-
-int spapr_vio_send_crq(SpaprVioDevice *dev, uint8_t *crq);
-
-SpaprVioDevice *vty_lookup(SpaprMachineState *spapr, target_ulong reg);
-void vty_putchars(SpaprVioDevice *sdev, uint8_t *buf, int len);
-void spapr_vty_create(SpaprVioBus *bus, Chardev *chardev);
-void spapr_vlan_create(SpaprVioBus *bus, NICInfo *nd);
-void spapr_vscsi_create(SpaprVioBus *bus);
-
-SpaprVioDevice *spapr_vty_get_default(SpaprVioBus *bus);
-
-extern const VMStateDescription vmstate_spapr_vio;
-
-#define VMSTATE_SPAPR_VIO(_f, _s) \
- VMSTATE_STRUCT(_f, _s, 0, vmstate_spapr_vio, SpaprVioDevice)
-
-void spapr_vio_set_bypass(SpaprVioDevice *dev, bool bypass);
-
-#endif /* HW_SPAPR_VIO_H */
+++ /dev/null
-/*
- * QEMU PowerPC sPAPR XIVE interrupt controller model
- *
- * Copyright (c) 2017-2018, IBM Corporation.
- *
- * This code is licensed under the GPL version 2 or later. See the
- * COPYING file in the top-level directory.
- */
-
-#ifndef PPC_SPAPR_XIVE_H
-#define PPC_SPAPR_XIVE_H
-
-#include "hw/ppc/spapr_irq.h"
-#include "hw/ppc/xive.h"
-
-#define TYPE_SPAPR_XIVE "spapr-xive"
-#define SPAPR_XIVE(obj) OBJECT_CHECK(SpaprXive, (obj), TYPE_SPAPR_XIVE)
-#define SPAPR_XIVE_CLASS(klass) \
- OBJECT_CLASS_CHECK(SpaprXiveClass, (klass), TYPE_SPAPR_XIVE)
-#define SPAPR_XIVE_GET_CLASS(obj) \
- OBJECT_GET_CLASS(SpaprXiveClass, (obj), TYPE_SPAPR_XIVE)
-
-typedef struct SpaprXive {
- XiveRouter parent;
-
- /* Internal interrupt source for IPIs and virtual devices */
- XiveSource source;
- hwaddr vc_base;
-
- /* END ESB MMIOs */
- XiveENDSource end_source;
- hwaddr end_base;
-
- /* DT */
- gchar *nodename;
-
- /* Routing table */
- XiveEAS *eat;
- uint32_t nr_irqs;
- XiveEND *endt;
- uint32_t nr_ends;
-
- /* TIMA mapping address */
- hwaddr tm_base;
- MemoryRegion tm_mmio;
-
- /* KVM support */
- int fd;
- void *tm_mmap;
- MemoryRegion tm_mmio_kvm;
- VMChangeStateEntry *change;
-
- uint8_t hv_prio;
-} SpaprXive;
-
-typedef struct SpaprXiveClass {
- XiveRouterClass parent;
-
- DeviceRealize parent_realize;
-} SpaprXiveClass;
-
-/*
- * The sPAPR machine has a unique XIVE IC device. Assign a fixed value
- * to the controller block id value. It can nevertheless be changed
- * for testing purpose.
- */
-#define SPAPR_XIVE_BLOCK_ID 0x0
-
-void spapr_xive_pic_print_info(SpaprXive *xive, Monitor *mon);
-
-struct SpaprMachineState;
-void spapr_xive_hcall_init(struct SpaprMachineState *spapr);
-void spapr_xive_mmio_set_enabled(SpaprXive *xive, bool enable);
-void spapr_xive_map_mmio(SpaprXive *xive);
-
-int spapr_xive_end_to_target(uint8_t end_blk, uint32_t end_idx,
- uint32_t *out_server, uint8_t *out_prio);
-
-/*
- * KVM XIVE device helpers
- */
-int kvmppc_xive_connect(SpaprInterruptController *intc, uint32_t nr_servers,
- Error **errp);
-void kvmppc_xive_disconnect(SpaprInterruptController *intc);
-void kvmppc_xive_reset(SpaprXive *xive, Error **errp);
-int kvmppc_xive_set_source_config(SpaprXive *xive, uint32_t lisn, XiveEAS *eas,
- Error **errp);
-void kvmppc_xive_sync_source(SpaprXive *xive, uint32_t lisn, Error **errp);
-uint64_t kvmppc_xive_esb_rw(XiveSource *xsrc, int srcno, uint32_t offset,
- uint64_t data, bool write);
-int kvmppc_xive_set_queue_config(SpaprXive *xive, uint8_t end_blk,
- uint32_t end_idx, XiveEND *end,
- Error **errp);
-int kvmppc_xive_get_queue_config(SpaprXive *xive, uint8_t end_blk,
- uint32_t end_idx, XiveEND *end,
- Error **errp);
-void kvmppc_xive_synchronize_state(SpaprXive *xive, Error **errp);
-int kvmppc_xive_pre_save(SpaprXive *xive);
-int kvmppc_xive_post_load(SpaprXive *xive, int version_id);
-
-#endif /* PPC_SPAPR_XIVE_H */
+++ /dev/null
-/*
- * QEMU PowerPC pSeries Logical Partition (aka sPAPR) hardware System Emulator
- *
- * PAPR Virtualized Interrupt System, aka ICS/ICP aka xics
- *
- * Copyright (c) 2010,2011 David Gibson, IBM Corporation.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
- * furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
- * THE SOFTWARE.
- *
- */
-
-#ifndef XICS_H
-#define XICS_H
-
-#include "exec/memory.h"
-#include "hw/qdev-core.h"
-#include "qom/object.h"
-
-#define XICS_IPI 0x2
-#define XICS_BUID 0x1
-#define XICS_IRQ_BASE (XICS_BUID << 12)
-
-/*
- * We currently only support one BUID which is our interrupt base
- * (the kernel implementation supports more but we don't exploit
- * that yet)
- */
-typedef struct PnvICPState PnvICPState;
-typedef struct ICSStateClass ICSStateClass;
-typedef struct ICSState ICSState;
-typedef struct ICSIRQState ICSIRQState;
-typedef struct XICSFabric XICSFabric;
-
-#define TYPE_ICP "icp"
-OBJECT_DECLARE_TYPE(ICPState, ICPStateClass,
- ICP)
-
-#define TYPE_PNV_ICP "pnv-icp"
-DECLARE_INSTANCE_CHECKER(PnvICPState, PNV_ICP,
- TYPE_PNV_ICP)
-
-
-struct ICPStateClass {
- DeviceClass parent_class;
-
- DeviceRealize parent_realize;
-};
-
-struct ICPState {
- /*< private >*/
- DeviceState parent_obj;
- /*< public >*/
- CPUState *cs;
- ICSState *xirr_owner;
- uint32_t xirr;
- uint8_t pending_priority;
- uint8_t mfrr;
- qemu_irq output;
-
- XICSFabric *xics;
-};
-
-#define ICP_PROP_XICS "xics"
-#define ICP_PROP_CPU "cpu"
-
-struct PnvICPState {
- ICPState parent_obj;
-
- MemoryRegion mmio;
- uint32_t links[3];
-};
-
-#define TYPE_ICS "ics"
-DECLARE_OBJ_CHECKERS(ICSState, ICSStateClass,
- ICS, TYPE_ICS)
-
-
-struct ICSStateClass {
- DeviceClass parent_class;
-
- DeviceRealize parent_realize;
- DeviceReset parent_reset;
-
- void (*reject)(ICSState *s, uint32_t irq);
- void (*resend)(ICSState *s);
-};
-
-struct ICSState {
- /*< private >*/
- DeviceState parent_obj;
- /*< public >*/
- uint32_t nr_irqs;
- uint32_t offset;
- ICSIRQState *irqs;
- XICSFabric *xics;
-};
-
-#define ICS_PROP_XICS "xics"
-
-static inline bool ics_valid_irq(ICSState *ics, uint32_t nr)
-{
- return (nr >= ics->offset) && (nr < (ics->offset + ics->nr_irqs));
-}
-
-struct ICSIRQState {
- uint32_t server;
- uint8_t priority;
- uint8_t saved_priority;
-#define XICS_STATUS_ASSERTED 0x1
-#define XICS_STATUS_SENT 0x2
-#define XICS_STATUS_REJECTED 0x4
-#define XICS_STATUS_MASKED_PENDING 0x8
-#define XICS_STATUS_PRESENTED 0x10
-#define XICS_STATUS_QUEUED 0x20
- uint8_t status;
-/* (flags & XICS_FLAGS_IRQ_MASK) == 0 means the interrupt is not allocated */
-#define XICS_FLAGS_IRQ_LSI 0x1
-#define XICS_FLAGS_IRQ_MSI 0x2
-#define XICS_FLAGS_IRQ_MASK 0x3
- uint8_t flags;
-};
-
-#define TYPE_XICS_FABRIC "xics-fabric"
-#define XICS_FABRIC(obj) \
- INTERFACE_CHECK(XICSFabric, (obj), TYPE_XICS_FABRIC)
-typedef struct XICSFabricClass XICSFabricClass;
-DECLARE_CLASS_CHECKERS(XICSFabricClass, XICS_FABRIC,
- TYPE_XICS_FABRIC)
-
-struct XICSFabricClass {
- InterfaceClass parent;
- ICSState *(*ics_get)(XICSFabric *xi, int irq);
- void (*ics_resend)(XICSFabric *xi);
- ICPState *(*icp_get)(XICSFabric *xi, int server);
-};
-
-ICPState *xics_icp_get(XICSFabric *xi, int server);
-
-/* Internal XICS interfaces */
-void icp_set_cppr(ICPState *icp, uint8_t cppr);
-void icp_set_mfrr(ICPState *icp, uint8_t mfrr);
-uint32_t icp_accept(ICPState *ss);
-uint32_t icp_ipoll(ICPState *ss, uint32_t *mfrr);
-void icp_eoi(ICPState *icp, uint32_t xirr);
-void icp_irq(ICSState *ics, int server, int nr, uint8_t priority);
-void icp_reset(ICPState *icp);
-
-void ics_write_xive(ICSState *ics, int nr, int server,
- uint8_t priority, uint8_t saved_priority);
-void ics_set_irq(void *opaque, int srcno, int val);
-
-static inline bool ics_irq_free(ICSState *ics, uint32_t srcno)
-{
- return !(ics->irqs[srcno].flags & XICS_FLAGS_IRQ_MASK);
-}
-
-void ics_set_irq_type(ICSState *ics, int srcno, bool lsi);
-void icp_pic_print_info(ICPState *icp, Monitor *mon);
-void ics_pic_print_info(ICSState *ics, Monitor *mon);
-
-void ics_resend(ICSState *ics);
-void icp_resend(ICPState *ss);
-
-Object *icp_create(Object *cpu, const char *type, XICSFabric *xi,
- Error **errp);
-void icp_destroy(ICPState *icp);
-
-/* KVM */
-void icp_get_kvm_state(ICPState *icp);
-int icp_set_kvm_state(ICPState *icp, Error **errp);
-void icp_synchronize_state(ICPState *icp);
-void icp_kvm_realize(DeviceState *dev, Error **errp);
-
-void ics_get_kvm_state(ICSState *ics);
-int ics_set_kvm_state_one(ICSState *ics, int srcno, Error **errp);
-int ics_set_kvm_state(ICSState *ics, Error **errp);
-void ics_synchronize_state(ICSState *ics);
-void ics_kvm_set_irq(ICSState *ics, int srcno, int val);
-
-#endif /* XICS_H */
+++ /dev/null
-/*
- * QEMU PowerPC pSeries Logical Partition (aka sPAPR) hardware System Emulator
- *
- * PAPR Virtualized Interrupt System, aka ICS/ICP aka xics
- *
- * Copyright (c) 2010, 2011 David Gibson, IBM Corporation.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
- * furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
- * THE SOFTWARE.
- */
-
-#ifndef XICS_SPAPR_H
-#define XICS_SPAPR_H
-
-#include "hw/ppc/spapr.h"
-#include "qom/object.h"
-
-#define TYPE_ICS_SPAPR "ics-spapr"
-/* This is reusing the ICSState typedef from TYPE_ICS */
-DECLARE_INSTANCE_CHECKER(ICSState, ICS_SPAPR,
- TYPE_ICS_SPAPR)
-
-int xics_kvm_connect(SpaprInterruptController *intc, uint32_t nr_servers,
- Error **errp);
-void xics_kvm_disconnect(SpaprInterruptController *intc);
-bool xics_kvm_has_broken_disconnect(SpaprMachineState *spapr);
-
-#endif /* XICS_SPAPR_H */
+++ /dev/null
-/*
- * QEMU PowerPC XIVE interrupt controller model
- *
- *
- * The POWER9 processor comes with a new interrupt controller, called
- * XIVE as "eXternal Interrupt Virtualization Engine".
- *
- * = Overall architecture
- *
- *
- * XIVE Interrupt Controller
- * +------------------------------------+ IPIs
- * | +---------+ +---------+ +--------+ | +-------+
- * | |VC | |CQ | |PC |----> | CORES |
- * | | esb | | | | |----> | |
- * | | eas | | Bridge | | tctx |----> | |
- * | |SC end | | | | nvt | | | |
- * +------+ | +---------+ +----+----+ +--------+ | +-+-+-+-+
- * | RAM | +------------------|-----------------+ | | |
- * | | | | | |
- * | | | | | |
- * | | +--------------------v------------------------v-v-v--+ other
- * | <--+ Power Bus +--> chips
- * | esb | +---------+-----------------------+------------------+
- * | eas | | |
- * | end | +--|------+ |
- * | nvt | +----+----+ | +----+----+
- * +------+ |SC | | |SC |
- * | | | | |
- * | PQ-bits | | | PQ-bits |
- * | local |-+ | in VC |
- * +---------+ +---------+
- * PCIe NX,NPU,CAPI
- *
- * SC: Source Controller (aka. IVSE)
- * VC: Virtualization Controller (aka. IVRE)
- * PC: Presentation Controller (aka. IVPE)
- * CQ: Common Queue (Bridge)
- *
- * PQ-bits: 2 bits source state machine (P:pending Q:queued)
- * esb: Event State Buffer (Array of PQ bits in an IVSE)
- * eas: Event Assignment Structure
- * end: Event Notification Descriptor
- * nvt: Notification Virtual Target
- * tctx: Thread interrupt Context
- *
- *
- * The XIVE IC is composed of three sub-engines :
- *
- * - Interrupt Virtualization Source Engine (IVSE), or Source
- * Controller (SC). These are found in PCI PHBs, in the PSI host
- * bridge controller, but also inside the main controller for the
- * core IPIs and other sub-chips (NX, CAP, NPU) of the
- * chip/processor. They are configured to feed the IVRE with events.
- *
- * - Interrupt Virtualization Routing Engine (IVRE) or Virtualization
- * Controller (VC). Its job is to match an event source with an
- * Event Notification Descriptor (END).
- *
- * - Interrupt Virtualization Presentation Engine (IVPE) or
- * Presentation Controller (PC). It maintains the interrupt context
- * state of each thread and handles the delivery of the external
- * exception to the thread.
- *
- * In XIVE 1.0, the sub-engines used to be referred as:
- *
- * SC Source Controller
- * VC Virtualization Controller
- * PC Presentation Controller
- * CQ Common Queue (PowerBUS Bridge)
- *
- *
- * = XIVE internal tables
- *
- * Each of the sub-engines uses a set of tables to redirect exceptions
- * from event sources to CPU threads.
- *
- * +-------+
- * User or OS | EQ |
- * or +------>|entries|
- * Hypervisor | | .. |
- * Memory | +-------+
- * | ^
- * | |
- * +-------------------------------------------------+
- * | |
- * Hypervisor +------+ +---+--+ +---+--+ +------+
- * Memory | ESB | | EAT | | ENDT | | NVTT |
- * (skiboot) +----+-+ +----+-+ +----+-+ +------+
- * ^ | ^ | ^ | ^
- * | | | | | | |
- * +-------------------------------------------------+
- * | | | | | | |
- * | | | | | | |
- * +----|--|--------|--|--------|--|-+ +-|-----+ +------+
- * | | | | | | | | | | tctx| |Thread|
- * IPI or --> | + v + v + v |---| + .. |-----> |
- * HW events --> | | | | | |
- * IVSE | IVRE | | IVPE | +------+
- * +---------------------------------+ +-------+
- *
- *
- *
- * The IVSE have a 2-bits state machine, P for pending and Q for queued,
- * for each source that allows events to be triggered. They are stored in
- * an Event State Buffer (ESB) array and can be controlled by MMIOs.
- *
- * If the event is let through, the IVRE looks up in the Event Assignment
- * Structure (EAS) table for an Event Notification Descriptor (END)
- * configured for the source. Each Event Notification Descriptor defines
- * a notification path to a CPU and an in-memory Event Queue, in which
- * will be enqueued an EQ data for the OS to pull.
- *
- * The IVPE determines if a Notification Virtual Target (NVT) can
- * handle the event by scanning the thread contexts of the VCPUs
- * dispatched on the processor HW threads. It maintains the state of
- * the thread interrupt context (TCTX) of each thread in a NVT table.
- *
- * = Acronyms
- *
- * Description In XIVE 1.0, used to be referred as
- *
- * EAS Event Assignment Structure IVE Interrupt Virt. Entry
- * EAT Event Assignment Table IVT Interrupt Virt. Table
- * ENDT Event Notif. Descriptor Table EQDT Event Queue Desc. Table
- * EQ Event Queue same
- * ESB Event State Buffer SBE State Bit Entry
- * NVT Notif. Virtual Target VPD Virtual Processor Desc.
- * NVTT Notif. Virtual Target Table VPDT Virtual Processor Desc. Table
- * TCTX Thread interrupt Context
- *
- *
- * Copyright (c) 2017-2018, IBM Corporation.
- *
- * This code is licensed under the GPL version 2 or later. See the
- * COPYING file in the top-level directory.
- *
- */
-
-#ifndef PPC_XIVE_H
-#define PPC_XIVE_H
-
-#include "sysemu/kvm.h"
-#include "hw/sysbus.h"
-#include "hw/ppc/xive_regs.h"
-#include "qom/object.h"
-
-/*
- * XIVE Notifier (Interface between Source and Router)
- */
-
-typedef struct XiveNotifier XiveNotifier;
-
-#define TYPE_XIVE_NOTIFIER "xive-notifier"
-#define XIVE_NOTIFIER(obj) \
- INTERFACE_CHECK(XiveNotifier, (obj), TYPE_XIVE_NOTIFIER)
-typedef struct XiveNotifierClass XiveNotifierClass;
-DECLARE_CLASS_CHECKERS(XiveNotifierClass, XIVE_NOTIFIER,
- TYPE_XIVE_NOTIFIER)
-
-struct XiveNotifierClass {
- InterfaceClass parent;
- void (*notify)(XiveNotifier *xn, uint32_t lisn);
-};
-
-/*
- * XIVE Interrupt Source
- */
-
-#define TYPE_XIVE_SOURCE "xive-source"
-OBJECT_DECLARE_SIMPLE_TYPE(XiveSource, XIVE_SOURCE)
-
-/*
- * XIVE Interrupt Source characteristics, which define how the ESB are
- * controlled.
- */
-#define XIVE_SRC_H_INT_ESB 0x1 /* ESB managed with hcall H_INT_ESB */
-#define XIVE_SRC_STORE_EOI 0x2 /* Store EOI supported */
-
-struct XiveSource {
- DeviceState parent;
-
- /* IRQs */
- uint32_t nr_irqs;
- unsigned long *lsi_map;
-
- /* PQ bits and LSI assertion bit */
- uint8_t *status;
-
- /* ESB memory region */
- uint64_t esb_flags;
- uint32_t esb_shift;
- MemoryRegion esb_mmio;
- MemoryRegion esb_mmio_emulated;
-
- /* KVM support */
- void *esb_mmap;
- MemoryRegion esb_mmio_kvm;
-
- XiveNotifier *xive;
-};
-
-/*
- * ESB MMIO setting. Can be one page, for both source triggering and
- * source management, or two different pages. See below for magic
- * values.
- */
-#define XIVE_ESB_4K 12 /* PSI HB only */
-#define XIVE_ESB_4K_2PAGE 13
-#define XIVE_ESB_64K 16
-#define XIVE_ESB_64K_2PAGE 17
-
-static inline bool xive_source_esb_has_2page(XiveSource *xsrc)
-{
- return xsrc->esb_shift == XIVE_ESB_64K_2PAGE ||
- xsrc->esb_shift == XIVE_ESB_4K_2PAGE;
-}
-
-static inline size_t xive_source_esb_len(XiveSource *xsrc)
-{
- return (1ull << xsrc->esb_shift) * xsrc->nr_irqs;
-}
-
-/* The trigger page is always the first/even page */
-static inline hwaddr xive_source_esb_page(XiveSource *xsrc, uint32_t srcno)
-{
- assert(srcno < xsrc->nr_irqs);
- return (1ull << xsrc->esb_shift) * srcno;
-}
-
-/* In a two pages ESB MMIO setting, the odd page is for management */
-static inline hwaddr xive_source_esb_mgmt(XiveSource *xsrc, int srcno)
-{
- hwaddr addr = xive_source_esb_page(xsrc, srcno);
-
- if (xive_source_esb_has_2page(xsrc)) {
- addr += (1 << (xsrc->esb_shift - 1));
- }
-
- return addr;
-}
-
-/*
- * Each interrupt source has a 2-bit state machine which can be
- * controlled by MMIO. P indicates that an interrupt is pending (has
- * been sent to a queue and is waiting for an EOI). Q indicates that
- * the interrupt has been triggered while pending.
- *
- * This acts as a coalescing mechanism in order to guarantee that a
- * given interrupt only occurs at most once in a queue.
- *
- * When doing an EOI, the Q bit will indicate if the interrupt
- * needs to be re-triggered.
- */
-#define XIVE_STATUS_ASSERTED 0x4 /* Extra bit for LSI */
-#define XIVE_ESB_VAL_P 0x2
-#define XIVE_ESB_VAL_Q 0x1
-
-#define XIVE_ESB_RESET 0x0
-#define XIVE_ESB_PENDING XIVE_ESB_VAL_P
-#define XIVE_ESB_QUEUED (XIVE_ESB_VAL_P | XIVE_ESB_VAL_Q)
-#define XIVE_ESB_OFF XIVE_ESB_VAL_Q
-
-/*
- * "magic" Event State Buffer (ESB) MMIO offsets.
- *
- * The following offsets into the ESB MMIO allow to read or manipulate
- * the PQ bits. They must be used with an 8-byte load instruction.
- * They all return the previous state of the interrupt (atomically).
- *
- * Additionally, some ESB pages support doing an EOI via a store and
- * some ESBs support doing a trigger via a separate trigger page.
- */
-#define XIVE_ESB_STORE_EOI 0x400 /* Store */
-#define XIVE_ESB_LOAD_EOI 0x000 /* Load */
-#define XIVE_ESB_GET 0x800 /* Load */
-#define XIVE_ESB_SET_PQ_00 0xc00 /* Load */
-#define XIVE_ESB_SET_PQ_01 0xd00 /* Load */
-#define XIVE_ESB_SET_PQ_10 0xe00 /* Load */
-#define XIVE_ESB_SET_PQ_11 0xf00 /* Load */
-
-uint8_t xive_source_esb_get(XiveSource *xsrc, uint32_t srcno);
-uint8_t xive_source_esb_set(XiveSource *xsrc, uint32_t srcno, uint8_t pq);
-
-void xive_source_pic_print_info(XiveSource *xsrc, uint32_t offset,
- Monitor *mon);
-
-static inline bool xive_source_irq_is_lsi(XiveSource *xsrc, uint32_t srcno)
-{
- assert(srcno < xsrc->nr_irqs);
- return test_bit(srcno, xsrc->lsi_map);
-}
-
-static inline void xive_source_irq_set_lsi(XiveSource *xsrc, uint32_t srcno)
-{
- assert(srcno < xsrc->nr_irqs);
- bitmap_set(xsrc->lsi_map, srcno, 1);
-}
-
-void xive_source_set_irq(void *opaque, int srcno, int val);
-
-/*
- * XIVE Thread interrupt Management (TM) context
- */
-
-#define TYPE_XIVE_TCTX "xive-tctx"
-OBJECT_DECLARE_SIMPLE_TYPE(XiveTCTX, XIVE_TCTX)
-
-/*
- * XIVE Thread interrupt Management register rings :
- *
- * QW-0 User event-based exception state
- * QW-1 O/S OS context for priority management, interrupt acks
- * QW-2 Pool hypervisor pool context for virtual processors dispatched
- * QW-3 Physical physical thread context and security context
- */
-#define XIVE_TM_RING_COUNT 4
-#define XIVE_TM_RING_SIZE 0x10
-
-typedef struct XivePresenter XivePresenter;
-
-struct XiveTCTX {
- DeviceState parent_obj;
-
- CPUState *cs;
- qemu_irq hv_output;
- qemu_irq os_output;
-
- uint8_t regs[XIVE_TM_RING_COUNT * XIVE_TM_RING_SIZE];
-
- XivePresenter *xptr;
-};
-
-/*
- * XIVE Router
- */
-typedef struct XiveFabric XiveFabric;
-
-struct XiveRouter {
- SysBusDevice parent;
-
- XiveFabric *xfb;
-};
-
-#define TYPE_XIVE_ROUTER "xive-router"
-OBJECT_DECLARE_TYPE(XiveRouter, XiveRouterClass,
- XIVE_ROUTER)
-
-struct XiveRouterClass {
- SysBusDeviceClass parent;
-
- /* XIVE table accessors */
- int (*get_eas)(XiveRouter *xrtr, uint8_t eas_blk, uint32_t eas_idx,
- XiveEAS *eas);
- int (*get_end)(XiveRouter *xrtr, uint8_t end_blk, uint32_t end_idx,
- XiveEND *end);
- int (*write_end)(XiveRouter *xrtr, uint8_t end_blk, uint32_t end_idx,
- XiveEND *end, uint8_t word_number);
- int (*get_nvt)(XiveRouter *xrtr, uint8_t nvt_blk, uint32_t nvt_idx,
- XiveNVT *nvt);
- int (*write_nvt)(XiveRouter *xrtr, uint8_t nvt_blk, uint32_t nvt_idx,
- XiveNVT *nvt, uint8_t word_number);
- uint8_t (*get_block_id)(XiveRouter *xrtr);
-};
-
-int xive_router_get_eas(XiveRouter *xrtr, uint8_t eas_blk, uint32_t eas_idx,
- XiveEAS *eas);
-int xive_router_get_end(XiveRouter *xrtr, uint8_t end_blk, uint32_t end_idx,
- XiveEND *end);
-int xive_router_write_end(XiveRouter *xrtr, uint8_t end_blk, uint32_t end_idx,
- XiveEND *end, uint8_t word_number);
-int xive_router_get_nvt(XiveRouter *xrtr, uint8_t nvt_blk, uint32_t nvt_idx,
- XiveNVT *nvt);
-int xive_router_write_nvt(XiveRouter *xrtr, uint8_t nvt_blk, uint32_t nvt_idx,
- XiveNVT *nvt, uint8_t word_number);
-void xive_router_notify(XiveNotifier *xn, uint32_t lisn);
-
-/*
- * XIVE Presenter
- */
-
-typedef struct XiveTCTXMatch {
- XiveTCTX *tctx;
- uint8_t ring;
-} XiveTCTXMatch;
-
-#define TYPE_XIVE_PRESENTER "xive-presenter"
-#define XIVE_PRESENTER(obj) \
- INTERFACE_CHECK(XivePresenter, (obj), TYPE_XIVE_PRESENTER)
-typedef struct XivePresenterClass XivePresenterClass;
-DECLARE_CLASS_CHECKERS(XivePresenterClass, XIVE_PRESENTER,
- TYPE_XIVE_PRESENTER)
-
-struct XivePresenterClass {
- InterfaceClass parent;
- int (*match_nvt)(XivePresenter *xptr, uint8_t format,
- uint8_t nvt_blk, uint32_t nvt_idx,
- bool cam_ignore, uint8_t priority,
- uint32_t logic_serv, XiveTCTXMatch *match);
- bool (*in_kernel)(const XivePresenter *xptr);
-};
-
-int xive_presenter_tctx_match(XivePresenter *xptr, XiveTCTX *tctx,
- uint8_t format,
- uint8_t nvt_blk, uint32_t nvt_idx,
- bool cam_ignore, uint32_t logic_serv);
-
-/*
- * XIVE Fabric (Interface between Interrupt Controller and Machine)
- */
-
-#define TYPE_XIVE_FABRIC "xive-fabric"
-#define XIVE_FABRIC(obj) \
- INTERFACE_CHECK(XiveFabric, (obj), TYPE_XIVE_FABRIC)
-typedef struct XiveFabricClass XiveFabricClass;
-DECLARE_CLASS_CHECKERS(XiveFabricClass, XIVE_FABRIC,
- TYPE_XIVE_FABRIC)
-
-struct XiveFabricClass {
- InterfaceClass parent;
- int (*match_nvt)(XiveFabric *xfb, uint8_t format,
- uint8_t nvt_blk, uint32_t nvt_idx,
- bool cam_ignore, uint8_t priority,
- uint32_t logic_serv, XiveTCTXMatch *match);
-};
-
-/*
- * XIVE END ESBs
- */
-
-#define TYPE_XIVE_END_SOURCE "xive-end-source"
-OBJECT_DECLARE_SIMPLE_TYPE(XiveENDSource, XIVE_END_SOURCE)
-
-struct XiveENDSource {
- DeviceState parent;
-
- uint32_t nr_ends;
-
- /* ESB memory region */
- uint32_t esb_shift;
- MemoryRegion esb_mmio;
-
- XiveRouter *xrtr;
-};
-
-/*
- * For legacy compatibility, the exceptions define up to 256 different
- * priorities. P9 implements only 9 levels : 8 active levels [0 - 7]
- * and the least favored level 0xFF.
- */
-#define XIVE_PRIORITY_MAX 7
-
-/*
- * XIVE Thread Interrupt Management Aera (TIMA)
- *
- * This region gives access to the registers of the thread interrupt
- * management context. It is four page wide, each page providing a
- * different view of the registers. The page with the lower offset is
- * the most privileged and gives access to the entire context.
- */
-#define XIVE_TM_HW_PAGE 0x0
-#define XIVE_TM_HV_PAGE 0x1
-#define XIVE_TM_OS_PAGE 0x2
-#define XIVE_TM_USER_PAGE 0x3
-
-void xive_tctx_tm_write(XivePresenter *xptr, XiveTCTX *tctx, hwaddr offset,
- uint64_t value, unsigned size);
-uint64_t xive_tctx_tm_read(XivePresenter *xptr, XiveTCTX *tctx, hwaddr offset,
- unsigned size);
-
-void xive_tctx_pic_print_info(XiveTCTX *tctx, Monitor *mon);
-Object *xive_tctx_create(Object *cpu, XivePresenter *xptr, Error **errp);
-void xive_tctx_reset(XiveTCTX *tctx);
-void xive_tctx_destroy(XiveTCTX *tctx);
-void xive_tctx_ipb_update(XiveTCTX *tctx, uint8_t ring, uint8_t ipb);
-
-/*
- * KVM XIVE device helpers
- */
-
-int kvmppc_xive_source_reset_one(XiveSource *xsrc, int srcno, Error **errp);
-void kvmppc_xive_source_set_irq(void *opaque, int srcno, int val);
-int kvmppc_xive_cpu_connect(XiveTCTX *tctx, Error **errp);
-int kvmppc_xive_cpu_synchronize_state(XiveTCTX *tctx, Error **errp);
-int kvmppc_xive_cpu_get_state(XiveTCTX *tctx, Error **errp);
-int kvmppc_xive_cpu_set_state(XiveTCTX *tctx, Error **errp);
-
-#endif /* PPC_XIVE_H */
+++ /dev/null
-/*
- * QEMU PowerPC XIVE internal structure definitions
- *
- *
- * The XIVE structures are accessed by the HW and their format is
- * architected to be big-endian. Some macros are provided to ease
- * access to the different fields.
- *
- *
- * Copyright (c) 2016-2018, IBM Corporation.
- *
- * This code is licensed under the GPL version 2 or later. See the
- * COPYING file in the top-level directory.
- */
-
-#ifndef PPC_XIVE_REGS_H
-#define PPC_XIVE_REGS_H
-
-#include "qemu/bswap.h"
-#include "qemu/host-utils.h"
-
-/*
- * Interrupt source number encoding on PowerBUS
- */
-/*
- * Trigger data definition
- *
- * The trigger definition is used for triggers both for HW source
- * interrupts (PHB, PSI), as well as for rerouting interrupts between
- * Interrupt Controller.
- *
- * HW source controllers set bit0 of word0 to ‘0’ as they provide EAS
- * information (EAS block + EAS index) in the 8 byte data and not END
- * information, which is use for rerouting interrupts.
- *
- * bit1 of word0 to ‘1’ signals that the state bit check has been
- * performed.
- */
-#define XIVE_TRIGGER_END PPC_BIT(0)
-#define XIVE_TRIGGER_PQ PPC_BIT(1)
-
-/*
- * QEMU macros to manipulate the trigger payload in native endian
- */
-#define XIVE_EAS_BLOCK(n) (((n) >> 28) & 0xf)
-#define XIVE_EAS_INDEX(n) ((n) & 0x0fffffff)
-#define XIVE_EAS(blk, idx) ((uint32_t)(blk) << 28 | (idx))
-
-#define TM_SHIFT 16
-
-/* TM register offsets */
-#define TM_QW0_USER 0x000 /* All rings */
-#define TM_QW1_OS 0x010 /* Ring 0..2 */
-#define TM_QW2_HV_POOL 0x020 /* Ring 0..1 */
-#define TM_QW3_HV_PHYS 0x030 /* Ring 0..1 */
-
-/* Byte offsets inside a QW QW0 QW1 QW2 QW3 */
-#define TM_NSR 0x0 /* + + - + */
-#define TM_CPPR 0x1 /* - + - + */
-#define TM_IPB 0x2 /* - + + + */
-#define TM_LSMFB 0x3 /* - + + + */
-#define TM_ACK_CNT 0x4 /* - + - - */
-#define TM_INC 0x5 /* - + - + */
-#define TM_AGE 0x6 /* - + - + */
-#define TM_PIPR 0x7 /* - + - + */
-
-#define TM_WORD0 0x0
-#define TM_WORD1 0x4
-
-/*
- * QW word 2 contains the valid bit at the top and other fields
- * depending on the QW.
- */
-#define TM_WORD2 0x8
-#define TM_QW0W2_VU PPC_BIT32(0)
-#define TM_QW0W2_LOGIC_SERV PPC_BITMASK32(1, 31) /* XX 2,31 ? */
-#define TM_QW1W2_VO PPC_BIT32(0)
-#define TM_QW1W2_OS_CAM PPC_BITMASK32(8, 31)
-#define TM_QW2W2_VP PPC_BIT32(0)
-#define TM_QW2W2_POOL_CAM PPC_BITMASK32(8, 31)
-#define TM_QW3W2_VT PPC_BIT32(0)
-#define TM_QW3W2_LP PPC_BIT32(6)
-#define TM_QW3W2_LE PPC_BIT32(7)
-#define TM_QW3W2_T PPC_BIT32(31)
-
-/*
- * In addition to normal loads to "peek" and writes (only when invalid)
- * using 4 and 8 bytes accesses, the above registers support these
- * "special" byte operations:
- *
- * - Byte load from QW0[NSR] - User level NSR (EBB)
- * - Byte store to QW0[NSR] - User level NSR (EBB)
- * - Byte load/store to QW1[CPPR] and QW3[CPPR] - CPPR access
- * - Byte load from QW3[TM_WORD2] - Read VT||00000||LP||LE on thrd 0
- * otherwise VT||0000000
- * - Byte store to QW3[TM_WORD2] - Set VT bit (and LP/LE if present)
- *
- * Then we have all these "special" CI ops at these offset that trigger
- * all sorts of side effects:
- */
-#define TM_SPC_ACK_EBB 0x800 /* Load8 ack EBB to reg*/
-#define TM_SPC_ACK_OS_REG 0x810 /* Load16 ack OS irq to reg */
-#define TM_SPC_PUSH_USR_CTX 0x808 /* Store32 Push/Validate user context */
-#define TM_SPC_PULL_USR_CTX 0x808 /* Load32 Pull/Invalidate user
- * context */
-#define TM_SPC_SET_OS_PENDING 0x812 /* Store8 Set OS irq pending bit */
-#define TM_SPC_PULL_OS_CTX 0x818 /* Load32/Load64 Pull/Invalidate OS
- * context to reg */
-#define TM_SPC_PULL_POOL_CTX 0x828 /* Load32/Load64 Pull/Invalidate Pool
- * context to reg*/
-#define TM_SPC_ACK_HV_REG 0x830 /* Load16 ack HV irq to reg */
-#define TM_SPC_PULL_USR_CTX_OL 0xc08 /* Store8 Pull/Inval usr ctx to odd
- * line */
-#define TM_SPC_ACK_OS_EL 0xc10 /* Store8 ack OS irq to even line */
-#define TM_SPC_ACK_HV_POOL_EL 0xc20 /* Store8 ack HV evt pool to even
- * line */
-#define TM_SPC_ACK_HV_EL 0xc30 /* Store8 ack HV irq to even line */
-/* XXX more... */
-
-/* NSR fields for the various QW ack types */
-#define TM_QW0_NSR_EB PPC_BIT8(0)
-#define TM_QW1_NSR_EO PPC_BIT8(0)
-#define TM_QW3_NSR_HE PPC_BITMASK8(0, 1)
-#define TM_QW3_NSR_HE_NONE 0
-#define TM_QW3_NSR_HE_POOL 1
-#define TM_QW3_NSR_HE_PHYS 2
-#define TM_QW3_NSR_HE_LSI 3
-#define TM_QW3_NSR_I PPC_BIT8(2)
-#define TM_QW3_NSR_GRP_LVL PPC_BIT8(3, 7)
-
-/*
- * EAS (Event Assignment Structure)
- *
- * One per interrupt source. Targets an interrupt to a given Event
- * Notification Descriptor (END) and provides the corresponding
- * logical interrupt number (END data)
- */
-typedef struct XiveEAS {
- /*
- * Use a single 64-bit definition to make it easier to perform
- * atomic updates
- */
- uint64_t w;
-#define EAS_VALID PPC_BIT(0)
-#define EAS_END_BLOCK PPC_BITMASK(4, 7) /* Destination END block# */
-#define EAS_END_INDEX PPC_BITMASK(8, 31) /* Destination END index */
-#define EAS_MASKED PPC_BIT(32) /* Masked */
-#define EAS_END_DATA PPC_BITMASK(33, 63) /* Data written to the END */
-} XiveEAS;
-
-#define xive_eas_is_valid(eas) (be64_to_cpu((eas)->w) & EAS_VALID)
-#define xive_eas_is_masked(eas) (be64_to_cpu((eas)->w) & EAS_MASKED)
-
-void xive_eas_pic_print_info(XiveEAS *eas, uint32_t lisn, Monitor *mon);
-
-static inline uint64_t xive_get_field64(uint64_t mask, uint64_t word)
-{
- return (be64_to_cpu(word) & mask) >> ctz64(mask);
-}
-
-static inline uint64_t xive_set_field64(uint64_t mask, uint64_t word,
- uint64_t value)
-{
- uint64_t tmp =
- (be64_to_cpu(word) & ~mask) | ((value << ctz64(mask)) & mask);
- return cpu_to_be64(tmp);
-}
-
-static inline uint32_t xive_get_field32(uint32_t mask, uint32_t word)
-{
- return (be32_to_cpu(word) & mask) >> ctz32(mask);
-}
-
-static inline uint32_t xive_set_field32(uint32_t mask, uint32_t word,
- uint32_t value)
-{
- uint32_t tmp =
- (be32_to_cpu(word) & ~mask) | ((value << ctz32(mask)) & mask);
- return cpu_to_be32(tmp);
-}
-
-/* Event Notification Descriptor (END) */
-typedef struct XiveEND {
- uint32_t w0;
-#define END_W0_VALID PPC_BIT32(0) /* "v" bit */
-#define END_W0_ENQUEUE PPC_BIT32(1) /* "q" bit */
-#define END_W0_UCOND_NOTIFY PPC_BIT32(2) /* "n" bit */
-#define END_W0_BACKLOG PPC_BIT32(3) /* "b" bit */
-#define END_W0_PRECL_ESC_CTL PPC_BIT32(4) /* "p" bit */
-#define END_W0_ESCALATE_CTL PPC_BIT32(5) /* "e" bit */
-#define END_W0_UNCOND_ESCALATE PPC_BIT32(6) /* "u" bit - DD2.0 */
-#define END_W0_SILENT_ESCALATE PPC_BIT32(7) /* "s" bit - DD2.0 */
-#define END_W0_QSIZE PPC_BITMASK32(12, 15)
-#define END_W0_SW0 PPC_BIT32(16)
-#define END_W0_FIRMWARE END_W0_SW0 /* Owned by FW */
-#define END_QSIZE_4K 0
-#define END_QSIZE_64K 4
-#define END_W0_HWDEP PPC_BITMASK32(24, 31)
- uint32_t w1;
-#define END_W1_ESn PPC_BITMASK32(0, 1)
-#define END_W1_ESn_P PPC_BIT32(0)
-#define END_W1_ESn_Q PPC_BIT32(1)
-#define END_W1_ESe PPC_BITMASK32(2, 3)
-#define END_W1_ESe_P PPC_BIT32(2)
-#define END_W1_ESe_Q PPC_BIT32(3)
-#define END_W1_GENERATION PPC_BIT32(9)
-#define END_W1_PAGE_OFF PPC_BITMASK32(10, 31)
- uint32_t w2;
-#define END_W2_MIGRATION_REG PPC_BITMASK32(0, 3)
-#define END_W2_OP_DESC_HI PPC_BITMASK32(4, 31)
- uint32_t w3;
-#define END_W3_OP_DESC_LO PPC_BITMASK32(0, 31)
- uint32_t w4;
-#define END_W4_ESC_END_BLOCK PPC_BITMASK32(4, 7)
-#define END_W4_ESC_END_INDEX PPC_BITMASK32(8, 31)
- uint32_t w5;
-#define END_W5_ESC_END_DATA PPC_BITMASK32(1, 31)
- uint32_t w6;
-#define END_W6_FORMAT_BIT PPC_BIT32(8)
-#define END_W6_NVT_BLOCK PPC_BITMASK32(9, 12)
-#define END_W6_NVT_INDEX PPC_BITMASK32(13, 31)
- uint32_t w7;
-#define END_W7_F0_IGNORE PPC_BIT32(0)
-#define END_W7_F0_BLK_GROUPING PPC_BIT32(1)
-#define END_W7_F0_PRIORITY PPC_BITMASK32(8, 15)
-#define END_W7_F1_WAKEZ PPC_BIT32(0)
-#define END_W7_F1_LOG_SERVER_ID PPC_BITMASK32(1, 31)
-} XiveEND;
-
-#define xive_end_is_valid(end) (be32_to_cpu((end)->w0) & END_W0_VALID)
-#define xive_end_is_enqueue(end) (be32_to_cpu((end)->w0) & END_W0_ENQUEUE)
-#define xive_end_is_notify(end) (be32_to_cpu((end)->w0) & END_W0_UCOND_NOTIFY)
-#define xive_end_is_backlog(end) (be32_to_cpu((end)->w0) & END_W0_BACKLOG)
-#define xive_end_is_escalate(end) (be32_to_cpu((end)->w0) & END_W0_ESCALATE_CTL)
-#define xive_end_is_uncond_escalation(end) \
- (be32_to_cpu((end)->w0) & END_W0_UNCOND_ESCALATE)
-#define xive_end_is_silent_escalation(end) \
- (be32_to_cpu((end)->w0) & END_W0_SILENT_ESCALATE)
-
-static inline uint64_t xive_end_qaddr(XiveEND *end)
-{
- return ((uint64_t) be32_to_cpu(end->w2) & 0x0fffffff) << 32 |
- be32_to_cpu(end->w3);
-}
-
-void xive_end_pic_print_info(XiveEND *end, uint32_t end_idx, Monitor *mon);
-void xive_end_queue_pic_print_info(XiveEND *end, uint32_t width, Monitor *mon);
-void xive_end_eas_pic_print_info(XiveEND *end, uint32_t end_idx, Monitor *mon);
-
-/* Notification Virtual Target (NVT) */
-typedef struct XiveNVT {
- uint32_t w0;
-#define NVT_W0_VALID PPC_BIT32(0)
- uint32_t w1;
-#define NVT_W1_EQ_BLOCK PPC_BITMASK32(0, 3)
-#define NVT_W1_EQ_INDEX PPC_BITMASK32(4, 31)
- uint32_t w2;
- uint32_t w3;
- uint32_t w4;
-#define NVT_W4_IPB PPC_BITMASK32(16, 23)
- uint32_t w5;
- uint32_t w6;
- uint32_t w7;
- uint32_t w8;
-#define NVT_W8_GRP_VALID PPC_BIT32(0)
- uint32_t w9;
- uint32_t wa;
- uint32_t wb;
- uint32_t wc;
- uint32_t wd;
- uint32_t we;
- uint32_t wf;
-} XiveNVT;
-
-#define xive_nvt_is_valid(nvt) (be32_to_cpu((nvt)->w0) & NVT_W0_VALID)
-
-/*
- * The VP number space in a block is defined by the END_W6_NVT_INDEX
- * field of the XIVE END
- */
-#define XIVE_NVT_SHIFT 19
-#define XIVE_NVT_COUNT (1 << XIVE_NVT_SHIFT)
-
-static inline uint32_t xive_nvt_cam_line(uint8_t nvt_blk, uint32_t nvt_idx)
-{
- return (nvt_blk << XIVE_NVT_SHIFT) | nvt_idx;
-}
-
-static inline uint32_t xive_nvt_idx(uint32_t cam_line)
-{
- return cam_line & ((1 << XIVE_NVT_SHIFT) - 1);
-}
-
-static inline uint32_t xive_nvt_blk(uint32_t cam_line)
-{
- return (cam_line >> XIVE_NVT_SHIFT) & 0xf;
-}
-
-#endif /* PPC_XIVE_REGS_H */
+++ /dev/null
-/*
- * RDMA device interface
- *
- * Copyright (C) 2019 Oracle
- * Copyright (C) 2019 Red Hat Inc
- *
- * Authors:
- * Yuval Shaia <yuval.shaia@oracle.com>
- *
- * This work is licensed under the terms of the GNU GPL, version 2 or later.
- * See the COPYING file in the top-level directory.
- *
- */
-
-#ifndef RDMA_H
-#define RDMA_H
-
-#include "qom/object.h"
-
-#define INTERFACE_RDMA_PROVIDER "rdma"
-
-typedef struct RdmaProviderClass RdmaProviderClass;
-DECLARE_CLASS_CHECKERS(RdmaProviderClass, RDMA_PROVIDER,
- INTERFACE_RDMA_PROVIDER)
-#define RDMA_PROVIDER(obj) \
- INTERFACE_CHECK(RdmaProvider, (obj), \
- INTERFACE_RDMA_PROVIDER)
-
-typedef struct RdmaProvider RdmaProvider;
-
-struct RdmaProviderClass {
- InterfaceClass parent;
-
- void (*print_statistics)(Monitor *mon, RdmaProvider *obj);
-};
-
-#endif
+++ /dev/null
-/*
- * QEMU RISC-V Boot Helper
- *
- * Copyright (c) 2017 SiFive, Inc.
- * Copyright (c) 2019 Alistair Francis <alistair.francis@wdc.com>
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms and conditions of the GNU General Public License,
- * version 2 or later, as published by the Free Software Foundation.
- *
- * This program is distributed in the hope it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License along with
- * this program. If not, see <http://www.gnu.org/licenses/>.
- */
-
-#ifndef RISCV_BOOT_H
-#define RISCV_BOOT_H
-
-#include "exec/cpu-defs.h"
-#include "hw/loader.h"
-
-bool riscv_is_32_bit(MachineState *machine);
-
-target_ulong riscv_calc_kernel_start_addr(MachineState *machine,
- target_ulong firmware_end_addr);
-target_ulong riscv_find_and_load_firmware(MachineState *machine,
- const char *default_machine_firmware,
- hwaddr firmware_load_addr,
- symbol_fn_t sym_cb);
-char *riscv_find_firmware(const char *firmware_filename);
-target_ulong riscv_load_firmware(const char *firmware_filename,
- hwaddr firmware_load_addr,
- symbol_fn_t sym_cb);
-target_ulong riscv_load_kernel(const char *kernel_filename,
- target_ulong firmware_end_addr,
- symbol_fn_t sym_cb);
-hwaddr riscv_load_initrd(const char *filename, uint64_t mem_size,
- uint64_t kernel_entry, hwaddr *start);
-uint32_t riscv_load_fdt(hwaddr dram_start, uint64_t dram_size, void *fdt);
-void riscv_setup_rom_reset_vec(hwaddr saddr, hwaddr rom_base,
- hwaddr rom_size, uint64_t kernel_entry,
- uint32_t fdt_load_addr, void *fdt);
-void riscv_rom_copy_firmware_info(hwaddr rom_base, hwaddr rom_size,
- uint32_t reset_vec_size,
- uint64_t kernel_entry);
-
-#endif /* RISCV_BOOT_H */
+++ /dev/null
-/* SPDX-License-Identifier: BSD-2-Clause */
-/*
- * Copyright (c) 2019 Western Digital Corporation or its affiliates.
- *
- * Based on include/sbi/{fw_dynamic.h,sbi_scratch.h} from the OpenSBI project.
- */
-#ifndef OPENSBI_H
-#define OPENSBI_H
-
-/** Expected value of info magic ('OSBI' ascii string in hex) */
-#define FW_DYNAMIC_INFO_MAGIC_VALUE 0x4942534f
-
-/** Maximum supported info version */
-#define FW_DYNAMIC_INFO_VERSION 0x2
-
-/** Possible next mode values */
-#define FW_DYNAMIC_INFO_NEXT_MODE_U 0x0
-#define FW_DYNAMIC_INFO_NEXT_MODE_S 0x1
-#define FW_DYNAMIC_INFO_NEXT_MODE_M 0x3
-
-enum sbi_scratch_options {
- /** Disable prints during boot */
- SBI_SCRATCH_NO_BOOT_PRINTS = (1 << 0),
- /** Enable runtime debug prints */
- SBI_SCRATCH_DEBUG_PRINTS = (1 << 1),
-};
-
-/** Representation dynamic info passed by previous booting stage */
-struct fw_dynamic_info {
- /** Info magic */
- target_long magic;
- /** Info version */
- target_long version;
- /** Next booting stage address */
- target_long next_addr;
- /** Next booting stage mode */
- target_long next_mode;
- /** Options for OpenSBI library */
- target_long options;
- /**
- * Preferred boot HART id
- *
- * It is possible that the previous booting stage uses same link
- * address as the FW_DYNAMIC firmware. In this case, the relocation
- * lottery mechanism can potentially overwrite the previous booting
- * stage while other HARTs are still running in the previous booting
- * stage leading to boot-time crash. To avoid this boot-time crash,
- * the previous booting stage can specify last HART that will jump
- * to the FW_DYNAMIC firmware as the preferred boot HART.
- *
- * To avoid specifying a preferred boot HART, the previous booting
- * stage can set it to -1UL which will force the FW_DYNAMIC firmware
- * to use the relocation lottery mechanism.
- */
- target_long boot_hart;
-};
-
-#endif
+++ /dev/null
-/*
- * Microchip PolarFire SoC machine interface
- *
- * Copyright (c) 2020 Wind River Systems, Inc.
- *
- * Author:
- * Bin Meng <bin.meng@windriver.com>
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms and conditions of the GNU General Public License,
- * version 2 or later, as published by the Free Software Foundation.
- *
- * This program is distributed in the hope it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License along with
- * this program. If not, see <http://www.gnu.org/licenses/>.
- */
-
-#ifndef HW_MICROCHIP_PFSOC_H
-#define HW_MICROCHIP_PFSOC_H
-
-#include "hw/char/mchp_pfsoc_mmuart.h"
-#include "hw/dma/sifive_pdma.h"
-#include "hw/misc/mchp_pfsoc_dmc.h"
-#include "hw/misc/mchp_pfsoc_ioscb.h"
-#include "hw/misc/mchp_pfsoc_sysreg.h"
-#include "hw/net/cadence_gem.h"
-#include "hw/sd/cadence_sdhci.h"
-
-typedef struct MicrochipPFSoCState {
- /*< private >*/
- DeviceState parent_obj;
-
- /*< public >*/
- CPUClusterState e_cluster;
- CPUClusterState u_cluster;
- RISCVHartArrayState e_cpus;
- RISCVHartArrayState u_cpus;
- DeviceState *plic;
- MchpPfSoCDdrSgmiiPhyState ddr_sgmii_phy;
- MchpPfSoCDdrCfgState ddr_cfg;
- MchpPfSoCIoscbState ioscb;
- MchpPfSoCMMUartState *serial0;
- MchpPfSoCMMUartState *serial1;
- MchpPfSoCMMUartState *serial2;
- MchpPfSoCMMUartState *serial3;
- MchpPfSoCMMUartState *serial4;
- MchpPfSoCSysregState sysreg;
- SiFivePDMAState dma;
- CadenceGEMState gem0;
- CadenceGEMState gem1;
- CadenceSDHCIState sdhci;
-} MicrochipPFSoCState;
-
-#define TYPE_MICROCHIP_PFSOC "microchip.pfsoc"
-#define MICROCHIP_PFSOC(obj) \
- OBJECT_CHECK(MicrochipPFSoCState, (obj), TYPE_MICROCHIP_PFSOC)
-
-typedef struct MicrochipIcicleKitState {
- /*< private >*/
- MachineState parent_obj;
-
- /*< public >*/
- MicrochipPFSoCState soc;
-} MicrochipIcicleKitState;
-
-#define TYPE_MICROCHIP_ICICLE_KIT_MACHINE \
- MACHINE_TYPE_NAME("microchip-icicle-kit")
-#define MICROCHIP_ICICLE_KIT_MACHINE(obj) \
- OBJECT_CHECK(MicrochipIcicleKitState, (obj), \
- TYPE_MICROCHIP_ICICLE_KIT_MACHINE)
-
-enum {
- MICROCHIP_PFSOC_RSVD0,
- MICROCHIP_PFSOC_DEBUG,
- MICROCHIP_PFSOC_E51_DTIM,
- MICROCHIP_PFSOC_BUSERR_UNIT0,
- MICROCHIP_PFSOC_BUSERR_UNIT1,
- MICROCHIP_PFSOC_BUSERR_UNIT2,
- MICROCHIP_PFSOC_BUSERR_UNIT3,
- MICROCHIP_PFSOC_BUSERR_UNIT4,
- MICROCHIP_PFSOC_CLINT,
- MICROCHIP_PFSOC_L2CC,
- MICROCHIP_PFSOC_DMA,
- MICROCHIP_PFSOC_L2LIM,
- MICROCHIP_PFSOC_PLIC,
- MICROCHIP_PFSOC_MMUART0,
- MICROCHIP_PFSOC_SYSREG,
- MICROCHIP_PFSOC_MPUCFG,
- MICROCHIP_PFSOC_DDR_SGMII_PHY,
- MICROCHIP_PFSOC_EMMC_SD,
- MICROCHIP_PFSOC_DDR_CFG,
- MICROCHIP_PFSOC_MMUART1,
- MICROCHIP_PFSOC_MMUART2,
- MICROCHIP_PFSOC_MMUART3,
- MICROCHIP_PFSOC_MMUART4,
- MICROCHIP_PFSOC_I2C1,
- MICROCHIP_PFSOC_GEM0,
- MICROCHIP_PFSOC_GEM1,
- MICROCHIP_PFSOC_GPIO0,
- MICROCHIP_PFSOC_GPIO1,
- MICROCHIP_PFSOC_GPIO2,
- MICROCHIP_PFSOC_ENVM_CFG,
- MICROCHIP_PFSOC_ENVM_DATA,
- MICROCHIP_PFSOC_IOSCB,
- MICROCHIP_PFSOC_DRAM_LO,
- MICROCHIP_PFSOC_DRAM_LO_ALIAS,
- MICROCHIP_PFSOC_DRAM_HI,
- MICROCHIP_PFSOC_DRAM_HI_ALIAS
-};
-
-enum {
- MICROCHIP_PFSOC_DMA_IRQ0 = 5,
- MICROCHIP_PFSOC_DMA_IRQ1 = 6,
- MICROCHIP_PFSOC_DMA_IRQ2 = 7,
- MICROCHIP_PFSOC_DMA_IRQ3 = 8,
- MICROCHIP_PFSOC_DMA_IRQ4 = 9,
- MICROCHIP_PFSOC_DMA_IRQ5 = 10,
- MICROCHIP_PFSOC_DMA_IRQ6 = 11,
- MICROCHIP_PFSOC_DMA_IRQ7 = 12,
- MICROCHIP_PFSOC_GEM0_IRQ = 64,
- MICROCHIP_PFSOC_GEM1_IRQ = 70,
- MICROCHIP_PFSOC_EMMC_SD_IRQ = 88,
- MICROCHIP_PFSOC_MMUART0_IRQ = 90,
- MICROCHIP_PFSOC_MMUART1_IRQ = 91,
- MICROCHIP_PFSOC_MMUART2_IRQ = 92,
- MICROCHIP_PFSOC_MMUART3_IRQ = 93,
- MICROCHIP_PFSOC_MMUART4_IRQ = 94,
-};
-
-#define MICROCHIP_PFSOC_MANAGEMENT_CPU_COUNT 1
-#define MICROCHIP_PFSOC_COMPUTE_CPU_COUNT 4
-
-#define MICROCHIP_PFSOC_PLIC_HART_CONFIG "MS"
-#define MICROCHIP_PFSOC_PLIC_NUM_SOURCES 185
-#define MICROCHIP_PFSOC_PLIC_NUM_PRIORITIES 7
-#define MICROCHIP_PFSOC_PLIC_PRIORITY_BASE 0x04
-#define MICROCHIP_PFSOC_PLIC_PENDING_BASE 0x1000
-#define MICROCHIP_PFSOC_PLIC_ENABLE_BASE 0x2000
-#define MICROCHIP_PFSOC_PLIC_ENABLE_STRIDE 0x80
-#define MICROCHIP_PFSOC_PLIC_CONTEXT_BASE 0x200000
-#define MICROCHIP_PFSOC_PLIC_CONTEXT_STRIDE 0x1000
-
-#endif /* HW_MICROCHIP_PFSOC_H */
+++ /dev/null
-/*
- * QEMU RISC-V NUMA Helper
- *
- * Copyright (c) 2020 Western Digital Corporation or its affiliates.
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms and conditions of the GNU General Public License,
- * version 2 or later, as published by the Free Software Foundation.
- *
- * This program is distributed in the hope it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License along with
- * this program. If not, see <http://www.gnu.org/licenses/>.
- */
-
-#ifndef RISCV_NUMA_H
-#define RISCV_NUMA_H
-
-#include "hw/sysbus.h"
-#include "sysemu/numa.h"
-
-/**
- * riscv_socket_count:
- * @ms: pointer to machine state
- *
- * Returns: number of sockets for a numa system and 1 for a non-numa system
- */
-int riscv_socket_count(const MachineState *ms);
-
-/**
- * riscv_socket_first_hartid:
- * @ms: pointer to machine state
- * @socket_id: socket index
- *
- * Returns: first hartid for a valid socket and -1 for an invalid socket
- */
-int riscv_socket_first_hartid(const MachineState *ms, int socket_id);
-
-/**
- * riscv_socket_last_hartid:
- * @ms: pointer to machine state
- * @socket_id: socket index
- *
- * Returns: last hartid for a valid socket and -1 for an invalid socket
- */
-int riscv_socket_last_hartid(const MachineState *ms, int socket_id);
-
-/**
- * riscv_socket_hart_count:
- * @ms: pointer to machine state
- * @socket_id: socket index
- *
- * Returns: number of harts for a valid socket and -1 for an invalid socket
- */
-int riscv_socket_hart_count(const MachineState *ms, int socket_id);
-
-/**
- * riscv_socket_mem_offset:
- * @ms: pointer to machine state
- * @socket_id: socket index
- *
- * Returns: offset of ram belonging to given socket
- */
-uint64_t riscv_socket_mem_offset(const MachineState *ms, int socket_id);
-
-/**
- * riscv_socket_mem_size:
- * @ms: pointer to machine state
- * @socket_id: socket index
- *
- * Returns: size of ram belonging to given socket
- */
-uint64_t riscv_socket_mem_size(const MachineState *ms, int socket_id);
-
-/**
- * riscv_socket_check_hartids:
- * @ms: pointer to machine state
- * @socket_id: socket index
- *
- * Returns: true if hardids belonging to given socket are contiguous else false
- */
-bool riscv_socket_check_hartids(const MachineState *ms, int socket_id);
-
-/**
- * riscv_socket_fdt_write_id:
- * @ms: pointer to machine state
- * @socket_id: socket index
- *
- * Write NUMA node-id FDT property for given FDT node
- */
-void riscv_socket_fdt_write_id(const MachineState *ms, void *fdt,
- const char *node_name, int socket_id);
-
-/**
- * riscv_socket_fdt_write_distance_matrix:
- * @ms: pointer to machine state
- * @socket_id: socket index
- *
- * Write NUMA distance matrix in FDT for given machine
- */
-void riscv_socket_fdt_write_distance_matrix(const MachineState *ms, void *fdt);
-
-CpuInstanceProperties
-riscv_numa_cpu_index_to_props(MachineState *ms, unsigned cpu_index);
-
-int64_t riscv_numa_get_default_cpu_node_id(const MachineState *ms, int idx);
-
-const CPUArchIdList *riscv_numa_possible_cpu_arch_ids(MachineState *ms);
-
-#endif /* RISCV_NUMA_H */
+++ /dev/null
-/*
- * QEMU RISC-V Board Compatible with OpenTitan FPGA platform
- *
- * Copyright (c) 2020 Western Digital
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms and conditions of the GNU General Public License,
- * version 2 or later, as published by the Free Software Foundation.
- *
- * This program is distributed in the hope it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License along with
- * this program. If not, see <http://www.gnu.org/licenses/>.
- */
-
-#ifndef HW_OPENTITAN_H
-#define HW_OPENTITAN_H
-
-#include "hw/riscv/riscv_hart.h"
-#include "hw/intc/ibex_plic.h"
-#include "hw/char/ibex_uart.h"
-#include "qom/object.h"
-
-#define TYPE_RISCV_IBEX_SOC "riscv.lowrisc.ibex.soc"
-OBJECT_DECLARE_SIMPLE_TYPE(LowRISCIbexSoCState, RISCV_IBEX_SOC)
-
-struct LowRISCIbexSoCState {
- /*< private >*/
- SysBusDevice parent_obj;
-
- /*< public >*/
- RISCVHartArrayState cpus;
- IbexPlicState plic;
- IbexUartState uart;
-
- MemoryRegion flash_mem;
- MemoryRegion rom;
-};
-
-typedef struct OpenTitanState {
- /*< private >*/
- SysBusDevice parent_obj;
-
- /*< public >*/
- LowRISCIbexSoCState soc;
-} OpenTitanState;
-
-enum {
- IBEX_DEV_ROM,
- IBEX_DEV_RAM,
- IBEX_DEV_FLASH,
- IBEX_DEV_UART,
- IBEX_DEV_GPIO,
- IBEX_DEV_SPI,
- IBEX_DEV_FLASH_CTRL,
- IBEX_DEV_RV_TIMER,
- IBEX_DEV_AES,
- IBEX_DEV_HMAC,
- IBEX_DEV_PLIC,
- IBEX_DEV_PWRMGR,
- IBEX_DEV_RSTMGR,
- IBEX_DEV_CLKMGR,
- IBEX_DEV_PINMUX,
- IBEX_DEV_ALERT_HANDLER,
- IBEX_DEV_NMI_GEN,
- IBEX_DEV_USBDEV,
- IBEX_DEV_PADCTRL,
-};
-
-enum {
- IBEX_UART_RX_PARITY_ERR_IRQ = 0x28,
- IBEX_UART_RX_TIMEOUT_IRQ = 0x27,
- IBEX_UART_RX_BREAK_ERR_IRQ = 0x26,
- IBEX_UART_RX_FRAME_ERR_IRQ = 0x25,
- IBEX_UART_RX_OVERFLOW_IRQ = 0x24,
- IBEX_UART_TX_EMPTY_IRQ = 0x23,
- IBEX_UART_RX_WATERMARK_IRQ = 0x22,
- IBEX_UART_TX_WATERMARK_IRQ = 0x21,
-};
-
-#endif
+++ /dev/null
-/*
- * QEMU RISC-V Hart Array interface
- *
- * Copyright (c) 2017 SiFive, Inc.
- *
- * Holds the state of a heterogenous array of RISC-V harts
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms and conditions of the GNU General Public License,
- * version 2 or later, as published by the Free Software Foundation.
- *
- * This program is distributed in the hope it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License along with
- * this program. If not, see <http://www.gnu.org/licenses/>.
- */
-
-#ifndef HW_RISCV_HART_H
-#define HW_RISCV_HART_H
-
-#include "hw/sysbus.h"
-#include "target/riscv/cpu.h"
-#include "qom/object.h"
-
-#define TYPE_RISCV_HART_ARRAY "riscv.hart_array"
-
-OBJECT_DECLARE_SIMPLE_TYPE(RISCVHartArrayState, RISCV_HART_ARRAY)
-
-struct RISCVHartArrayState {
- /*< private >*/
- SysBusDevice parent_obj;
-
- /*< public >*/
- uint32_t num_harts;
- uint32_t hartid_base;
- char *cpu_type;
- uint64_t resetvec;
- RISCVCPU *harts;
-};
-
-#endif
+++ /dev/null
-/*
- * SiFive CPU types
- *
- * Copyright (c) 2017 SiFive, Inc.
- * Copyright (c) 2019 Bin Meng <bmeng.cn@gmail.com>
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms and conditions of the GNU General Public License,
- * version 2 or later, as published by the Free Software Foundation.
- *
- * This program is distributed in the hope it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License along with
- * this program. If not, see <http://www.gnu.org/licenses/>.
- */
-
-#ifndef HW_SIFIVE_CPU_H
-#define HW_SIFIVE_CPU_H
-
-#if defined(TARGET_RISCV32)
-#define SIFIVE_E_CPU TYPE_RISCV_CPU_SIFIVE_E31
-#define SIFIVE_U_CPU TYPE_RISCV_CPU_SIFIVE_U34
-#elif defined(TARGET_RISCV64)
-#define SIFIVE_E_CPU TYPE_RISCV_CPU_SIFIVE_E51
-#define SIFIVE_U_CPU TYPE_RISCV_CPU_SIFIVE_U54
-#endif
-
-#endif /* HW_SIFIVE_CPU_H */
+++ /dev/null
-/*
- * SiFive E series machine interface
- *
- * Copyright (c) 2017 SiFive, Inc.
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms and conditions of the GNU General Public License,
- * version 2 or later, as published by the Free Software Foundation.
- *
- * This program is distributed in the hope it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License along with
- * this program. If not, see <http://www.gnu.org/licenses/>.
- */
-
-#ifndef HW_SIFIVE_E_H
-#define HW_SIFIVE_E_H
-
-#include "hw/riscv/riscv_hart.h"
-#include "hw/riscv/sifive_cpu.h"
-#include "hw/gpio/sifive_gpio.h"
-
-#define TYPE_RISCV_E_SOC "riscv.sifive.e.soc"
-#define RISCV_E_SOC(obj) \
- OBJECT_CHECK(SiFiveESoCState, (obj), TYPE_RISCV_E_SOC)
-
-typedef struct SiFiveESoCState {
- /*< private >*/
- DeviceState parent_obj;
-
- /*< public >*/
- RISCVHartArrayState cpus;
- DeviceState *plic;
- SIFIVEGPIOState gpio;
- MemoryRegion xip_mem;
- MemoryRegion mask_rom;
-} SiFiveESoCState;
-
-typedef struct SiFiveEState {
- /*< private >*/
- SysBusDevice parent_obj;
-
- /*< public >*/
- SiFiveESoCState soc;
- bool revb;
-} SiFiveEState;
-
-#define TYPE_RISCV_E_MACHINE MACHINE_TYPE_NAME("sifive_e")
-#define RISCV_E_MACHINE(obj) \
- OBJECT_CHECK(SiFiveEState, (obj), TYPE_RISCV_E_MACHINE)
-
-enum {
- SIFIVE_E_DEV_DEBUG,
- SIFIVE_E_DEV_MROM,
- SIFIVE_E_DEV_OTP,
- SIFIVE_E_DEV_CLINT,
- SIFIVE_E_DEV_PLIC,
- SIFIVE_E_DEV_AON,
- SIFIVE_E_DEV_PRCI,
- SIFIVE_E_DEV_OTP_CTRL,
- SIFIVE_E_DEV_GPIO0,
- SIFIVE_E_DEV_UART0,
- SIFIVE_E_DEV_QSPI0,
- SIFIVE_E_DEV_PWM0,
- SIFIVE_E_DEV_UART1,
- SIFIVE_E_DEV_QSPI1,
- SIFIVE_E_DEV_PWM1,
- SIFIVE_E_DEV_QSPI2,
- SIFIVE_E_DEV_PWM2,
- SIFIVE_E_DEV_XIP,
- SIFIVE_E_DEV_DTIM
-};
-
-enum {
- SIFIVE_E_UART0_IRQ = 3,
- SIFIVE_E_UART1_IRQ = 4,
- SIFIVE_E_GPIO0_IRQ0 = 8
-};
-
-#define SIFIVE_E_PLIC_HART_CONFIG "M"
-#define SIFIVE_E_PLIC_NUM_SOURCES 127
-#define SIFIVE_E_PLIC_NUM_PRIORITIES 7
-#define SIFIVE_E_PLIC_PRIORITY_BASE 0x04
-#define SIFIVE_E_PLIC_PENDING_BASE 0x1000
-#define SIFIVE_E_PLIC_ENABLE_BASE 0x2000
-#define SIFIVE_E_PLIC_ENABLE_STRIDE 0x80
-#define SIFIVE_E_PLIC_CONTEXT_BASE 0x200000
-#define SIFIVE_E_PLIC_CONTEXT_STRIDE 0x1000
-
-#endif
+++ /dev/null
-/*
- * SiFive U series machine interface
- *
- * Copyright (c) 2017 SiFive, Inc.
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms and conditions of the GNU General Public License,
- * version 2 or later, as published by the Free Software Foundation.
- *
- * This program is distributed in the hope it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License along with
- * this program. If not, see <http://www.gnu.org/licenses/>.
- */
-
-#ifndef HW_SIFIVE_U_H
-#define HW_SIFIVE_U_H
-
-#include "hw/dma/sifive_pdma.h"
-#include "hw/net/cadence_gem.h"
-#include "hw/riscv/riscv_hart.h"
-#include "hw/riscv/sifive_cpu.h"
-#include "hw/gpio/sifive_gpio.h"
-#include "hw/misc/sifive_u_otp.h"
-#include "hw/misc/sifive_u_prci.h"
-
-#define TYPE_RISCV_U_SOC "riscv.sifive.u.soc"
-#define RISCV_U_SOC(obj) \
- OBJECT_CHECK(SiFiveUSoCState, (obj), TYPE_RISCV_U_SOC)
-
-typedef struct SiFiveUSoCState {
- /*< private >*/
- DeviceState parent_obj;
-
- /*< public >*/
- CPUClusterState e_cluster;
- CPUClusterState u_cluster;
- RISCVHartArrayState e_cpus;
- RISCVHartArrayState u_cpus;
- DeviceState *plic;
- SiFiveUPRCIState prci;
- SIFIVEGPIOState gpio;
- SiFiveUOTPState otp;
- SiFivePDMAState dma;
- CadenceGEMState gem;
-
- uint32_t serial;
- char *cpu_type;
-} SiFiveUSoCState;
-
-#define TYPE_RISCV_U_MACHINE MACHINE_TYPE_NAME("sifive_u")
-#define RISCV_U_MACHINE(obj) \
- OBJECT_CHECK(SiFiveUState, (obj), TYPE_RISCV_U_MACHINE)
-
-typedef struct SiFiveUState {
- /*< private >*/
- MachineState parent_obj;
-
- /*< public >*/
- SiFiveUSoCState soc;
-
- void *fdt;
- int fdt_size;
-
- bool start_in_flash;
- uint32_t msel;
- uint32_t serial;
-} SiFiveUState;
-
-enum {
- SIFIVE_U_DEV_DEBUG,
- SIFIVE_U_DEV_MROM,
- SIFIVE_U_DEV_CLINT,
- SIFIVE_U_DEV_L2CC,
- SIFIVE_U_DEV_PDMA,
- SIFIVE_U_DEV_L2LIM,
- SIFIVE_U_DEV_PLIC,
- SIFIVE_U_DEV_PRCI,
- SIFIVE_U_DEV_UART0,
- SIFIVE_U_DEV_UART1,
- SIFIVE_U_DEV_GPIO,
- SIFIVE_U_DEV_OTP,
- SIFIVE_U_DEV_DMC,
- SIFIVE_U_DEV_FLASH0,
- SIFIVE_U_DEV_DRAM,
- SIFIVE_U_DEV_GEM,
- SIFIVE_U_DEV_GEM_MGMT
-};
-
-enum {
- SIFIVE_U_L2CC_IRQ0 = 1,
- SIFIVE_U_L2CC_IRQ1 = 2,
- SIFIVE_U_L2CC_IRQ2 = 3,
- SIFIVE_U_UART0_IRQ = 4,
- SIFIVE_U_UART1_IRQ = 5,
- SIFIVE_U_GPIO_IRQ0 = 7,
- SIFIVE_U_GPIO_IRQ1 = 8,
- SIFIVE_U_GPIO_IRQ2 = 9,
- SIFIVE_U_GPIO_IRQ3 = 10,
- SIFIVE_U_GPIO_IRQ4 = 11,
- SIFIVE_U_GPIO_IRQ5 = 12,
- SIFIVE_U_GPIO_IRQ6 = 13,
- SIFIVE_U_GPIO_IRQ7 = 14,
- SIFIVE_U_GPIO_IRQ8 = 15,
- SIFIVE_U_GPIO_IRQ9 = 16,
- SIFIVE_U_GPIO_IRQ10 = 17,
- SIFIVE_U_GPIO_IRQ11 = 18,
- SIFIVE_U_GPIO_IRQ12 = 19,
- SIFIVE_U_GPIO_IRQ13 = 20,
- SIFIVE_U_GPIO_IRQ14 = 21,
- SIFIVE_U_GPIO_IRQ15 = 22,
- SIFIVE_U_PDMA_IRQ0 = 23,
- SIFIVE_U_PDMA_IRQ1 = 24,
- SIFIVE_U_PDMA_IRQ2 = 25,
- SIFIVE_U_PDMA_IRQ3 = 26,
- SIFIVE_U_PDMA_IRQ4 = 27,
- SIFIVE_U_PDMA_IRQ5 = 28,
- SIFIVE_U_PDMA_IRQ6 = 29,
- SIFIVE_U_PDMA_IRQ7 = 30,
- SIFIVE_U_GEM_IRQ = 0x35
-};
-
-enum {
- SIFIVE_U_HFCLK_FREQ = 33333333,
- SIFIVE_U_RTCCLK_FREQ = 1000000
-};
-
-enum {
- MSEL_MEMMAP_QSPI0_FLASH = 1,
- MSEL_L2LIM_QSPI0_FLASH = 6,
- MSEL_L2LIM_QSPI2_SD = 11
-};
-
-#define SIFIVE_U_MANAGEMENT_CPU_COUNT 1
-#define SIFIVE_U_COMPUTE_CPU_COUNT 4
-
-#define SIFIVE_U_PLIC_HART_CONFIG "MS"
-#define SIFIVE_U_PLIC_NUM_SOURCES 54
-#define SIFIVE_U_PLIC_NUM_PRIORITIES 7
-#define SIFIVE_U_PLIC_PRIORITY_BASE 0x04
-#define SIFIVE_U_PLIC_PENDING_BASE 0x1000
-#define SIFIVE_U_PLIC_ENABLE_BASE 0x2000
-#define SIFIVE_U_PLIC_ENABLE_STRIDE 0x80
-#define SIFIVE_U_PLIC_CONTEXT_BASE 0x200000
-#define SIFIVE_U_PLIC_CONTEXT_STRIDE 0x1000
-
-#endif
+++ /dev/null
-/*
- * Spike machine interface
- *
- * Copyright (c) 2017 SiFive, Inc.
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms and conditions of the GNU General Public License,
- * version 2 or later, as published by the Free Software Foundation.
- *
- * This program is distributed in the hope it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License along with
- * this program. If not, see <http://www.gnu.org/licenses/>.
- */
-
-#ifndef HW_RISCV_SPIKE_H
-#define HW_RISCV_SPIKE_H
-
-#include "hw/riscv/riscv_hart.h"
-#include "hw/sysbus.h"
-#include "qom/object.h"
-
-#define SPIKE_CPUS_MAX 8
-#define SPIKE_SOCKETS_MAX 8
-
-#define TYPE_SPIKE_MACHINE MACHINE_TYPE_NAME("spike")
-typedef struct SpikeState SpikeState;
-DECLARE_INSTANCE_CHECKER(SpikeState, SPIKE_MACHINE,
- TYPE_SPIKE_MACHINE)
-
-struct SpikeState {
- /*< private >*/
- MachineState parent;
-
- /*< public >*/
- RISCVHartArrayState soc[SPIKE_SOCKETS_MAX];
- void *fdt;
- int fdt_size;
-};
-
-enum {
- SPIKE_MROM,
- SPIKE_CLINT,
- SPIKE_DRAM
-};
-
-#if defined(TARGET_RISCV32)
-#define SPIKE_V1_10_0_CPU TYPE_RISCV_CPU_BASE32
-#elif defined(TARGET_RISCV64)
-#define SPIKE_V1_10_0_CPU TYPE_RISCV_CPU_BASE64
-#endif
-
-#endif
+++ /dev/null
-/*
- * QEMU RISC-V VirtIO machine interface
- *
- * Copyright (c) 2017 SiFive, Inc.
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms and conditions of the GNU General Public License,
- * version 2 or later, as published by the Free Software Foundation.
- *
- * This program is distributed in the hope it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License along with
- * this program. If not, see <http://www.gnu.org/licenses/>.
- */
-
-#ifndef HW_RISCV_VIRT_H
-#define HW_RISCV_VIRT_H
-
-#include "hw/riscv/riscv_hart.h"
-#include "hw/sysbus.h"
-#include "hw/block/flash.h"
-#include "qom/object.h"
-
-#define VIRT_CPUS_MAX 8
-#define VIRT_SOCKETS_MAX 8
-
-#define TYPE_RISCV_VIRT_MACHINE MACHINE_TYPE_NAME("virt")
-typedef struct RISCVVirtState RISCVVirtState;
-DECLARE_INSTANCE_CHECKER(RISCVVirtState, RISCV_VIRT_MACHINE,
- TYPE_RISCV_VIRT_MACHINE)
-
-struct RISCVVirtState {
- /*< private >*/
- MachineState parent;
-
- /*< public >*/
- RISCVHartArrayState soc[VIRT_SOCKETS_MAX];
- DeviceState *plic[VIRT_SOCKETS_MAX];
- PFlashCFI01 *flash[2];
-
- void *fdt;
- int fdt_size;
-};
-
-enum {
- VIRT_DEBUG,
- VIRT_MROM,
- VIRT_TEST,
- VIRT_RTC,
- VIRT_CLINT,
- VIRT_PLIC,
- VIRT_UART0,
- VIRT_VIRTIO,
- VIRT_FLASH,
- VIRT_DRAM,
- VIRT_PCIE_MMIO,
- VIRT_PCIE_PIO,
- VIRT_PCIE_ECAM
-};
-
-enum {
- UART0_IRQ = 10,
- RTC_IRQ = 11,
- VIRTIO_IRQ = 1, /* 1 to 8 */
- VIRTIO_COUNT = 8,
- PCIE_IRQ = 0x20, /* 32 to 35 */
- VIRTIO_NDEV = 0x35 /* Arbitrary maximum number of interrupts */
-};
-
-#define VIRT_PLIC_HART_CONFIG "MS"
-#define VIRT_PLIC_NUM_SOURCES 127
-#define VIRT_PLIC_NUM_PRIORITIES 7
-#define VIRT_PLIC_PRIORITY_BASE 0x04
-#define VIRT_PLIC_PENDING_BASE 0x1000
-#define VIRT_PLIC_ENABLE_BASE 0x2000
-#define VIRT_PLIC_ENABLE_STRIDE 0x80
-#define VIRT_PLIC_CONTEXT_BASE 0x200000
-#define VIRT_PLIC_CONTEXT_STRIDE 0x1000
-#define VIRT_PLIC_SIZE(__num_context) \
- (VIRT_PLIC_CONTEXT_BASE + (__num_context) * VIRT_PLIC_CONTEXT_STRIDE)
-
-#define FDT_PCI_ADDR_CELLS 3
-#define FDT_PCI_INT_CELLS 1
-#define FDT_PLIC_ADDR_CELLS 0
-#define FDT_PLIC_INT_CELLS 1
-#define FDT_INT_MAP_WIDTH (FDT_PCI_ADDR_CELLS + FDT_PCI_INT_CELLS + 1 + \
- FDT_PLIC_ADDR_CELLS + FDT_PLIC_INT_CELLS)
-
-#if defined(TARGET_RISCV32)
-#define VIRT_CPU TYPE_RISCV_CPU_BASE32
-#elif defined(TARGET_RISCV64)
-#define VIRT_CPU TYPE_RISCV_CPU_BASE64
-#endif
-
-#endif
+++ /dev/null
-/*
- * Allwinner Real Time Clock emulation
- *
- * Copyright (C) 2019 Niek Linnenbank <nieklinnenbank@gmail.com>
- *
- * This program is free software: you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation, either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program. If not, see <http://www.gnu.org/licenses/>.
- */
-
-#ifndef HW_MISC_ALLWINNER_RTC_H
-#define HW_MISC_ALLWINNER_RTC_H
-
-#include "qom/object.h"
-#include "hw/sysbus.h"
-
-/**
- * Constants
- * @{
- */
-
-/** Highest register address used by RTC device */
-#define AW_RTC_REGS_MAXADDR (0x200)
-
-/** Total number of known registers */
-#define AW_RTC_REGS_NUM (AW_RTC_REGS_MAXADDR / sizeof(uint32_t))
-
-/** @} */
-
-/**
- * Object model types
- * @{
- */
-
-/** Generic Allwinner RTC device (abstract) */
-#define TYPE_AW_RTC "allwinner-rtc"
-
-/** Allwinner RTC sun4i family (A10, A12) */
-#define TYPE_AW_RTC_SUN4I TYPE_AW_RTC "-sun4i"
-
-/** Allwinner RTC sun6i family and newer (A31, H2+, H3, etc) */
-#define TYPE_AW_RTC_SUN6I TYPE_AW_RTC "-sun6i"
-
-/** Allwinner RTC sun7i family (A20) */
-#define TYPE_AW_RTC_SUN7I TYPE_AW_RTC "-sun7i"
-
-/** @} */
-
-/**
- * Object model macros
- * @{
- */
-
-OBJECT_DECLARE_TYPE(AwRtcState, AwRtcClass, AW_RTC)
-
-/** @} */
-
-/**
- * Allwinner RTC per-object instance state.
- */
-struct AwRtcState {
- /*< private >*/
- SysBusDevice parent_obj;
- /*< public >*/
-
- /**
- * Actual year represented by the device when year counter is zero
- *
- * Can be overridden by the user using the corresponding 'base-year'
- * property. The base year used by the target OS driver can vary, for
- * example the Linux driver for sun6i uses 1970 while NetBSD uses 2000.
- */
- int base_year;
-
- /** Maps I/O registers in physical memory */
- MemoryRegion iomem;
-
- /** Array of hardware registers */
- uint32_t regs[AW_RTC_REGS_NUM];
-
-};
-
-/**
- * Allwinner RTC class-level struct.
- *
- * This struct is filled by each sunxi device specific code
- * such that the generic code can use this struct to support
- * all devices.
- */
-struct AwRtcClass {
- /*< private >*/
- SysBusDeviceClass parent_class;
- /*< public >*/
-
- /** Defines device specific register map */
- const uint8_t *regmap;
-
- /** Size of the regmap in bytes */
- size_t regmap_size;
-
- /**
- * Read device specific register
- *
- * @offset: register offset to read
- * @return true if register read successful, false otherwise
- */
- bool (*read)(AwRtcState *s, uint32_t offset);
-
- /**
- * Write device specific register
- *
- * @offset: register offset to write
- * @data: value to set in register
- * @return true if register write successful, false otherwise
- */
- bool (*write)(AwRtcState *s, uint32_t offset, uint32_t data);
-
-};
-
-#endif /* HW_MISC_ALLWINNER_RTC_H */
+++ /dev/null
-/*
- * ASPEED Real Time Clock
- * Joel Stanley <joel@jms.id.au>
- *
- * Copyright 2019 IBM Corp
- * SPDX-License-Identifier: GPL-2.0-or-later
- */
-#ifndef HW_RTC_ASPEED_RTC_H
-#define HW_RTC_ASPEED_RTC_H
-
-#include "hw/sysbus.h"
-#include "qom/object.h"
-
-struct AspeedRtcState {
- SysBusDevice parent_obj;
-
- MemoryRegion iomem;
- qemu_irq irq;
-
- uint32_t reg[0x18];
- int offset;
-
-};
-
-#define TYPE_ASPEED_RTC "aspeed.rtc"
-OBJECT_DECLARE_SIMPLE_TYPE(AspeedRtcState, ASPEED_RTC)
-
-#endif /* HW_RTC_ASPEED_RTC_H */
+++ /dev/null
-/*
- * Goldfish virtual platform RTC
- *
- * Copyright (C) 2019 Western Digital Corporation or its affiliates.
- *
- * For more details on Google Goldfish virtual platform refer:
- * https://android.googlesource.com/platform/external/qemu/+/master/docs/GOLDFISH-VIRTUAL-HARDWARE.TXT
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms and conditions of the GNU General Public License,
- * version 2 or later, as published by the Free Software Foundation.
- *
- * This program is distributed in the hope it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License along with
- * this program. If not, see <http://www.gnu.org/licenses/>.
- */
-
-#ifndef HW_RTC_GOLDFISH_RTC_H
-#define HW_RTC_GOLDFISH_RTC_H
-
-#include "hw/sysbus.h"
-#include "qom/object.h"
-
-#define TYPE_GOLDFISH_RTC "goldfish_rtc"
-OBJECT_DECLARE_SIMPLE_TYPE(GoldfishRTCState, GOLDFISH_RTC)
-
-struct GoldfishRTCState {
- SysBusDevice parent_obj;
-
- MemoryRegion iomem;
- QEMUTimer *timer;
- qemu_irq irq;
-
- uint64_t tick_offset;
- uint64_t tick_offset_vmstate;
- uint64_t alarm_next;
- uint32_t alarm_running;
- uint32_t irq_pending;
- uint32_t irq_enabled;
- uint32_t time_high;
-};
-
-#endif
+++ /dev/null
-/*
- * QEMU M48T59 and M48T08 NVRAM emulation
- *
- * Copyright (c) 2003-2005, 2007 Jocelyn Mayer
- * Copyright (c) 2013 Hervé Poussineau
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
- * furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
- * THE SOFTWARE.
- */
-
-#ifndef HW_RTC_M48T59_H
-#define HW_RTC_M48T59_H
-
-#include "exec/hwaddr.h"
-#include "qom/object.h"
-
-#define TYPE_NVRAM "nvram"
-
-typedef struct NvramClass NvramClass;
-DECLARE_CLASS_CHECKERS(NvramClass, NVRAM,
- TYPE_NVRAM)
-#define NVRAM(obj) \
- INTERFACE_CHECK(Nvram, (obj), TYPE_NVRAM)
-
-typedef struct Nvram Nvram;
-
-struct NvramClass {
- InterfaceClass parent;
-
- uint32_t (*read)(Nvram *obj, uint32_t addr);
- void (*write)(Nvram *obj, uint32_t addr, uint32_t val);
- void (*toggle_lock)(Nvram *obj, int lock);
-};
-
-#endif /* HW_M48T59_H */
+++ /dev/null
-/*
- * QEMU MC146818 RTC emulation
- *
- * Copyright (c) 2003-2004 Fabrice Bellard
- *
- * SPDX-License-Identifier: MIT
- */
-
-#ifndef HW_RTC_MC146818RTC_H
-#define HW_RTC_MC146818RTC_H
-
-#include "qapi/qapi-types-machine.h"
-#include "qemu/queue.h"
-#include "qemu/timer.h"
-#include "hw/isa/isa.h"
-#include "qom/object.h"
-
-#define TYPE_MC146818_RTC "mc146818rtc"
-OBJECT_DECLARE_SIMPLE_TYPE(RTCState, MC146818_RTC)
-
-struct RTCState {
- ISADevice parent_obj;
-
- MemoryRegion io;
- MemoryRegion coalesced_io;
- uint8_t cmos_data[128];
- uint8_t cmos_index;
- int32_t base_year;
- uint64_t base_rtc;
- uint64_t last_update;
- int64_t offset;
- qemu_irq irq;
- int it_shift;
- /* periodic timer */
- QEMUTimer *periodic_timer;
- int64_t next_periodic_time;
- /* update-ended timer */
- QEMUTimer *update_timer;
- uint64_t next_alarm_time;
- uint16_t irq_reinject_on_ack_count;
- uint32_t irq_coalesced;
- uint32_t period;
- QEMUTimer *coalesced_timer;
- Notifier clock_reset_notifier;
- LostTickPolicy lost_tick_policy;
- Notifier suspend_notifier;
- QLIST_ENTRY(RTCState) link;
-};
-
-#define RTC_ISA_IRQ 8
-#define RTC_ISA_BASE 0x70
-
-ISADevice *mc146818_rtc_init(ISABus *bus, int base_year,
- qemu_irq intercept_irq);
-void rtc_set_memory(ISADevice *dev, int addr, int val);
-int rtc_get_memory(ISADevice *dev, int addr);
-
-#endif /* MC146818RTC_H */
+++ /dev/null
-/*
- * QEMU MC146818 RTC emulation
- *
- * Copyright (c) 2003-2004 Fabrice Bellard
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
- * furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
- * THE SOFTWARE.
- */
-
-#ifndef HW_RTC_MC146818RTC_REGS_H
-#define HW_RTC_MC146818RTC_REGS_H
-
-#include "qemu/timer.h"
-#include "qemu/host-utils.h"
-
-#define RTC_SECONDS 0
-#define RTC_SECONDS_ALARM 1
-#define RTC_MINUTES 2
-#define RTC_MINUTES_ALARM 3
-#define RTC_HOURS 4
-#define RTC_HOURS_ALARM 5
-#define RTC_ALARM_DONT_CARE 0xC0
-
-#define RTC_DAY_OF_WEEK 6
-#define RTC_DAY_OF_MONTH 7
-#define RTC_MONTH 8
-#define RTC_YEAR 9
-
-#define RTC_REG_A 10
-#define RTC_REG_B 11
-#define RTC_REG_C 12
-#define RTC_REG_D 13
-
-/* PC cmos mappings */
-#define RTC_CENTURY 0x32
-#define RTC_IBM_PS2_CENTURY_BYTE 0x37
-
-#define REG_A_UIP 0x80
-
-#define REG_B_SET 0x80
-#define REG_B_PIE 0x40
-#define REG_B_AIE 0x20
-#define REG_B_UIE 0x10
-#define REG_B_SQWE 0x08
-#define REG_B_DM 0x04
-#define REG_B_24H 0x02
-
-#define REG_C_UF 0x10
-#define REG_C_IRQF 0x80
-#define REG_C_PF 0x40
-#define REG_C_AF 0x20
-#define REG_C_MASK 0x70
-
-static inline uint32_t periodic_period_to_clock(int period_code)
-{
- if (!period_code) {
- return 0;
- }
-
- if (period_code <= 2) {
- period_code += 7;
- }
- /* period in 32 Khz cycles */
- return 1 << (period_code - 1);
-}
-
-#define RTC_CLOCK_RATE 32768
-
-static inline int64_t periodic_clock_to_ns(int64_t clocks)
-{
- return muldiv64(clocks, NANOSECONDS_PER_SECOND, RTC_CLOCK_RATE);
-}
-
-#endif
+++ /dev/null
-/*
- * ARM AMBA PrimeCell PL031 RTC
- *
- * Copyright (c) 2007 CodeSourcery
- *
- * This file is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * Contributions after 2012-01-13 are licensed under the terms of the
- * GNU GPL, version 2 or (at your option) any later version.
- */
-
-#ifndef HW_RTC_PL031_H
-#define HW_RTC_PL031_H
-
-#include "hw/sysbus.h"
-#include "qemu/timer.h"
-#include "qom/object.h"
-
-#define TYPE_PL031 "pl031"
-OBJECT_DECLARE_SIMPLE_TYPE(PL031State, PL031)
-
-struct PL031State {
- SysBusDevice parent_obj;
-
- MemoryRegion iomem;
- QEMUTimer *timer;
- qemu_irq irq;
-
- /*
- * Needed to preserve the tick_count across migration, even if the
- * absolute value of the rtc_clock is different on the source and
- * destination.
- */
- uint32_t tick_offset_vmstate;
- uint32_t tick_offset;
- bool tick_offset_migrated;
- bool migrate_tick_offset;
-
- uint32_t mr;
- uint32_t lr;
- uint32_t cr;
- uint32_t im;
- uint32_t is;
-};
-
-#endif
+++ /dev/null
-/*
- * QEMU sun4v Real Time Clock device
- *
- * The sun4v_rtc device (sun4v tod clock)
- *
- * Copyright (c) 2016 Artyom Tarasenko
- *
- * This code is licensed under the GNU GPL v3 or (at your option) any later
- * version.
- */
-
-#ifndef HW_RTC_SUN4V
-#define HW_RTC_SUN4V
-
-#include "exec/hwaddr.h"
-
-void sun4v_rtc_init(hwaddr addr);
-
-#endif
+++ /dev/null
-/*
- * QEMU model of the Xilinx ZynqMP Real Time Clock (RTC).
- *
- * Copyright (c) 2017 Xilinx Inc.
- *
- * Written-by: Alistair Francis
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
- * furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
- * THE SOFTWARE.
- */
-
-#ifndef HW_RTC_XLNX_ZYNQMP_H
-#define HW_RTC_XLNX_ZYNQMP_H
-
-#include "hw/register.h"
-#include "hw/sysbus.h"
-#include "qom/object.h"
-
-#define TYPE_XLNX_ZYNQMP_RTC "xlnx-zynmp.rtc"
-
-OBJECT_DECLARE_SIMPLE_TYPE(XlnxZynqMPRTC, XLNX_ZYNQMP_RTC)
-
-REG32(SET_TIME_WRITE, 0x0)
-REG32(SET_TIME_READ, 0x4)
-REG32(CALIB_WRITE, 0x8)
- FIELD(CALIB_WRITE, FRACTION_EN, 20, 1)
- FIELD(CALIB_WRITE, FRACTION_DATA, 16, 4)
- FIELD(CALIB_WRITE, MAX_TICK, 0, 16)
-REG32(CALIB_READ, 0xc)
- FIELD(CALIB_READ, FRACTION_EN, 20, 1)
- FIELD(CALIB_READ, FRACTION_DATA, 16, 4)
- FIELD(CALIB_READ, MAX_TICK, 0, 16)
-REG32(CURRENT_TIME, 0x10)
-REG32(CURRENT_TICK, 0x14)
- FIELD(CURRENT_TICK, VALUE, 0, 16)
-REG32(ALARM, 0x18)
-REG32(RTC_INT_STATUS, 0x20)
- FIELD(RTC_INT_STATUS, ALARM, 1, 1)
- FIELD(RTC_INT_STATUS, SECONDS, 0, 1)
-REG32(RTC_INT_MASK, 0x24)
- FIELD(RTC_INT_MASK, ALARM, 1, 1)
- FIELD(RTC_INT_MASK, SECONDS, 0, 1)
-REG32(RTC_INT_EN, 0x28)
- FIELD(RTC_INT_EN, ALARM, 1, 1)
- FIELD(RTC_INT_EN, SECONDS, 0, 1)
-REG32(RTC_INT_DIS, 0x2c)
- FIELD(RTC_INT_DIS, ALARM, 1, 1)
- FIELD(RTC_INT_DIS, SECONDS, 0, 1)
-REG32(ADDR_ERROR, 0x30)
- FIELD(ADDR_ERROR, STATUS, 0, 1)
-REG32(ADDR_ERROR_INT_MASK, 0x34)
- FIELD(ADDR_ERROR_INT_MASK, MASK, 0, 1)
-REG32(ADDR_ERROR_INT_EN, 0x38)
- FIELD(ADDR_ERROR_INT_EN, MASK, 0, 1)
-REG32(ADDR_ERROR_INT_DIS, 0x3c)
- FIELD(ADDR_ERROR_INT_DIS, MASK, 0, 1)
-REG32(CONTROL, 0x40)
- FIELD(CONTROL, BATTERY_DISABLE, 31, 1)
- FIELD(CONTROL, OSC_CNTRL, 24, 4)
- FIELD(CONTROL, SLVERR_ENABLE, 0, 1)
-REG32(SAFETY_CHK, 0x50)
-
-#define XLNX_ZYNQMP_RTC_R_MAX (R_SAFETY_CHK + 1)
-
-struct XlnxZynqMPRTC {
- SysBusDevice parent_obj;
- MemoryRegion iomem;
- qemu_irq irq_rtc_int;
- qemu_irq irq_addr_error_int;
-
- uint32_t tick_offset;
-
- uint32_t regs[XLNX_ZYNQMP_RTC_R_MAX];
- RegisterInfo regs_info[XLNX_ZYNQMP_RTC_R_MAX];
-};
-
-#endif
+++ /dev/null
-/*
- * RX62N MCU Object
- *
- * Datasheet: RX62N Group, RX621 Group User's Manual: Hardware
- * (Rev.1.40 R01UH0033EJ0140)
- *
- * Copyright (c) 2019 Yoshinori Sato
- *
- * SPDX-License-Identifier: GPL-2.0-or-later
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms and conditions of the GNU General Public License,
- * version 2 or later, as published by the Free Software Foundation.
- *
- * This program is distributed in the hope it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License along with
- * this program. If not, see <http://www.gnu.org/licenses/>.
- */
-
-#ifndef HW_RX_RX62N_MCU_H
-#define HW_RX_RX62N_MCU_H
-
-#include "target/rx/cpu.h"
-#include "hw/intc/rx_icu.h"
-#include "hw/timer/renesas_tmr.h"
-#include "hw/timer/renesas_cmt.h"
-#include "hw/char/renesas_sci.h"
-#include "qemu/units.h"
-#include "qom/object.h"
-
-#define TYPE_RX62N_MCU "rx62n-mcu"
-typedef struct RX62NState RX62NState;
-DECLARE_INSTANCE_CHECKER(RX62NState, RX62N_MCU,
- TYPE_RX62N_MCU)
-
-#define TYPE_R5F562N7_MCU "r5f562n7-mcu"
-#define TYPE_R5F562N8_MCU "r5f562n8-mcu"
-
-#define EXT_CS_BASE 0x01000000
-#define VECTOR_TABLE_BASE 0xffffff80
-#define RX62N_CFLASH_BASE 0xfff80000
-
-#define RX62N_NR_TMR 2
-#define RX62N_NR_CMT 2
-#define RX62N_NR_SCI 6
-
-struct RX62NState {
- /*< private >*/
- DeviceState parent_obj;
- /*< public >*/
-
- RXCPU cpu;
- RXICUState icu;
- RTMRState tmr[RX62N_NR_TMR];
- RCMTState cmt[RX62N_NR_CMT];
- RSCIState sci[RX62N_NR_SCI];
-
- MemoryRegion *sysmem;
- bool kernel;
-
- MemoryRegion iram;
- MemoryRegion iomem1;
- MemoryRegion d_flash;
- MemoryRegion iomem2;
- MemoryRegion iomem3;
- MemoryRegion c_flash;
- qemu_irq irq[NR_IRQS];
-
- /* Input Clock (XTAL) frequency */
- uint32_t xtal_freq_hz;
- /* Peripheral Module Clock frequency */
- uint32_t pclk_freq_hz;
-};
-
-#endif
+++ /dev/null
-/*
- * Emulated ccw-attached 3270 definitions
- *
- * Copyright 2017 IBM Corp.
- * Author(s): Yang Chen <bjcyang@linux.vnet.ibm.com>
- * Jing Liu <liujbjl@linux.vnet.ibm.com>
- *
- * This work is licensed under the terms of the GNU GPL, version 2 or (at
- * your option) any later version. See the COPYING file in the top-level
- * directory.
- */
-
-#ifndef HW_S390X_3270_CCW_H
-#define HW_S390X_3270_CCW_H
-
-#include "hw/sysbus.h"
-#include "hw/s390x/css.h"
-#include "hw/s390x/ccw-device.h"
-#include "qom/object.h"
-
-#define EMULATED_CCW_3270_CU_TYPE 0x3270
-#define EMULATED_CCW_3270_CHPID_TYPE 0x1a
-
-#define TYPE_EMULATED_CCW_3270 "emulated-ccw-3270"
-
-/* Local Channel Commands */
-#define TC_WRITE 0x01 /* Write */
-#define TC_RDBUF 0x02 /* Read buffer */
-#define TC_EWRITE 0x05 /* Erase write */
-#define TC_READMOD 0x06 /* Read modified */
-#define TC_EWRITEA 0x0d /* Erase write alternate */
-#define TC_WRITESF 0x11 /* Write structured field */
-
-OBJECT_DECLARE_TYPE(EmulatedCcw3270Device, EmulatedCcw3270Class, EMULATED_CCW_3270)
-
-struct EmulatedCcw3270Device {
- CcwDevice parent_obj;
-};
-
-struct EmulatedCcw3270Class {
- CCWDeviceClass parent_class;
-
- void (*init)(EmulatedCcw3270Device *, Error **);
- int (*read_payload_3270)(EmulatedCcw3270Device *);
- int (*write_payload_3270)(EmulatedCcw3270Device *, uint8_t);
-};
-
-#endif
+++ /dev/null
-/*
- * s390 adapter definitions
- *
- * Copyright 2013,2014 IBM Corp.
- * Author(s): Cornelia Huck <cornelia.huck@de.ibm.com>
- *
- * This work is licensed under the terms of the GNU GPL, version 2 or (at
- * your option) any later version. See the COPYING file in the top-level
- * directory.
- */
-
-#ifndef S390X_ADAPTER_H
-#define S390X_ADAPTER_H
-
-struct AdapterInfo {
- uint64_t ind_addr;
- uint64_t summary_addr;
- uint64_t ind_offset;
- uint32_t summary_offset;
- uint32_t adapter_id;
-};
-
-#endif
+++ /dev/null
-/*
- * ap bridge
- *
- * Copyright 2018 IBM Corp.
- *
- * This work is licensed under the terms of the GNU GPL, version 2 or (at
- * your option) any later version. See the COPYING file in the top-level
- * directory.
- */
-
-#ifndef HW_S390X_AP_BRIDGE_H
-#define HW_S390X_AP_BRIDGE_H
-
-#define TYPE_AP_BRIDGE "ap-bridge"
-#define TYPE_AP_BUS "ap-bus"
-
-void s390_init_ap(void);
-
-#endif
+++ /dev/null
-/*
- * Adjunct Processor (AP) matrix device interfaces
- *
- * Copyright 2018 IBM Corp.
- *
- * This work is licensed under the terms of the GNU GPL, version 2 or (at
- * your option) any later version. See the COPYING file in the top-level
- * directory.
- */
-
-#ifndef HW_S390X_AP_DEVICE_H
-#define HW_S390X_AP_DEVICE_H
-
-#include "hw/qdev-core.h"
-#include "qom/object.h"
-
-#define TYPE_AP_DEVICE "ap-device"
-
-struct APDevice {
- DeviceState parent_obj;
-};
-typedef struct APDevice APDevice;
-
-DECLARE_INSTANCE_CHECKER(APDevice, AP_DEVICE,
- TYPE_AP_DEVICE)
-
-#endif /* HW_S390X_AP_DEVICE_H */
+++ /dev/null
-/*
- * virtual css bridge definition
- *
- * Copyright 2012,2016 IBM Corp.
- * Author(s): Cornelia Huck <cornelia.huck@de.ibm.com>
- * Pierre Morel <pmorel@linux.vnet.ibm.com>
- *
- * This work is licensed under the terms of the GNU GPL, version 2 or (at
- * your option) any later version. See the COPYING file in the top-level
- * directory.
- */
-
-#ifndef HW_S390X_CSS_BRIDGE_H
-#define HW_S390X_CSS_BRIDGE_H
-
-#include "qom/object.h"
-#include "hw/sysbus.h"
-
-/* virtual css bridge */
-struct VirtualCssBridge {
- SysBusDevice sysbus_dev;
- bool css_dev_path;
-};
-
-#define TYPE_VIRTUAL_CSS_BRIDGE "virtual-css-bridge"
-OBJECT_DECLARE_SIMPLE_TYPE(VirtualCssBridge, VIRTUAL_CSS_BRIDGE)
-
-/* virtual css bus type */
-struct VirtualCssBus {
- BusState parent_obj;
-};
-
-#define TYPE_VIRTUAL_CSS_BUS "virtual-css-bus"
-OBJECT_DECLARE_SIMPLE_TYPE(VirtualCssBus, VIRTUAL_CSS_BUS)
-VirtualCssBus *virtual_css_bus_init(void);
-
-#endif
+++ /dev/null
-/*
- * Channel subsystem structures and definitions.
- *
- * Copyright 2012 IBM Corp.
- * Author(s): Cornelia Huck <cornelia.huck@de.ibm.com>
- *
- * This work is licensed under the terms of the GNU GPL, version 2 or (at
- * your option) any later version. See the COPYING file in the top-level
- * directory.
- */
-
-#ifndef CSS_H
-#define CSS_H
-
-#include "hw/s390x/adapter.h"
-#include "hw/s390x/s390_flic.h"
-#include "hw/s390x/ioinst.h"
-#include "sysemu/kvm.h"
-#include "target/s390x/cpu-qom.h"
-
-/* Channel subsystem constants. */
-#define MAX_DEVNO 65535
-#define MAX_SCHID 65535
-#define MAX_SSID 3
-#define MAX_CSSID 255
-#define MAX_CHPID 255
-
-#define MAX_ISC 7
-
-#define MAX_CIWS 62
-
-#define VIRTUAL_CSSID 0xfe
-#define VIRTIO_CCW_CHPID 0 /* used by convention */
-
-typedef struct CIW {
- uint8_t type;
- uint8_t command;
- uint16_t count;
-} QEMU_PACKED CIW;
-
-typedef struct SenseId {
- /* common part */
- uint8_t reserved; /* always 0x'FF' */
- uint16_t cu_type; /* control unit type */
- uint8_t cu_model; /* control unit model */
- uint16_t dev_type; /* device type */
- uint8_t dev_model; /* device model */
- uint8_t unused; /* padding byte */
- /* extended part */
- CIW ciw[MAX_CIWS]; /* variable # of CIWs */
-} SenseId; /* Note: No QEMU_PACKED due to unaligned members */
-
-/* Channel measurements, from linux/drivers/s390/cio/cmf.c. */
-typedef struct CMB {
- uint16_t ssch_rsch_count;
- uint16_t sample_count;
- uint32_t device_connect_time;
- uint32_t function_pending_time;
- uint32_t device_disconnect_time;
- uint32_t control_unit_queuing_time;
- uint32_t device_active_only_time;
- uint32_t reserved[2];
-} QEMU_PACKED CMB;
-
-typedef struct CMBE {
- uint32_t ssch_rsch_count;
- uint32_t sample_count;
- uint32_t device_connect_time;
- uint32_t function_pending_time;
- uint32_t device_disconnect_time;
- uint32_t control_unit_queuing_time;
- uint32_t device_active_only_time;
- uint32_t device_busy_time;
- uint32_t initial_command_response_time;
- uint32_t reserved[7];
-} QEMU_PACKED CMBE;
-
-typedef enum CcwDataStreamOp {
- CDS_OP_R = 0, /* read, false when used as is_write */
- CDS_OP_W = 1, /* write, true when used as is_write */
- CDS_OP_A = 2 /* advance, should not be used as is_write */
-} CcwDataStreamOp;
-
-/* normal usage is via SuchchDev.cds instead of instantiating */
-typedef struct CcwDataStream {
-#define CDS_F_IDA 0x01
-#define CDS_F_MIDA 0x02
-#define CDS_F_I2K 0x04
-#define CDS_F_C64 0x08
-#define CDS_F_FMT 0x10 /* CCW format-1 */
-#define CDS_F_STREAM_BROKEN 0x80
- uint8_t flags;
- uint8_t at_idaw;
- uint16_t at_byte;
- uint16_t count;
- uint32_t cda_orig;
- int (*op_handler)(struct CcwDataStream *cds, void *buff, int len,
- CcwDataStreamOp op);
- hwaddr cda;
- bool do_skip;
-} CcwDataStream;
-
-/*
- * IO instructions conclude according to this. Currently we have only
- * cc codes. Valid values are 0, 1, 2, 3 and the generic semantic for
- * IO instructions is described briefly. For more details consult the PoP.
- */
-typedef enum IOInstEnding {
- /* produced expected result */
- IOINST_CC_EXPECTED = 0,
- /* status conditions were present or produced alternate result */
- IOINST_CC_STATUS_PRESENT = 1,
- /* inst. ineffective because busy with previously initiated function */
- IOINST_CC_BUSY = 2,
- /* inst. ineffective because not operational */
- IOINST_CC_NOT_OPERATIONAL = 3
-} IOInstEnding;
-
-typedef struct SubchDev SubchDev;
-struct SubchDev {
- /* channel-subsystem related things: */
- SCHIB curr_status; /* Needs alignment and thus must come first */
- ORB orb;
- uint8_t cssid;
- uint8_t ssid;
- uint16_t schid;
- uint16_t devno;
- uint8_t sense_data[32];
- hwaddr channel_prog;
- CCW1 last_cmd;
- bool last_cmd_valid;
- bool ccw_fmt_1;
- bool thinint_active;
- uint8_t ccw_no_data_cnt;
- uint16_t migrated_schid; /* used for missmatch detection */
- CcwDataStream cds;
- /* transport-provided data: */
- int (*ccw_cb) (SubchDev *, CCW1);
- void (*disable_cb)(SubchDev *);
- IOInstEnding (*do_subchannel_work) (SubchDev *);
- SenseId id;
- void *driver_data;
-};
-
-static inline void sch_gen_unit_exception(SubchDev *sch)
-{
- sch->curr_status.scsw.ctrl &= ~SCSW_ACTL_START_PEND;
- sch->curr_status.scsw.ctrl |= SCSW_STCTL_PRIMARY |
- SCSW_STCTL_SECONDARY |
- SCSW_STCTL_ALERT |
- SCSW_STCTL_STATUS_PEND;
- sch->curr_status.scsw.cpa = sch->channel_prog + 8;
- sch->curr_status.scsw.dstat = SCSW_DSTAT_UNIT_EXCEP;
-}
-
-extern const VMStateDescription vmstate_subch_dev;
-
-/*
- * Identify a device within the channel subsystem.
- * Note that this can be used to identify either the subchannel or
- * the attached I/O device, as there's always one I/O device per
- * subchannel.
- */
-typedef struct CssDevId {
- uint8_t cssid;
- uint8_t ssid;
- uint16_t devid;
- bool valid;
-} CssDevId;
-
-extern const PropertyInfo css_devid_propinfo;
-
-#define DEFINE_PROP_CSS_DEV_ID(_n, _s, _f) \
- DEFINE_PROP(_n, _s, _f, css_devid_propinfo, CssDevId)
-
-typedef struct IndAddr {
- hwaddr addr;
- uint64_t map;
- unsigned long refcnt;
- int32_t len;
- QTAILQ_ENTRY(IndAddr) sibling;
-} IndAddr;
-
-extern const VMStateDescription vmstate_ind_addr;
-
-#define VMSTATE_PTR_TO_IND_ADDR(_f, _s) \
- VMSTATE_STRUCT(_f, _s, 1, vmstate_ind_addr, IndAddr*)
-
-IndAddr *get_indicator(hwaddr ind_addr, int len);
-void release_indicator(AdapterInfo *adapter, IndAddr *indicator);
-int map_indicator(AdapterInfo *adapter, IndAddr *indicator);
-
-typedef SubchDev *(*css_subch_cb_func)(uint8_t m, uint8_t cssid, uint8_t ssid,
- uint16_t schid);
-int css_create_css_image(uint8_t cssid, bool default_image);
-bool css_devno_used(uint8_t cssid, uint8_t ssid, uint16_t devno);
-void css_subch_assign(uint8_t cssid, uint8_t ssid, uint16_t schid,
- uint16_t devno, SubchDev *sch);
-void css_sch_build_virtual_schib(SubchDev *sch, uint8_t chpid, uint8_t type);
-int css_sch_build_schib(SubchDev *sch, CssDevId *dev_id);
-unsigned int css_find_free_chpid(uint8_t cssid);
-uint16_t css_build_subchannel_id(SubchDev *sch);
-void copy_scsw_to_guest(SCSW *dest, const SCSW *src);
-void css_inject_io_interrupt(SubchDev *sch);
-void css_reset(void);
-void css_reset_sch(SubchDev *sch);
-void css_crw_add_to_queue(CRW crw);
-void css_queue_crw(uint8_t rsc, uint8_t erc, int solicited,
- int chain, uint16_t rsid);
-void css_generate_sch_crws(uint8_t cssid, uint8_t ssid, uint16_t schid,
- int hotplugged, int add);
-void css_generate_chp_crws(uint8_t cssid, uint8_t chpid);
-void css_generate_css_crws(uint8_t cssid);
-void css_clear_sei_pending(void);
-IOInstEnding s390_ccw_cmd_request(SubchDev *sch);
-IOInstEnding do_subchannel_work_virtual(SubchDev *sub);
-IOInstEnding do_subchannel_work_passthrough(SubchDev *sub);
-
-int s390_ccw_halt(SubchDev *sch);
-int s390_ccw_clear(SubchDev *sch);
-IOInstEnding s390_ccw_store(SubchDev *sch);
-
-typedef enum {
- CSS_IO_ADAPTER_VIRTIO = 0,
- CSS_IO_ADAPTER_PCI = 1,
- CSS_IO_ADAPTER_TYPE_NUMS,
-} CssIoAdapterType;
-
-void css_adapter_interrupt(CssIoAdapterType type, uint8_t isc);
-int css_do_sic(CPUS390XState *env, uint8_t isc, uint16_t mode);
-uint32_t css_get_adapter_id(CssIoAdapterType type, uint8_t isc);
-void css_register_io_adapters(CssIoAdapterType type, bool swap, bool maskable,
- uint8_t flags, Error **errp);
-
-#ifndef CONFIG_USER_ONLY
-SubchDev *css_find_subch(uint8_t m, uint8_t cssid, uint8_t ssid,
- uint16_t schid);
-bool css_subch_visible(SubchDev *sch);
-void css_conditional_io_interrupt(SubchDev *sch);
-IOInstEnding css_do_stsch(SubchDev *sch, SCHIB *schib);
-bool css_schid_final(int m, uint8_t cssid, uint8_t ssid, uint16_t schid);
-IOInstEnding css_do_msch(SubchDev *sch, const SCHIB *schib);
-IOInstEnding css_do_xsch(SubchDev *sch);
-IOInstEnding css_do_csch(SubchDev *sch);
-IOInstEnding css_do_hsch(SubchDev *sch);
-IOInstEnding css_do_ssch(SubchDev *sch, ORB *orb);
-int css_do_tsch_get_irb(SubchDev *sch, IRB *irb, int *irb_len);
-void css_do_tsch_update_subch(SubchDev *sch);
-int css_do_stcrw(CRW *crw);
-void css_undo_stcrw(CRW *crw);
-int css_collect_chp_desc(int m, uint8_t cssid, uint8_t f_chpid, uint8_t l_chpid,
- int rfmt, void *buf);
-void css_do_schm(uint8_t mbk, int update, int dct, uint64_t mbo);
-int css_enable_mcsse(void);
-int css_enable_mss(void);
-IOInstEnding css_do_rsch(SubchDev *sch);
-int css_do_rchp(uint8_t cssid, uint8_t chpid);
-bool css_present(uint8_t cssid);
-#endif
-
-extern const PropertyInfo css_devid_ro_propinfo;
-
-#define DEFINE_PROP_CSS_DEV_ID_RO(_n, _s, _f) \
- DEFINE_PROP(_n, _s, _f, css_devid_ro_propinfo, CssDevId)
-
-/**
- * Create a subchannel for the given bus id.
- *
- * If @p bus_id is valid, verify that it is not already in use, and find a
- * free devno for it.
- * If @p bus_id is not valid find a free subchannel id and device number
- * across all subchannel sets and all css images starting from the default
- * css image.
- *
- * If either of the former actions succeed, allocate a subchannel structure,
- * initialise it with the bus id, subchannel id and device number, register
- * it with the CSS and return it. Otherwise return NULL.
- *
- * The caller becomes owner of the returned subchannel structure and
- * is responsible for unregistering and freeing it.
- */
-SubchDev *css_create_sch(CssDevId bus_id, Error **errp);
-
-/** Turn on css migration */
-void css_register_vmstate(void);
-
-
-void ccw_dstream_init(CcwDataStream *cds, CCW1 const *ccw, ORB const *orb);
-
-static inline void ccw_dstream_rewind(CcwDataStream *cds)
-{
- cds->at_byte = 0;
- cds->at_idaw = 0;
- cds->cda = cds->cda_orig;
-}
-
-static inline bool ccw_dstream_good(CcwDataStream *cds)
-{
- return !(cds->flags & CDS_F_STREAM_BROKEN);
-}
-
-static inline uint16_t ccw_dstream_residual_count(CcwDataStream *cds)
-{
- return cds->count - cds->at_byte;
-}
-
-static inline uint16_t ccw_dstream_avail(CcwDataStream *cds)
-{
- return ccw_dstream_good(cds) ? ccw_dstream_residual_count(cds) : 0;
-}
-
-static inline int ccw_dstream_advance(CcwDataStream *cds, int len)
-{
- return cds->op_handler(cds, NULL, len, CDS_OP_A);
-}
-
-static inline int ccw_dstream_write_buf(CcwDataStream *cds, void *buff, int len)
-{
- return cds->op_handler(cds, buff, len, CDS_OP_W);
-}
-
-static inline int ccw_dstream_read_buf(CcwDataStream *cds, void *buff, int len)
-{
- return cds->op_handler(cds, buff, len, CDS_OP_R);
-}
-
-#define ccw_dstream_read(cds, v) ccw_dstream_read_buf((cds), &(v), sizeof(v))
-#define ccw_dstream_write(cds, v) ccw_dstream_write_buf((cds), &(v), sizeof(v))
-
-#endif
+++ /dev/null
-/*
- * EBCDIC/ASCII conversion Support
- *
- * Copyright (c) 2011 Alexander Graf
- * Copyright IBM, Corp. 2013
- *
- * This work is licensed under the terms of the GNU GPL, version 2 or (at your
- * option) any later version. See the COPYING file in the top-level directory.
- *
- */
-
-#ifndef EBCDIC_H
-#define EBCDIC_H
-
-/* EBCDIC handling */
-static const uint8_t ebcdic2ascii[] = {
- 0x00, 0x01, 0x02, 0x03, 0x07, 0x09, 0x07, 0x7F,
- 0x07, 0x07, 0x07, 0x0B, 0x0C, 0x0D, 0x0E, 0x0F,
- 0x10, 0x11, 0x12, 0x13, 0x07, 0x0A, 0x08, 0x07,
- 0x18, 0x19, 0x07, 0x07, 0x07, 0x07, 0x07, 0x07,
- 0x07, 0x07, 0x1C, 0x07, 0x07, 0x0A, 0x17, 0x1B,
- 0x07, 0x07, 0x07, 0x07, 0x07, 0x05, 0x06, 0x07,
- 0x07, 0x07, 0x16, 0x07, 0x07, 0x07, 0x07, 0x04,
- 0x07, 0x07, 0x07, 0x07, 0x14, 0x15, 0x07, 0x1A,
- 0x20, 0xFF, 0x83, 0x84, 0x85, 0xA0, 0x07, 0x86,
- 0x87, 0xA4, 0x5B, 0x2E, 0x3C, 0x28, 0x2B, 0x21,
- 0x26, 0x82, 0x88, 0x89, 0x8A, 0xA1, 0x8C, 0x07,
- 0x8D, 0xE1, 0x5D, 0x24, 0x2A, 0x29, 0x3B, 0x5E,
- 0x2D, 0x2F, 0x07, 0x8E, 0x07, 0x07, 0x07, 0x8F,
- 0x80, 0xA5, 0x07, 0x2C, 0x25, 0x5F, 0x3E, 0x3F,
- 0x07, 0x90, 0x07, 0x07, 0x07, 0x07, 0x07, 0x07,
- 0x70, 0x60, 0x3A, 0x23, 0x40, 0x27, 0x3D, 0x22,
- 0x07, 0x61, 0x62, 0x63, 0x64, 0x65, 0x66, 0x67,
- 0x68, 0x69, 0xAE, 0xAF, 0x07, 0x07, 0x07, 0xF1,
- 0xF8, 0x6A, 0x6B, 0x6C, 0x6D, 0x6E, 0x6F, 0x70,
- 0x71, 0x72, 0xA6, 0xA7, 0x91, 0x07, 0x92, 0x07,
- 0xE6, 0x7E, 0x73, 0x74, 0x75, 0x76, 0x77, 0x78,
- 0x79, 0x7A, 0xAD, 0xAB, 0x07, 0x07, 0x07, 0x07,
- 0x9B, 0x9C, 0x9D, 0xFA, 0x07, 0x07, 0x07, 0xAC,
- 0xAB, 0x07, 0xAA, 0x7C, 0x07, 0x07, 0x07, 0x07,
- 0x7B, 0x41, 0x42, 0x43, 0x44, 0x45, 0x46, 0x47,
- 0x48, 0x49, 0x07, 0x93, 0x94, 0x95, 0xA2, 0x07,
- 0x7D, 0x4A, 0x4B, 0x4C, 0x4D, 0x4E, 0x4F, 0x50,
- 0x51, 0x52, 0x07, 0x96, 0x81, 0x97, 0xA3, 0x98,
- 0x5C, 0xF6, 0x53, 0x54, 0x55, 0x56, 0x57, 0x58,
- 0x59, 0x5A, 0xFD, 0x07, 0x99, 0x07, 0x07, 0x07,
- 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37,
- 0x38, 0x39, 0x07, 0x07, 0x9A, 0x07, 0x07, 0x07,
-};
-
-static const uint8_t ascii2ebcdic[] = {
- 0x00, 0x01, 0x02, 0x03, 0x37, 0x2D, 0x2E, 0x2F,
- 0x16, 0x05, 0x15, 0x0B, 0x0C, 0x0D, 0x0E, 0x0F,
- 0x10, 0x11, 0x12, 0x13, 0x3C, 0x3D, 0x32, 0x26,
- 0x18, 0x19, 0x3F, 0x27, 0x22, 0x1D, 0x1E, 0x1F,
- 0x40, 0x5A, 0x7F, 0x7B, 0x5B, 0x6C, 0x50, 0x7D,
- 0x4D, 0x5D, 0x5C, 0x4E, 0x6B, 0x60, 0x4B, 0x61,
- 0xF0, 0xF1, 0xF2, 0xF3, 0xF4, 0xF5, 0xF6, 0xF7,
- 0xF8, 0xF9, 0x7A, 0x5E, 0x4C, 0x7E, 0x6E, 0x6F,
- 0x7C, 0xC1, 0xC2, 0xC3, 0xC4, 0xC5, 0xC6, 0xC7,
- 0xC8, 0xC9, 0xD1, 0xD2, 0xD3, 0xD4, 0xD5, 0xD6,
- 0xD7, 0xD8, 0xD9, 0xE2, 0xE3, 0xE4, 0xE5, 0xE6,
- 0xE7, 0xE8, 0xE9, 0xBA, 0xE0, 0xBB, 0xB0, 0x6D,
- 0x79, 0x81, 0x82, 0x83, 0x84, 0x85, 0x86, 0x87,
- 0x88, 0x89, 0x91, 0x92, 0x93, 0x94, 0x95, 0x96,
- 0x97, 0x98, 0x99, 0xA2, 0xA3, 0xA4, 0xA5, 0xA6,
- 0xA7, 0xA8, 0xA9, 0xC0, 0x4F, 0xD0, 0xA1, 0x07,
- 0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F,
- 0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F,
- 0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F,
- 0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F,
- 0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F,
- 0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F,
- 0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F,
- 0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F,
- 0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F,
- 0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F,
- 0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F,
- 0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F,
- 0x3F, 0x59, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F,
- 0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F,
- 0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F,
- 0x90, 0x3F, 0x3F, 0x3F, 0x3F, 0xEA, 0x3F, 0xFF
-};
-
-static inline void ebcdic_put(uint8_t *p, const char *ascii, int len)
-{
- int i;
-
- for (i = 0; i < len; i++) {
- p[i] = ascii2ebcdic[(uint8_t)ascii[i]];
- }
-}
-
-static inline void ascii_put(uint8_t *p, const char *ebcdic, int len)
-{
- int i;
-
- for (i = 0; i < len; i++) {
- p[i] = ebcdic2ascii[(uint8_t)ebcdic[i]];
- }
-}
-
-#endif /* EBCDIC_H */
+++ /dev/null
-/*
- * SCLP
- * Event Facility definitions
- *
- * Copyright IBM, Corp. 2012
- *
- * Authors:
- * Heinz Graalfs <graalfs@de.ibm.com>
- *
- * This work is licensed under the terms of the GNU GPL, version 2 or (at your
- * option) any later version. See the COPYING file in the top-level directory.
- *
- */
-
-#ifndef HW_S390_SCLP_EVENT_FACILITY_H
-#define HW_S390_SCLP_EVENT_FACILITY_H
-
-#include "qemu/thread.h"
-#include "hw/qdev-core.h"
-#include "hw/s390x/sclp.h"
-#include "qom/object.h"
-
-/* SCLP event types */
-#define SCLP_EVENT_OPRTNS_COMMAND 0x01
-#define SCLP_EVENT_MESSAGE 0x02
-#define SCLP_EVENT_CONFIG_MGT_DATA 0x04
-#define SCLP_EVENT_PMSGCMD 0x09
-#define SCLP_EVENT_ASCII_CONSOLE_DATA 0x1a
-#define SCLP_EVENT_SIGNAL_QUIESCE 0x1d
-
-/* SCLP event masks */
-#define SCLP_EVMASK(T) (1ULL << (sizeof(sccb_mask_t) * 8 - (T)))
-
-#define SCLP_EVENT_MASK_OP_CMD SCLP_EVMASK(SCLP_EVENT_OPRTNS_COMMAND)
-#define SCLP_EVENT_MASK_MSG SCLP_EVMASK(SCLP_EVENT_MESSAGE)
-#define SCLP_EVENT_MASK_CONFIG_MGT_DATA SCLP_EVMASK(SCLP_EVENT_CONFIG_MGT_DATA)
-#define SCLP_EVENT_MASK_PMSGCMD SCLP_EVMASK(SCLP_EVENT_PMSGCMD)
-#define SCLP_EVENT_MASK_MSG_ASCII SCLP_EVMASK(SCLP_EVENT_ASCII_CONSOLE_DATA)
-#define SCLP_EVENT_MASK_SIGNAL_QUIESCE SCLP_EVMASK(SCLP_EVENT_SIGNAL_QUIESCE)
-
-#define SCLP_UNCONDITIONAL_READ 0x00
-#define SCLP_SELECTIVE_READ 0x01
-
-#define TYPE_SCLP_EVENT "s390-sclp-event-type"
-OBJECT_DECLARE_TYPE(SCLPEvent, SCLPEventClass,
- SCLP_EVENT)
-
-#define TYPE_SCLP_CPU_HOTPLUG "sclp-cpu-hotplug"
-#define TYPE_SCLP_QUIESCE "sclpquiesce"
-
-#define SCLP_EVENT_MASK_LEN_MAX 1021
-
-typedef struct WriteEventMask {
- SCCBHeader h;
- uint16_t _reserved;
- uint16_t mask_length;
- uint8_t masks[];
-/*
- * Layout of the masks is
- * uint8_t cp_receive_mask[mask_length];
- * uint8_t cp_send_mask[mask_length];
- * uint8_t receive_mask[mask_length];
- * uint8_t send_mask[mask_length];
- * where 1 <= mask_length <= SCLP_EVENT_MASK_LEN_MAX
- */
-} QEMU_PACKED WriteEventMask;
-
-#define WEM_CP_RECEIVE_MASK(wem, mask_len) ((wem)->masks)
-#define WEM_CP_SEND_MASK(wem, mask_len) ((wem)->masks + (mask_len))
-#define WEM_RECEIVE_MASK(wem, mask_len) ((wem)->masks + 2 * (mask_len))
-#define WEM_SEND_MASK(wem, mask_len) ((wem)->masks + 3 * (mask_len))
-
-typedef uint64_t sccb_mask_t;
-
-typedef struct EventBufferHeader {
- uint16_t length;
- uint8_t type;
- uint8_t flags;
- uint16_t _reserved;
-} QEMU_PACKED EventBufferHeader;
-
-typedef struct MdbHeader {
- uint16_t length;
- uint16_t type;
- uint32_t tag;
- uint32_t revision_code;
-} QEMU_PACKED MdbHeader;
-
-typedef struct MTO {
- uint16_t line_type_flags;
- uint8_t alarm_control;
- uint8_t _reserved[3];
- char message[];
-} QEMU_PACKED MTO;
-
-typedef struct GO {
- uint32_t domid;
- uint8_t hhmmss_time[8];
- uint8_t th_time[3];
- uint8_t _reserved_0;
- uint8_t dddyyyy_date[7];
- uint8_t _reserved_1;
- uint16_t general_msg_flags;
- uint8_t _reserved_2[10];
- uint8_t originating_system_name[8];
- uint8_t job_guest_name[8];
-} QEMU_PACKED GO;
-
-#define MESSAGE_TEXT 0x0004
-
-typedef struct MDBO {
- uint16_t length;
- uint16_t type;
- union {
- GO go;
- MTO mto;
- };
-} QEMU_PACKED MDBO;
-
-typedef struct MDB {
- MdbHeader header;
- MDBO mdbo[];
-} QEMU_PACKED MDB;
-
-typedef struct SclpMsg {
- EventBufferHeader header;
- MDB mdb;
-} QEMU_PACKED SclpMsg;
-
-#define GDS_ID_MDSMU 0x1310
-#define GDS_ID_CPMSU 0x1212
-#define GDS_ID_TEXTCMD 0x1320
-
-typedef struct GdsVector {
- uint16_t length;
- uint16_t gds_id;
-} QEMU_PACKED GdsVector;
-
-#define GDS_KEY_SELFDEFTEXTMSG 0x31
-#define GDS_KEY_TEXTMSG 0x30
-
-typedef struct GdsSubvector {
- uint8_t length;
- uint8_t key;
-} QEMU_PACKED GdsSubvector;
-
-/* MDS Message Unit */
-typedef struct MDMSU {
- GdsVector mdmsu;
- GdsVector cpmsu;
- GdsVector text_command;
- GdsSubvector self_def_text_message;
- GdsSubvector text_message;
-} QEMU_PACKED MDMSU;
-
-typedef struct WriteEventData {
- SCCBHeader h;
- EventBufferHeader ebh;
-} QEMU_PACKED WriteEventData;
-
-typedef struct ReadEventData {
- SCCBHeader h;
- union {
- sccb_mask_t mask;
- EventBufferHeader ebh;
- };
-} QEMU_PACKED ReadEventData;
-
-struct SCLPEvent {
- DeviceState qdev;
- bool event_pending;
- char *name;
-};
-
-struct SCLPEventClass {
- DeviceClass parent_class;
- int (*init)(SCLPEvent *event);
-
- /* get SCLP's send mask */
- sccb_mask_t (*get_send_mask)(void);
-
- /* get SCLP's receive mask */
- sccb_mask_t (*get_receive_mask)(void);
-
- int (*read_event_data)(SCLPEvent *event, EventBufferHeader *evt_buf_hdr,
- int *slen);
-
- int (*write_event_data)(SCLPEvent *event, EventBufferHeader *evt_buf_hdr);
-
- /* can we handle this event type? */
- bool (*can_handle_event)(uint8_t type);
-};
-
-#define TYPE_SCLP_EVENT_FACILITY "s390-sclp-event-facility"
-typedef struct SCLPEventFacility SCLPEventFacility;
-typedef struct SCLPEventFacilityClass SCLPEventFacilityClass;
-DECLARE_OBJ_CHECKERS(SCLPEventFacility, SCLPEventFacilityClass,
- EVENT_FACILITY, TYPE_SCLP_EVENT_FACILITY)
-
-struct SCLPEventFacilityClass {
- SysBusDeviceClass parent_class;
- void (*command_handler)(SCLPEventFacility *ef, SCCB *sccb, uint64_t code);
- bool (*event_pending)(SCLPEventFacility *ef);
-};
-
-BusState *sclp_get_event_facility_bus(void);
-
-#endif
+++ /dev/null
-/*
- * S/390 channel I/O instructions
- *
- * Copyright 2012 IBM Corp.
- * Author(s): Cornelia Huck <cornelia.huck@de.ibm.com>
- *
- * This work is licensed under the terms of the GNU GPL, version 2 or (at
- * your option) any later version. See the COPYING file in the top-level
- * directory.
-*/
-
-#ifndef S390X_IOINST_H
-#define S390X_IOINST_H
-
-/*
- * Channel I/O related definitions, as defined in the Principles
- * Of Operation (and taken from the Linux implementation).
- */
-
-/* subchannel status word (command mode only) */
-typedef struct SCSW {
- uint16_t flags;
- uint16_t ctrl;
- uint32_t cpa;
- uint8_t dstat;
- uint8_t cstat;
- uint16_t count;
-} SCSW;
-QEMU_BUILD_BUG_MSG(sizeof(SCSW) != 12, "size of SCSW is wrong");
-
-#define SCSW_FLAGS_MASK_KEY 0xf000
-#define SCSW_FLAGS_MASK_SCTL 0x0800
-#define SCSW_FLAGS_MASK_ESWF 0x0400
-#define SCSW_FLAGS_MASK_CC 0x0300
-#define SCSW_FLAGS_MASK_FMT 0x0080
-#define SCSW_FLAGS_MASK_PFCH 0x0040
-#define SCSW_FLAGS_MASK_ISIC 0x0020
-#define SCSW_FLAGS_MASK_ALCC 0x0010
-#define SCSW_FLAGS_MASK_SSI 0x0008
-#define SCSW_FLAGS_MASK_ZCC 0x0004
-#define SCSW_FLAGS_MASK_ECTL 0x0002
-#define SCSW_FLAGS_MASK_PNO 0x0001
-
-#define SCSW_CTRL_MASK_FCTL 0x7000
-#define SCSW_CTRL_MASK_ACTL 0x0fe0
-#define SCSW_CTRL_MASK_STCTL 0x001f
-
-#define SCSW_FCTL_CLEAR_FUNC 0x1000
-#define SCSW_FCTL_HALT_FUNC 0x2000
-#define SCSW_FCTL_START_FUNC 0x4000
-
-#define SCSW_ACTL_SUSP 0x0020
-#define SCSW_ACTL_DEVICE_ACTIVE 0x0040
-#define SCSW_ACTL_SUBCH_ACTIVE 0x0080
-#define SCSW_ACTL_CLEAR_PEND 0x0100
-#define SCSW_ACTL_HALT_PEND 0x0200
-#define SCSW_ACTL_START_PEND 0x0400
-#define SCSW_ACTL_RESUME_PEND 0x0800
-
-#define SCSW_STCTL_STATUS_PEND 0x0001
-#define SCSW_STCTL_SECONDARY 0x0002
-#define SCSW_STCTL_PRIMARY 0x0004
-#define SCSW_STCTL_INTERMEDIATE 0x0008
-#define SCSW_STCTL_ALERT 0x0010
-
-#define SCSW_DSTAT_ATTENTION 0x80
-#define SCSW_DSTAT_STAT_MOD 0x40
-#define SCSW_DSTAT_CU_END 0x20
-#define SCSW_DSTAT_BUSY 0x10
-#define SCSW_DSTAT_CHANNEL_END 0x08
-#define SCSW_DSTAT_DEVICE_END 0x04
-#define SCSW_DSTAT_UNIT_CHECK 0x02
-#define SCSW_DSTAT_UNIT_EXCEP 0x01
-
-#define SCSW_CSTAT_PCI 0x80
-#define SCSW_CSTAT_INCORR_LEN 0x40
-#define SCSW_CSTAT_PROG_CHECK 0x20
-#define SCSW_CSTAT_PROT_CHECK 0x10
-#define SCSW_CSTAT_DATA_CHECK 0x08
-#define SCSW_CSTAT_CHN_CTRL_CHK 0x04
-#define SCSW_CSTAT_INTF_CTRL_CHK 0x02
-#define SCSW_CSTAT_CHAIN_CHECK 0x01
-
-/* path management control word */
-typedef struct PMCW {
- uint32_t intparm;
- uint16_t flags;
- uint16_t devno;
- uint8_t lpm;
- uint8_t pnom;
- uint8_t lpum;
- uint8_t pim;
- uint16_t mbi;
- uint8_t pom;
- uint8_t pam;
- uint8_t chpid[8];
- uint32_t chars;
-} PMCW;
-QEMU_BUILD_BUG_MSG(sizeof(PMCW) != 28, "size of PMCW is wrong");
-
-#define PMCW_FLAGS_MASK_QF 0x8000
-#define PMCW_FLAGS_MASK_W 0x4000
-#define PMCW_FLAGS_MASK_ISC 0x3800
-#define PMCW_FLAGS_MASK_ENA 0x0080
-#define PMCW_FLAGS_MASK_LM 0x0060
-#define PMCW_FLAGS_MASK_MME 0x0018
-#define PMCW_FLAGS_MASK_MP 0x0004
-#define PMCW_FLAGS_MASK_TF 0x0002
-#define PMCW_FLAGS_MASK_DNV 0x0001
-#define PMCW_FLAGS_MASK_INVALID 0x0700
-
-#define PMCW_CHARS_MASK_ST 0x00e00000
-#define PMCW_CHARS_MASK_MBFC 0x00000004
-#define PMCW_CHARS_MASK_XMWME 0x00000002
-#define PMCW_CHARS_MASK_CSENSE 0x00000001
-#define PMCW_CHARS_MASK_INVALID 0xff1ffff8
-
-/* subchannel information block */
-typedef struct SCHIB {
- PMCW pmcw;
- SCSW scsw;
- uint64_t mba;
- uint8_t mda[4];
-} QEMU_PACKED SCHIB;
-
-/* interruption response block */
-typedef struct IRB {
- SCSW scsw;
- uint32_t esw[5];
- uint32_t ecw[8];
- uint32_t emw[8];
-} IRB;
-QEMU_BUILD_BUG_MSG(sizeof(IRB) != 96, "size of IRB is wrong");
-
-/* operation request block */
-typedef struct ORB {
- uint32_t intparm;
- uint16_t ctrl0;
- uint8_t lpm;
- uint8_t ctrl1;
- uint32_t cpa;
-} ORB;
-QEMU_BUILD_BUG_MSG(sizeof(ORB) != 12, "size of ORB is wrong");
-
-#define ORB_CTRL0_MASK_KEY 0xf000
-#define ORB_CTRL0_MASK_SPND 0x0800
-#define ORB_CTRL0_MASK_STR 0x0400
-#define ORB_CTRL0_MASK_MOD 0x0200
-#define ORB_CTRL0_MASK_SYNC 0x0100
-#define ORB_CTRL0_MASK_FMT 0x0080
-#define ORB_CTRL0_MASK_PFCH 0x0040
-#define ORB_CTRL0_MASK_ISIC 0x0020
-#define ORB_CTRL0_MASK_ALCC 0x0010
-#define ORB_CTRL0_MASK_SSIC 0x0008
-#define ORB_CTRL0_MASK_C64 0x0002
-#define ORB_CTRL0_MASK_I2K 0x0001
-#define ORB_CTRL0_MASK_INVALID 0x0004
-
-#define ORB_CTRL1_MASK_ILS 0x80
-#define ORB_CTRL1_MASK_MIDAW 0x40
-#define ORB_CTRL1_MASK_ORBX 0x01
-#define ORB_CTRL1_MASK_INVALID 0x3e
-
-/* channel command word (type 0) */
-typedef struct CCW0 {
- uint8_t cmd_code;
- uint8_t cda0;
- uint16_t cda1;
- uint8_t flags;
- uint8_t reserved;
- uint16_t count;
-} CCW0;
-QEMU_BUILD_BUG_MSG(sizeof(CCW0) != 8, "size of CCW0 is wrong");
-
-/* channel command word (type 1) */
-typedef struct CCW1 {
- uint8_t cmd_code;
- uint8_t flags;
- uint16_t count;
- uint32_t cda;
-} CCW1;
-QEMU_BUILD_BUG_MSG(sizeof(CCW1) != 8, "size of CCW1 is wrong");
-
-#define CCW_FLAG_DC 0x80
-#define CCW_FLAG_CC 0x40
-#define CCW_FLAG_SLI 0x20
-#define CCW_FLAG_SKIP 0x10
-#define CCW_FLAG_PCI 0x08
-#define CCW_FLAG_IDA 0x04
-#define CCW_FLAG_SUSPEND 0x02
-#define CCW_FLAG_MIDA 0x01
-
-#define CCW_CMD_NOOP 0x03
-#define CCW_CMD_BASIC_SENSE 0x04
-#define CCW_CMD_TIC 0x08
-#define CCW_CMD_SENSE_ID 0xe4
-
-typedef struct CRW {
- uint16_t flags;
- uint16_t rsid;
-} CRW;
-QEMU_BUILD_BUG_MSG(sizeof(CRW) != 4, "size of CRW is wrong");
-
-#define CRW_FLAGS_MASK_S 0x4000
-#define CRW_FLAGS_MASK_R 0x2000
-#define CRW_FLAGS_MASK_C 0x1000
-#define CRW_FLAGS_MASK_RSC 0x0f00
-#define CRW_FLAGS_MASK_A 0x0080
-#define CRW_FLAGS_MASK_ERC 0x003f
-
-#define CRW_ERC_EVENT 0x00 /* event information pending */
-#define CRW_ERC_AVAIL 0x01 /* available */
-#define CRW_ERC_INIT 0x02 /* initialized */
-#define CRW_ERC_TERROR 0x03 /* temporary error */
-#define CRW_ERC_IPI 0x04 /* installed parm initialized */
-#define CRW_ERC_TERM 0x05 /* terminal */
-#define CRW_ERC_PERRN 0x06 /* perm. error, facility not init */
-#define CRW_ERC_PERRI 0x07 /* perm. error, facility init */
-#define CRW_ERC_PMOD 0x08 /* installed parameters modified */
-#define CRW_ERC_IPR 0x0A /* installed parameters restored */
-
-#define CRW_RSC_SUBCH 0x3
-#define CRW_RSC_CHP 0x4
-#define CRW_RSC_CSS 0xb
-
-/* I/O interruption code */
-typedef struct IOIntCode {
- uint32_t subsys_id;
- uint32_t intparm;
- uint32_t interrupt_id;
-} QEMU_PACKED IOIntCode;
-
-/* schid disintegration */
-#define IOINST_SCHID_ONE(_schid) ((_schid & 0x00010000) >> 16)
-#define IOINST_SCHID_M(_schid) ((_schid & 0x00080000) >> 19)
-#define IOINST_SCHID_CSSID(_schid) ((_schid & 0xff000000) >> 24)
-#define IOINST_SCHID_SSID(_schid) ((_schid & 0x00060000) >> 17)
-#define IOINST_SCHID_NR(_schid) (_schid & 0x0000ffff)
-
-#define IO_INT_WORD_ISC(_int_word) ((_int_word & 0x38000000) >> 27)
-#define ISC_TO_ISC_BITS(_isc) ((0x80 >> _isc) << 24)
-
-#define IO_INT_WORD_AI 0x80000000
-
-int ioinst_disassemble_sch_ident(uint32_t value, int *m, int *cssid, int *ssid,
- int *schid);
-
-#endif
+++ /dev/null
-/*
- * Protected Virtualization header
- *
- * Copyright IBM Corp. 2020
- * Author(s):
- * Janosch Frank <frankja@linux.ibm.com>
- *
- * This work is licensed under the terms of the GNU GPL, version 2 or (at
- * your option) any later version. See the COPYING file in the top-level
- * directory.
- */
-#ifndef HW_S390_PV_H
-#define HW_S390_PV_H
-
-#ifdef CONFIG_KVM
-#include "cpu.h"
-#include "hw/s390x/s390-virtio-ccw.h"
-
-static inline bool s390_is_pv(void)
-{
- static S390CcwMachineState *ccw;
- Object *obj;
-
- if (ccw) {
- return ccw->pv;
- }
-
- /* we have to bail out for the "none" machine */
- obj = object_dynamic_cast(qdev_get_machine(),
- TYPE_S390_CCW_MACHINE);
- if (!obj) {
- return false;
- }
- ccw = S390_CCW_MACHINE(obj);
- return ccw->pv;
-}
-
-int s390_pv_vm_enable(void);
-void s390_pv_vm_disable(void);
-int s390_pv_set_sec_parms(uint64_t origin, uint64_t length);
-int s390_pv_unpack(uint64_t addr, uint64_t size, uint64_t tweak);
-void s390_pv_prep_reset(void);
-int s390_pv_verify(void);
-void s390_pv_unshare(void);
-void s390_pv_inject_reset_error(CPUState *cs);
-#else /* CONFIG_KVM */
-static inline bool s390_is_pv(void) { return false; }
-static inline int s390_pv_vm_enable(void) { return 0; }
-static inline void s390_pv_vm_disable(void) {}
-static inline int s390_pv_set_sec_parms(uint64_t origin, uint64_t length) { return 0; }
-static inline int s390_pv_unpack(uint64_t addr, uint64_t size, uint64_t tweak) { return 0; }
-static inline void s390_pv_prep_reset(void) {}
-static inline int s390_pv_verify(void) { return 0; }
-static inline void s390_pv_unshare(void) {}
-static inline void s390_pv_inject_reset_error(CPUState *cs) {};
-#endif /* CONFIG_KVM */
-
-#endif /* HW_S390_PV_H */
+++ /dev/null
-/*
- * s390 CCW Assignment Support
- *
- * Copyright 2017 IBM Corp.
- * Author(s): Dong Jia Shi <bjsdjshi@linux.vnet.ibm.com>
- * Xiao Feng Ren <renxiaof@linux.vnet.ibm.com>
- *
- * This work is licensed under the terms of the GNU GPL, version 2 or (at
- * your option) any later version. See the COPYING file in the top-level
- * directory.
- */
-
-#ifndef HW_S390_CCW_H
-#define HW_S390_CCW_H
-
-#include "hw/s390x/ccw-device.h"
-#include "qom/object.h"
-
-#define TYPE_S390_CCW "s390-ccw"
-typedef struct S390CCWDevice S390CCWDevice;
-typedef struct S390CCWDeviceClass S390CCWDeviceClass;
-DECLARE_OBJ_CHECKERS(S390CCWDevice, S390CCWDeviceClass,
- S390_CCW_DEVICE, TYPE_S390_CCW)
-
-struct S390CCWDevice {
- CcwDevice parent_obj;
- CssDevId hostid;
- char *mdevid;
- int32_t bootindex;
-};
-
-struct S390CCWDeviceClass {
- CCWDeviceClass parent_class;
- void (*realize)(S390CCWDevice *dev, char *sysfsdev, Error **errp);
- void (*unrealize)(S390CCWDevice *dev);
- IOInstEnding (*handle_request) (SubchDev *sch);
- int (*handle_halt) (SubchDev *sch);
- int (*handle_clear) (SubchDev *sch);
- IOInstEnding (*handle_store) (SubchDev *sch);
-};
-
-#endif
+++ /dev/null
-/*
- * s390 PCI BUS definitions
- *
- * Copyright 2014 IBM Corp.
- * Author(s): Frank Blaschka <frank.blaschka@de.ibm.com>
- * Hong Bo Li <lihbbj@cn.ibm.com>
- * Yi Min Zhao <zyimin@cn.ibm.com>
- *
- * This work is licensed under the terms of the GNU GPL, version 2 or (at
- * your option) any later version. See the COPYING file in the top-level
- * directory.
- */
-
-#ifndef HW_S390_PCI_BUS_H
-#define HW_S390_PCI_BUS_H
-
-#include "hw/pci/pci.h"
-#include "hw/pci/pci_host.h"
-#include "hw/s390x/sclp.h"
-#include "hw/s390x/s390_flic.h"
-#include "hw/s390x/css.h"
-#include "hw/s390x/s390-pci-clp.h"
-#include "qom/object.h"
-
-#define TYPE_S390_PCI_HOST_BRIDGE "s390-pcihost"
-#define TYPE_S390_PCI_BUS "s390-pcibus"
-#define TYPE_S390_PCI_DEVICE "zpci"
-#define TYPE_S390_PCI_IOMMU "s390-pci-iommu"
-#define TYPE_S390_IOMMU_MEMORY_REGION "s390-iommu-memory-region"
-#define FH_MASK_ENABLE 0x80000000
-#define FH_MASK_INSTANCE 0x7f000000
-#define FH_MASK_SHM 0x00ff0000
-#define FH_MASK_INDEX 0x0000ffff
-#define FH_SHM_VFIO 0x00010000
-#define FH_SHM_EMUL 0x00020000
-#define ZPCI_MAX_FID 0xffffffff
-#define ZPCI_MAX_UID 0xffff
-#define UID_UNDEFINED 0
-#define UID_CHECKING_ENABLED 0x01
-
-OBJECT_DECLARE_SIMPLE_TYPE(S390pciState, S390_PCI_HOST_BRIDGE)
-OBJECT_DECLARE_SIMPLE_TYPE(S390PCIBus, S390_PCI_BUS)
-OBJECT_DECLARE_SIMPLE_TYPE(S390PCIBusDevice, S390_PCI_DEVICE)
-OBJECT_DECLARE_SIMPLE_TYPE(S390PCIIOMMU, S390_PCI_IOMMU)
-
-#define HP_EVENT_TO_CONFIGURED 0x0301
-#define HP_EVENT_RESERVED_TO_STANDBY 0x0302
-#define HP_EVENT_DECONFIGURE_REQUEST 0x0303
-#define HP_EVENT_CONFIGURED_TO_STBRES 0x0304
-#define HP_EVENT_STANDBY_TO_RESERVED 0x0308
-
-#define ERR_EVENT_INVALAS 0x1
-#define ERR_EVENT_OORANGE 0x2
-#define ERR_EVENT_INVALTF 0x3
-#define ERR_EVENT_TPROTE 0x4
-#define ERR_EVENT_APROTE 0x5
-#define ERR_EVENT_KEYE 0x6
-#define ERR_EVENT_INVALTE 0x7
-#define ERR_EVENT_INVALTL 0x8
-#define ERR_EVENT_TT 0x9
-#define ERR_EVENT_INVALMS 0xa
-#define ERR_EVENT_SERR 0xb
-#define ERR_EVENT_NOMSI 0x10
-#define ERR_EVENT_INVALBV 0x11
-#define ERR_EVENT_AIBV 0x12
-#define ERR_EVENT_AIRERR 0x13
-#define ERR_EVENT_FMBA 0x2a
-#define ERR_EVENT_FMBUP 0x2b
-#define ERR_EVENT_FMBPRO 0x2c
-#define ERR_EVENT_CCONF 0x30
-#define ERR_EVENT_SERVAC 0x3a
-#define ERR_EVENT_PERMERR 0x3b
-
-#define ERR_EVENT_Q_BIT 0x2
-#define ERR_EVENT_MVN_OFFSET 16
-
-#define ZPCI_MSI_VEC_BITS 11
-#define ZPCI_MSI_VEC_MASK 0x7ff
-
-#define ZPCI_MSI_ADDR 0xfe00000000000000ULL
-#define ZPCI_SDMA_ADDR 0x100000000ULL
-#define ZPCI_EDMA_ADDR 0x1ffffffffffffffULL
-
-#define PAGE_SHIFT 12
-#define PAGE_SIZE (1 << PAGE_SHIFT)
-#define PAGE_MASK (~(PAGE_SIZE-1))
-#define PAGE_DEFAULT_ACC 0
-#define PAGE_DEFAULT_KEY (PAGE_DEFAULT_ACC << 4)
-
-/* I/O Translation Anchor (IOTA) */
-enum ZpciIoatDtype {
- ZPCI_IOTA_STO = 0,
- ZPCI_IOTA_RTTO = 1,
- ZPCI_IOTA_RSTO = 2,
- ZPCI_IOTA_RFTO = 3,
- ZPCI_IOTA_PFAA = 4,
- ZPCI_IOTA_IOPFAA = 5,
- ZPCI_IOTA_IOPTO = 7
-};
-
-#define ZPCI_IOTA_IOT_ENABLED 0x800ULL
-#define ZPCI_IOTA_DT_ST (ZPCI_IOTA_STO << 2)
-#define ZPCI_IOTA_DT_RT (ZPCI_IOTA_RTTO << 2)
-#define ZPCI_IOTA_DT_RS (ZPCI_IOTA_RSTO << 2)
-#define ZPCI_IOTA_DT_RF (ZPCI_IOTA_RFTO << 2)
-#define ZPCI_IOTA_DT_PF (ZPCI_IOTA_PFAA << 2)
-#define ZPCI_IOTA_FS_4K 0
-#define ZPCI_IOTA_FS_1M 1
-#define ZPCI_IOTA_FS_2G 2
-#define ZPCI_KEY (PAGE_DEFAULT_KEY << 5)
-
-#define ZPCI_IOTA_STO_FLAG (ZPCI_IOTA_IOT_ENABLED | ZPCI_KEY | ZPCI_IOTA_DT_ST)
-#define ZPCI_IOTA_RTTO_FLAG (ZPCI_IOTA_IOT_ENABLED | ZPCI_KEY | ZPCI_IOTA_DT_RT)
-#define ZPCI_IOTA_RSTO_FLAG (ZPCI_IOTA_IOT_ENABLED | ZPCI_KEY | ZPCI_IOTA_DT_RS)
-#define ZPCI_IOTA_RFTO_FLAG (ZPCI_IOTA_IOT_ENABLED | ZPCI_KEY | ZPCI_IOTA_DT_RF)
-#define ZPCI_IOTA_RFAA_FLAG (ZPCI_IOTA_IOT_ENABLED | ZPCI_KEY |\
- ZPCI_IOTA_DT_PF | ZPCI_IOTA_FS_2G)
-
-/* I/O Region and segment tables */
-#define ZPCI_INDEX_MASK 0x7ffULL
-
-#define ZPCI_TABLE_TYPE_MASK 0xc
-#define ZPCI_TABLE_TYPE_RFX 0xc
-#define ZPCI_TABLE_TYPE_RSX 0x8
-#define ZPCI_TABLE_TYPE_RTX 0x4
-#define ZPCI_TABLE_TYPE_SX 0x0
-
-#define ZPCI_TABLE_LEN_RFX 0x3
-#define ZPCI_TABLE_LEN_RSX 0x3
-#define ZPCI_TABLE_LEN_RTX 0x3
-
-#define ZPCI_TABLE_OFFSET_MASK 0xc0
-#define ZPCI_TABLE_SIZE 0x4000
-#define ZPCI_TABLE_ALIGN ZPCI_TABLE_SIZE
-#define ZPCI_TABLE_ENTRY_SIZE (sizeof(unsigned long))
-#define ZPCI_TABLE_ENTRIES (ZPCI_TABLE_SIZE / ZPCI_TABLE_ENTRY_SIZE)
-
-#define ZPCI_TABLE_BITS 11
-#define ZPCI_PT_BITS 8
-#define ZPCI_ST_SHIFT (ZPCI_PT_BITS + PAGE_SHIFT)
-#define ZPCI_RT_SHIFT (ZPCI_ST_SHIFT + ZPCI_TABLE_BITS)
-
-#define ZPCI_RTE_FLAG_MASK 0x3fffULL
-#define ZPCI_RTE_ADDR_MASK (~ZPCI_RTE_FLAG_MASK)
-#define ZPCI_STE_FLAG_MASK 0x7ffULL
-#define ZPCI_STE_ADDR_MASK (~ZPCI_STE_FLAG_MASK)
-
-#define ZPCI_SFAA_MASK (~((1ULL << 20) - 1))
-
-/* I/O Page tables */
-#define ZPCI_PTE_VALID_MASK 0x400
-#define ZPCI_PTE_INVALID 0x400
-#define ZPCI_PTE_VALID 0x000
-#define ZPCI_PT_SIZE 0x800
-#define ZPCI_PT_ALIGN ZPCI_PT_SIZE
-#define ZPCI_PT_ENTRIES (ZPCI_PT_SIZE / ZPCI_TABLE_ENTRY_SIZE)
-#define ZPCI_PT_MASK (ZPCI_PT_ENTRIES - 1)
-
-#define ZPCI_PTE_FLAG_MASK 0xfffULL
-#define ZPCI_PTE_ADDR_MASK (~ZPCI_PTE_FLAG_MASK)
-
-/* Shared bits */
-#define ZPCI_TABLE_VALID 0x00
-#define ZPCI_TABLE_INVALID 0x20
-#define ZPCI_TABLE_PROTECTED 0x200
-#define ZPCI_TABLE_UNPROTECTED 0x000
-#define ZPCI_TABLE_FC 0x400
-
-#define ZPCI_TABLE_VALID_MASK 0x20
-#define ZPCI_TABLE_PROT_MASK 0x200
-
-#define ZPCI_ETT_RT 1
-#define ZPCI_ETT_ST 0
-#define ZPCI_ETT_PT -1
-
-/* PCI Function States
- *
- * reserved: default; device has just been plugged or is in progress of being
- * unplugged
- * standby: device is present but not configured; transition from any
- * configured state/to this state via sclp configure/deconfigure
- *
- * The following states make up the "configured" meta-state:
- * disabled: device is configured but not enabled; transition between this
- * state and enabled via clp enable/disable
- * enbaled: device is ready for use; transition to disabled via clp disable;
- * may enter an error state
- * blocked: ignore all DMA and interrupts; transition back to enabled or from
- * error state via mpcifc
- * error: an error occurred; transition back to enabled via mpcifc
- * permanent error: an unrecoverable error occurred; transition to standby via
- * sclp deconfigure
- */
-typedef enum {
- ZPCI_FS_RESERVED,
- ZPCI_FS_STANDBY,
- ZPCI_FS_DISABLED,
- ZPCI_FS_ENABLED,
- ZPCI_FS_BLOCKED,
- ZPCI_FS_ERROR,
- ZPCI_FS_PERMANENT_ERROR,
-} ZpciState;
-
-typedef struct SeiContainer {
- QTAILQ_ENTRY(SeiContainer) link;
- uint32_t fid;
- uint32_t fh;
- uint8_t cc;
- uint16_t pec;
- uint64_t faddr;
- uint32_t e;
-} SeiContainer;
-
-typedef struct PciCcdfErr {
- uint32_t reserved1;
- uint32_t fh;
- uint32_t fid;
- uint32_t e;
- uint64_t faddr;
- uint32_t reserved3;
- uint16_t reserved4;
- uint16_t pec;
-} QEMU_PACKED PciCcdfErr;
-
-typedef struct PciCcdfAvail {
- uint32_t reserved1;
- uint32_t fh;
- uint32_t fid;
- uint32_t reserved2;
- uint32_t reserved3;
- uint32_t reserved4;
- uint32_t reserved5;
- uint16_t reserved6;
- uint16_t pec;
-} QEMU_PACKED PciCcdfAvail;
-
-typedef struct ChscSeiNt2Res {
- uint16_t length;
- uint16_t code;
- uint16_t reserved1;
- uint8_t reserved2;
- uint8_t nt;
- uint8_t flags;
- uint8_t reserved3;
- uint8_t reserved4;
- uint8_t cc;
- uint32_t reserved5[13];
- uint8_t ccdf[4016];
-} QEMU_PACKED ChscSeiNt2Res;
-
-typedef struct S390MsixInfo {
- uint8_t table_bar;
- uint8_t pba_bar;
- uint16_t entries;
- uint32_t table_offset;
- uint32_t pba_offset;
-} S390MsixInfo;
-
-typedef struct S390IOTLBEntry {
- uint64_t iova;
- uint64_t translated_addr;
- uint64_t len;
- uint64_t perm;
-} S390IOTLBEntry;
-
-typedef struct S390PCIDMACount {
- int id;
- int users;
- uint32_t avail;
- QTAILQ_ENTRY(S390PCIDMACount) link;
-} S390PCIDMACount;
-
-struct S390PCIIOMMU {
- Object parent_obj;
- S390PCIBusDevice *pbdev;
- AddressSpace as;
- MemoryRegion mr;
- IOMMUMemoryRegion iommu_mr;
- bool enabled;
- uint64_t g_iota;
- uint64_t pba;
- uint64_t pal;
- GHashTable *iotlb;
- S390PCIDMACount *dma_limit;
-};
-
-typedef struct S390PCIIOMMUTable {
- uint64_t key;
- S390PCIIOMMU *iommu[PCI_SLOT_MAX];
-} S390PCIIOMMUTable;
-
-/* Function Measurement Block */
-#define DEFAULT_MUI 4000
-#define UPDATE_U_BIT 0x1ULL
-#define FMBK_MASK 0xfULL
-
-typedef struct ZpciFmbFmt0 {
- uint64_t dma_rbytes;
- uint64_t dma_wbytes;
-} ZpciFmbFmt0;
-
-#define ZPCI_FMB_CNT_LD 0
-#define ZPCI_FMB_CNT_ST 1
-#define ZPCI_FMB_CNT_STB 2
-#define ZPCI_FMB_CNT_RPCIT 3
-#define ZPCI_FMB_CNT_MAX 4
-
-#define ZPCI_FMB_FORMAT 0
-
-typedef struct ZpciFmb {
- uint32_t format;
- uint32_t sample;
- uint64_t last_update;
- uint64_t counter[ZPCI_FMB_CNT_MAX];
- ZpciFmbFmt0 fmt0;
-} ZpciFmb;
-QEMU_BUILD_BUG_MSG(offsetof(ZpciFmb, fmt0) != 48, "padding in ZpciFmb");
-
-#define ZPCI_DEFAULT_FN_GRP 0x20
-typedef struct S390PCIGroup {
- ClpRspQueryPciGrp zpci_group;
- int id;
- QTAILQ_ENTRY(S390PCIGroup) link;
-} S390PCIGroup;
-S390PCIGroup *s390_group_create(int id);
-S390PCIGroup *s390_group_find(int id);
-
-struct S390PCIBusDevice {
- DeviceState qdev;
- PCIDevice *pdev;
- ZpciState state;
- char *target;
- uint16_t uid;
- uint32_t idx;
- uint32_t fh;
- uint32_t fid;
- bool fid_defined;
- uint64_t fmb_addr;
- ZpciFmb fmb;
- QEMUTimer *fmb_timer;
- uint8_t isc;
- uint16_t noi;
- uint16_t maxstbl;
- uint8_t sum;
- S390PCIGroup *pci_group;
- ClpRspQueryPci zpci_fn;
- S390MsixInfo msix;
- AdapterRoutes routes;
- S390PCIIOMMU *iommu;
- MemoryRegion msix_notify_mr;
- IndAddr *summary_ind;
- IndAddr *indicator;
- bool pci_unplug_request_processed;
- bool unplug_requested;
- QTAILQ_ENTRY(S390PCIBusDevice) link;
-};
-
-struct S390PCIBus {
- BusState qbus;
-};
-
-struct S390pciState {
- PCIHostState parent_obj;
- uint32_t next_idx;
- int bus_no;
- S390PCIBus *bus;
- GHashTable *iommu_table;
- GHashTable *zpci_table;
- QTAILQ_HEAD(, SeiContainer) pending_sei;
- QTAILQ_HEAD(, S390PCIBusDevice) zpci_devs;
- QTAILQ_HEAD(, S390PCIDMACount) zpci_dma_limit;
- QTAILQ_HEAD(, S390PCIGroup) zpci_groups;
-};
-
-S390pciState *s390_get_phb(void);
-int pci_chsc_sei_nt2_get_event(void *res);
-int pci_chsc_sei_nt2_have_event(void);
-void s390_pci_sclp_configure(SCCB *sccb);
-void s390_pci_sclp_deconfigure(SCCB *sccb);
-void s390_pci_iommu_enable(S390PCIIOMMU *iommu);
-void s390_pci_iommu_disable(S390PCIIOMMU *iommu);
-void s390_pci_generate_error_event(uint16_t pec, uint32_t fh, uint32_t fid,
- uint64_t faddr, uint32_t e);
-uint16_t s390_guest_io_table_walk(uint64_t g_iota, hwaddr addr,
- S390IOTLBEntry *entry);
-S390PCIBusDevice *s390_pci_find_dev_by_idx(S390pciState *s, uint32_t idx);
-S390PCIBusDevice *s390_pci_find_dev_by_fh(S390pciState *s, uint32_t fh);
-S390PCIBusDevice *s390_pci_find_dev_by_fid(S390pciState *s, uint32_t fid);
-S390PCIBusDevice *s390_pci_find_dev_by_target(S390pciState *s,
- const char *target);
-S390PCIBusDevice *s390_pci_find_next_avail_dev(S390pciState *s,
- S390PCIBusDevice *pbdev);
-
-#endif
+++ /dev/null
-/*
- * s390 CLP instruction definitions
- *
- * Copyright 2019 IBM Corp.
- * Author(s): Pierre Morel <pmorel@de.ibm.com>
- *
- * This work is licensed under the terms of the GNU GPL, version 2 or (at
- * your option) any later version. See the COPYING file in the top-level
- * directory.
- */
-
-#ifndef HW_S390_PCI_CLP
-#define HW_S390_PCI_CLP
-
-/* CLP common request & response block size */
-#define CLP_BLK_SIZE 4096
-#define PCI_BAR_COUNT 6
-#define PCI_MAX_FUNCTIONS 4096
-
-typedef struct ClpReqHdr {
- uint16_t len;
- uint16_t cmd;
-} QEMU_PACKED ClpReqHdr;
-
-typedef struct ClpRspHdr {
- uint16_t len;
- uint16_t rsp;
-} QEMU_PACKED ClpRspHdr;
-
-/* CLP Response Codes */
-#define CLP_RC_OK 0x0010 /* Command request successfully */
-#define CLP_RC_CMD 0x0020 /* Command code not recognized */
-#define CLP_RC_PERM 0x0030 /* Command not authorized */
-#define CLP_RC_FMT 0x0040 /* Invalid command request format */
-#define CLP_RC_LEN 0x0050 /* Invalid command request length */
-#define CLP_RC_8K 0x0060 /* Command requires 8K LPCB */
-#define CLP_RC_RESNOT0 0x0070 /* Reserved field not zero */
-#define CLP_RC_NODATA 0x0080 /* No data available */
-#define CLP_RC_FC_UNKNOWN 0x0100 /* Function code not recognized */
-
-/*
- * Call Logical Processor - Command Codes
- */
-#define CLP_LIST_PCI 0x0002
-#define CLP_QUERY_PCI_FN 0x0003
-#define CLP_QUERY_PCI_FNGRP 0x0004
-#define CLP_SET_PCI_FN 0x0005
-
-/* PCI function handle list entry */
-typedef struct ClpFhListEntry {
- uint16_t device_id;
- uint16_t vendor_id;
-#define CLP_FHLIST_MASK_CONFIG 0x80000000
- uint32_t config;
- uint32_t fid;
- uint32_t fh;
-} QEMU_PACKED ClpFhListEntry;
-
-#define CLP_RC_SETPCIFN_FH 0x0101 /* Invalid PCI fn handle */
-#define CLP_RC_SETPCIFN_FHOP 0x0102 /* Fn handle not valid for op */
-#define CLP_RC_SETPCIFN_DMAAS 0x0103 /* Invalid DMA addr space */
-#define CLP_RC_SETPCIFN_RES 0x0104 /* Insufficient resources */
-#define CLP_RC_SETPCIFN_ALRDY 0x0105 /* Fn already in requested state */
-#define CLP_RC_SETPCIFN_ERR 0x0106 /* Fn in permanent error state */
-#define CLP_RC_SETPCIFN_RECPND 0x0107 /* Error recovery pending */
-#define CLP_RC_SETPCIFN_BUSY 0x0108 /* Fn busy */
-#define CLP_RC_LISTPCI_BADRT 0x010a /* Resume token not recognized */
-#define CLP_RC_QUERYPCIFG_PFGID 0x010b /* Unrecognized PFGID */
-
-/* request or response block header length */
-#define LIST_PCI_HDR_LEN 32
-
-/* Number of function handles fitting in response block */
-#define CLP_FH_LIST_NR_ENTRIES \
- ((CLP_BLK_SIZE - 2 * LIST_PCI_HDR_LEN) \
- / sizeof(ClpFhListEntry))
-
-#define CLP_SET_ENABLE_PCI_FN 0 /* Yes, 0 enables it */
-#define CLP_SET_DISABLE_PCI_FN 1 /* Yes, 1 disables it */
-
-#define CLP_UTIL_STR_LEN 64
-#define CLP_PFIP_NR_SEGMENTS 4
-
-#define CLP_MASK_FMT 0xf0000000
-
-/* List PCI functions request */
-typedef struct ClpReqListPci {
- ClpReqHdr hdr;
- uint32_t fmt;
- uint64_t reserved1;
- uint64_t resume_token;
- uint64_t reserved2;
-} QEMU_PACKED ClpReqListPci;
-
-/* List PCI functions response */
-typedef struct ClpRspListPci {
- ClpRspHdr hdr;
- uint32_t fmt;
- uint64_t reserved1;
- uint64_t resume_token;
- uint32_t mdd;
- uint16_t max_fn;
- uint8_t flags;
- uint8_t entry_size;
- ClpFhListEntry fh_list[CLP_FH_LIST_NR_ENTRIES];
-} QEMU_PACKED ClpRspListPci;
-
-/* Query PCI function request */
-typedef struct ClpReqQueryPci {
- ClpReqHdr hdr;
- uint32_t fmt;
- uint64_t reserved1;
- uint32_t fh; /* function handle */
- uint32_t reserved2;
- uint64_t reserved3;
-} QEMU_PACKED ClpReqQueryPci;
-
-/* Query PCI function response */
-typedef struct ClpRspQueryPci {
- ClpRspHdr hdr;
- uint32_t fmt;
- uint64_t reserved1;
- uint16_t vfn; /* virtual fn number */
-#define CLP_RSP_QPCI_MASK_UTIL 0x01
- uint8_t flags;
- uint8_t pfgid;
- uint32_t fid; /* pci function id */
- uint8_t bar_size[PCI_BAR_COUNT];
- uint16_t pchid;
- uint32_t bar[PCI_BAR_COUNT];
- uint8_t pfip[CLP_PFIP_NR_SEGMENTS];
- uint16_t reserved2;
- uint8_t fmbl;
- uint8_t pft;
- uint64_t sdma; /* start dma as */
- uint64_t edma; /* end dma as */
- uint32_t reserved3[11];
- uint32_t uid;
- uint8_t util_str[CLP_UTIL_STR_LEN]; /* utility string */
-} QEMU_PACKED ClpRspQueryPci;
-
-/* Query PCI function group request */
-typedef struct ClpReqQueryPciGrp {
- ClpReqHdr hdr;
- uint32_t fmt;
- uint64_t reserved1;
- uint8_t reserved2[3];
- uint8_t g;
- uint32_t reserved3;
- uint64_t reserved4;
-} QEMU_PACKED ClpReqQueryPciGrp;
-
-/* Query PCI function group response */
-typedef struct ClpRspQueryPciGrp {
- ClpRspHdr hdr;
- uint32_t fmt;
- uint64_t reserved1;
-#define CLP_RSP_QPCIG_MASK_NOI 0xfff
- uint16_t i;
- uint8_t version;
-#define CLP_RSP_QPCIG_MASK_FRAME 0x2
-#define CLP_RSP_QPCIG_MASK_REFRESH 0x1
- uint8_t fr;
- uint16_t maxstbl;
- uint16_t mui;
- uint64_t reserved3;
- uint64_t dasm; /* dma address space mask */
- uint64_t msia; /* MSI address */
- uint64_t reserved4;
- uint64_t reserved5;
-} QEMU_PACKED ClpRspQueryPciGrp;
-
-/* Set PCI function request */
-typedef struct ClpReqSetPci {
- ClpReqHdr hdr;
- uint32_t fmt;
- uint64_t reserved1;
- uint32_t fh; /* function handle */
- uint16_t reserved2;
- uint8_t oc; /* operation controls */
- uint8_t ndas; /* number of dma spaces */
- uint64_t reserved3;
-} QEMU_PACKED ClpReqSetPci;
-
-/* Set PCI function response */
-typedef struct ClpRspSetPci {
- ClpRspHdr hdr;
- uint32_t fmt;
- uint64_t reserved1;
- uint32_t fh; /* function handle */
- uint32_t reserved3;
- uint64_t reserved4;
-} QEMU_PACKED ClpRspSetPci;
-
-typedef struct ClpReqRspListPci {
- ClpReqListPci request;
- ClpRspListPci response;
-} QEMU_PACKED ClpReqRspListPci;
-
-typedef struct ClpReqRspSetPci {
- ClpReqSetPci request;
- ClpRspSetPci response;
-} QEMU_PACKED ClpReqRspSetPci;
-
-typedef struct ClpReqRspQueryPci {
- ClpReqQueryPci request;
- ClpRspQueryPci response;
-} QEMU_PACKED ClpReqRspQueryPci;
-
-typedef struct ClpReqRspQueryPciGrp {
- ClpReqQueryPciGrp request;
- ClpRspQueryPciGrp response;
-} QEMU_PACKED ClpReqRspQueryPciGrp;
-
-#endif
+++ /dev/null
-/*
- * s390 PCI instruction definitions
- *
- * Copyright 2014 IBM Corp.
- * Author(s): Frank Blaschka <frank.blaschka@de.ibm.com>
- * Hong Bo Li <lihbbj@cn.ibm.com>
- * Yi Min Zhao <zyimin@cn.ibm.com>
- *
- * This work is licensed under the terms of the GNU GPL, version 2 or (at
- * your option) any later version. See the COPYING file in the top-level
- * directory.
- */
-
-#ifndef HW_S390_PCI_INST_H
-#define HW_S390_PCI_INST_H
-
-#include "s390-pci-bus.h"
-#include "sysemu/dma.h"
-
-/* Load/Store status codes */
-#define ZPCI_PCI_ST_FUNC_NOT_ENABLED 4
-#define ZPCI_PCI_ST_FUNC_IN_ERR 8
-#define ZPCI_PCI_ST_BLOCKED 12
-#define ZPCI_PCI_ST_INSUF_RES 16
-#define ZPCI_PCI_ST_INVAL_AS 20
-#define ZPCI_PCI_ST_FUNC_ALREADY_ENABLED 24
-#define ZPCI_PCI_ST_DMA_AS_NOT_ENABLED 28
-#define ZPCI_PCI_ST_2ND_OP_IN_INV_AS 36
-#define ZPCI_PCI_ST_FUNC_NOT_AVAIL 40
-#define ZPCI_PCI_ST_ALREADY_IN_RQ_STATE 44
-
-/* Load/Store return codes */
-#define ZPCI_PCI_LS_OK 0
-#define ZPCI_PCI_LS_ERR 1
-#define ZPCI_PCI_LS_BUSY 2
-#define ZPCI_PCI_LS_INVAL_HANDLE 3
-
-/* Modify PCI status codes */
-#define ZPCI_MOD_ST_RES_NOT_AVAIL 4
-#define ZPCI_MOD_ST_INSUF_RES 16
-#define ZPCI_MOD_ST_SEQUENCE 24
-#define ZPCI_MOD_ST_DMAAS_INVAL 28
-#define ZPCI_MOD_ST_FRAME_INVAL 32
-#define ZPCI_MOD_ST_ERROR_RECOVER 40
-
-/* Modify PCI Function Controls */
-#define ZPCI_MOD_FC_REG_INT 2
-#define ZPCI_MOD_FC_DEREG_INT 3
-#define ZPCI_MOD_FC_REG_IOAT 4
-#define ZPCI_MOD_FC_DEREG_IOAT 5
-#define ZPCI_MOD_FC_REREG_IOAT 6
-#define ZPCI_MOD_FC_RESET_ERROR 7
-#define ZPCI_MOD_FC_RESET_BLOCK 9
-#define ZPCI_MOD_FC_SET_MEASURE 10
-
-/* Store PCI Function Controls status codes */
-#define ZPCI_STPCIFC_ST_PERM_ERROR 8
-#define ZPCI_STPCIFC_ST_INVAL_DMAAS 28
-#define ZPCI_STPCIFC_ST_ERROR_RECOVER 40
-
-/* Refresh PCI Translations status codes */
-#define ZPCI_RPCIT_ST_INSUFF_RES 16
-
-/* FIB function controls */
-#define ZPCI_FIB_FC_ENABLED 0x80
-#define ZPCI_FIB_FC_ERROR 0x40
-#define ZPCI_FIB_FC_LS_BLOCKED 0x20
-#define ZPCI_FIB_FC_DMAAS_REG 0x10
-
-/* FIB function controls */
-#define ZPCI_FIB_FC_ENABLED 0x80
-#define ZPCI_FIB_FC_ERROR 0x40
-#define ZPCI_FIB_FC_LS_BLOCKED 0x20
-#define ZPCI_FIB_FC_DMAAS_REG 0x10
-
-/* Function Information Block */
-typedef struct ZpciFib {
- uint8_t fmt; /* format */
- uint8_t reserved1[7];
- uint8_t fc; /* function controls */
- uint8_t reserved2;
- uint16_t reserved3;
- uint32_t reserved4;
- uint64_t pba; /* PCI base address */
- uint64_t pal; /* PCI address limit */
- uint64_t iota; /* I/O Translation Anchor */
-#define FIB_DATA_ISC(x) (((x) >> 28) & 0x7)
-#define FIB_DATA_NOI(x) (((x) >> 16) & 0xfff)
-#define FIB_DATA_AIBVO(x) (((x) >> 8) & 0x3f)
-#define FIB_DATA_SUM(x) (((x) >> 7) & 0x1)
-#define FIB_DATA_AISBO(x) ((x) & 0x3f)
- uint32_t data;
- uint32_t reserved5;
- uint64_t aibv; /* Adapter int bit vector address */
- uint64_t aisb; /* Adapter int summary bit address */
- uint64_t fmb_addr; /* Function measurement address and key */
- uint32_t reserved6;
- uint32_t gd;
-} QEMU_PACKED ZpciFib;
-
-int pci_dereg_irqs(S390PCIBusDevice *pbdev);
-void pci_dereg_ioat(S390PCIIOMMU *iommu);
-int clp_service_call(S390CPU *cpu, uint8_t r2, uintptr_t ra);
-int pcilg_service_call(S390CPU *cpu, uint8_t r1, uint8_t r2, uintptr_t ra);
-int pcistg_service_call(S390CPU *cpu, uint8_t r1, uint8_t r2, uintptr_t ra);
-int rpcit_service_call(S390CPU *cpu, uint8_t r1, uint8_t r2, uintptr_t ra);
-int pcistb_service_call(S390CPU *cpu, uint8_t r1, uint8_t r3, uint64_t gaddr,
- uint8_t ar, uintptr_t ra);
-int mpcifc_service_call(S390CPU *cpu, uint8_t r1, uint64_t fiba, uint8_t ar,
- uintptr_t ra);
-int stpcifc_service_call(S390CPU *cpu, uint8_t r1, uint64_t fiba, uint8_t ar,
- uintptr_t ra);
-void fmb_timer_free(S390PCIBusDevice *pbdev);
-
-#define ZPCI_IO_BAR_MIN 0
-#define ZPCI_IO_BAR_MAX 5
-#define ZPCI_CONFIG_BAR 15
-
-#endif
+++ /dev/null
-/*
- * s390 vfio-pci interfaces
- *
- * Copyright 2020 IBM Corp.
- * Author(s): Matthew Rosato <mjrosato@linux.ibm.com>
- *
- * This work is licensed under the terms of the GNU GPL, version 2 or (at
- * your option) any later version. See the COPYING file in the top-level
- * directory.
- */
-
-#ifndef HW_S390_PCI_VFIO_H
-#define HW_S390_PCI_VFIO_H
-
-#include "hw/s390x/s390-pci-bus.h"
-#include CONFIG_DEVICES
-
-#ifdef CONFIG_VFIO
-bool s390_pci_update_dma_avail(int fd, unsigned int *avail);
-S390PCIDMACount *s390_pci_start_dma_count(S390pciState *s,
- S390PCIBusDevice *pbdev);
-void s390_pci_end_dma_count(S390pciState *s, S390PCIDMACount *cnt);
-void s390_pci_get_clp_info(S390PCIBusDevice *pbdev);
-#else
-static inline bool s390_pci_update_dma_avail(int fd, unsigned int *avail)
-{
- return false;
-}
-static inline S390PCIDMACount *s390_pci_start_dma_count(S390pciState *s,
- S390PCIBusDevice *pbdev)
-{
- return NULL;
-}
-static inline void s390_pci_end_dma_count(S390pciState *s,
- S390PCIDMACount *cnt) { }
-static inline void s390_pci_get_clp_info(S390PCIBusDevice *pbdev) { }
-#endif
-
-#endif
+++ /dev/null
-/*
- * virtio ccw machine definitions
- *
- * Copyright 2012, 2016 IBM Corp.
- * Author(s): Cornelia Huck <cornelia.huck@de.ibm.com>
- *
- * This work is licensed under the terms of the GNU GPL, version 2 or (at
- * your option) any later version. See the COPYING file in the top-level
- * directory.
- */
-#ifndef HW_S390X_S390_VIRTIO_CCW_H
-#define HW_S390X_S390_VIRTIO_CCW_H
-
-#include "hw/boards.h"
-#include "qom/object.h"
-
-#define TYPE_S390_CCW_MACHINE "s390-ccw-machine"
-
-OBJECT_DECLARE_TYPE(S390CcwMachineState, S390CcwMachineClass, S390_CCW_MACHINE)
-
-
-struct S390CcwMachineState {
- /*< private >*/
- MachineState parent_obj;
-
- /*< public >*/
- bool aes_key_wrap;
- bool dea_key_wrap;
- bool pv;
- uint8_t loadparm[8];
-};
-
-struct S390CcwMachineClass {
- /*< private >*/
- MachineClass parent_class;
-
- /*< public >*/
- bool ri_allowed;
- bool cpu_model_allowed;
- bool css_migration_enabled;
- bool hpage_1m_allowed;
-};
-
-/* runtime-instrumentation allowed by the machine */
-bool ri_allowed(void);
-/* cpu model allowed by the machine */
-bool cpu_model_allowed(void);
-/* 1M huge page mappings allowed by the machine */
-bool hpage_1m_allowed(void);
-
-/**
- * Returns true if (vmstate based) migration of the channel subsystem
- * is enabled, false if it is disabled.
- */
-bool css_migration_enabled(void);
-
-#endif
+++ /dev/null
-/*
- * QEMU S390x floating interrupt controller (flic)
- *
- * Copyright 2014 IBM Corp.
- * Author(s): Jens Freimann <jfrei@linux.vnet.ibm.com>
- * Cornelia Huck <cornelia.huck@de.ibm.com>
- *
- * This work is licensed under the terms of the GNU GPL, version 2 or (at
- * your option) any later version. See the COPYING file in the top-level
- * directory.
- */
-
-#ifndef HW_S390_FLIC_H
-#define HW_S390_FLIC_H
-
-#include "hw/sysbus.h"
-#include "hw/s390x/adapter.h"
-#include "hw/virtio/virtio.h"
-#include "qemu/queue.h"
-#include "qom/object.h"
-
-/*
- * Reserve enough gsis to accommodate all virtio devices.
- * If any other user of adapter routes needs more of these,
- * we need to bump the value; but virtio looks like the
- * maximum right now.
- */
-#define ADAPTER_ROUTES_MAX_GSI VIRTIO_QUEUE_MAX
-
-typedef struct AdapterRoutes {
- AdapterInfo adapter;
- int num_routes;
- int gsi[ADAPTER_ROUTES_MAX_GSI];
-} AdapterRoutes;
-
-extern const VMStateDescription vmstate_adapter_routes;
-
-#define VMSTATE_ADAPTER_ROUTES(_f, _s) \
- VMSTATE_STRUCT(_f, _s, 1, vmstate_adapter_routes, AdapterRoutes)
-
-#define TYPE_S390_FLIC_COMMON "s390-flic"
-OBJECT_DECLARE_TYPE(S390FLICState, S390FLICStateClass,
- S390_FLIC_COMMON)
-
-struct S390FLICState {
- SysBusDevice parent_obj;
- /* to limit AdapterRoutes.num_routes for compat */
- uint32_t adapter_routes_max_batch;
- bool ais_supported;
-};
-
-
-struct S390FLICStateClass {
- DeviceClass parent_class;
-
- int (*register_io_adapter)(S390FLICState *fs, uint32_t id, uint8_t isc,
- bool swap, bool maskable, uint8_t flags);
- int (*io_adapter_map)(S390FLICState *fs, uint32_t id, uint64_t map_addr,
- bool do_map);
- int (*add_adapter_routes)(S390FLICState *fs, AdapterRoutes *routes);
- void (*release_adapter_routes)(S390FLICState *fs, AdapterRoutes *routes);
- int (*clear_io_irq)(S390FLICState *fs, uint16_t subchannel_id,
- uint16_t subchannel_nr);
- int (*modify_ais_mode)(S390FLICState *fs, uint8_t isc, uint16_t mode);
- int (*inject_airq)(S390FLICState *fs, uint8_t type, uint8_t isc,
- uint8_t flags);
- void (*inject_service)(S390FLICState *fs, uint32_t parm);
- void (*inject_io)(S390FLICState *fs, uint16_t subchannel_id,
- uint16_t subchannel_nr, uint32_t io_int_parm,
- uint32_t io_int_word);
- void (*inject_crw_mchk)(S390FLICState *fs);
-};
-
-#define TYPE_KVM_S390_FLIC "s390-flic-kvm"
-typedef struct KVMS390FLICState KVMS390FLICState;
-DECLARE_INSTANCE_CHECKER(KVMS390FLICState, KVM_S390_FLIC,
- TYPE_KVM_S390_FLIC)
-
-#define TYPE_QEMU_S390_FLIC "s390-flic-qemu"
-OBJECT_DECLARE_SIMPLE_TYPE(QEMUS390FLICState, QEMU_S390_FLIC)
-
-#define SIC_IRQ_MODE_ALL 0
-#define SIC_IRQ_MODE_SINGLE 1
-#define AIS_MODE_MASK(isc) (0x80 >> isc)
-
-#define ISC_TO_PENDING_IO(_isc) (0x80 >> (_isc))
-#define CR6_TO_PENDING_IO(_cr6) (((_cr6) >> 24) & 0xff)
-
-/* organize the ISC bits so that the macros above work */
-#define FLIC_PENDING_IO_ISC7 (1 << 0)
-#define FLIC_PENDING_IO_ISC6 (1 << 1)
-#define FLIC_PENDING_IO_ISC5 (1 << 2)
-#define FLIC_PENDING_IO_ISC4 (1 << 3)
-#define FLIC_PENDING_IO_ISC3 (1 << 4)
-#define FLIC_PENDING_IO_ISC2 (1 << 5)
-#define FLIC_PENDING_IO_ISC1 (1 << 6)
-#define FLIC_PENDING_IO_ISC0 (1 << 7)
-#define FLIC_PENDING_SERVICE (1 << 8)
-#define FLIC_PENDING_MCHK_CR (1 << 9)
-
-#define FLIC_PENDING_IO (FLIC_PENDING_IO_ISC0 | FLIC_PENDING_IO_ISC1 | \
- FLIC_PENDING_IO_ISC2 | FLIC_PENDING_IO_ISC3 | \
- FLIC_PENDING_IO_ISC4 | FLIC_PENDING_IO_ISC5 | \
- FLIC_PENDING_IO_ISC6 | FLIC_PENDING_IO_ISC7)
-
-typedef struct QEMUS390FlicIO {
- uint16_t id;
- uint16_t nr;
- uint32_t parm;
- uint32_t word;
- QLIST_ENTRY(QEMUS390FlicIO) next;
-} QEMUS390FlicIO;
-
-struct QEMUS390FLICState {
- S390FLICState parent_obj;
- uint32_t pending;
- uint32_t service_param;
- uint8_t simm;
- uint8_t nimm;
- QLIST_HEAD(, QEMUS390FlicIO) io[8];
-};
-
-uint32_t qemu_s390_flic_dequeue_service(QEMUS390FLICState *flic);
-QEMUS390FlicIO *qemu_s390_flic_dequeue_io(QEMUS390FLICState *flic,
- uint64_t cr6);
-void qemu_s390_flic_dequeue_crw_mchk(QEMUS390FLICState *flic);
-bool qemu_s390_flic_has_service(QEMUS390FLICState *flic);
-bool qemu_s390_flic_has_io(QEMUS390FLICState *fs, uint64_t cr6);
-bool qemu_s390_flic_has_crw_mchk(QEMUS390FLICState *flic);
-bool qemu_s390_flic_has_any(QEMUS390FLICState *flic);
-
-void s390_flic_init(void);
-
-S390FLICState *s390_get_flic(void);
-QEMUS390FLICState *s390_get_qemu_flic(S390FLICState *fs);
-S390FLICStateClass *s390_get_flic_class(S390FLICState *fs);
-void s390_crw_mchk(void);
-void s390_io_interrupt(uint16_t subchannel_id, uint16_t subchannel_nr,
- uint32_t io_int_parm, uint32_t io_int_word);
-bool ais_needed(void *opaque);
-
-#endif /* HW_S390_FLIC_H */
+++ /dev/null
-/*
- * SCLP Support
- *
- * Copyright IBM, Corp. 2012
- *
- * Authors:
- * Christian Borntraeger <borntraeger@de.ibm.com>
- *
- * This work is licensed under the terms of the GNU GPL, version 2 or (at your
- * option) any later version. See the COPYING file in the top-level directory.
- *
- */
-
-#ifndef HW_S390_SCLP_H
-#define HW_S390_SCLP_H
-
-#include "hw/sysbus.h"
-#include "target/s390x/cpu-qom.h"
-#include "qom/object.h"
-
-#define SCLP_CMD_CODE_MASK 0xffff00ff
-
-/* SCLP command codes */
-#define SCLP_CMDW_READ_SCP_INFO 0x00020001
-#define SCLP_CMDW_READ_SCP_INFO_FORCED 0x00120001
-#define SCLP_READ_STORAGE_ELEMENT_INFO 0x00040001
-#define SCLP_ATTACH_STORAGE_ELEMENT 0x00080001
-#define SCLP_ASSIGN_STORAGE 0x000D0001
-#define SCLP_UNASSIGN_STORAGE 0x000C0001
-#define SCLP_CMD_READ_EVENT_DATA 0x00770005
-#define SCLP_CMD_WRITE_EVENT_DATA 0x00760005
-#define SCLP_CMD_WRITE_EVENT_MASK 0x00780005
-
-/* SCLP Memory hotplug codes */
-#define SCLP_FC_ASSIGN_ATTACH_READ_STOR 0xE00000000000ULL
-#define SCLP_STARTING_SUBINCREMENT_ID 0x10001
-#define SCLP_INCREMENT_UNIT 0x10000
-#define MAX_STORAGE_INCREMENTS 1020
-
-/* CPU hotplug SCLP codes */
-#define SCLP_HAS_CPU_INFO 0x0C00000000000000ULL
-#define SCLP_CMDW_READ_CPU_INFO 0x00010001
-#define SCLP_CMDW_CONFIGURE_CPU 0x00110001
-#define SCLP_CMDW_DECONFIGURE_CPU 0x00100001
-
-/* SCLP PCI codes */
-#define SCLP_HAS_IOA_RECONFIG 0x0000000040000000ULL
-#define SCLP_CMDW_CONFIGURE_IOA 0x001a0001
-#define SCLP_CMDW_DECONFIGURE_IOA 0x001b0001
-#define SCLP_RECONFIG_PCI_ATYPE 2
-
-/* SCLP response codes */
-#define SCLP_RC_NORMAL_READ_COMPLETION 0x0010
-#define SCLP_RC_NORMAL_COMPLETION 0x0020
-#define SCLP_RC_SCCB_BOUNDARY_VIOLATION 0x0100
-#define SCLP_RC_NO_ACTION_REQUIRED 0x0120
-#define SCLP_RC_INVALID_SCLP_COMMAND 0x01f0
-#define SCLP_RC_CONTAINED_EQUIPMENT_CHECK 0x0340
-#define SCLP_RC_INSUFFICIENT_SCCB_LENGTH 0x0300
-#define SCLP_RC_STANDBY_READ_COMPLETION 0x0410
-#define SCLP_RC_ADAPTER_IN_RESERVED_STATE 0x05f0
-#define SCLP_RC_ADAPTER_TYPE_NOT_RECOGNIZED 0x06f0
-#define SCLP_RC_ADAPTER_ID_NOT_RECOGNIZED 0x09f0
-#define SCLP_RC_INVALID_FUNCTION 0x40f0
-#define SCLP_RC_NO_EVENT_BUFFERS_STORED 0x60f0
-#define SCLP_RC_INVALID_SELECTION_MASK 0x70f0
-#define SCLP_RC_INCONSISTENT_LENGTHS 0x72f0
-#define SCLP_RC_EVENT_BUFFER_SYNTAX_ERROR 0x73f0
-#define SCLP_RC_INVALID_MASK_LENGTH 0x74f0
-
-
-/* Service Call Control Block (SCCB) and its elements */
-
-#define SCCB_SIZE 4096
-
-#define SCLP_VARIABLE_LENGTH_RESPONSE 0x80
-#define SCLP_EVENT_BUFFER_ACCEPTED 0x80
-
-#define SCLP_FC_NORMAL_WRITE 0
-
-/*
- * Normally packed structures are not the right thing to do, since all code
- * must take care of endianness. We cannot use ldl_phys and friends for two
- * reasons, though:
- * - some of the embedded structures below the SCCB can appear multiple times
- * at different locations, so there is no fixed offset
- * - we work on a private copy of the SCCB, since there are several length
- * fields, that would cause a security nightmare if we allow the guest to
- * alter the structure while we parse it. We cannot use ldl_p and friends
- * either without doing pointer arithmetics
- * So we have to double check that all users of sclp data structures use the
- * right endianness wrappers.
- */
-typedef struct SCCBHeader {
- uint16_t length;
- uint8_t function_code;
- uint8_t control_mask[3];
- uint16_t response_code;
-} QEMU_PACKED SCCBHeader;
-
-#define SCCB_DATA_LEN (SCCB_SIZE - sizeof(SCCBHeader))
-#define SCCB_CPU_FEATURE_LEN 6
-
-/* CPU information */
-typedef struct CPUEntry {
- uint8_t address;
- uint8_t reserved0;
- uint8_t features[SCCB_CPU_FEATURE_LEN];
- uint8_t reserved2[6];
- uint8_t type;
- uint8_t reserved1;
-} QEMU_PACKED CPUEntry;
-
-#define SCLP_READ_SCP_INFO_FIXED_CPU_OFFSET 128
-typedef struct ReadInfo {
- SCCBHeader h;
- uint16_t rnmax;
- uint8_t rnsize;
- uint8_t _reserved1[16 - 11]; /* 11-15 */
- uint16_t entries_cpu; /* 16-17 */
- uint16_t offset_cpu; /* 18-19 */
- uint8_t _reserved2[24 - 20]; /* 20-23 */
- uint8_t loadparm[8]; /* 24-31 */
- uint8_t _reserved3[48 - 32]; /* 32-47 */
- uint64_t facilities; /* 48-55 */
- uint8_t _reserved0[76 - 56]; /* 56-75 */
- uint32_t ibc_val;
- uint8_t conf_char[99 - 80]; /* 80-98 */
- uint8_t mha_pow;
- uint32_t rnsize2;
- uint64_t rnmax2;
- uint8_t _reserved6[116 - 112]; /* 112-115 */
- uint8_t conf_char_ext[120 - 116]; /* 116-119 */
- uint16_t highest_cpu;
- uint8_t _reserved5[124 - 122]; /* 122-123 */
- uint32_t hmfai;
- uint8_t _reserved7[134 - 128]; /* 128-133 */
- uint8_t fac134;
- uint8_t _reserved8[144 - 135]; /* 135-143 */
- struct CPUEntry entries[];
- /*
- * When the Extended-Length SCCB (ELS) feature is enabled the
- * start of the entries field begins at an offset denoted by the
- * offset_cpu field, otherwise it's at an offset of 128.
- */
-} QEMU_PACKED ReadInfo;
-
-typedef struct ReadCpuInfo {
- SCCBHeader h;
- uint16_t nr_configured; /* 8-9 */
- uint16_t offset_configured; /* 10-11 */
- uint16_t nr_standby; /* 12-13 */
- uint16_t offset_standby; /* 14-15 */
- uint8_t reserved0[24-16]; /* 16-23 */
- struct CPUEntry entries[];
-} QEMU_PACKED ReadCpuInfo;
-
-typedef struct ReadStorageElementInfo {
- SCCBHeader h;
- uint16_t max_id;
- uint16_t assigned;
- uint16_t standby;
- uint8_t _reserved0[16 - 14]; /* 14-15 */
- uint32_t entries[];
-} QEMU_PACKED ReadStorageElementInfo;
-
-typedef struct AttachStorageElement {
- SCCBHeader h;
- uint8_t _reserved0[10 - 8]; /* 8-9 */
- uint16_t assigned;
- uint8_t _reserved1[16 - 12]; /* 12-15 */
- uint32_t entries[];
-} QEMU_PACKED AttachStorageElement;
-
-typedef struct AssignStorage {
- SCCBHeader h;
- uint16_t rn;
-} QEMU_PACKED AssignStorage;
-
-typedef struct IoaCfgSccb {
- SCCBHeader header;
- uint8_t atype;
- uint8_t reserved1;
- uint16_t reserved2;
- uint32_t aid;
-} QEMU_PACKED IoaCfgSccb;
-
-typedef struct SCCB {
- SCCBHeader h;
- char data[];
- } QEMU_PACKED SCCB;
-
-#define TYPE_SCLP "sclp"
-OBJECT_DECLARE_TYPE(SCLPDevice, SCLPDeviceClass,
- SCLP)
-
-struct SCLPEventFacility;
-
-struct SCLPDevice {
- /* private */
- DeviceState parent_obj;
- struct SCLPEventFacility *event_facility;
- int increment_size;
-
- /* public */
-};
-
-struct SCLPDeviceClass {
- /* private */
- DeviceClass parent_class;
- void (*read_SCP_info)(SCLPDevice *sclp, SCCB *sccb);
- void (*read_cpu_info)(SCLPDevice *sclp, SCCB *sccb);
-
- /* public */
- void (*execute)(SCLPDevice *sclp, SCCB *sccb, uint32_t code);
- void (*service_interrupt)(SCLPDevice *sclp, uint32_t sccb);
-};
-
-static inline int sccb_data_len(SCCB *sccb)
-{
- return be16_to_cpu(sccb->h.length) - sizeof(sccb->h);
-}
-
-
-void s390_sclp_init(void);
-void sclp_service_interrupt(uint32_t sccb);
-void raise_irq_cpu_hotplug(void);
-int sclp_service_call(CPUS390XState *env, uint64_t sccb, uint32_t code);
-int sclp_service_call_protected(CPUS390XState *env, uint64_t sccb,
- uint32_t code);
-
-#endif
+++ /dev/null
-/*
- * s390 storage attributes device
- *
- * Copyright 2016 IBM Corp.
- * Author(s): Claudio Imbrenda <imbrenda@linux.vnet.ibm.com>
- *
- * This work is licensed under the terms of the GNU GPL, version 2 or (at
- * your option) any later version. See the COPYING file in the top-level
- * directory.
- */
-
-#ifndef S390_STORAGE_ATTRIBUTES_H
-#define S390_STORAGE_ATTRIBUTES_H
-
-#include "hw/qdev-core.h"
-#include "monitor/monitor.h"
-#include "qom/object.h"
-
-#define TYPE_S390_STATTRIB "s390-storage_attributes"
-#define TYPE_QEMU_S390_STATTRIB "s390-storage_attributes-qemu"
-#define TYPE_KVM_S390_STATTRIB "s390-storage_attributes-kvm"
-
-OBJECT_DECLARE_TYPE(S390StAttribState, S390StAttribClass, S390_STATTRIB)
-
-struct S390StAttribState {
- DeviceState parent_obj;
- uint64_t migration_cur_gfn;
- bool migration_enabled;
-};
-
-
-struct S390StAttribClass {
- DeviceClass parent_class;
- /* Return value: < 0 on error, or new count */
- int (*get_stattr)(S390StAttribState *sa, uint64_t *start_gfn,
- uint32_t count, uint8_t *values);
- int (*peek_stattr)(S390StAttribState *sa, uint64_t start_gfn,
- uint32_t count, uint8_t *values);
- int (*set_stattr)(S390StAttribState *sa, uint64_t start_gfn,
- uint32_t count, uint8_t *values);
- void (*synchronize)(S390StAttribState *sa);
- int (*set_migrationmode)(S390StAttribState *sa, bool value);
- int (*get_active)(S390StAttribState *sa);
- long long (*get_dirtycount)(S390StAttribState *sa);
-};
-
-typedef struct QEMUS390StAttribState QEMUS390StAttribState;
-DECLARE_INSTANCE_CHECKER(QEMUS390StAttribState, QEMU_S390_STATTRIB,
- TYPE_QEMU_S390_STATTRIB)
-
-struct QEMUS390StAttribState {
- S390StAttribState parent_obj;
-};
-
-typedef struct KVMS390StAttribState KVMS390StAttribState;
-DECLARE_INSTANCE_CHECKER(KVMS390StAttribState, KVM_S390_STATTRIB,
- TYPE_KVM_S390_STATTRIB)
-
-struct KVMS390StAttribState {
- S390StAttribState parent_obj;
- uint64_t still_dirty;
- uint8_t *incoming_buffer;
-};
-
-void s390_stattrib_init(void);
-
-#ifdef CONFIG_KVM
-Object *kvm_s390_stattrib_create(void);
-#else
-static inline Object *kvm_s390_stattrib_create(void)
-{
- return NULL;
-}
-#endif
-
-void hmp_info_cmma(Monitor *mon, const QDict *qdict);
-void hmp_migrationmode(Monitor *mon, const QDict *qdict);
-
-#endif /* S390_STORAGE_ATTRIBUTES_H */
+++ /dev/null
-/*
- * s390 storage key device
- *
- * Copyright 2015 IBM Corp.
- * Author(s): Jason J. Herne <jjherne@linux.vnet.ibm.com>
- *
- * This work is licensed under the terms of the GNU GPL, version 2 or (at
- * your option) any later version. See the COPYING file in the top-level
- * directory.
- */
-
-#ifndef S390_STORAGE_KEYS_H
-#define S390_STORAGE_KEYS_H
-
-#include "hw/qdev-core.h"
-#include "monitor/monitor.h"
-#include "qom/object.h"
-
-#define TYPE_S390_SKEYS "s390-skeys"
-OBJECT_DECLARE_TYPE(S390SKeysState, S390SKeysClass, S390_SKEYS)
-
-struct S390SKeysState {
- DeviceState parent_obj;
- bool migration_enabled;
-
-};
-
-
-struct S390SKeysClass {
- DeviceClass parent_class;
- int (*skeys_enabled)(S390SKeysState *ks);
- int (*get_skeys)(S390SKeysState *ks, uint64_t start_gfn, uint64_t count,
- uint8_t *keys);
- int (*set_skeys)(S390SKeysState *ks, uint64_t start_gfn, uint64_t count,
- uint8_t *keys);
-};
-
-#define TYPE_KVM_S390_SKEYS "s390-skeys-kvm"
-#define TYPE_QEMU_S390_SKEYS "s390-skeys-qemu"
-typedef struct QEMUS390SKeysState QEMUS390SKeysState;
-DECLARE_INSTANCE_CHECKER(QEMUS390SKeysState, QEMU_S390_SKEYS,
- TYPE_QEMU_S390_SKEYS)
-
-struct QEMUS390SKeysState {
- S390SKeysState parent_obj;
- uint8_t *keydata;
- uint32_t key_count;
-};
-
-void s390_skeys_init(void);
-
-S390SKeysState *s390_get_skeys_device(void);
-
-void hmp_dump_skeys(Monitor *mon, const QDict *qdict);
-void hmp_info_skeys(Monitor *mon, const QDict *qdict);
-
-#endif /* S390_STORAGE_KEYS_H */
+++ /dev/null
-/*
- * TOD (Time Of Day) clock
- *
- * Copyright 2018 Red Hat, Inc.
- * Author(s): David Hildenbrand <david@redhat.com>
- *
- * This work is licensed under the terms of the GNU GPL, version 2 or later.
- * See the COPYING file in the top-level directory.
- */
-
-#ifndef HW_S390_TOD_H
-#define HW_S390_TOD_H
-
-#include "hw/qdev-core.h"
-#include "target/s390x/s390-tod.h"
-#include "qom/object.h"
-
-typedef struct S390TOD {
- uint8_t high;
- uint64_t low;
-} S390TOD;
-
-#define TYPE_S390_TOD "s390-tod"
-OBJECT_DECLARE_TYPE(S390TODState, S390TODClass, S390_TOD)
-#define TYPE_KVM_S390_TOD TYPE_S390_TOD "-kvm"
-#define TYPE_QEMU_S390_TOD TYPE_S390_TOD "-qemu"
-
-struct S390TODState {
- /* private */
- DeviceState parent_obj;
-
- /*
- * Used by TCG to remember the time base. Used by KVM to backup the TOD
- * while the TOD is stopped.
- */
- S390TOD base;
- /* Used by KVM to remember if the TOD is stopped and base is valid. */
- bool stopped;
-};
-
-struct S390TODClass {
- /* private */
- DeviceClass parent_class;
- void (*parent_realize)(DeviceState *dev, Error **errp);
-
- /* public */
- void (*get)(const S390TODState *td, S390TOD *tod, Error **errp);
- void (*set)(S390TODState *td, const S390TOD *tod, Error **errp);
-};
-
-void s390_init_tod(void);
-S390TODState *s390_get_todstate(void);
-
-#endif
+++ /dev/null
-/*
- * vfio based subchannel assignment support
- *
- * Copyright 2017, 2019 IBM Corp.
- * Author(s): Dong Jia Shi <bjsdjshi@linux.vnet.ibm.com>
- * Xiao Feng Ren <renxiaof@linux.vnet.ibm.com>
- * Pierre Morel <pmorel@linux.vnet.ibm.com>
- *
- * This work is licensed under the terms of the GNU GPL, version 2 or (at
- * your option) any later version. See the COPYING file in the top-level
- * directory.
- */
-
-#ifndef HW_VFIO_CCW_H
-#define HW_VFIO_CCW_H
-
-#include "hw/vfio/vfio-common.h"
-#include "hw/s390x/s390-ccw.h"
-#include "hw/s390x/ccw-device.h"
-#include "qom/object.h"
-
-#define TYPE_VFIO_CCW "vfio-ccw"
-OBJECT_DECLARE_SIMPLE_TYPE(VFIOCCWDevice, VFIO_CCW)
-
-#define TYPE_VFIO_CCW "vfio-ccw"
-
-#endif
+++ /dev/null
-#ifndef HW_SCSI_EMULATION_H
-#define HW_SCSI_EMULATION_H
-
-typedef struct SCSIBlockLimits {
- bool wsnz;
- uint16_t min_io_size;
- uint32_t max_unmap_descr;
- uint32_t opt_io_size;
- uint32_t max_unmap_sectors;
- uint32_t unmap_sectors;
- uint32_t max_io_sectors;
-} SCSIBlockLimits;
-
-int scsi_emulate_block_limits(uint8_t *outbuf, const SCSIBlockLimits *bl);
-
-#endif
+++ /dev/null
-#ifndef QEMU_HW_ESP_H
-#define QEMU_HW_ESP_H
-
-#include "hw/scsi/scsi.h"
-#include "hw/sysbus.h"
-#include "qom/object.h"
-
-/* esp.c */
-#define ESP_MAX_DEVS 7
-typedef void (*ESPDMAMemoryReadWriteFunc)(void *opaque, uint8_t *buf, int len);
-
-#define ESP_REGS 16
-#define TI_BUFSZ 16
-#define ESP_CMDBUF_SZ 32
-
-typedef struct ESPState ESPState;
-
-enum pdma_origin_id {
- PDMA,
- TI,
- CMD,
- ASYNC,
-};
-
-struct ESPState {
- uint8_t rregs[ESP_REGS];
- uint8_t wregs[ESP_REGS];
- qemu_irq irq;
- qemu_irq irq_data;
- uint8_t chip_id;
- bool tchi_written;
- int32_t ti_size;
- uint32_t ti_rptr, ti_wptr;
- uint32_t status;
- uint32_t deferred_status;
- bool deferred_complete;
- uint32_t dma;
- uint8_t ti_buf[TI_BUFSZ];
- SCSIBus bus;
- SCSIDevice *current_dev;
- SCSIRequest *current_req;
- uint8_t cmdbuf[ESP_CMDBUF_SZ];
- uint32_t cmdlen;
- uint32_t do_cmd;
-
- /* The amount of data left in the current DMA transfer. */
- uint32_t dma_left;
- /* The size of the current DMA transfer. Zero if no transfer is in
- progress. */
- uint32_t dma_counter;
- int dma_enabled;
-
- uint32_t async_len;
- uint8_t *async_buf;
-
- ESPDMAMemoryReadWriteFunc dma_memory_read;
- ESPDMAMemoryReadWriteFunc dma_memory_write;
- void *dma_opaque;
- void (*dma_cb)(ESPState *s);
- uint8_t pdma_buf[32];
- int pdma_origin;
- uint32_t pdma_len;
- uint32_t pdma_start;
- uint32_t pdma_cur;
- void (*pdma_cb)(ESPState *s);
-};
-
-#define TYPE_ESP "esp"
-OBJECT_DECLARE_SIMPLE_TYPE(SysBusESPState, ESP)
-
-struct SysBusESPState {
- /*< private >*/
- SysBusDevice parent_obj;
- /*< public >*/
-
- MemoryRegion iomem;
- MemoryRegion pdma;
- uint32_t it_shift;
- ESPState esp;
-};
-
-#define ESP_TCLO 0x0
-#define ESP_TCMID 0x1
-#define ESP_FIFO 0x2
-#define ESP_CMD 0x3
-#define ESP_RSTAT 0x4
-#define ESP_WBUSID 0x4
-#define ESP_RINTR 0x5
-#define ESP_WSEL 0x5
-#define ESP_RSEQ 0x6
-#define ESP_WSYNTP 0x6
-#define ESP_RFLAGS 0x7
-#define ESP_WSYNO 0x7
-#define ESP_CFG1 0x8
-#define ESP_RRES1 0x9
-#define ESP_WCCF 0x9
-#define ESP_RRES2 0xa
-#define ESP_WTEST 0xa
-#define ESP_CFG2 0xb
-#define ESP_CFG3 0xc
-#define ESP_RES3 0xd
-#define ESP_TCHI 0xe
-#define ESP_RES4 0xf
-
-#define CMD_DMA 0x80
-#define CMD_CMD 0x7f
-
-#define CMD_NOP 0x00
-#define CMD_FLUSH 0x01
-#define CMD_RESET 0x02
-#define CMD_BUSRESET 0x03
-#define CMD_TI 0x10
-#define CMD_ICCS 0x11
-#define CMD_MSGACC 0x12
-#define CMD_PAD 0x18
-#define CMD_SATN 0x1a
-#define CMD_RSTATN 0x1b
-#define CMD_SEL 0x41
-#define CMD_SELATN 0x42
-#define CMD_SELATNS 0x43
-#define CMD_ENSEL 0x44
-#define CMD_DISSEL 0x45
-
-#define STAT_DO 0x00
-#define STAT_DI 0x01
-#define STAT_CD 0x02
-#define STAT_ST 0x03
-#define STAT_MO 0x06
-#define STAT_MI 0x07
-#define STAT_PIO_MASK 0x06
-
-#define STAT_TC 0x10
-#define STAT_PE 0x20
-#define STAT_GE 0x40
-#define STAT_INT 0x80
-
-#define BUSID_DID 0x07
-
-#define INTR_FC 0x08
-#define INTR_BS 0x10
-#define INTR_DC 0x20
-#define INTR_RST 0x80
-
-#define SEQ_0 0x0
-#define SEQ_CD 0x4
-
-#define CFG1_RESREPT 0x40
-
-#define TCHI_FAS100A 0x4
-#define TCHI_AM53C974 0x12
-
-void esp_dma_enable(ESPState *s, int irq, int level);
-void esp_request_cancelled(SCSIRequest *req);
-void esp_command_complete(SCSIRequest *req, uint32_t status, size_t resid);
-void esp_transfer_data(SCSIRequest *req, uint32_t len);
-void esp_hard_reset(ESPState *s);
-uint64_t esp_reg_read(ESPState *s, uint32_t saddr);
-void esp_reg_write(ESPState *s, uint32_t saddr, uint64_t val);
-extern const VMStateDescription vmstate_esp;
-
-#endif
+++ /dev/null
-#ifndef QEMU_HW_SCSI_H
-#define QEMU_HW_SCSI_H
-
-#include "block/aio.h"
-#include "hw/block/block.h"
-#include "hw/qdev-core.h"
-#include "scsi/utils.h"
-#include "qemu/notify.h"
-#include "qom/object.h"
-
-#define MAX_SCSI_DEVS 255
-
-typedef struct SCSIBus SCSIBus;
-typedef struct SCSIBusInfo SCSIBusInfo;
-typedef struct SCSIDevice SCSIDevice;
-typedef struct SCSIRequest SCSIRequest;
-typedef struct SCSIReqOps SCSIReqOps;
-
-#define SCSI_SENSE_BUF_SIZE_OLD 96
-#define SCSI_SENSE_BUF_SIZE 252
-
-struct SCSIRequest {
- SCSIBus *bus;
- SCSIDevice *dev;
- const SCSIReqOps *ops;
- uint32_t refcount;
- uint32_t tag;
- uint32_t lun;
- uint32_t status;
- void *hba_private;
- size_t resid;
- SCSICommand cmd;
- NotifierList cancel_notifiers;
-
- /* Note:
- * - fields before sense are initialized by scsi_req_alloc;
- * - sense[] is uninitialized;
- * - fields after sense are memset to 0 by scsi_req_alloc.
- * */
-
- uint8_t sense[SCSI_SENSE_BUF_SIZE];
- uint32_t sense_len;
- bool enqueued;
- bool io_canceled;
- bool retry;
- bool dma_started;
- BlockAIOCB *aiocb;
- QEMUSGList *sg;
- QTAILQ_ENTRY(SCSIRequest) next;
-};
-
-#define TYPE_SCSI_DEVICE "scsi-device"
-OBJECT_DECLARE_TYPE(SCSIDevice, SCSIDeviceClass, SCSI_DEVICE)
-
-struct SCSIDeviceClass {
- DeviceClass parent_class;
- void (*realize)(SCSIDevice *dev, Error **errp);
- void (*unrealize)(SCSIDevice *dev);
- int (*parse_cdb)(SCSIDevice *dev, SCSICommand *cmd, uint8_t *buf,
- void *hba_private);
- SCSIRequest *(*alloc_req)(SCSIDevice *s, uint32_t tag, uint32_t lun,
- uint8_t *buf, void *hba_private);
- void (*unit_attention_reported)(SCSIDevice *s);
-};
-
-struct SCSIDevice
-{
- DeviceState qdev;
- VMChangeStateEntry *vmsentry;
- QEMUBH *bh;
- uint32_t id;
- BlockConf conf;
- SCSISense unit_attention;
- bool sense_is_ua;
- uint8_t sense[SCSI_SENSE_BUF_SIZE];
- uint32_t sense_len;
- QTAILQ_HEAD(, SCSIRequest) requests;
- uint32_t channel;
- uint32_t lun;
- int blocksize;
- int type;
- uint64_t max_lba;
- uint64_t wwn;
- uint64_t port_wwn;
- int scsi_version;
- int default_scsi_version;
- bool needs_vpd_bl_emulation;
- bool hba_supports_iothread;
-};
-
-extern const VMStateDescription vmstate_scsi_device;
-
-#define VMSTATE_SCSI_DEVICE(_field, _state) { \
- .name = (stringify(_field)), \
- .size = sizeof(SCSIDevice), \
- .vmsd = &vmstate_scsi_device, \
- .flags = VMS_STRUCT, \
- .offset = vmstate_offset_value(_state, _field, SCSIDevice), \
-}
-
-/* cdrom.c */
-int cdrom_read_toc(int nb_sectors, uint8_t *buf, int msf, int start_track);
-int cdrom_read_toc_raw(int nb_sectors, uint8_t *buf, int msf, int session_num);
-
-/* scsi-bus.c */
-struct SCSIReqOps {
- size_t size;
- void (*free_req)(SCSIRequest *req);
- int32_t (*send_command)(SCSIRequest *req, uint8_t *buf);
- void (*read_data)(SCSIRequest *req);
- void (*write_data)(SCSIRequest *req);
- uint8_t *(*get_buf)(SCSIRequest *req);
-
- void (*save_request)(QEMUFile *f, SCSIRequest *req);
- void (*load_request)(QEMUFile *f, SCSIRequest *req);
-};
-
-struct SCSIBusInfo {
- int tcq;
- int max_channel, max_target, max_lun;
- int (*parse_cdb)(SCSIDevice *dev, SCSICommand *cmd, uint8_t *buf,
- void *hba_private);
- void (*transfer_data)(SCSIRequest *req, uint32_t arg);
- void (*complete)(SCSIRequest *req, uint32_t arg, size_t resid);
- void (*cancel)(SCSIRequest *req);
- void (*change)(SCSIBus *bus, SCSIDevice *dev, SCSISense sense);
- QEMUSGList *(*get_sg_list)(SCSIRequest *req);
-
- void (*save_request)(QEMUFile *f, SCSIRequest *req);
- void *(*load_request)(QEMUFile *f, SCSIRequest *req);
- void (*free_request)(SCSIBus *bus, void *priv);
-};
-
-#define TYPE_SCSI_BUS "SCSI"
-OBJECT_DECLARE_SIMPLE_TYPE(SCSIBus, SCSI_BUS)
-
-struct SCSIBus {
- BusState qbus;
- int busnr;
-
- SCSISense unit_attention;
- const SCSIBusInfo *info;
-};
-
-void scsi_bus_new(SCSIBus *bus, size_t bus_size, DeviceState *host,
- const SCSIBusInfo *info, const char *bus_name);
-
-static inline SCSIBus *scsi_bus_from_device(SCSIDevice *d)
-{
- return DO_UPCAST(SCSIBus, qbus, d->qdev.parent_bus);
-}
-
-SCSIDevice *scsi_bus_legacy_add_drive(SCSIBus *bus, BlockBackend *blk,
- int unit, bool removable, int bootindex,
- bool share_rw,
- BlockdevOnError rerror,
- BlockdevOnError werror,
- const char *serial, Error **errp);
-void scsi_bus_legacy_handle_cmdline(SCSIBus *bus);
-void scsi_legacy_handle_cmdline(void);
-
-SCSIRequest *scsi_req_alloc(const SCSIReqOps *reqops, SCSIDevice *d,
- uint32_t tag, uint32_t lun, void *hba_private);
-SCSIRequest *scsi_req_new(SCSIDevice *d, uint32_t tag, uint32_t lun,
- uint8_t *buf, void *hba_private);
-int32_t scsi_req_enqueue(SCSIRequest *req);
-SCSIRequest *scsi_req_ref(SCSIRequest *req);
-void scsi_req_unref(SCSIRequest *req);
-
-int scsi_bus_parse_cdb(SCSIDevice *dev, SCSICommand *cmd, uint8_t *buf,
- void *hba_private);
-int scsi_req_parse_cdb(SCSIDevice *dev, SCSICommand *cmd, uint8_t *buf);
-void scsi_req_build_sense(SCSIRequest *req, SCSISense sense);
-void scsi_req_print(SCSIRequest *req);
-void scsi_req_continue(SCSIRequest *req);
-void scsi_req_data(SCSIRequest *req, int len);
-void scsi_req_complete(SCSIRequest *req, int status);
-uint8_t *scsi_req_get_buf(SCSIRequest *req);
-int scsi_req_get_sense(SCSIRequest *req, uint8_t *buf, int len);
-void scsi_req_cancel_complete(SCSIRequest *req);
-void scsi_req_cancel(SCSIRequest *req);
-void scsi_req_cancel_async(SCSIRequest *req, Notifier *notifier);
-void scsi_req_retry(SCSIRequest *req);
-void scsi_device_purge_requests(SCSIDevice *sdev, SCSISense sense);
-void scsi_device_set_ua(SCSIDevice *sdev, SCSISense sense);
-void scsi_device_report_change(SCSIDevice *dev, SCSISense sense);
-void scsi_device_unit_attention_reported(SCSIDevice *dev);
-void scsi_generic_read_device_inquiry(SCSIDevice *dev);
-int scsi_device_get_sense(SCSIDevice *dev, uint8_t *buf, int len, bool fixed);
-int scsi_SG_IO_FROM_DEV(BlockBackend *blk, uint8_t *cmd, uint8_t cmd_size,
- uint8_t *buf, uint8_t buf_size);
-SCSIDevice *scsi_device_find(SCSIBus *bus, int channel, int target, int lun);
-SCSIDevice *scsi_device_get(SCSIBus *bus, int channel, int target, int lun);
-
-/* scsi-generic.c. */
-extern const SCSIReqOps scsi_generic_req_ops;
-
-#endif
+++ /dev/null
-/*
- * Allwinner (sun4i and above) SD Host Controller emulation
- *
- * Copyright (C) 2019 Niek Linnenbank <nieklinnenbank@gmail.com>
- *
- * This program is free software: you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation, either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program. If not, see <http://www.gnu.org/licenses/>.
- */
-
-#ifndef HW_SD_ALLWINNER_SDHOST_H
-#define HW_SD_ALLWINNER_SDHOST_H
-
-#include "qom/object.h"
-#include "hw/sysbus.h"
-#include "hw/sd/sd.h"
-
-/**
- * Object model types
- * @{
- */
-
-/** Generic Allwinner SD Host Controller (abstract) */
-#define TYPE_AW_SDHOST "allwinner-sdhost"
-
-/** Allwinner sun4i family (A10, A12) */
-#define TYPE_AW_SDHOST_SUN4I TYPE_AW_SDHOST "-sun4i"
-
-/** Allwinner sun5i family and newer (A13, H2+, H3, etc) */
-#define TYPE_AW_SDHOST_SUN5I TYPE_AW_SDHOST "-sun5i"
-
-/** @} */
-
-/**
- * Object model macros
- * @{
- */
-
-OBJECT_DECLARE_TYPE(AwSdHostState, AwSdHostClass, AW_SDHOST)
-
-/** @} */
-
-/**
- * Allwinner SD Host Controller object instance state.
- */
-struct AwSdHostState {
- /*< private >*/
- SysBusDevice busdev;
- /*< public >*/
-
- /** Secure Digital (SD) bus, which connects to SD card (if present) */
- SDBus sdbus;
-
- /** Maps I/O registers in physical memory */
- MemoryRegion iomem;
-
- /** Interrupt output signal to notify CPU */
- qemu_irq irq;
-
- /** Memory region where DMA transfers are done */
- MemoryRegion *dma_mr;
-
- /** Address space used internally for DMA transfers */
- AddressSpace dma_as;
-
- /** Number of bytes left in current DMA transfer */
- uint32_t transfer_cnt;
-
- /**
- * @name Hardware Registers
- * @{
- */
-
- uint32_t global_ctl; /**< Global Control */
- uint32_t clock_ctl; /**< Clock Control */
- uint32_t timeout; /**< Timeout */
- uint32_t bus_width; /**< Bus Width */
- uint32_t block_size; /**< Block Size */
- uint32_t byte_count; /**< Byte Count */
-
- uint32_t command; /**< Command */
- uint32_t command_arg; /**< Command Argument */
- uint32_t response[4]; /**< Command Response */
-
- uint32_t irq_mask; /**< Interrupt Mask */
- uint32_t irq_status; /**< Raw Interrupt Status */
- uint32_t status; /**< Status */
-
- uint32_t fifo_wlevel; /**< FIFO Water Level */
- uint32_t fifo_func_sel; /**< FIFO Function Select */
- uint32_t debug_enable; /**< Debug Enable */
- uint32_t auto12_arg; /**< Auto Command 12 Argument */
- uint32_t newtiming_set; /**< SD New Timing Set */
- uint32_t newtiming_debug; /**< SD New Timing Debug */
- uint32_t hardware_rst; /**< Hardware Reset */
- uint32_t dmac; /**< Internal DMA Controller Control */
- uint32_t desc_base; /**< Descriptor List Base Address */
- uint32_t dmac_status; /**< Internal DMA Controller Status */
- uint32_t dmac_irq; /**< Internal DMA Controller IRQ Enable */
- uint32_t card_threshold; /**< Card Threshold Control */
- uint32_t startbit_detect; /**< eMMC DDR Start Bit Detection Control */
- uint32_t response_crc; /**< Response CRC */
- uint32_t data_crc[8]; /**< Data CRC */
- uint32_t status_crc; /**< Status CRC */
-
- /** @} */
-
-};
-
-/**
- * Allwinner SD Host Controller class-level struct.
- *
- * This struct is filled by each sunxi device specific code
- * such that the generic code can use this struct to support
- * all devices.
- */
-struct AwSdHostClass {
- /*< private >*/
- SysBusDeviceClass parent_class;
- /*< public >*/
-
- /** Maximum buffer size in bytes per DMA descriptor */
- size_t max_desc_size;
-
-};
-
-#endif /* HW_SD_ALLWINNER_SDHOST_H */
+++ /dev/null
-/*
- * Aspeed SD Host Controller
- * Eddie James <eajames@linux.ibm.com>
- *
- * Copyright (C) 2019 IBM Corp
- * SPDX-License-Identifer: GPL-2.0-or-later
- */
-
-#ifndef ASPEED_SDHCI_H
-#define ASPEED_SDHCI_H
-
-#include "hw/sd/sdhci.h"
-#include "qom/object.h"
-
-#define TYPE_ASPEED_SDHCI "aspeed.sdhci"
-OBJECT_DECLARE_SIMPLE_TYPE(AspeedSDHCIState, ASPEED_SDHCI)
-
-#define ASPEED_SDHCI_CAPABILITIES 0x01E80080
-#define ASPEED_SDHCI_NUM_SLOTS 2
-#define ASPEED_SDHCI_NUM_REGS (ASPEED_SDHCI_REG_SIZE / sizeof(uint32_t))
-#define ASPEED_SDHCI_REG_SIZE 0x100
-
-struct AspeedSDHCIState {
- SysBusDevice parent;
-
- SDHCIState slots[ASPEED_SDHCI_NUM_SLOTS];
- uint8_t num_slots;
-
- MemoryRegion iomem;
- qemu_irq irq;
-
- uint32_t regs[ASPEED_SDHCI_NUM_REGS];
-};
-
-#endif /* ASPEED_SDHCI_H */
+++ /dev/null
-/*
- * Raspberry Pi (BCM2835) SD Host Controller
- *
- * Copyright (c) 2017 Antfield SAS
- *
- * Authors:
- * Clement Deschamps <clement.deschamps@antfield.fr>
- * Luc Michel <luc.michel@antfield.fr>
- *
- * This work is licensed under the terms of the GNU GPL, version 2 or later.
- * See the COPYING file in the top-level directory.
- */
-
-#ifndef BCM2835_SDHOST_H
-#define BCM2835_SDHOST_H
-
-#include "hw/sysbus.h"
-#include "hw/sd/sd.h"
-#include "qom/object.h"
-
-#define TYPE_BCM2835_SDHOST "bcm2835-sdhost"
-OBJECT_DECLARE_SIMPLE_TYPE(BCM2835SDHostState, BCM2835_SDHOST)
-
-#define BCM2835_SDHOST_FIFO_LEN 16
-
-struct BCM2835SDHostState {
- SysBusDevice busdev;
- SDBus sdbus;
- MemoryRegion iomem;
-
- uint32_t cmd;
- uint32_t cmdarg;
- uint32_t status;
- uint32_t rsp[4];
- uint32_t config;
- uint32_t edm;
- uint32_t vdd;
- uint32_t hbct;
- uint32_t hblc;
- int32_t fifo_pos;
- int32_t fifo_len;
- uint32_t fifo[BCM2835_SDHOST_FIFO_LEN];
- uint32_t datacnt;
-
- qemu_irq irq;
-};
-
-#endif
+++ /dev/null
-/*
- * Cadence SDHCI emulation
- *
- * Copyright (c) 2020 Wind River Systems, Inc.
- *
- * Author:
- * Bin Meng <bin.meng@windriver.com>
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 or
- * (at your option) version 3 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License along
- * with this program; if not, see <http://www.gnu.org/licenses/>.
- */
-
-#ifndef CADENCE_SDHCI_H
-#define CADENCE_SDHCI_H
-
-#include "hw/sd/sdhci.h"
-
-#define CADENCE_SDHCI_REG_SIZE 0x100
-#define CADENCE_SDHCI_NUM_REGS (CADENCE_SDHCI_REG_SIZE / sizeof(uint32_t))
-
-typedef struct CadenceSDHCIState {
- SysBusDevice parent;
-
- MemoryRegion container;
- MemoryRegion iomem;
- BusState *bus;
-
- uint32_t regs[CADENCE_SDHCI_NUM_REGS];
-
- SDHCIState sdhci;
-} CadenceSDHCIState;
-
-#define TYPE_CADENCE_SDHCI "cadence.sdhci"
-#define CADENCE_SDHCI(obj) OBJECT_CHECK(CadenceSDHCIState, (obj), \
- TYPE_CADENCE_SDHCI)
-
-#endif /* CADENCE_SDHCI_H */
+++ /dev/null
-/*
- * SD Memory Card emulation. Mostly correct for MMC too.
- *
- * Copyright (c) 2006 Andrzej Zaborowski <balrog@zabor.org>
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- *
- * 1. Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in
- * the documentation and/or other materials provided with the
- * distribution.
- *
- * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS''
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
- * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
- * PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR
- * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
- * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
- * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
- * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
- * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-
-#ifndef HW_SD_H
-#define HW_SD_H
-
-#include "hw/qdev-core.h"
-#include "qom/object.h"
-
-#define OUT_OF_RANGE (1 << 31)
-#define ADDRESS_ERROR (1 << 30)
-#define BLOCK_LEN_ERROR (1 << 29)
-#define ERASE_SEQ_ERROR (1 << 28)
-#define ERASE_PARAM (1 << 27)
-#define WP_VIOLATION (1 << 26)
-#define CARD_IS_LOCKED (1 << 25)
-#define LOCK_UNLOCK_FAILED (1 << 24)
-#define COM_CRC_ERROR (1 << 23)
-#define ILLEGAL_COMMAND (1 << 22)
-#define CARD_ECC_FAILED (1 << 21)
-#define CC_ERROR (1 << 20)
-#define SD_ERROR (1 << 19)
-#define CID_CSD_OVERWRITE (1 << 16)
-#define WP_ERASE_SKIP (1 << 15)
-#define CARD_ECC_DISABLED (1 << 14)
-#define ERASE_RESET (1 << 13)
-#define CURRENT_STATE (7 << 9)
-#define READY_FOR_DATA (1 << 8)
-#define APP_CMD (1 << 5)
-#define AKE_SEQ_ERROR (1 << 3)
-
-enum SDPhySpecificationVersion {
- SD_PHY_SPECv1_10_VERS = 1,
- SD_PHY_SPECv2_00_VERS = 2,
- SD_PHY_SPECv3_01_VERS = 3,
-};
-
-typedef enum {
- SD_VOLTAGE_0_4V = 400, /* currently not supported */
- SD_VOLTAGE_1_8V = 1800,
- SD_VOLTAGE_3_0V = 3000,
- SD_VOLTAGE_3_3V = 3300,
-} sd_voltage_mv_t;
-
-typedef enum {
- UHS_NOT_SUPPORTED = 0,
- UHS_I = 1,
- UHS_II = 2, /* currently not supported */
- UHS_III = 3, /* currently not supported */
-} sd_uhs_mode_t;
-
-typedef enum {
- sd_none = -1,
- sd_bc = 0, /* broadcast -- no response */
- sd_bcr, /* broadcast with response */
- sd_ac, /* addressed -- no data transfer */
- sd_adtc, /* addressed with data transfer */
-} sd_cmd_type_t;
-
-typedef struct {
- uint8_t cmd;
- uint32_t arg;
- uint8_t crc;
-} SDRequest;
-
-
-#define TYPE_SD_CARD "sd-card"
-OBJECT_DECLARE_TYPE(SDState, SDCardClass, SD_CARD)
-
-struct SDCardClass {
- /*< private >*/
- DeviceClass parent_class;
- /*< public >*/
-
- int (*do_command)(SDState *sd, SDRequest *req, uint8_t *response);
- /**
- * Write a byte to a SD card.
- * @sd: card
- * @value: byte to write
- *
- * Write a byte on the data lines of a SD card.
- */
- void (*write_byte)(SDState *sd, uint8_t value);
- /**
- * Read a byte from a SD card.
- * @sd: card
- *
- * Read a byte from the data lines of a SD card.
- *
- * Return: byte value read
- */
- uint8_t (*read_byte)(SDState *sd);
- bool (*data_ready)(SDState *sd);
- void (*set_voltage)(SDState *sd, uint16_t millivolts);
- uint8_t (*get_dat_lines)(SDState *sd);
- bool (*get_cmd_line)(SDState *sd);
- void (*enable)(SDState *sd, bool enable);
- bool (*get_inserted)(SDState *sd);
- bool (*get_readonly)(SDState *sd);
-};
-
-#define TYPE_SD_BUS "sd-bus"
-OBJECT_DECLARE_TYPE(SDBus, SDBusClass,
- SD_BUS)
-
-struct SDBus {
- BusState qbus;
-};
-
-struct SDBusClass {
- /*< private >*/
- BusClass parent_class;
- /*< public >*/
-
- /* These methods are called by the SD device to notify the controller
- * when the card insertion or readonly status changes
- */
- void (*set_inserted)(DeviceState *dev, bool inserted);
- void (*set_readonly)(DeviceState *dev, bool readonly);
-};
-
-/* Functions to be used by qdevified callers (working via
- * an SDBus rather than directly with SDState)
- */
-void sdbus_set_voltage(SDBus *sdbus, uint16_t millivolts);
-uint8_t sdbus_get_dat_lines(SDBus *sdbus);
-bool sdbus_get_cmd_line(SDBus *sdbus);
-int sdbus_do_command(SDBus *sd, SDRequest *req, uint8_t *response);
-/**
- * Write a byte to a SD bus.
- * @sd: bus
- * @value: byte to write
- *
- * Write a byte on the data lines of a SD bus.
- */
-void sdbus_write_byte(SDBus *sd, uint8_t value);
-/**
- * Read a byte from a SD bus.
- * @sd: bus
- *
- * Read a byte from the data lines of a SD bus.
- *
- * Return: byte value read
- */
-uint8_t sdbus_read_byte(SDBus *sd);
-/**
- * Write data to a SD bus.
- * @sdbus: bus
- * @buf: data to write
- * @length: number of bytes to write
- *
- * Write multiple bytes of data on the data lines of a SD bus.
- */
-void sdbus_write_data(SDBus *sdbus, const void *buf, size_t length);
-/**
- * Read data from a SD bus.
- * @sdbus: bus
- * @buf: buffer to read data into
- * @length: number of bytes to read
- *
- * Read multiple bytes of data on the data lines of a SD bus.
- */
-void sdbus_read_data(SDBus *sdbus, void *buf, size_t length);
-bool sdbus_data_ready(SDBus *sd);
-bool sdbus_get_inserted(SDBus *sd);
-bool sdbus_get_readonly(SDBus *sd);
-/**
- * sdbus_reparent_card: Reparent an SD card from one controller to another
- * @from: controller bus to remove card from
- * @to: controller bus to move card to
- *
- * Reparent an SD card, effectively unplugging it from one controller
- * and inserting it into another. This is useful for SoCs like the
- * bcm2835 which have two SD controllers and connect a single SD card
- * to them, selected by the guest reprogramming GPIO line routing.
- */
-void sdbus_reparent_card(SDBus *from, SDBus *to);
-
-/* Functions to be used by SD devices to report back to qdevified controllers */
-void sdbus_set_inserted(SDBus *sd, bool inserted);
-void sdbus_set_readonly(SDBus *sd, bool inserted);
-
-#endif /* HW_SD_H */
+++ /dev/null
-/*
- * SD Memory Card emulation (deprecated legacy API)
- *
- * Copyright (c) 2006 Andrzej Zaborowski <balrog@zabor.org>
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- *
- * 1. Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in
- * the documentation and/or other materials provided with the
- * distribution.
- *
- * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS''
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
- * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
- * PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR
- * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
- * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
- * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
- * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
- * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-#ifndef HW_SDCARD_LEGACY_H
-#define HW_SDCARD_LEGACY_H
-
-#include "hw/sd/sd.h"
-
-/* Legacy functions to be used only by non-qdevified callers */
-SDState *sd_init(BlockBackend *blk, bool is_spi);
-int sd_do_command(SDState *card, SDRequest *request, uint8_t *response);
-void sd_write_byte(SDState *card, uint8_t value);
-uint8_t sd_read_byte(SDState *card);
-void sd_set_cb(SDState *card, qemu_irq readonly, qemu_irq insert);
-
-/* sd_enable should not be used -- it is only used on the nseries boards,
- * where it is part of a broken implementation of the MMC card slot switch
- * (there should be two card slots which are multiplexed to a single MMC
- * controller, but instead we model it with one card and controller and
- * disable the card when the second slot is selected, so it looks like the
- * second slot is always empty).
- */
-void sd_enable(SDState *card, bool enable);
-
-#endif /* HW_SDCARD_LEGACY_H */
+++ /dev/null
-/*
- * SD Association Host Standard Specification v2.0 controller emulation
- *
- * Copyright (c) 2011 Samsung Electronics Co., Ltd.
- * Mitsyanko Igor <i.mitsyanko@samsung.com>
- * Peter A.G. Crosthwaite <peter.crosthwaite@petalogix.com>
- *
- * Based on MMC controller for Samsung S5PC1xx-based board emulation
- * by Alexey Merkulov and Vladimir Monakhov.
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License as published by the
- * Free Software Foundation; either version 2 of the License, or (at your
- * option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
- * See the GNU General Public License for more details.
- *
- * You should have received a copy of the GNU _General Public License along
- * with this program; if not, see <http://www.gnu.org/licenses/>.
- */
-
-#ifndef SDHCI_H
-#define SDHCI_H
-
-#include "hw/pci/pci.h"
-#include "hw/sysbus.h"
-#include "hw/sd/sd.h"
-#include "qom/object.h"
-
-/* SD/MMC host controller state */
-struct SDHCIState {
- /*< private >*/
- union {
- PCIDevice pcidev;
- SysBusDevice busdev;
- };
-
- /*< public >*/
- SDBus sdbus;
- MemoryRegion iomem;
- AddressSpace sysbus_dma_as;
- AddressSpace *dma_as;
- MemoryRegion *dma_mr;
- const MemoryRegionOps *io_ops;
-
- QEMUTimer *insert_timer; /* timer for 'changing' sd card. */
- QEMUTimer *transfer_timer;
- qemu_irq irq;
-
- /* Registers cleared on reset */
- uint32_t sdmasysad; /* SDMA System Address register */
- uint16_t blksize; /* Host DMA Buff Boundary and Transfer BlkSize Reg */
- uint16_t blkcnt; /* Blocks count for current transfer */
- uint32_t argument; /* Command Argument Register */
- uint16_t trnmod; /* Transfer Mode Setting Register */
- uint16_t cmdreg; /* Command Register */
- uint32_t rspreg[4]; /* Response Registers 0-3 */
- uint32_t prnsts; /* Present State Register */
- uint8_t hostctl1; /* Host Control Register */
- uint8_t pwrcon; /* Power control Register */
- uint8_t blkgap; /* Block Gap Control Register */
- uint8_t wakcon; /* WakeUp Control Register */
- uint16_t clkcon; /* Clock control Register */
- uint8_t timeoutcon; /* Timeout Control Register */
- uint8_t admaerr; /* ADMA Error Status Register */
- uint16_t norintsts; /* Normal Interrupt Status Register */
- uint16_t errintsts; /* Error Interrupt Status Register */
- uint16_t norintstsen; /* Normal Interrupt Status Enable Register */
- uint16_t errintstsen; /* Error Interrupt Status Enable Register */
- uint16_t norintsigen; /* Normal Interrupt Signal Enable Register */
- uint16_t errintsigen; /* Error Interrupt Signal Enable Register */
- uint16_t acmd12errsts; /* Auto CMD12 error status register */
- uint16_t hostctl2; /* Host Control 2 */
- uint64_t admasysaddr; /* ADMA System Address Register */
- uint16_t vendor_spec; /* Vendor specific register */
-
- /* Read-only registers */
- uint64_t capareg; /* Capabilities Register */
- uint64_t maxcurr; /* Maximum Current Capabilities Register */
- uint16_t version; /* Host Controller Version Register */
-
- uint8_t *fifo_buffer; /* SD host i/o FIFO buffer */
- uint32_t buf_maxsz;
- uint16_t data_count; /* current element in FIFO buffer */
- uint8_t stopped_state;/* Current SDHC state */
- bool pending_insert_state;
- /* Buffer Data Port Register - virtual access point to R and W buffers */
- /* Software Reset Register - always reads as 0 */
- /* Force Event Auto CMD12 Error Interrupt Reg - write only */
- /* Force Event Error Interrupt Register- write only */
- /* RO Host Controller Version Register always reads as 0x2401 */
-
- /* Configurable properties */
- bool pending_insert_quirk; /* Quirk for Raspberry Pi card insert int */
- uint32_t quirks;
- uint8_t sd_spec_version;
- uint8_t uhs_mode;
- uint8_t vendor; /* For vendor specific functionality */
-};
-typedef struct SDHCIState SDHCIState;
-
-#define SDHCI_VENDOR_NONE 0
-#define SDHCI_VENDOR_IMX 1
-
-/*
- * Controller does not provide transfer-complete interrupt when not
- * busy.
- *
- * NOTE: This definition is taken out of Linux kernel and so the
- * original bit number is preserved
- */
-#define SDHCI_QUIRK_NO_BUSY_IRQ BIT(14)
-
-#define TYPE_PCI_SDHCI "sdhci-pci"
-DECLARE_INSTANCE_CHECKER(SDHCIState, PCI_SDHCI,
- TYPE_PCI_SDHCI)
-
-#define TYPE_SYSBUS_SDHCI "generic-sdhci"
-DECLARE_INSTANCE_CHECKER(SDHCIState, SYSBUS_SDHCI,
- TYPE_SYSBUS_SDHCI)
-
-#define TYPE_IMX_USDHC "imx-usdhc"
-
-#define TYPE_S3C_SDHCI "s3c-sdhci"
-
-#endif /* SDHCI_H */
+++ /dev/null
-/*
- * Semihosting Console
- *
- * Copyright (c) 2019 Linaro Ltd
- *
- * SPDX-License-Identifier: GPL-2.0-or-later
- */
-
-#ifndef SEMIHOST_CONSOLE_H
-#define SEMIHOST_CONSOLE_H
-
-#include "cpu.h"
-
-/**
- * qemu_semihosting_console_outs:
- * @env: CPUArchState
- * @s: host address of null terminated guest string
- *
- * Send a null terminated guest string to the debug console. This may
- * be the remote gdb session if a softmmu guest is currently being
- * debugged.
- *
- * Returns: number of bytes written.
- */
-int qemu_semihosting_console_outs(CPUArchState *env, target_ulong s);
-
-/**
- * qemu_semihosting_console_outc:
- * @env: CPUArchState
- * @s: host address of null terminated guest string
- *
- * Send single character from guest memory to the debug console. This
- * may be the remote gdb session if a softmmu guest is currently being
- * debugged.
- *
- * Returns: nothing
- */
-void qemu_semihosting_console_outc(CPUArchState *env, target_ulong c);
-
-/**
- * qemu_semihosting_console_inc:
- * @env: CPUArchState
- *
- * Receive single character from debug console. This may be the remote
- * gdb session if a softmmu guest is currently being debugged. As this
- * call may block if no data is available we suspend the CPU and will
- * re-execute the instruction when data is there. Therefore two
- * conditions must be met:
- * - CPUState is synchronized before calling this function
- * - pc is only updated once the character is successfully returned
- *
- * Returns: character read OR cpu_loop_exit!
- */
-target_ulong qemu_semihosting_console_inc(CPUArchState *env);
-
-/**
- * qemu_semihosting_log_out:
- * @s: pointer to string
- * @len: length of string
- *
- * Send a string to the debug output. Unlike console_out these strings
- * can't be sent to a remote gdb instance as they don't exist in guest
- * memory.
- *
- * Returns: number of bytes written
- */
-int qemu_semihosting_log_out(const char *s, int len);
-
-#endif /* SEMIHOST_CONSOLE_H */
+++ /dev/null
-/*
- * Semihosting support
- *
- * Copyright (c) 2015 Imagination Technologies
- *
- * This library is free software; you can redistribute it and/or
- * modify it under the terms of the GNU Lesser General Public
- * License as published by the Free Software Foundation; either
- * version 2.1 of the License, or (at your option) any later version.
- *
- * This library is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
- * Lesser General Public License for more details.
- *
- * You should have received a copy of the GNU Lesser General Public
- * License along with this library; if not, see <http://www.gnu.org/licenses/>.
- */
-
-#ifndef SEMIHOST_H
-#define SEMIHOST_H
-
-typedef enum SemihostingTarget {
- SEMIHOSTING_TARGET_AUTO = 0,
- SEMIHOSTING_TARGET_NATIVE,
- SEMIHOSTING_TARGET_GDB
-} SemihostingTarget;
-
-#ifdef CONFIG_USER_ONLY
-static inline bool semihosting_enabled(void)
-{
- return true;
-}
-
-static inline SemihostingTarget semihosting_get_target(void)
-{
- return SEMIHOSTING_TARGET_AUTO;
-}
-
-static inline const char *semihosting_get_arg(int i)
-{
- return NULL;
-}
-
-static inline int semihosting_get_argc(void)
-{
- return 0;
-}
-
-static inline const char *semihosting_get_cmdline(void)
-{
- return NULL;
-}
-
-static inline Chardev *semihosting_get_chardev(void)
-{
- return NULL;
-}
-static inline void qemu_semihosting_console_init(void)
-{
-}
-#else /* !CONFIG_USER_ONLY */
-bool semihosting_enabled(void);
-SemihostingTarget semihosting_get_target(void);
-const char *semihosting_get_arg(int i);
-int semihosting_get_argc(void);
-const char *semihosting_get_cmdline(void);
-void semihosting_arg_fallback(const char *file, const char *cmd);
-Chardev *semihosting_get_chardev(void);
-/* for vl.c hooks */
-void qemu_semihosting_enable(void);
-int qemu_semihosting_config_options(const char *opt);
-void qemu_semihosting_connect_chardevs(void);
-void qemu_semihosting_console_init(void);
-#endif /* CONFIG_USER_ONLY */
-
-#endif /* SEMIHOST_H */
+++ /dev/null
-#ifndef QEMU_SH_H
-#define QEMU_SH_H
-/* Definitions for SH board emulation. */
-
-#include "hw/sh4/sh_intc.h"
-#include "target/sh4/cpu-qom.h"
-
-#define A7ADDR(x) ((x) & 0x1fffffff)
-#define P4ADDR(x) ((x) | 0xe0000000)
-
-/* sh7750.c */
-struct SH7750State;
-
-struct SH7750State *sh7750_init(SuperHCPU *cpu, MemoryRegion *sysmem);
-
-typedef struct {
- /* The callback will be triggered if any of the designated lines change */
- uint16_t portamask_trigger;
- uint16_t portbmask_trigger;
- /* Return 0 if no action was taken */
- int (*port_change_cb) (uint16_t porta, uint16_t portb,
- uint16_t * periph_pdtra,
- uint16_t * periph_portdira,
- uint16_t * periph_pdtrb,
- uint16_t * periph_portdirb);
-} sh7750_io_device;
-
-int sh7750_register_io_device(struct SH7750State *s,
- sh7750_io_device * device);
-
-/* sh_serial.c */
-#define SH_SERIAL_FEAT_SCIF (1 << 0)
-void sh_serial_init(MemoryRegion *sysmem,
- hwaddr base, int feat,
- uint32_t freq, Chardev *chr,
- qemu_irq eri_source,
- qemu_irq rxi_source,
- qemu_irq txi_source,
- qemu_irq tei_source,
- qemu_irq bri_source);
-
-/* sh7750.c */
-qemu_irq sh7750_irl(struct SH7750State *s);
-
-/* tc58128.c */
-int tc58128_init(struct SH7750State *s, const char *zone1, const char *zone2);
-
-#endif
+++ /dev/null
-#ifndef SH_INTC_H
-#define SH_INTC_H
-
-#include "exec/memory.h"
-
-typedef unsigned char intc_enum;
-
-struct intc_vect {
- intc_enum enum_id;
- unsigned short vect;
-};
-
-#define INTC_VECT(enum_id, vect) { enum_id, vect }
-
-struct intc_group {
- intc_enum enum_id;
- intc_enum enum_ids[32];
-};
-
-#define INTC_GROUP(enum_id, ...) { enum_id, { __VA_ARGS__ } }
-
-struct intc_mask_reg {
- unsigned long set_reg, clr_reg, reg_width;
- intc_enum enum_ids[32];
- unsigned long value;
-};
-
-struct intc_prio_reg {
- unsigned long set_reg, clr_reg, reg_width, field_width;
- intc_enum enum_ids[16];
- unsigned long value;
-};
-
-#define _INTC_ARRAY(a) a, ARRAY_SIZE(a)
-
-struct intc_source {
- unsigned short vect;
- intc_enum next_enum_id;
-
- int asserted; /* emulates the interrupt signal line from device to intc */
- int enable_count;
- int enable_max;
- int pending; /* emulates the result of signal and masking */
- struct intc_desc *parent;
-};
-
-struct intc_desc {
- MemoryRegion iomem;
- MemoryRegion *iomem_aliases;
- qemu_irq *irqs;
- struct intc_source *sources;
- int nr_sources;
- struct intc_mask_reg *mask_regs;
- int nr_mask_regs;
- struct intc_prio_reg *prio_regs;
- int nr_prio_regs;
- int pending; /* number of interrupt sources that has pending set */
-};
-
-int sh_intc_get_pending_vector(struct intc_desc *desc, int imask);
-struct intc_source *sh_intc_source(struct intc_desc *desc, intc_enum id);
-void sh_intc_toggle_source(struct intc_source *source,
- int enable_adj, int assert_adj);
-
-void sh_intc_register_sources(struct intc_desc *desc,
- struct intc_vect *vectors,
- int nr_vectors,
- struct intc_group *groups,
- int nr_groups);
-
-int sh_intc_init(MemoryRegion *sysmem,
- struct intc_desc *desc,
- int nr_sources,
- struct intc_mask_reg *mask_regs,
- int nr_mask_regs,
- struct intc_prio_reg *prio_regs,
- int nr_prio_regs);
-
-void sh_intc_set_irl(void *opaque, int n, int level);
-
-#endif /* SH_INTC_H */
+++ /dev/null
-/*
- * QEMU PIIX South Bridge Emulation
- *
- * Copyright (c) 2006 Fabrice Bellard
- * Copyright (c) 2018 Hervé Poussineau
- *
- * This work is licensed under the terms of the GNU GPL, version 2 or later.
- * See the COPYING file in the top-level directory.
- *
- */
-
-#ifndef HW_SOUTHBRIDGE_PIIX_H
-#define HW_SOUTHBRIDGE_PIIX_H
-
-#include "hw/pci/pci.h"
-#include "qom/object.h"
-
-#define TYPE_PIIX4_PM "PIIX4_PM"
-
-I2CBus *piix4_pm_init(PCIBus *bus, int devfn, uint32_t smb_io_base,
- qemu_irq sci_irq, qemu_irq smi_irq,
- int smm_enabled, DeviceState **piix4_pm);
-
-/* PIRQRC[A:D]: PIRQx Route Control Registers */
-#define PIIX_PIRQCA 0x60
-#define PIIX_PIRQCB 0x61
-#define PIIX_PIRQCC 0x62
-#define PIIX_PIRQCD 0x63
-
-/*
- * Reset Control Register: PCI-accessible ISA-Compatible Register at address
- * 0xcf9, provided by the PCI/ISA bridge (PIIX3 PCI function 0, 8086:7000).
- */
-#define PIIX_RCR_IOPORT 0xcf9
-
-#define PIIX_NUM_PIC_IRQS 16 /* i8259 * 2 */
-#define PIIX_NUM_PIRQS 4ULL /* PIRQ[A-D] */
-
-struct PIIXState {
- PCIDevice dev;
-
- /*
- * bitmap to track pic levels.
- * The pic level is the logical OR of all the PCI irqs mapped to it
- * So one PIC level is tracked by PIIX_NUM_PIRQS bits.
- *
- * PIRQ is mapped to PIC pins, we track it by
- * PIIX_NUM_PIRQS * PIIX_NUM_PIC_IRQS = 64 bits with
- * pic_irq * PIIX_NUM_PIRQS + pirq
- */
-#if PIIX_NUM_PIC_IRQS * PIIX_NUM_PIRQS > 64
-#error "unable to encode pic state in 64bit in pic_levels."
-#endif
- uint64_t pic_levels;
-
- qemu_irq *pic;
-
- /* This member isn't used. Just for save/load compatibility */
- int32_t pci_irq_levels_vmstate[PIIX_NUM_PIRQS];
-
- /* Reset Control Register contents */
- uint8_t rcr;
-
- /* IO memory region for Reset Control Register (PIIX_RCR_IOPORT) */
- MemoryRegion rcr_mem;
-};
-typedef struct PIIXState PIIX3State;
-
-#define TYPE_PIIX3_PCI_DEVICE "pci-piix3"
-DECLARE_INSTANCE_CHECKER(PIIX3State, PIIX3_PCI_DEVICE,
- TYPE_PIIX3_PCI_DEVICE)
-
-extern PCIDevice *piix4_dev;
-
-PIIX3State *piix3_create(PCIBus *pci_bus, ISABus **isa_bus);
-
-DeviceState *piix4_create(PCIBus *pci_bus, ISABus **isa_bus, I2CBus **smbus);
-
-#endif
+++ /dev/null
-/*
- * QEMU GRLIB Components
- *
- * Copyright (c) 2010-2019 AdaCore
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
- * furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
- * THE SOFTWARE.
- */
-
-#ifndef GRLIB_H
-#define GRLIB_H
-
-#include "hw/sysbus.h"
-
-/* Emulation of GrLib device is base on the GRLIB IP Core User's Manual:
- * http://www.gaisler.com/products/grlib/grip.pdf
- */
-
-/* IRQMP */
-#define TYPE_GRLIB_IRQMP "grlib,irqmp"
-
-typedef void (*set_pil_in_fn) (void *opaque, uint32_t pil_in);
-
-void grlib_irqmp_set_irq(void *opaque, int irq, int level);
-
-void grlib_irqmp_ack(DeviceState *dev, int intno);
-
-/* GPTimer */
-#define TYPE_GRLIB_GPTIMER "grlib,gptimer"
-
-/* APB UART */
-#define TYPE_GRLIB_APB_UART "grlib,apbuart"
-
-#endif /* GRLIB_H */
+++ /dev/null
-#ifndef SPARC32_DMA_H
-#define SPARC32_DMA_H
-
-#include "hw/sysbus.h"
-#include "hw/scsi/esp.h"
-#include "hw/net/lance.h"
-#include "qom/object.h"
-
-#define DMA_REGS 4
-
-#define TYPE_SPARC32_DMA_DEVICE "sparc32-dma-device"
-OBJECT_DECLARE_SIMPLE_TYPE(DMADeviceState, SPARC32_DMA_DEVICE)
-
-
-struct DMADeviceState {
- SysBusDevice parent_obj;
-
- MemoryRegion iomem;
- uint32_t dmaregs[DMA_REGS];
- qemu_irq irq;
- void *iommu;
- qemu_irq gpio[2];
-};
-
-#define TYPE_SPARC32_ESPDMA_DEVICE "sparc32-espdma"
-OBJECT_DECLARE_SIMPLE_TYPE(ESPDMADeviceState, SPARC32_ESPDMA_DEVICE)
-
-struct ESPDMADeviceState {
- DMADeviceState parent_obj;
-
- SysBusESPState esp;
-};
-
-#define TYPE_SPARC32_LEDMA_DEVICE "sparc32-ledma"
-OBJECT_DECLARE_SIMPLE_TYPE(LEDMADeviceState, SPARC32_LEDMA_DEVICE)
-
-struct LEDMADeviceState {
- DMADeviceState parent_obj;
-
- SysBusPCNetState lance;
-};
-
-#define TYPE_SPARC32_DMA "sparc32-dma"
-OBJECT_DECLARE_SIMPLE_TYPE(SPARC32DMAState, SPARC32_DMA)
-
-struct SPARC32DMAState {
- SysBusDevice parent_obj;
-
- MemoryRegion dmamem;
- MemoryRegion ledma_alias;
- ESPDMADeviceState espdma;
- LEDMADeviceState ledma;
-};
-
-/* sparc32_dma.c */
-void ledma_memory_read(void *opaque, hwaddr addr,
- uint8_t *buf, int len, int do_bswap);
-void ledma_memory_write(void *opaque, hwaddr addr,
- uint8_t *buf, int len, int do_bswap);
-void espdma_memory_read(void *opaque, uint8_t *buf, int len);
-void espdma_memory_write(void *opaque, uint8_t *buf, int len);
-
-#endif
+++ /dev/null
-#ifndef HW_SPARC_SPARC64_H
-#define HW_SPARC_SPARC64_H
-
-#include "target/sparc/cpu-qom.h"
-
-#define IVEC_MAX 0x40
-
-SPARCCPU *sparc64_cpu_devinit(const char *cpu_type, uint64_t prom_addr);
-
-void sparc64_cpu_set_ivec_irq(void *opaque, int irq, int level);
-
-#endif
+++ /dev/null
-/*
- * QEMU Sun4m iommu emulation
- *
- * Copyright (c) 2003-2005 Fabrice Bellard
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
- * furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
- * THE SOFTWARE.
- */
-
-#ifndef SUN4M_IOMMU_H
-#define SUN4M_IOMMU_H
-
-#include "hw/sysbus.h"
-#include "qom/object.h"
-
-#define IOMMU_NREGS (4 * 4096 / 4)
-
-struct IOMMUState {
- SysBusDevice parent_obj;
-
- AddressSpace iommu_as;
- IOMMUMemoryRegion iommu;
-
- MemoryRegion iomem;
- uint32_t regs[IOMMU_NREGS];
- hwaddr iostart;
- qemu_irq irq;
- uint32_t version;
-};
-typedef struct IOMMUState IOMMUState;
-
-#define TYPE_SUN4M_IOMMU "sun4m-iommu"
-DECLARE_INSTANCE_CHECKER(IOMMUState, SUN4M_IOMMU,
- TYPE_SUN4M_IOMMU)
-
-#define TYPE_SUN4M_IOMMU_MEMORY_REGION "sun4m-iommu-memory-region"
-
-#endif
+++ /dev/null
-/*
- * QEMU sun4u IOMMU emulation
- *
- * Copyright (c) 2006 Fabrice Bellard
- * Copyright (c) 2012,2013 Artyom Tarasenko
- * Copyright (c) 2017 Mark Cave-Ayland
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
- * furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
- * THE SOFTWARE.
- */
-
-#ifndef SUN4U_IOMMU_H
-#define SUN4U_IOMMU_H
-
-#include "hw/sysbus.h"
-#include "qom/object.h"
-
-#define IOMMU_NREGS 3
-
-struct IOMMUState {
- SysBusDevice parent_obj;
-
- AddressSpace iommu_as;
- IOMMUMemoryRegion iommu;
-
- MemoryRegion iomem;
- uint64_t regs[IOMMU_NREGS];
-};
-typedef struct IOMMUState IOMMUState;
-
-#define TYPE_SUN4U_IOMMU "sun4u-iommu"
-DECLARE_INSTANCE_CHECKER(IOMMUState, SUN4U_IOMMU,
- TYPE_SUN4U_IOMMU)
-
-#define TYPE_SUN4U_IOMMU_MEMORY_REGION "sun4u-iommu-memory-region"
-
-#endif
+++ /dev/null
-/*
- * ASPEED AST2400 SMC Controller (SPI Flash Only)
- *
- * Copyright (C) 2016 IBM Corp.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
- * furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
- * THE SOFTWARE.
- */
-
-#ifndef ASPEED_SMC_H
-#define ASPEED_SMC_H
-
-#include "hw/ssi/ssi.h"
-#include "hw/sysbus.h"
-#include "qom/object.h"
-
-typedef struct AspeedSegments {
- hwaddr addr;
- uint32_t size;
-} AspeedSegments;
-
-struct AspeedSMCState;
-typedef struct AspeedSMCController {
- const char *name;
- uint8_t r_conf;
- uint8_t r_ce_ctrl;
- uint8_t r_ctrl0;
- uint8_t r_timings;
- uint8_t nregs_timings;
- uint8_t conf_enable_w0;
- uint8_t max_slaves;
- const AspeedSegments *segments;
- hwaddr flash_window_base;
- uint32_t flash_window_size;
- bool has_dma;
- hwaddr dma_flash_mask;
- hwaddr dma_dram_mask;
- uint32_t nregs;
- uint32_t (*segment_to_reg)(const struct AspeedSMCState *s,
- const AspeedSegments *seg);
- void (*reg_to_segment)(const struct AspeedSMCState *s, uint32_t reg,
- AspeedSegments *seg);
-} AspeedSMCController;
-
-typedef struct AspeedSMCFlash {
- struct AspeedSMCState *controller;
-
- uint8_t id;
- uint32_t size;
-
- MemoryRegion mmio;
- DeviceState *flash;
-} AspeedSMCFlash;
-
-#define TYPE_ASPEED_SMC "aspeed.smc"
-OBJECT_DECLARE_TYPE(AspeedSMCState, AspeedSMCClass, ASPEED_SMC)
-
-struct AspeedSMCClass {
- SysBusDevice parent_obj;
- const AspeedSMCController *ctrl;
-};
-
-#define ASPEED_SMC_R_MAX (0x100 / 4)
-
-struct AspeedSMCState {
- SysBusDevice parent_obj;
-
- const AspeedSMCController *ctrl;
-
- MemoryRegion mmio;
- MemoryRegion mmio_flash;
-
- qemu_irq irq;
- int irqline;
-
- uint32_t num_cs;
- qemu_irq *cs_lines;
- bool inject_failure;
-
- SSIBus *spi;
-
- uint32_t regs[ASPEED_SMC_R_MAX];
-
- /* depends on the controller type */
- uint8_t r_conf;
- uint8_t r_ce_ctrl;
- uint8_t r_ctrl0;
- uint8_t r_timings;
- uint8_t conf_enable_w0;
-
- /* for DMA support */
- uint64_t sdram_base;
-
- AddressSpace flash_as;
- MemoryRegion *dram_mr;
- AddressSpace dram_as;
-
- AspeedSMCFlash *flashes;
-
- uint8_t snoop_index;
- uint8_t snoop_dummies;
-};
-
-#endif /* ASPEED_SMC_H */
+++ /dev/null
-/*
- * IMX SPI Controller
- *
- * Copyright 2016 Jean-Christophe Dubois <jcd@tribudubois.net>
- *
- * This work is licensed under the terms of the GNU GPL, version 2 or later.
- * See the COPYING file in the top-level directory.
- */
-
-#ifndef IMX_SPI_H
-#define IMX_SPI_H
-
-#include "hw/sysbus.h"
-#include "hw/ssi/ssi.h"
-#include "qemu/bitops.h"
-#include "qemu/fifo32.h"
-#include "qom/object.h"
-
-#define ECSPI_FIFO_SIZE 64
-
-#define ECSPI_RXDATA 0
-#define ECSPI_TXDATA 1
-#define ECSPI_CONREG 2
-#define ECSPI_CONFIGREG 3
-#define ECSPI_INTREG 4
-#define ECSPI_DMAREG 5
-#define ECSPI_STATREG 6
-#define ECSPI_PERIODREG 7
-#define ECSPI_TESTREG 8
-#define ECSPI_MSGDATA 16
-#define ECSPI_MAX 17
-
-/* ECSPI_CONREG */
-#define ECSPI_CONREG_EN (1 << 0)
-#define ECSPI_CONREG_HT (1 << 1)
-#define ECSPI_CONREG_XCH (1 << 2)
-#define ECSPI_CONREG_SMC (1 << 3)
-#define ECSPI_CONREG_CHANNEL_MODE_SHIFT 4
-#define ECSPI_CONREG_CHANNEL_MODE_LENGTH 4
-#define ECSPI_CONREG_DRCTL_SHIFT 16
-#define ECSPI_CONREG_DRCTL_LENGTH 2
-#define ECSPI_CONREG_CHANNEL_SELECT_SHIFT 18
-#define ECSPI_CONREG_CHANNEL_SELECT_LENGTH 2
-#define ECSPI_CONREG_BURST_LENGTH_SHIFT 20
-#define ECSPI_CONREG_BURST_LENGTH_LENGTH 12
-
-/* ECSPI_CONFIGREG */
-#define ECSPI_CONFIGREG_SS_CTL_SHIFT 8
-#define ECSPI_CONFIGREG_SS_CTL_LENGTH 4
-
-/* ECSPI_INTREG */
-#define ECSPI_INTREG_TEEN (1 << 0)
-#define ECSPI_INTREG_TDREN (1 << 1)
-#define ECSPI_INTREG_TFEN (1 << 2)
-#define ECSPI_INTREG_RREN (1 << 3)
-#define ECSPI_INTREG_RDREN (1 << 4)
-#define ECSPI_INTREG_RFEN (1 << 5)
-#define ECSPI_INTREG_ROEN (1 << 6)
-#define ECSPI_INTREG_TCEN (1 << 7)
-
-/* ECSPI_DMAREG */
-#define ECSPI_DMAREG_RXTDEN (1 << 31)
-#define ECSPI_DMAREG_RXDEN (1 << 23)
-#define ECSPI_DMAREG_TEDEN (1 << 7)
-#define ECSPI_DMAREG_RX_THRESHOLD_SHIFT 16
-#define ECSPI_DMAREG_RX_THRESHOLD_LENGTH 6
-
-/* ECSPI_STATREG */
-#define ECSPI_STATREG_TE (1 << 0)
-#define ECSPI_STATREG_TDR (1 << 1)
-#define ECSPI_STATREG_TF (1 << 2)
-#define ECSPI_STATREG_RR (1 << 3)
-#define ECSPI_STATREG_RDR (1 << 4)
-#define ECSPI_STATREG_RF (1 << 5)
-#define ECSPI_STATREG_RO (1 << 6)
-#define ECSPI_STATREG_TC (1 << 7)
-
-#define EXTRACT(value, name) extract32(value, name##_SHIFT, name##_LENGTH)
-
-#define TYPE_IMX_SPI "imx.spi"
-OBJECT_DECLARE_SIMPLE_TYPE(IMXSPIState, IMX_SPI)
-
-struct IMXSPIState {
- /* <private> */
- SysBusDevice parent_obj;
-
- /* <public> */
- MemoryRegion iomem;
-
- qemu_irq irq;
-
- qemu_irq cs_lines[4];
-
- SSIBus *bus;
-
- uint32_t regs[ECSPI_MAX];
-
- Fifo32 rx_fifo;
- Fifo32 tx_fifo;
-
- int16_t burst_length;
-};
-
-#endif /* IMX_SPI_H */
+++ /dev/null
-/*
- * Microsemi SmartFusion2 SPI
- *
- * Copyright (c) 2017 Subbaraya Sundeep <sundeep.lkml@gmail.com>
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
- * furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
- * THE SOFTWARE.
- */
-
-#ifndef HW_MSS_SPI_H
-#define HW_MSS_SPI_H
-
-#include "hw/sysbus.h"
-#include "hw/ssi/ssi.h"
-#include "qemu/fifo32.h"
-#include "qom/object.h"
-
-#define TYPE_MSS_SPI "mss-spi"
-OBJECT_DECLARE_SIMPLE_TYPE(MSSSpiState, MSS_SPI)
-
-#define R_SPI_MAX 16
-
-struct MSSSpiState {
- SysBusDevice parent_obj;
-
- MemoryRegion mmio;
-
- qemu_irq irq;
-
- qemu_irq cs_line;
-
- SSIBus *spi;
-
- Fifo32 rx_fifo;
- Fifo32 tx_fifo;
-
- int fifo_depth;
- uint32_t frame_count;
- bool enabled;
-
- uint32_t regs[R_SPI_MAX];
-};
-
-#endif /* HW_MSS_SPI_H */
+++ /dev/null
-/*
- * Nuvoton NPCM7xx Flash Interface Unit (FIU)
- *
- * Copyright 2020 Google LLC
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License as published by the
- * Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
- * for more details.
- */
-#ifndef NPCM7XX_FIU_H
-#define NPCM7XX_FIU_H
-
-#include "hw/ssi/ssi.h"
-#include "hw/sysbus.h"
-
-/*
- * Number of registers in our device state structure. Don't change this without
- * incrementing the version_id in the vmstate.
- */
-#define NPCM7XX_FIU_NR_REGS (0x7c / sizeof(uint32_t))
-
-typedef struct NPCM7xxFIUState NPCM7xxFIUState;
-
-/**
- * struct NPCM7xxFIUFlash - Per-chipselect flash controller state.
- * @direct_access: Memory region for direct flash access.
- * @fiu: Pointer to flash controller shared state.
- */
-typedef struct NPCM7xxFIUFlash {
- MemoryRegion direct_access;
- NPCM7xxFIUState *fiu;
-} NPCM7xxFIUFlash;
-
-/**
- * NPCM7xxFIUState - Device state for one Flash Interface Unit.
- * @parent: System bus device.
- * @mmio: Memory region for register access.
- * @cs_count: Number of flash chips that may be connected to this module.
- * @active_cs: Currently active chip select, or -1 if no chip is selected.
- * @cs_lines: GPIO lines that may be wired to flash chips.
- * @flash: Array of @cs_count per-flash-chip state objects.
- * @spi: The SPI bus mastered by this controller.
- * @regs: Register contents.
- *
- * Each FIU has a shared bank of registers, and controls up to four chip
- * selects. Each chip select has a dedicated memory region which may be used to
- * read and write the flash connected to that chip select as if it were memory.
- */
-struct NPCM7xxFIUState {
- SysBusDevice parent;
-
- MemoryRegion mmio;
-
- int32_t cs_count;
- int32_t active_cs;
- qemu_irq *cs_lines;
- NPCM7xxFIUFlash *flash;
-
- SSIBus *spi;
-
- uint32_t regs[NPCM7XX_FIU_NR_REGS];
-};
-
-#define TYPE_NPCM7XX_FIU "npcm7xx-fiu"
-#define NPCM7XX_FIU(obj) OBJECT_CHECK(NPCM7xxFIUState, (obj), TYPE_NPCM7XX_FIU)
-
-#endif /* NPCM7XX_FIU_H */
+++ /dev/null
-/*
- * ARM PrimeCell PL022 Synchronous Serial Port
- *
- * Copyright (c) 2007 CodeSourcery.
- * Written by Paul Brook
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 or
- * (at your option) any later version.
- */
-
-/* This is a model of the Arm PrimeCell PL022 synchronous serial port.
- * The PL022 TRM is:
- * http://infocenter.arm.com/help/topic/com.arm.doc.ddi0194h/DDI0194H_ssp_pl022_trm.pdf
- *
- * QEMU interface:
- * + sysbus IRQ: SSPINTR combined interrupt line
- * + sysbus MMIO region 0: MemoryRegion for the device's registers
- */
-
-#ifndef HW_SSI_PL022_H
-#define HW_SSI_PL022_H
-
-#include "hw/sysbus.h"
-#include "qom/object.h"
-
-#define TYPE_PL022 "pl022"
-OBJECT_DECLARE_SIMPLE_TYPE(PL022State, PL022)
-
-struct PL022State {
- SysBusDevice parent_obj;
-
- MemoryRegion iomem;
- uint32_t cr0;
- uint32_t cr1;
- uint32_t bitmask;
- uint32_t sr;
- uint32_t cpsr;
- uint32_t is;
- uint32_t im;
- /* The FIFO head points to the next empty entry. */
- int tx_fifo_head;
- int rx_fifo_head;
- int tx_fifo_len;
- int rx_fifo_len;
- uint16_t tx_fifo[8];
- uint16_t rx_fifo[8];
- qemu_irq irq;
- SSIBus *ssi;
-};
-
-#endif
+++ /dev/null
-/* QEMU Synchronous Serial Interface support. */
-
-/* In principle SSI is a point-point interface. As such the qemu
- implementation has a single slave device on a "bus".
- However it is fairly common for boards to have multiple slaves
- connected to a single master, and select devices with an external
- chip select. This is implemented in qemu by having an explicit mux device.
- It is assumed that master and slave are both using the same transfer width.
- */
-
-#ifndef QEMU_SSI_H
-#define QEMU_SSI_H
-
-#include "hw/qdev-core.h"
-#include "qom/object.h"
-
-typedef enum SSICSMode SSICSMode;
-
-#define TYPE_SSI_SLAVE "ssi-slave"
-OBJECT_DECLARE_TYPE(SSISlave, SSISlaveClass,
- SSI_SLAVE)
-
-#define SSI_GPIO_CS "ssi-gpio-cs"
-
-enum SSICSMode {
- SSI_CS_NONE = 0,
- SSI_CS_LOW,
- SSI_CS_HIGH,
-};
-
-/* Slave devices. */
-struct SSISlaveClass {
- DeviceClass parent_class;
-
- void (*realize)(SSISlave *dev, Error **errp);
-
- /* if you have standard or no CS behaviour, just override transfer.
- * This is called when the device cs is active (true by default).
- */
- uint32_t (*transfer)(SSISlave *dev, uint32_t val);
- /* called when the CS line changes. Optional, devices only need to implement
- * this if they have side effects associated with the cs line (beyond
- * tristating the txrx lines).
- */
- int (*set_cs)(SSISlave *dev, bool select);
- /* define whether or not CS exists and is active low/high */
- SSICSMode cs_polarity;
-
- /* if you have non-standard CS behaviour override this to take control
- * of the CS behaviour at the device level. transfer, set_cs, and
- * cs_polarity are unused if this is overwritten. Transfer_raw will
- * always be called for the device for every txrx access to the parent bus
- */
- uint32_t (*transfer_raw)(SSISlave *dev, uint32_t val);
-};
-
-struct SSISlave {
- DeviceState parent_obj;
-
- /* Chip select state */
- bool cs;
-};
-
-extern const VMStateDescription vmstate_ssi_slave;
-
-#define VMSTATE_SSI_SLAVE(_field, _state) { \
- .name = (stringify(_field)), \
- .size = sizeof(SSISlave), \
- .vmsd = &vmstate_ssi_slave, \
- .flags = VMS_STRUCT, \
- .offset = vmstate_offset_value(_state, _field, SSISlave), \
-}
-
-DeviceState *ssi_create_slave(SSIBus *bus, const char *name);
-/**
- * ssi_realize_and_unref: realize and unref an SSI slave device
- * @dev: SSI slave device to realize
- * @bus: SSI bus to put it on
- * @errp: error pointer
- *
- * Call 'realize' on @dev, put it on the specified @bus, and drop the
- * reference to it. Errors are reported via @errp and by returning
- * false.
- *
- * This function is useful if you have created @dev via qdev_new()
- * (which takes a reference to the device it returns to you), so that
- * you can set properties on it before realizing it. If you don't need
- * to set properties then ssi_create_slave() is probably better (as it
- * does the create, init and realize in one step).
- *
- * If you are embedding the SSI slave into another QOM device and
- * initialized it via some variant on object_initialize_child() then
- * do not use this function, because that family of functions arrange
- * for the only reference to the child device to be held by the parent
- * via the child<> property, and so the reference-count-drop done here
- * would be incorrect. (Instead you would want ssi_realize(), which
- * doesn't currently exist but would be trivial to create if we had
- * any code that wanted it.)
- */
-bool ssi_realize_and_unref(DeviceState *dev, SSIBus *bus, Error **errp);
-
-/* Master interface. */
-SSIBus *ssi_create_bus(DeviceState *parent, const char *name);
-
-uint32_t ssi_transfer(SSIBus *bus, uint32_t val);
-
-#endif
+++ /dev/null
-/*
- * STM32F2XX SPI
- *
- * Copyright (c) 2014 Alistair Francis <alistair@alistair23.me>
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
- * furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
- * THE SOFTWARE.
- */
-
-#ifndef HW_STM32F2XX_SPI_H
-#define HW_STM32F2XX_SPI_H
-
-#include "hw/sysbus.h"
-#include "hw/ssi/ssi.h"
-#include "qom/object.h"
-
-#define STM_SPI_CR1 0x00
-#define STM_SPI_CR2 0x04
-#define STM_SPI_SR 0x08
-#define STM_SPI_DR 0x0C
-#define STM_SPI_CRCPR 0x10
-#define STM_SPI_RXCRCR 0x14
-#define STM_SPI_TXCRCR 0x18
-#define STM_SPI_I2SCFGR 0x1C
-#define STM_SPI_I2SPR 0x20
-
-#define STM_SPI_CR1_SPE (1 << 6)
-#define STM_SPI_CR1_MSTR (1 << 2)
-
-#define STM_SPI_SR_RXNE 1
-
-#define TYPE_STM32F2XX_SPI "stm32f2xx-spi"
-OBJECT_DECLARE_SIMPLE_TYPE(STM32F2XXSPIState, STM32F2XX_SPI)
-
-struct STM32F2XXSPIState {
- /* <private> */
- SysBusDevice parent_obj;
-
- /* <public> */
- MemoryRegion mmio;
-
- uint32_t spi_cr1;
- uint32_t spi_cr2;
- uint32_t spi_sr;
- uint32_t spi_dr;
- uint32_t spi_crcpr;
- uint32_t spi_rxcrcr;
- uint32_t spi_txcrcr;
- uint32_t spi_i2scfgr;
- uint32_t spi_i2spr;
-
- qemu_irq irq;
- SSIBus *ssi;
-};
-
-#endif /* HW_STM32F2XX_SPI_H */
+++ /dev/null
-/*
- * Header file for the Xilinx Zynq SPI controller
- *
- * Copyright (C) 2015 Xilinx Inc
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
- * furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
- * THE SOFTWARE.
- */
-
-#ifndef XILINX_SPIPS_H
-#define XILINX_SPIPS_H
-
-#include "hw/ssi/ssi.h"
-#include "qemu/fifo32.h"
-#include "hw/stream.h"
-#include "hw/sysbus.h"
-#include "qom/object.h"
-
-typedef struct XilinxSPIPS XilinxSPIPS;
-
-#define XLNX_SPIPS_R_MAX (0x100 / 4)
-#define XLNX_ZYNQMP_SPIPS_R_MAX (0x830 / 4)
-
-/* Bite off 4k chunks at a time */
-#define LQSPI_CACHE_SIZE 1024
-
-#define QSPI_DMA_MAX_BURST_SIZE 2048
-
-typedef enum {
- READ = 0x3, READ_4 = 0x13,
- FAST_READ = 0xb, FAST_READ_4 = 0x0c,
- DOR = 0x3b, DOR_4 = 0x3c,
- QOR = 0x6b, QOR_4 = 0x6c,
- DIOR = 0xbb, DIOR_4 = 0xbc,
- QIOR = 0xeb, QIOR_4 = 0xec,
-
- PP = 0x2, PP_4 = 0x12,
- DPP = 0xa2,
- QPP = 0x32, QPP_4 = 0x34,
-} FlashCMD;
-
-struct XilinxSPIPS {
- SysBusDevice parent_obj;
-
- MemoryRegion iomem;
- MemoryRegion mmlqspi;
-
- qemu_irq irq;
- int irqline;
-
- uint8_t num_cs;
- uint8_t num_busses;
-
- uint8_t snoop_state;
- int cmd_dummies;
- uint8_t link_state;
- uint8_t link_state_next;
- uint8_t link_state_next_when;
- qemu_irq *cs_lines;
- bool *cs_lines_state;
- SSIBus **spi;
-
- Fifo8 rx_fifo;
- Fifo8 tx_fifo;
-
- uint8_t num_txrx_bytes;
- uint32_t rx_discard;
-
- uint32_t regs[XLNX_SPIPS_R_MAX];
-
- bool man_start_com;
-};
-
-struct XilinxQSPIPS {
- XilinxSPIPS parent_obj;
-
- uint8_t lqspi_buf[LQSPI_CACHE_SIZE];
- hwaddr lqspi_cached_addr;
- Error *migration_blocker;
- bool mmio_execution_enabled;
-};
-typedef struct XilinxQSPIPS XilinxQSPIPS;
-
-struct XlnxZynqMPQSPIPS {
- XilinxQSPIPS parent_obj;
-
- StreamSlave *dma;
- int gqspi_irqline;
-
- uint32_t regs[XLNX_ZYNQMP_SPIPS_R_MAX];
-
- /* GQSPI has seperate tx/rx fifos */
- Fifo8 rx_fifo_g;
- Fifo8 tx_fifo_g;
- Fifo32 fifo_g;
- /*
- * At the end of each generic command, misaligned extra bytes are discard
- * or padded to tx and rx respectively to round it out (and avoid need for
- * individual byte access. Since we use byte fifos, keep track of the
- * alignment WRT to word access.
- */
- uint8_t rx_fifo_g_align;
- uint8_t tx_fifo_g_align;
- bool man_start_com_g;
- uint32_t dma_burst_size;
- uint8_t dma_buf[QSPI_DMA_MAX_BURST_SIZE];
-};
-
-struct XilinxSPIPSClass {
- SysBusDeviceClass parent_class;
-
- const MemoryRegionOps *reg_ops;
-
- uint32_t rx_fifo_size;
- uint32_t tx_fifo_size;
-};
-
-#define TYPE_XILINX_SPIPS "xlnx.ps7-spi"
-#define TYPE_XILINX_QSPIPS "xlnx.ps7-qspi"
-#define TYPE_XLNX_ZYNQMP_QSPIPS "xlnx.usmp-gqspi"
-
-OBJECT_DECLARE_TYPE(XilinxSPIPS, XilinxSPIPSClass, XILINX_SPIPS)
-
-OBJECT_DECLARE_SIMPLE_TYPE(XilinxQSPIPS, XILINX_QSPIPS)
-
-OBJECT_DECLARE_SIMPLE_TYPE(XlnxZynqMPQSPIPS, XLNX_ZYNQMP_QSPIPS)
-
-#endif /* XILINX_SPIPS_H */
+++ /dev/null
-/*
- * Global peripheral timer block for ARM A9MP
- *
- * (C) 2013 Xilinx Inc.
- *
- * Written by François LEGAL
- * Written by Peter Crosthwaite <peter.crosthwaite@xilinx.com>
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version
- * 2 of the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License along
- * with this program; if not, see <http://www.gnu.org/licenses/>.
- */
-
-#ifndef A9GTIMER_H
-#define A9GTIMER_H
-
-#include "hw/sysbus.h"
-#include "qom/object.h"
-
-#define A9_GTIMER_MAX_CPUS 4
-
-#define TYPE_A9_GTIMER "arm.cortex-a9-global-timer"
-OBJECT_DECLARE_SIMPLE_TYPE(A9GTimerState, A9_GTIMER)
-
-#define R_COUNTER_LO 0x00
-#define R_COUNTER_HI 0x04
-
-#define R_CONTROL 0x08
-#define R_CONTROL_TIMER_ENABLE (1 << 0)
-#define R_CONTROL_COMP_ENABLE (1 << 1)
-#define R_CONTROL_IRQ_ENABLE (1 << 2)
-#define R_CONTROL_AUTO_INCREMENT (1 << 3)
-#define R_CONTROL_PRESCALER_SHIFT 8
-#define R_CONTROL_PRESCALER_LEN 8
-#define R_CONTROL_PRESCALER_MASK (((1 << R_CONTROL_PRESCALER_LEN) - 1) << \
- R_CONTROL_PRESCALER_SHIFT)
-
-#define R_CONTROL_BANKED (R_CONTROL_COMP_ENABLE | \
- R_CONTROL_IRQ_ENABLE | \
- R_CONTROL_AUTO_INCREMENT)
-#define R_CONTROL_NEEDS_SYNC (R_CONTROL_TIMER_ENABLE | \
- R_CONTROL_PRESCALER_MASK)
-
-#define R_INTERRUPT_STATUS 0x0C
-#define R_COMPARATOR_LO 0x10
-#define R_COMPARATOR_HI 0x14
-#define R_AUTO_INCREMENT 0x18
-
-typedef struct A9GTimerPerCPU A9GTimerPerCPU;
-
-struct A9GTimerPerCPU {
- A9GTimerState *parent;
-
- uint32_t control; /* only per cpu banked bits valid */
- uint64_t compare;
- uint32_t status;
- uint32_t inc;
-
- MemoryRegion iomem;
- qemu_irq irq; /* PPI interrupts */
-};
-
-struct A9GTimerState {
- /*< private >*/
- SysBusDevice parent_obj;
- /*< public >*/
-
- MemoryRegion iomem;
- /* static props */
- uint32_t num_cpu;
-
- QEMUTimer *timer;
-
- uint64_t counter; /* current timer value */
-
- uint64_t ref_counter;
- uint64_t cpu_ref_time; /* the cpu time as of last update of ref_counter */
- uint32_t control; /* only non per cpu banked bits valid */
-
- A9GTimerPerCPU per_cpu[A9_GTIMER_MAX_CPUS];
-};
-
-typedef struct A9GTimerUpdate {
- uint64_t now;
- uint64_t new;
-} A9GTimerUpdate;
-
-#endif /* A9GTIMER_H */
+++ /dev/null
-#ifndef ALLWINNER_A10_PIT_H
-#define ALLWINNER_A10_PIT_H
-
-#include "hw/ptimer.h"
-#include "hw/sysbus.h"
-#include "qom/object.h"
-
-#define TYPE_AW_A10_PIT "allwinner-A10-timer"
-OBJECT_DECLARE_SIMPLE_TYPE(AwA10PITState, AW_A10_PIT)
-
-#define AW_A10_PIT_TIMER_NR 6
-#define AW_A10_PIT_TIMER_IRQ 0x1
-#define AW_A10_PIT_WDOG_IRQ 0x100
-
-#define AW_A10_PIT_TIMER_IRQ_EN 0
-#define AW_A10_PIT_TIMER_IRQ_ST 0x4
-
-#define AW_A10_PIT_TIMER_CONTROL 0x0
-#define AW_A10_PIT_TIMER_EN 0x1
-#define AW_A10_PIT_TIMER_RELOAD 0x2
-#define AW_A10_PIT_TIMER_MODE 0x80
-
-#define AW_A10_PIT_TIMER_INTERVAL 0x4
-#define AW_A10_PIT_TIMER_COUNT 0x8
-#define AW_A10_PIT_WDOG_CONTROL 0x90
-#define AW_A10_PIT_WDOG_MODE 0x94
-
-#define AW_A10_PIT_COUNT_CTL 0xa0
-#define AW_A10_PIT_COUNT_RL_EN 0x2
-#define AW_A10_PIT_COUNT_CLR_EN 0x1
-#define AW_A10_PIT_COUNT_LO 0xa4
-#define AW_A10_PIT_COUNT_HI 0xa8
-
-#define AW_A10_PIT_TIMER_BASE 0x10
-#define AW_A10_PIT_TIMER_BASE_END \
- (AW_A10_PIT_TIMER_BASE * 6 + AW_A10_PIT_TIMER_COUNT)
-
-#define AW_A10_PIT_DEFAULT_CLOCK 0x4
-
-
-typedef struct AwA10TimerContext {
- AwA10PITState *container;
- int index;
-} AwA10TimerContext;
-
-struct AwA10PITState {
- /*< private >*/
- SysBusDevice parent_obj;
- /*< public >*/
- qemu_irq irq[AW_A10_PIT_TIMER_NR];
- ptimer_state * timer[AW_A10_PIT_TIMER_NR];
- AwA10TimerContext timer_context[AW_A10_PIT_TIMER_NR];
- MemoryRegion iomem;
- uint32_t clk_freq[4];
-
- uint32_t irq_enable;
- uint32_t irq_status;
- uint32_t control[AW_A10_PIT_TIMER_NR];
- uint32_t interval[AW_A10_PIT_TIMER_NR];
- uint32_t count[AW_A10_PIT_TIMER_NR];
- uint32_t watch_dog_mode;
- uint32_t watch_dog_control;
- uint32_t count_lo;
- uint32_t count_hi;
- uint32_t count_ctl;
-};
-
-#endif
+++ /dev/null
-/*
- * Private peripheral timer/watchdog blocks for ARM 11MPCore and A9MP
- *
- * Copyright (c) 2006-2007 CodeSourcery.
- * Copyright (c) 2011 Linaro Limited
- * Written by Paul Brook, Peter Maydell
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version
- * 2 of the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License along
- * with this program; if not, see <http://www.gnu.org/licenses/>.
- */
-#ifndef HW_TIMER_ARM_MPTIMER_H
-#define HW_TIMER_ARM_MPTIMER_H
-
-#include "hw/sysbus.h"
-#include "qom/object.h"
-
-#define ARM_MPTIMER_MAX_CPUS 4
-
-/* State of a single timer or watchdog block */
-typedef struct {
- uint32_t control;
- uint32_t status;
- struct ptimer_state *timer;
- qemu_irq irq;
- MemoryRegion iomem;
-} TimerBlock;
-
-#define TYPE_ARM_MPTIMER "arm_mptimer"
-OBJECT_DECLARE_SIMPLE_TYPE(ARMMPTimerState, ARM_MPTIMER)
-
-struct ARMMPTimerState {
- /*< private >*/
- SysBusDevice parent_obj;
- /*< public >*/
-
- uint32_t num_cpu;
- TimerBlock timerblock[ARM_MPTIMER_MAX_CPUS];
- MemoryRegion iomem;
-};
-
-#endif
+++ /dev/null
-/*
- * ARMv7M SysTick timer
- *
- * Copyright (c) 2006-2007 CodeSourcery.
- * Written by Paul Brook
- * Copyright (c) 2017 Linaro Ltd
- * Written by Peter Maydell
- *
- * This code is licensed under the GPL (version 2 or later).
- */
-
-#ifndef HW_TIMER_ARMV7M_SYSTICK_H
-#define HW_TIMER_ARMV7M_SYSTICK_H
-
-#include "hw/sysbus.h"
-#include "qom/object.h"
-#include "hw/ptimer.h"
-
-#define TYPE_SYSTICK "armv7m_systick"
-
-OBJECT_DECLARE_SIMPLE_TYPE(SysTickState, SYSTICK)
-
-struct SysTickState {
- /*< private >*/
- SysBusDevice parent_obj;
- /*< public >*/
-
- uint32_t control;
- uint32_t reload;
- int64_t tick;
- ptimer_state *ptimer;
- MemoryRegion iomem;
- qemu_irq irq;
-};
-
-/*
- * Multiplication factor to convert from system clock ticks to qemu timer
- * ticks. This should be set (by board code, usually) to a value
- * equal to NANOSECONDS_PER_SECOND / frq, where frq is the clock frequency
- * in Hz of the CPU.
- *
- * This value is used by the systick device when it is running in
- * its "use the CPU clock" mode (ie when SYST_CSR.CLKSOURCE == 1) to
- * set how fast the timer should tick.
- *
- * TODO: we should refactor this so that rather than using a global
- * we use a device property or something similar. This is complicated
- * because (a) the property would need to be plumbed through from the
- * board code down through various layers to the systick device
- * and (b) the property needs to be modifiable after realize, because
- * the stellaris board uses this to implement the behaviour where the
- * guest can reprogram the PLL registers to downclock the CPU, and the
- * systick device needs to react accordingly. Possibly this should
- * be deferred until we have a good API for modelling clock trees.
- */
-extern int system_clock_scale;
-
-#endif
+++ /dev/null
-/*
- * ASPEED AST2400 Timer
- *
- * Andrew Jeffery <andrew@aj.id.au>
- *
- * Copyright (C) 2016 IBM Corp.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License along
- * with this program; if not, write to the Free Software Foundation, Inc.,
- * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
- */
-#ifndef ASPEED_TIMER_H
-#define ASPEED_TIMER_H
-
-#include "qemu/timer.h"
-#include "hw/misc/aspeed_scu.h"
-#include "qom/object.h"
-
-#define TYPE_ASPEED_TIMER "aspeed.timer"
-OBJECT_DECLARE_TYPE(AspeedTimerCtrlState, AspeedTimerClass, ASPEED_TIMER)
-#define TYPE_ASPEED_2400_TIMER TYPE_ASPEED_TIMER "-ast2400"
-#define TYPE_ASPEED_2500_TIMER TYPE_ASPEED_TIMER "-ast2500"
-#define TYPE_ASPEED_2600_TIMER TYPE_ASPEED_TIMER "-ast2600"
-
-#define ASPEED_TIMER_NR_TIMERS 8
-
-typedef struct AspeedTimer {
- qemu_irq irq;
-
- uint8_t id;
- QEMUTimer timer;
-
- /**
- * Track the line level as the ASPEED timers implement edge triggered
- * interrupts, signalling with both the rising and falling edge.
- */
- int32_t level;
- uint32_t reload;
- uint32_t match[2];
- uint64_t start;
-} AspeedTimer;
-
-struct AspeedTimerCtrlState {
- /*< private >*/
- SysBusDevice parent;
-
- /*< public >*/
- MemoryRegion iomem;
-
- uint32_t ctrl;
- uint32_t ctrl2;
- uint32_t ctrl3;
- uint32_t irq_sts;
- AspeedTimer timers[ASPEED_TIMER_NR_TIMERS];
-
- AspeedSCUState *scu;
-};
-
-
-struct AspeedTimerClass {
- SysBusDeviceClass parent_class;
-
- uint64_t (*read)(AspeedTimerCtrlState *s, hwaddr offset);
- void (*write)(AspeedTimerCtrlState *s, hwaddr offset, uint64_t value);
-};
-
-#endif /* ASPEED_TIMER_H */
+++ /dev/null
-/*
- * AVR 16-bit timer
- *
- * Copyright (c) 2018 University of Kent
- * Author: Ed Robbins
- *
- * This library is free software; you can redistribute it and/or
- * modify it under the terms of the GNU Lesser General Public
- * License as published by the Free Software Foundation; either
- * version 2.1 of the License, or (at your option) any later version.
- *
- * This library is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
- * Lesser General Public License for more details.
- *
- * You should have received a copy of the GNU Lesser General Public
- * License along with this library; if not, see
- * <http://www.gnu.org/licenses/lgpl-2.1.html>
- */
-
-/*
- * Driver for 16 bit timers on 8 bit AVR devices.
- * Note:
- * On ATmega640/V-1280/V-1281/V-2560/V-2561/V timers 1, 3, 4 and 5 are 16 bit
- */
-
-#ifndef HW_TIMER_AVR_TIMER16_H
-#define HW_TIMER_AVR_TIMER16_H
-
-#include "hw/sysbus.h"
-#include "qemu/timer.h"
-#include "hw/hw.h"
-#include "qom/object.h"
-
-enum NextInterrupt {
- OVERFLOW,
- COMPA,
- COMPB,
- COMPC,
- CAPT
-};
-
-#define TYPE_AVR_TIMER16 "avr-timer16"
-OBJECT_DECLARE_SIMPLE_TYPE(AVRTimer16State, AVR_TIMER16)
-
-struct AVRTimer16State {
- /* <private> */
- SysBusDevice parent_obj;
-
- /* <public> */
- MemoryRegion iomem;
- MemoryRegion imsk_iomem;
- MemoryRegion ifr_iomem;
- QEMUTimer *timer;
- qemu_irq capt_irq;
- qemu_irq compa_irq;
- qemu_irq compb_irq;
- qemu_irq compc_irq;
- qemu_irq ovf_irq;
-
- bool enabled;
-
- /* registers */
- uint8_t cra;
- uint8_t crb;
- uint8_t crc;
- uint8_t cntl;
- uint8_t cnth;
- uint8_t icrl;
- uint8_t icrh;
- uint8_t ocral;
- uint8_t ocrah;
- uint8_t ocrbl;
- uint8_t ocrbh;
- uint8_t ocrcl;
- uint8_t ocrch;
- /*
- * Reads and writes to CNT and ICR utilise a bizarre temporary
- * register, which we emulate
- */
- uint8_t rtmp;
- uint8_t imsk;
- uint8_t ifr;
-
- uint8_t id;
- uint64_t cpu_freq_hz;
- uint64_t freq_hz;
- uint64_t period_ns;
- uint64_t reset_time_ns;
- enum NextInterrupt next_interrupt;
-};
-
-#endif /* HW_TIMER_AVR_TIMER16_H */
+++ /dev/null
-/*
- * BCM2835 SYS timer emulation
- *
- * Copyright (c) 2019 Philippe Mathieu-Daudé <f4bug@amsat.org>
- *
- * SPDX-License-Identifier: GPL-2.0-or-later
- */
-
-#ifndef BCM2835_SYSTIMER_H
-#define BCM2835_SYSTIMER_H
-
-#include "hw/sysbus.h"
-#include "hw/irq.h"
-#include "qemu/timer.h"
-#include "qom/object.h"
-
-#define TYPE_BCM2835_SYSTIMER "bcm2835-sys-timer"
-OBJECT_DECLARE_SIMPLE_TYPE(BCM2835SystemTimerState, BCM2835_SYSTIMER)
-
-#define BCM2835_SYSTIMER_COUNT 4
-
-typedef struct {
- unsigned id;
- QEMUTimer timer;
- qemu_irq irq;
- BCM2835SystemTimerState *state;
-} BCM2835SystemTimerCompare;
-
-struct BCM2835SystemTimerState {
- /*< private >*/
- SysBusDevice parent_obj;
-
- /*< public >*/
- MemoryRegion iomem;
- struct {
- uint32_t ctrl_status;
- uint32_t compare[BCM2835_SYSTIMER_COUNT];
- } reg;
- BCM2835SystemTimerCompare tmr[BCM2835_SYSTIMER_COUNT];
-};
-
-#endif
+++ /dev/null
-/*
- * ARM CMSDK APB dual-timer emulation
- *
- * Copyright (c) 2018 Linaro Limited
- * Written by Peter Maydell
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 or
- * (at your option) any later version.
- */
-
-/*
- * This is a model of the "APB dual-input timer" which is part of the Cortex-M
- * System Design Kit (CMSDK) and documented in the Cortex-M System
- * Design Kit Technical Reference Manual (ARM DDI0479C):
- * https://developer.arm.com/products/system-design/system-design-kits/cortex-m-system-design-kit
- *
- * QEMU interface:
- * + QOM property "pclk-frq": frequency at which the timer is clocked
- * + sysbus MMIO region 0: the register bank
- * + sysbus IRQ 0: combined timer interrupt TIMINTC
- * + sysbus IRO 1: timer block 1 interrupt TIMINT1
- * + sysbus IRQ 2: timer block 2 interrupt TIMINT2
- */
-
-#ifndef CMSDK_APB_DUALTIMER_H
-#define CMSDK_APB_DUALTIMER_H
-
-#include "hw/sysbus.h"
-#include "hw/ptimer.h"
-#include "qom/object.h"
-
-#define TYPE_CMSDK_APB_DUALTIMER "cmsdk-apb-dualtimer"
-OBJECT_DECLARE_SIMPLE_TYPE(CMSDKAPBDualTimer, CMSDK_APB_DUALTIMER)
-
-
-/* One of the two identical timer modules in the dual-timer module */
-typedef struct CMSDKAPBDualTimerModule {
- CMSDKAPBDualTimer *parent;
- struct ptimer_state *timer;
- qemu_irq timerint;
- /*
- * We must track the guest LOAD and VALUE register state by hand
- * rather than leaving this state only in the ptimer limit/count,
- * because if CONTROL.SIZE is 0 then only the low 16 bits of the
- * counter actually counts, but the high half is still guest
- * accessible.
- */
- uint32_t load;
- uint32_t value;
- uint32_t control;
- uint32_t intstatus;
-} CMSDKAPBDualTimerModule;
-
-#define CMSDK_APB_DUALTIMER_NUM_MODULES 2
-
-struct CMSDKAPBDualTimer {
- /*< private >*/
- SysBusDevice parent_obj;
-
- /*< public >*/
- MemoryRegion iomem;
- qemu_irq timerintc;
- uint32_t pclk_frq;
-
- CMSDKAPBDualTimerModule timermod[CMSDK_APB_DUALTIMER_NUM_MODULES];
- uint32_t timeritcr;
- uint32_t timeritop;
-};
-
-#endif
+++ /dev/null
-/*
- * ARM CMSDK APB timer emulation
- *
- * Copyright (c) 2017 Linaro Limited
- * Written by Peter Maydell
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 or
- * (at your option) any later version.
- */
-
-#ifndef CMSDK_APB_TIMER_H
-#define CMSDK_APB_TIMER_H
-
-#include "hw/qdev-properties.h"
-#include "hw/sysbus.h"
-#include "hw/ptimer.h"
-#include "qom/object.h"
-
-#define TYPE_CMSDK_APB_TIMER "cmsdk-apb-timer"
-OBJECT_DECLARE_SIMPLE_TYPE(CMSDKAPBTIMER, CMSDK_APB_TIMER)
-
-struct CMSDKAPBTIMER {
- /*< private >*/
- SysBusDevice parent_obj;
-
- /*< public >*/
- MemoryRegion iomem;
- qemu_irq timerint;
- uint32_t pclk_frq;
- struct ptimer_state *timer;
-
- uint32_t ctrl;
- uint32_t value;
- uint32_t reload;
- uint32_t intstatus;
-};
-
-/**
- * cmsdk_apb_timer_create - convenience function to create TYPE_CMSDK_APB_TIMER
- * @addr: location in system memory to map registers
- * @pclk_frq: frequency in Hz of the PCLK clock (used for calculating baud rate)
- */
-static inline DeviceState *cmsdk_apb_timer_create(hwaddr addr,
- qemu_irq timerint,
- uint32_t pclk_frq)
-{
- DeviceState *dev;
- SysBusDevice *s;
-
- dev = qdev_new(TYPE_CMSDK_APB_TIMER);
- s = SYS_BUS_DEVICE(dev);
- qdev_prop_set_uint32(dev, "pclk-frq", pclk_frq);
- sysbus_realize_and_unref(s, &error_fatal);
- sysbus_mmio_map(s, 0, addr);
- sysbus_connect_irq(s, 0, timerint);
- return dev;
-}
-
-#endif
+++ /dev/null
-/*
- * Canon DIGIC timer block declarations.
- *
- * Copyright (C) 2013 Antony Pavlov <antonynpavlov@gmail.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- */
-
-#ifndef HW_TIMER_DIGIC_TIMER_H
-#define HW_TIMER_DIGIC_TIMER_H
-
-#include "hw/sysbus.h"
-#include "hw/ptimer.h"
-#include "qom/object.h"
-
-#define TYPE_DIGIC_TIMER "digic-timer"
-OBJECT_DECLARE_SIMPLE_TYPE(DigicTimerState, DIGIC_TIMER)
-
-#define DIGIC_TIMER_CONTROL 0x00
-#define DIGIC_TIMER_CONTROL_RST 0x80000000
-#define DIGIC_TIMER_CONTROL_EN 0x00000001
-#define DIGIC_TIMER_RELVALUE 0x08
-#define DIGIC_TIMER_VALUE 0x0c
-
-struct DigicTimerState {
- /*< private >*/
- SysBusDevice parent_obj;
- /*< public >*/
-
- MemoryRegion iomem;
- ptimer_state *ptimer;
-
- uint32_t control;
- uint32_t relvalue;
-};
-
-#endif /* HW_TIMER_DIGIC_TIMER_H */
+++ /dev/null
-/*
- * QEMU Emulated HPET support
- *
- * Copyright IBM, Corp. 2008
- *
- * Authors:
- * Beth Kon <bkon@us.ibm.com>
- *
- * This work is licensed under the terms of the GNU GPL, version 2. See
- * the COPYING file in the top-level directory.
- *
- */
-
-#ifndef HW_HPET_H
-#define HW_HPET_H
-
-#include "qom/object.h"
-
-#define HPET_BASE 0xfed00000
-#define HPET_LEN 0x400
-#define HPET_CLK_PERIOD 10 /* 10 ns*/
-
-#define FS_PER_NS 1000000 /* 1000000 femtoseconds == 1 ns */
-#define HPET_MIN_TIMERS 3
-#define HPET_MAX_TIMERS 32
-
-#define HPET_NUM_IRQ_ROUTES 32
-
-#define HPET_LEGACY_PIT_INT 0
-#define HPET_LEGACY_RTC_INT 1
-
-#define HPET_CFG_ENABLE 0x001
-#define HPET_CFG_LEGACY 0x002
-
-#define HPET_ID 0x000
-#define HPET_PERIOD 0x004
-#define HPET_CFG 0x010
-#define HPET_STATUS 0x020
-#define HPET_COUNTER 0x0f0
-#define HPET_TN_CFG 0x000
-#define HPET_TN_CMP 0x008
-#define HPET_TN_ROUTE 0x010
-#define HPET_CFG_WRITE_MASK 0x3
-
-#define HPET_ID_NUM_TIM_SHIFT 8
-#define HPET_ID_NUM_TIM_MASK 0x1f00
-
-#define HPET_TN_TYPE_LEVEL 0x002
-#define HPET_TN_ENABLE 0x004
-#define HPET_TN_PERIODIC 0x008
-#define HPET_TN_PERIODIC_CAP 0x010
-#define HPET_TN_SIZE_CAP 0x020
-#define HPET_TN_SETVAL 0x040
-#define HPET_TN_32BIT 0x100
-#define HPET_TN_INT_ROUTE_MASK 0x3e00
-#define HPET_TN_FSB_ENABLE 0x4000
-#define HPET_TN_FSB_CAP 0x8000
-#define HPET_TN_CFG_WRITE_MASK 0x7f4e
-#define HPET_TN_INT_ROUTE_SHIFT 9
-#define HPET_TN_INT_ROUTE_CAP_SHIFT 32
-#define HPET_TN_CFG_BITS_READONLY_OR_RESERVED 0xffff80b1U
-
-struct hpet_fw_entry
-{
- uint32_t event_timer_block_id;
- uint64_t address;
- uint16_t min_tick;
- uint8_t page_prot;
-} QEMU_PACKED;
-
-struct hpet_fw_config
-{
- uint8_t count;
- struct hpet_fw_entry hpet[8];
-} QEMU_PACKED;
-
-extern struct hpet_fw_config hpet_cfg;
-
-#define TYPE_HPET "hpet"
-
-static inline bool hpet_find(void)
-{
- return object_resolve_path_type("", TYPE_HPET, NULL);
-}
-
-#endif
+++ /dev/null
-/*
- * QEMU 8253/8254 interval timer emulation
- *
- * Copyright (c) 2003-2004 Fabrice Bellard
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
- * furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
- * THE SOFTWARE.
- */
-
-#ifndef HW_I8254_H
-#define HW_I8254_H
-
-#include "hw/qdev-properties.h"
-#include "hw/isa/isa.h"
-#include "qapi/error.h"
-#include "qom/object.h"
-
-#define PIT_FREQ 1193182
-
-typedef struct PITChannelInfo {
- int gate;
- int mode;
- int initial_count;
- int out;
-} PITChannelInfo;
-
-#define TYPE_PIT_COMMON "pit-common"
-OBJECT_DECLARE_TYPE(PITCommonState, PITCommonClass, PIT_COMMON)
-
-#define TYPE_I8254 "isa-pit"
-#define TYPE_KVM_I8254 "kvm-pit"
-
-static inline ISADevice *i8254_pit_init(ISABus *bus, int base, int isa_irq,
- qemu_irq alt_irq)
-{
- DeviceState *dev;
- ISADevice *d;
-
- d = isa_new(TYPE_I8254);
- dev = DEVICE(d);
- qdev_prop_set_uint32(dev, "iobase", base);
- isa_realize_and_unref(d, bus, &error_fatal);
- qdev_connect_gpio_out(dev, 0,
- isa_irq >= 0 ? isa_get_irq(d, isa_irq) : alt_irq);
-
- return d;
-}
-
-static inline ISADevice *kvm_pit_init(ISABus *bus, int base)
-{
- DeviceState *dev;
- ISADevice *d;
-
- d = isa_new(TYPE_KVM_I8254);
- dev = DEVICE(d);
- qdev_prop_set_uint32(dev, "iobase", base);
- isa_realize_and_unref(d, bus, &error_fatal);
-
- return d;
-}
-
-void pit_set_gate(ISADevice *dev, int channel, int val);
-void pit_get_channel_info(ISADevice *dev, int channel, PITChannelInfo *info);
-
-#endif /* HW_I8254_H */
+++ /dev/null
-/*
- * QEMU 8253/8254 - internal interfaces
- *
- * Copyright (c) 2011 Jan Kiszka, Siemens AG
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
- * furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
- * THE SOFTWARE.
- */
-
-#ifndef QEMU_I8254_INTERNAL_H
-#define QEMU_I8254_INTERNAL_H
-
-#include "hw/isa/isa.h"
-#include "hw/timer/i8254.h"
-#include "qemu/timer.h"
-
-typedef struct PITChannelState {
- int count; /* can be 65536 */
- uint16_t latched_count;
- uint8_t count_latched;
- uint8_t status_latched;
- uint8_t status;
- uint8_t read_state;
- uint8_t write_state;
- uint8_t write_latch;
- uint8_t rw_mode;
- uint8_t mode;
- uint8_t bcd; /* not supported */
- uint8_t gate; /* timer start */
- int64_t count_load_time;
- /* irq handling */
- int64_t next_transition_time;
- QEMUTimer *irq_timer;
- qemu_irq irq;
- uint32_t irq_disabled;
-} PITChannelState;
-
-struct PITCommonState {
- ISADevice dev;
- MemoryRegion ioports;
- uint32_t iobase;
- PITChannelState channels[3];
-};
-
-struct PITCommonClass {
- ISADeviceClass parent_class;
-
- void (*set_channel_gate)(PITCommonState *s, PITChannelState *sc, int val);
- void (*get_channel_info)(PITCommonState *s, PITChannelState *sc,
- PITChannelInfo *info);
- void (*pre_save)(PITCommonState *s);
- void (*post_load)(PITCommonState *s);
-};
-
-int pit_get_out(PITChannelState *s, int64_t current_time);
-int64_t pit_get_next_transition_time(PITChannelState *s, int64_t current_time);
-void pit_get_channel_info_common(PITCommonState *s, PITChannelState *sc,
- PITChannelInfo *info);
-void pit_reset_common(PITCommonState *s);
-
-#endif /* QEMU_I8254_INTERNAL_H */
+++ /dev/null
-/*
- * i.MX EPIT Timer
- *
- * Copyright (c) 2008 OK Labs
- * Copyright (c) 2011 NICTA Pty Ltd
- * Originally written by Hans Jiang
- * Updated by Peter Chubb
- * Updated by Jean-Christophe Dubois <jcd@tribudubois.net>
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
- * furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
- * THE SOFTWARE.
- */
-
-#ifndef IMX_EPIT_H
-#define IMX_EPIT_H
-
-#include "hw/sysbus.h"
-#include "hw/ptimer.h"
-#include "hw/misc/imx_ccm.h"
-#include "qom/object.h"
-
-/*
- * EPIT: Enhanced periodic interrupt timer
- */
-
-#define CR_EN (1 << 0)
-#define CR_ENMOD (1 << 1)
-#define CR_OCIEN (1 << 2)
-#define CR_RLD (1 << 3)
-#define CR_PRESCALE_SHIFT (4)
-#define CR_PRESCALE_MASK (0xfff)
-#define CR_SWR (1 << 16)
-#define CR_IOVW (1 << 17)
-#define CR_DBGEN (1 << 18)
-#define CR_WAITEN (1 << 19)
-#define CR_DOZEN (1 << 20)
-#define CR_STOPEN (1 << 21)
-#define CR_CLKSRC_SHIFT (24)
-#define CR_CLKSRC_MASK (0x3 << CR_CLKSRC_SHIFT)
-
-#define EPIT_TIMER_MAX 0XFFFFFFFFUL
-
-#define TYPE_IMX_EPIT "imx.epit"
-OBJECT_DECLARE_SIMPLE_TYPE(IMXEPITState, IMX_EPIT)
-
-struct IMXEPITState {
- /*< private >*/
- SysBusDevice parent_obj;
-
- /*< public >*/
- ptimer_state *timer_reload;
- ptimer_state *timer_cmp;
- MemoryRegion iomem;
- IMXCCMState *ccm;
-
- uint32_t cr;
- uint32_t sr;
- uint32_t lr;
- uint32_t cmp;
- uint32_t cnt;
-
- uint32_t freq;
- qemu_irq irq;
-};
-
-#endif /* IMX_EPIT_H */
+++ /dev/null
-/*
- * i.MX GPT Timer
- *
- * Copyright (c) 2008 OK Labs
- * Copyright (c) 2011 NICTA Pty Ltd
- * Originally written by Hans Jiang
- * Updated by Peter Chubb
- * Updated by Jean-Christophe Dubois <jcd@tribudubois.net>
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
- * furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
- * THE SOFTWARE.
- */
-
-#ifndef IMX_GPT_H
-#define IMX_GPT_H
-
-#include "hw/sysbus.h"
-#include "hw/ptimer.h"
-#include "hw/misc/imx_ccm.h"
-#include "qom/object.h"
-
-/*
- * GPT : General purpose timer
- *
- * This timer counts up continuously while it is enabled, resetting itself
- * to 0 when it reaches GPT_TIMER_MAX (in freerun mode) or when it
- * reaches the value of one of the ocrX (in periodic mode).
- */
-
-#define GPT_TIMER_MAX 0XFFFFFFFFUL
-
-/* Control register. Not all of these bits have any effect (yet) */
-#define GPT_CR_EN (1 << 0) /* GPT Enable */
-#define GPT_CR_ENMOD (1 << 1) /* GPT Enable Mode */
-#define GPT_CR_DBGEN (1 << 2) /* GPT Debug mode enable */
-#define GPT_CR_WAITEN (1 << 3) /* GPT Wait Mode Enable */
-#define GPT_CR_DOZEN (1 << 4) /* GPT Doze mode enable */
-#define GPT_CR_STOPEN (1 << 5) /* GPT Stop Mode Enable */
-#define GPT_CR_CLKSRC_SHIFT (6)
-#define GPT_CR_CLKSRC_MASK (0x7)
-
-#define GPT_CR_FRR (1 << 9) /* Freerun or Restart */
-#define GPT_CR_SWR (1 << 15) /* Software Reset */
-#define GPT_CR_IM1 (3 << 16) /* Input capture channel 1 mode (2 bits) */
-#define GPT_CR_IM2 (3 << 18) /* Input capture channel 2 mode (2 bits) */
-#define GPT_CR_OM1 (7 << 20) /* Output Compare Channel 1 Mode (3 bits) */
-#define GPT_CR_OM2 (7 << 23) /* Output Compare Channel 2 Mode (3 bits) */
-#define GPT_CR_OM3 (7 << 26) /* Output Compare Channel 3 Mode (3 bits) */
-#define GPT_CR_FO1 (1 << 29) /* Force Output Compare Channel 1 */
-#define GPT_CR_FO2 (1 << 30) /* Force Output Compare Channel 2 */
-#define GPT_CR_FO3 (1 << 31) /* Force Output Compare Channel 3 */
-
-#define GPT_SR_OF1 (1 << 0)
-#define GPT_SR_OF2 (1 << 1)
-#define GPT_SR_OF3 (1 << 2)
-#define GPT_SR_ROV (1 << 5)
-
-#define GPT_IR_OF1IE (1 << 0)
-#define GPT_IR_OF2IE (1 << 1)
-#define GPT_IR_OF3IE (1 << 2)
-#define GPT_IR_ROVIE (1 << 5)
-
-#define TYPE_IMX25_GPT "imx25.gpt"
-#define TYPE_IMX31_GPT "imx31.gpt"
-#define TYPE_IMX6_GPT "imx6.gpt"
-#define TYPE_IMX7_GPT "imx7.gpt"
-
-#define TYPE_IMX_GPT TYPE_IMX25_GPT
-
-typedef struct IMXGPTState IMXGPTState;
-DECLARE_INSTANCE_CHECKER(IMXGPTState, IMX_GPT,
- TYPE_IMX_GPT)
-
-struct IMXGPTState {
- /*< private >*/
- SysBusDevice parent_obj;
-
- /*< public >*/
- ptimer_state *timer;
- MemoryRegion iomem;
- IMXCCMState *ccm;
-
- uint32_t cr;
- uint32_t pr;
- uint32_t sr;
- uint32_t ir;
- uint32_t ocr1;
- uint32_t ocr2;
- uint32_t ocr3;
- uint32_t icr1;
- uint32_t icr2;
- uint32_t cnt;
-
- uint32_t next_timeout;
- uint32_t next_int;
-
- uint32_t freq;
-
- qemu_irq irq;
-
- const IMXClk *clocks;
-};
-
-#endif /* IMX_GPT_H */
+++ /dev/null
-/*
- * This file is subject to the terms and conditions of the GNU General Public
- * License. See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * Copyright (C) 2016 Imagination Technologies
- *
- */
-
-#ifndef MIPS_GICTIMER_H
-#define MIPS_GICTIMER_H
-
-typedef struct MIPSGICTimerVPState MIPSGICTimerVPState;
-typedef struct MIPSGICTimerState MIPSGICTimerState;
-
-typedef void MIPSGICTimerCB(void *opaque, uint32_t vp_index);
-
-struct MIPSGICTimerVPState {
- QEMUTimer *qtimer;
- uint32_t vp_index;
- uint32_t comparelo;
- MIPSGICTimerState *gictimer;
-};
-
-struct MIPSGICTimerState {
- void *opaque;
- uint8_t countstop;
- uint32_t sh_counterlo;
- int32_t num_vps;
- MIPSGICTimerVPState *vptimers;
- MIPSGICTimerCB *cb;
-};
-
-uint32_t mips_gictimer_get_freq(MIPSGICTimerState *gic);
-uint32_t mips_gictimer_get_sh_count(MIPSGICTimerState *gic);
-void mips_gictimer_store_sh_count(MIPSGICTimerState *gic, uint64_t count);
-uint32_t mips_gictimer_get_vp_compare(MIPSGICTimerState *gictimer,
- uint32_t vp_index);
-void mips_gictimer_store_vp_compare(MIPSGICTimerState *gic, uint32_t vp_index,
- uint64_t compare);
-uint8_t mips_gictimer_get_countstop(MIPSGICTimerState *gic);
-void mips_gictimer_start_count(MIPSGICTimerState *gic);
-void mips_gictimer_stop_count(MIPSGICTimerState *gic);
-MIPSGICTimerState *mips_gictimer_init(void *opaque, uint32_t nvps,
- MIPSGICTimerCB *cb);
-
-#endif /* MIPS_GICTIMER_H */
+++ /dev/null
-/*
- * Microsemi SmartFusion2 Timer.
- *
- * Copyright (c) 2017 Subbaraya Sundeep <sundeep.lkml@gmail.com>
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
- * furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
- * THE SOFTWARE.
- */
-
-#ifndef HW_MSS_TIMER_H
-#define HW_MSS_TIMER_H
-
-#include "hw/sysbus.h"
-#include "hw/ptimer.h"
-#include "qom/object.h"
-
-#define TYPE_MSS_TIMER "mss-timer"
-OBJECT_DECLARE_SIMPLE_TYPE(MSSTimerState, MSS_TIMER)
-
-/*
- * There are two 32-bit down counting timers.
- * Timers 1 and 2 can be concatenated into a single 64-bit Timer
- * that operates either in Periodic mode or in One-shot mode.
- * Writing 1 to the TIM64_MODE register bit 0 sets the Timers in 64-bit mode.
- * In 64-bit mode, writing to the 32-bit registers has no effect.
- * Similarly, in 32-bit mode, writing to the 64-bit mode registers
- * has no effect. Only two 32-bit timers are supported currently.
- */
-#define NUM_TIMERS 2
-
-#define R_TIM1_MAX 6
-
-struct Msf2Timer {
- ptimer_state *ptimer;
-
- uint32_t regs[R_TIM1_MAX];
- qemu_irq irq;
-};
-
-struct MSSTimerState {
- SysBusDevice parent_obj;
-
- MemoryRegion mmio;
- uint32_t freq_hz;
- struct Msf2Timer timers[NUM_TIMERS];
-};
-
-#endif /* HW_MSS_TIMER_H */
+++ /dev/null
-/*
- * Nuvoton NPCM7xx Timer Controller
- *
- * Copyright 2020 Google LLC
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License as published by the
- * Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
- * for more details.
- */
-#ifndef NPCM7XX_TIMER_H
-#define NPCM7XX_TIMER_H
-
-#include "exec/memory.h"
-#include "hw/sysbus.h"
-#include "qemu/timer.h"
-
-/* Each Timer Module (TIM) instance holds five 25 MHz timers. */
-#define NPCM7XX_TIMERS_PER_CTRL (5)
-
-/*
- * Number of registers in our device state structure. Don't change this without
- * incrementing the version_id in the vmstate.
- */
-#define NPCM7XX_TIMER_NR_REGS (0x54 / sizeof(uint32_t))
-
-/* The basic watchdog timer period is 2^14 clock cycles. */
-#define NPCM7XX_WATCHDOG_BASETIME_SHIFT 14
-
-#define NPCM7XX_WATCHDOG_RESET_GPIO_OUT "npcm7xx-clk-watchdog-reset-gpio-out"
-
-typedef struct NPCM7xxTimerCtrlState NPCM7xxTimerCtrlState;
-
-/**
- * struct NPCM7xxBaseTimer - Basic functionality that both regular timer and
- * watchdog timer use.
- * @qtimer: QEMU timer that notifies us on expiration.
- * @expires_ns: Absolute virtual expiration time.
- * @remaining_ns: Remaining time until expiration if timer is paused.
- */
-typedef struct NPCM7xxBaseTimer {
- QEMUTimer qtimer;
- int64_t expires_ns;
- int64_t remaining_ns;
-} NPCM7xxBaseTimer;
-
-/**
- * struct NPCM7xxTimer - Individual timer state.
- * @ctrl: The timer module that owns this timer.
- * @irq: GIC interrupt line to fire on expiration (if enabled).
- * @base_timer: The basic timer functionality for this timer.
- * @tcsr: The Timer Control and Status Register.
- * @ticr: The Timer Initial Count Register.
- */
-typedef struct NPCM7xxTimer {
- NPCM7xxTimerCtrlState *ctrl;
-
- qemu_irq irq;
- NPCM7xxBaseTimer base_timer;
-
- uint32_t tcsr;
- uint32_t ticr;
-} NPCM7xxTimer;
-
-/**
- * struct NPCM7xxWatchdogTimer - The watchdog timer state.
- * @ctrl: The timer module that owns this timer.
- * @irq: GIC interrupt line to fire on expiration (if enabled).
- * @reset_signal: The GPIO used to send a reset signal.
- * @base_timer: The basic timer functionality for this timer.
- * @wtcr: The Watchdog Timer Control Register.
- */
-typedef struct NPCM7xxWatchdogTimer {
- NPCM7xxTimerCtrlState *ctrl;
-
- qemu_irq irq;
- qemu_irq reset_signal;
- NPCM7xxBaseTimer base_timer;
-
- uint32_t wtcr;
-} NPCM7xxWatchdogTimer;
-
-/**
- * struct NPCM7xxTimerCtrlState - Timer Module device state.
- * @parent: System bus device.
- * @iomem: Memory region through which registers are accessed.
- * @index: The index of this timer module.
- * @tisr: The Timer Interrupt Status Register.
- * @timer: The five individual timers managed by this module.
- * @watchdog_timer: The watchdog timer managed by this module.
- */
-struct NPCM7xxTimerCtrlState {
- SysBusDevice parent;
-
- MemoryRegion iomem;
-
- uint32_t tisr;
-
- NPCM7xxTimer timer[NPCM7XX_TIMERS_PER_CTRL];
- NPCM7xxWatchdogTimer watchdog_timer;
-};
-
-#define TYPE_NPCM7XX_TIMER "npcm7xx-timer"
-#define NPCM7XX_TIMER(obj) \
- OBJECT_CHECK(NPCM7xxTimerCtrlState, (obj), TYPE_NPCM7XX_TIMER)
-
-#endif /* NPCM7XX_TIMER_H */
+++ /dev/null
-/*
- * nRF51 System-on-Chip Timer peripheral
- *
- * QEMU interface:
- * + sysbus MMIO regions 0: GPIO registers
- * + sysbus irq
- *
- * Copyright 2018 Steffen Görtz <contrib@steffen-goertz.de>
- *
- * This code is licensed under the GPL version 2 or later. See
- * the COPYING file in the top-level directory.
- */
-#ifndef NRF51_TIMER_H
-#define NRF51_TIMER_H
-
-#include "hw/sysbus.h"
-#include "qemu/timer.h"
-#include "qom/object.h"
-#define TYPE_NRF51_TIMER "nrf51_soc.timer"
-OBJECT_DECLARE_SIMPLE_TYPE(NRF51TimerState, NRF51_TIMER)
-
-#define NRF51_TIMER_REG_COUNT 4
-
-#define NRF51_TIMER_TASK_START 0x000
-#define NRF51_TIMER_TASK_STOP 0x004
-#define NRF51_TIMER_TASK_COUNT 0x008
-#define NRF51_TIMER_TASK_CLEAR 0x00C
-#define NRF51_TIMER_TASK_SHUTDOWN 0x010
-#define NRF51_TIMER_TASK_CAPTURE_0 0x040
-#define NRF51_TIMER_TASK_CAPTURE_3 0x04C
-
-#define NRF51_TIMER_EVENT_COMPARE_0 0x140
-#define NRF51_TIMER_EVENT_COMPARE_1 0x144
-#define NRF51_TIMER_EVENT_COMPARE_2 0x148
-#define NRF51_TIMER_EVENT_COMPARE_3 0x14C
-
-#define NRF51_TIMER_REG_SHORTS 0x200
-#define NRF51_TIMER_REG_SHORTS_MASK 0xf0f
-#define NRF51_TIMER_REG_INTENSET 0x304
-#define NRF51_TIMER_REG_INTENCLR 0x308
-#define NRF51_TIMER_REG_INTEN_MASK 0xf0000
-#define NRF51_TIMER_REG_MODE 0x504
-#define NRF51_TIMER_REG_MODE_MASK 0x01
-#define NRF51_TIMER_TIMER 0
-#define NRF51_TIMER_COUNTER 1
-#define NRF51_TIMER_REG_BITMODE 0x508
-#define NRF51_TIMER_REG_BITMODE_MASK 0x03
-#define NRF51_TIMER_WIDTH_16 0
-#define NRF51_TIMER_WIDTH_8 1
-#define NRF51_TIMER_WIDTH_24 2
-#define NRF51_TIMER_WIDTH_32 3
-#define NRF51_TIMER_REG_PRESCALER 0x510
-#define NRF51_TIMER_REG_PRESCALER_MASK 0x0F
-#define NRF51_TIMER_REG_CC0 0x540
-#define NRF51_TIMER_REG_CC3 0x54C
-
-struct NRF51TimerState {
- SysBusDevice parent_obj;
-
- MemoryRegion iomem;
- qemu_irq irq;
-
- uint8_t id;
- QEMUTimer timer;
- int64_t timer_start_ns;
- int64_t update_counter_ns;
- uint32_t counter;
-
- bool running;
-
- uint8_t events_compare[NRF51_TIMER_REG_COUNT];
- uint32_t cc[NRF51_TIMER_REG_COUNT];
- uint32_t shorts;
- uint32_t inten;
- uint32_t mode;
- uint32_t bitmode;
- uint32_t prescaler;
-
-};
-
-
-#endif
+++ /dev/null
-/*
- * Renesas Compare-match timer Object
- *
- * Copyright (c) 2019 Yoshinori Sato
- *
- * SPDX-License-Identifier: GPL-2.0-or-later
- */
-
-#ifndef HW_TIMER_RENESAS_CMT_H
-#define HW_TIMER_RENESAS_CMT_H
-
-#include "qemu/timer.h"
-#include "hw/sysbus.h"
-#include "qom/object.h"
-
-#define TYPE_RENESAS_CMT "renesas-cmt"
-typedef struct RCMTState RCMTState;
-DECLARE_INSTANCE_CHECKER(RCMTState, RCMT,
- TYPE_RENESAS_CMT)
-
-enum {
- CMT_CH = 2,
- CMT_NR_IRQ = 1 * CMT_CH
-};
-
-struct RCMTState {
- /*< private >*/
- SysBusDevice parent_obj;
- /*< public >*/
-
- uint64_t input_freq;
- MemoryRegion memory;
-
- uint16_t cmstr;
- uint16_t cmcr[CMT_CH];
- uint16_t cmcnt[CMT_CH];
- uint16_t cmcor[CMT_CH];
- int64_t tick[CMT_CH];
- qemu_irq cmi[CMT_CH];
- QEMUTimer timer[CMT_CH];
-};
-
-#endif
+++ /dev/null
-/*
- * Renesas 8bit timer Object
- *
- * Copyright (c) 2018 Yoshinori Sato
- *
- * SPDX-License-Identifier: GPL-2.0-or-later
- */
-
-#ifndef HW_TIMER_RENESAS_TMR_H
-#define HW_TIMER_RENESAS_TMR_H
-
-#include "qemu/timer.h"
-#include "hw/sysbus.h"
-#include "qom/object.h"
-
-#define TYPE_RENESAS_TMR "renesas-tmr"
-typedef struct RTMRState RTMRState;
-DECLARE_INSTANCE_CHECKER(RTMRState, RTMR,
- TYPE_RENESAS_TMR)
-
-enum timer_event {
- cmia = 0,
- cmib = 1,
- ovi = 2,
- none = 3,
- TMR_NR_EVENTS = 4
-};
-
-enum {
- TMR_CH = 2,
- TMR_NR_IRQ = 3 * TMR_CH
-};
-
-struct RTMRState {
- /*< private >*/
- SysBusDevice parent_obj;
- /*< public >*/
-
- uint64_t input_freq;
- MemoryRegion memory;
-
- int64_t tick;
- uint8_t tcnt[TMR_CH];
- uint8_t tcora[TMR_CH];
- uint8_t tcorb[TMR_CH];
- uint8_t tcr[TMR_CH];
- uint8_t tccr[TMR_CH];
- uint8_t tcor[TMR_CH];
- uint8_t tcsr[TMR_CH];
- int64_t div_round[TMR_CH];
- uint8_t next[TMR_CH];
- qemu_irq cmia[TMR_CH];
- qemu_irq cmib[TMR_CH];
- qemu_irq ovi[TMR_CH];
- QEMUTimer timer[TMR_CH];
-};
-
-#endif
+++ /dev/null
-/*
- * STM32F2XX Timer
- *
- * Copyright (c) 2014 Alistair Francis <alistair@alistair23.me>
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
- * furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
- * THE SOFTWARE.
- */
-
-#ifndef HW_STM32F2XX_TIMER_H
-#define HW_STM32F2XX_TIMER_H
-
-#include "hw/sysbus.h"
-#include "qemu/timer.h"
-#include "qom/object.h"
-
-#define TIM_CR1 0x00
-#define TIM_CR2 0x04
-#define TIM_SMCR 0x08
-#define TIM_DIER 0x0C
-#define TIM_SR 0x10
-#define TIM_EGR 0x14
-#define TIM_CCMR1 0x18
-#define TIM_CCMR2 0x1C
-#define TIM_CCER 0x20
-#define TIM_CNT 0x24
-#define TIM_PSC 0x28
-#define TIM_ARR 0x2C
-#define TIM_CCR1 0x34
-#define TIM_CCR2 0x38
-#define TIM_CCR3 0x3C
-#define TIM_CCR4 0x40
-#define TIM_DCR 0x48
-#define TIM_DMAR 0x4C
-#define TIM_OR 0x50
-
-#define TIM_CR1_CEN 1
-
-#define TIM_EGR_UG 1
-
-#define TIM_CCER_CC2E (1 << 4)
-#define TIM_CCMR1_OC2M2 (1 << 14)
-#define TIM_CCMR1_OC2M1 (1 << 13)
-#define TIM_CCMR1_OC2M0 (1 << 12)
-#define TIM_CCMR1_OC2PE (1 << 11)
-
-#define TIM_DIER_UIE 1
-
-#define TYPE_STM32F2XX_TIMER "stm32f2xx-timer"
-typedef struct STM32F2XXTimerState STM32F2XXTimerState;
-DECLARE_INSTANCE_CHECKER(STM32F2XXTimerState, STM32F2XXTIMER,
- TYPE_STM32F2XX_TIMER)
-
-struct STM32F2XXTimerState {
- /* <private> */
- SysBusDevice parent_obj;
-
- /* <public> */
- MemoryRegion iomem;
- QEMUTimer *timer;
- qemu_irq irq;
-
- int64_t tick_offset;
- uint64_t hit_time;
- uint64_t freq_hz;
-
- uint32_t tim_cr1;
- uint32_t tim_cr2;
- uint32_t tim_smcr;
- uint32_t tim_dier;
- uint32_t tim_sr;
- uint32_t tim_egr;
- uint32_t tim_ccmr1;
- uint32_t tim_ccmr2;
- uint32_t tim_ccer;
- uint32_t tim_psc;
- uint32_t tim_arr;
- uint32_t tim_ccr1;
- uint32_t tim_ccr2;
- uint32_t tim_ccr3;
- uint32_t tim_ccr4;
- uint32_t tim_dcr;
- uint32_t tim_dmar;
- uint32_t tim_or;
-};
-
-#endif /* HW_STM32F2XX_TIMER_H */
+++ /dev/null
-/*
- * SuperH Timer
- *
- * Copyright (c) 2007 Magnus Damm
- *
- * This code is licensed under the GPL.
- */
-
-#ifndef HW_TIMER_TMU012_H
-#define HW_TIMER_TMU012_H
-
-#include "exec/hwaddr.h"
-
-#define TMU012_FEAT_TOCR (1 << 0)
-#define TMU012_FEAT_3CHAN (1 << 1)
-#define TMU012_FEAT_EXTCLK (1 << 2)
-
-void tmu012_init(MemoryRegion *sysmem, hwaddr base,
- int feat, uint32_t freq,
- qemu_irq ch0_irq, qemu_irq ch1_irq,
- qemu_irq ch2_irq0, qemu_irq ch2_irq1);
-
-#endif
+++ /dev/null
-#ifndef HW_TRICORE_H
-#define HW_TRICORE_H
-
-#include "exec/memory.h"
-
-struct tricore_boot_info {
- uint64_t ram_size;
- const char *kernel_filename;
-};
-#endif
+++ /dev/null
-/*
- * Misc PKUnity SoC declarations
- *
- * Copyright (C) 2010-2012 Guan Xuetao
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation, or any later version.
- * See the COPYING file in the top-level directory.
- */
-
-#ifndef QEMU_HW_PUV3_H
-#define QEMU_HW_PUV3_H
-
-#define PUV3_REGS_OFFSET (0x1000) /* 4K is reasonable */
-
-/* Hardware interrupts */
-#define PUV3_IRQS_NR (32)
-
-#define PUV3_IRQS_GPIOLOW0 (0)
-#define PUV3_IRQS_GPIOLOW1 (1)
-#define PUV3_IRQS_GPIOLOW2 (2)
-#define PUV3_IRQS_GPIOLOW3 (3)
-#define PUV3_IRQS_GPIOLOW4 (4)
-#define PUV3_IRQS_GPIOLOW5 (5)
-#define PUV3_IRQS_GPIOLOW6 (6)
-#define PUV3_IRQS_GPIOLOW7 (7)
-#define PUV3_IRQS_GPIOHIGH (8)
-#define PUV3_IRQS_PS2_KBD (22)
-#define PUV3_IRQS_PS2_AUX (23)
-#define PUV3_IRQS_OST0 (26)
-
-/* All puv3_*.c use DPRINTF for debug. */
-#ifdef DEBUG_PUV3
-#define DPRINTF(fmt, ...) printf("%s: " fmt , __func__, ## __VA_ARGS__)
-#else
-#define DPRINTF(fmt, ...) do {} while (0)
-#endif
-
-#endif /* QEMU_HW_PUV3_H */
+++ /dev/null
-#ifndef CHIPIDEA_H
-#define CHIPIDEA_H
-
-#include "hw/usb/hcd-ehci.h"
-#include "qom/object.h"
-
-struct ChipideaState {
- /*< private >*/
- EHCISysBusState parent_obj;
-
- MemoryRegion iomem[3];
-};
-
-#define TYPE_CHIPIDEA "usb-chipidea"
-OBJECT_DECLARE_SIMPLE_TYPE(ChipideaState, CHIPIDEA)
-
-#endif /* CHIPIDEA_H */
+++ /dev/null
-/* SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) */
-/*
- * Imported from the Linux kernel file drivers/usb/dwc2/hw.h, commit
- * a89bae709b3492b478480a2c9734e7e9393b279c ("usb: dwc2: Move
- * UTMI_PHY_DATA defines closer")
- *
- * hw.h - DesignWare HS OTG Controller hardware definitions
- *
- * Copyright 2004-2013 Synopsys, Inc.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- * notice, this list of conditions, and the following disclaimer,
- * without modification.
- * 2. Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * 3. The names of the above-listed copyright holders may not be used
- * to endorse or promote products derived from this software without
- * specific prior written permission.
- *
- * ALTERNATIVELY, this software may be distributed under the terms of the
- * GNU General Public License ("GPL") as published by the Free Software
- * Foundation; either version 2 of the License, or (at your option) any
- * later version.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
- * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
- * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
- * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
- * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
- * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
- * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
- * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
- * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
- * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-
-#ifndef __DWC2_HW_H__
-#define __DWC2_HW_H__
-
-#define HSOTG_REG(x) (x)
-
-#define GOTGCTL HSOTG_REG(0x000)
-#define GOTGCTL_CHIRPEN BIT(27)
-#define GOTGCTL_MULT_VALID_BC_MASK (0x1f << 22)
-#define GOTGCTL_MULT_VALID_BC_SHIFT 22
-#define GOTGCTL_OTGVER BIT(20)
-#define GOTGCTL_BSESVLD BIT(19)
-#define GOTGCTL_ASESVLD BIT(18)
-#define GOTGCTL_DBNC_SHORT BIT(17)
-#define GOTGCTL_CONID_B BIT(16)
-#define GOTGCTL_DBNCE_FLTR_BYPASS BIT(15)
-#define GOTGCTL_DEVHNPEN BIT(11)
-#define GOTGCTL_HSTSETHNPEN BIT(10)
-#define GOTGCTL_HNPREQ BIT(9)
-#define GOTGCTL_HSTNEGSCS BIT(8)
-#define GOTGCTL_SESREQ BIT(1)
-#define GOTGCTL_SESREQSCS BIT(0)
-
-#define GOTGINT HSOTG_REG(0x004)
-#define GOTGINT_DBNCE_DONE BIT(19)
-#define GOTGINT_A_DEV_TOUT_CHG BIT(18)
-#define GOTGINT_HST_NEG_DET BIT(17)
-#define GOTGINT_HST_NEG_SUC_STS_CHNG BIT(9)
-#define GOTGINT_SES_REQ_SUC_STS_CHNG BIT(8)
-#define GOTGINT_SES_END_DET BIT(2)
-
-#define GAHBCFG HSOTG_REG(0x008)
-#define GAHBCFG_AHB_SINGLE BIT(23)
-#define GAHBCFG_NOTI_ALL_DMA_WRIT BIT(22)
-#define GAHBCFG_REM_MEM_SUPP BIT(21)
-#define GAHBCFG_P_TXF_EMP_LVL BIT(8)
-#define GAHBCFG_NP_TXF_EMP_LVL BIT(7)
-#define GAHBCFG_DMA_EN BIT(5)
-#define GAHBCFG_HBSTLEN_MASK (0xf << 1)
-#define GAHBCFG_HBSTLEN_SHIFT 1
-#define GAHBCFG_HBSTLEN_SINGLE 0
-#define GAHBCFG_HBSTLEN_INCR 1
-#define GAHBCFG_HBSTLEN_INCR4 3
-#define GAHBCFG_HBSTLEN_INCR8 5
-#define GAHBCFG_HBSTLEN_INCR16 7
-#define GAHBCFG_GLBL_INTR_EN BIT(0)
-#define GAHBCFG_CTRL_MASK (GAHBCFG_P_TXF_EMP_LVL | \
- GAHBCFG_NP_TXF_EMP_LVL | \
- GAHBCFG_DMA_EN | \
- GAHBCFG_GLBL_INTR_EN)
-
-#define GUSBCFG HSOTG_REG(0x00C)
-#define GUSBCFG_FORCEDEVMODE BIT(30)
-#define GUSBCFG_FORCEHOSTMODE BIT(29)
-#define GUSBCFG_TXENDDELAY BIT(28)
-#define GUSBCFG_ICTRAFFICPULLREMOVE BIT(27)
-#define GUSBCFG_ICUSBCAP BIT(26)
-#define GUSBCFG_ULPI_INT_PROT_DIS BIT(25)
-#define GUSBCFG_INDICATORPASSTHROUGH BIT(24)
-#define GUSBCFG_INDICATORCOMPLEMENT BIT(23)
-#define GUSBCFG_TERMSELDLPULSE BIT(22)
-#define GUSBCFG_ULPI_INT_VBUS_IND BIT(21)
-#define GUSBCFG_ULPI_EXT_VBUS_DRV BIT(20)
-#define GUSBCFG_ULPI_CLK_SUSP_M BIT(19)
-#define GUSBCFG_ULPI_AUTO_RES BIT(18)
-#define GUSBCFG_ULPI_FS_LS BIT(17)
-#define GUSBCFG_OTG_UTMI_FS_SEL BIT(16)
-#define GUSBCFG_PHY_LP_CLK_SEL BIT(15)
-#define GUSBCFG_USBTRDTIM_MASK (0xf << 10)
-#define GUSBCFG_USBTRDTIM_SHIFT 10
-#define GUSBCFG_HNPCAP BIT(9)
-#define GUSBCFG_SRPCAP BIT(8)
-#define GUSBCFG_DDRSEL BIT(7)
-#define GUSBCFG_PHYSEL BIT(6)
-#define GUSBCFG_FSINTF BIT(5)
-#define GUSBCFG_ULPI_UTMI_SEL BIT(4)
-#define GUSBCFG_PHYIF16 BIT(3)
-#define GUSBCFG_PHYIF8 (0 << 3)
-#define GUSBCFG_TOUTCAL_MASK (0x7 << 0)
-#define GUSBCFG_TOUTCAL_SHIFT 0
-#define GUSBCFG_TOUTCAL_LIMIT 0x7
-#define GUSBCFG_TOUTCAL(_x) ((_x) << 0)
-
-#define GRSTCTL HSOTG_REG(0x010)
-#define GRSTCTL_AHBIDLE BIT(31)
-#define GRSTCTL_DMAREQ BIT(30)
-#define GRSTCTL_TXFNUM_MASK (0x1f << 6)
-#define GRSTCTL_TXFNUM_SHIFT 6
-#define GRSTCTL_TXFNUM_LIMIT 0x1f
-#define GRSTCTL_TXFNUM(_x) ((_x) << 6)
-#define GRSTCTL_TXFFLSH BIT(5)
-#define GRSTCTL_RXFFLSH BIT(4)
-#define GRSTCTL_IN_TKNQ_FLSH BIT(3)
-#define GRSTCTL_FRMCNTRRST BIT(2)
-#define GRSTCTL_HSFTRST BIT(1)
-#define GRSTCTL_CSFTRST BIT(0)
-
-#define GINTSTS HSOTG_REG(0x014)
-#define GINTMSK HSOTG_REG(0x018)
-#define GINTSTS_WKUPINT BIT(31)
-#define GINTSTS_SESSREQINT BIT(30)
-#define GINTSTS_DISCONNINT BIT(29)
-#define GINTSTS_CONIDSTSCHNG BIT(28)
-#define GINTSTS_LPMTRANRCVD BIT(27)
-#define GINTSTS_PTXFEMP BIT(26)
-#define GINTSTS_HCHINT BIT(25)
-#define GINTSTS_PRTINT BIT(24)
-#define GINTSTS_RESETDET BIT(23)
-#define GINTSTS_FET_SUSP BIT(22)
-#define GINTSTS_INCOMPL_IP BIT(21)
-#define GINTSTS_INCOMPL_SOOUT BIT(21)
-#define GINTSTS_INCOMPL_SOIN BIT(20)
-#define GINTSTS_OEPINT BIT(19)
-#define GINTSTS_IEPINT BIT(18)
-#define GINTSTS_EPMIS BIT(17)
-#define GINTSTS_RESTOREDONE BIT(16)
-#define GINTSTS_EOPF BIT(15)
-#define GINTSTS_ISOUTDROP BIT(14)
-#define GINTSTS_ENUMDONE BIT(13)
-#define GINTSTS_USBRST BIT(12)
-#define GINTSTS_USBSUSP BIT(11)
-#define GINTSTS_ERLYSUSP BIT(10)
-#define GINTSTS_I2CINT BIT(9)
-#define GINTSTS_ULPI_CK_INT BIT(8)
-#define GINTSTS_GOUTNAKEFF BIT(7)
-#define GINTSTS_GINNAKEFF BIT(6)
-#define GINTSTS_NPTXFEMP BIT(5)
-#define GINTSTS_RXFLVL BIT(4)
-#define GINTSTS_SOF BIT(3)
-#define GINTSTS_OTGINT BIT(2)
-#define GINTSTS_MODEMIS BIT(1)
-#define GINTSTS_CURMODE_HOST BIT(0)
-
-#define GRXSTSR HSOTG_REG(0x01C)
-#define GRXSTSP HSOTG_REG(0x020)
-#define GRXSTS_FN_MASK (0x7f << 25)
-#define GRXSTS_FN_SHIFT 25
-#define GRXSTS_PKTSTS_MASK (0xf << 17)
-#define GRXSTS_PKTSTS_SHIFT 17
-#define GRXSTS_PKTSTS_GLOBALOUTNAK 1
-#define GRXSTS_PKTSTS_OUTRX 2
-#define GRXSTS_PKTSTS_HCHIN 2
-#define GRXSTS_PKTSTS_OUTDONE 3
-#define GRXSTS_PKTSTS_HCHIN_XFER_COMP 3
-#define GRXSTS_PKTSTS_SETUPDONE 4
-#define GRXSTS_PKTSTS_DATATOGGLEERR 5
-#define GRXSTS_PKTSTS_SETUPRX 6
-#define GRXSTS_PKTSTS_HCHHALTED 7
-#define GRXSTS_HCHNUM_MASK (0xf << 0)
-#define GRXSTS_HCHNUM_SHIFT 0
-#define GRXSTS_DPID_MASK (0x3 << 15)
-#define GRXSTS_DPID_SHIFT 15
-#define GRXSTS_BYTECNT_MASK (0x7ff << 4)
-#define GRXSTS_BYTECNT_SHIFT 4
-#define GRXSTS_EPNUM_MASK (0xf << 0)
-#define GRXSTS_EPNUM_SHIFT 0
-
-#define GRXFSIZ HSOTG_REG(0x024)
-#define GRXFSIZ_DEPTH_MASK (0xffff << 0)
-#define GRXFSIZ_DEPTH_SHIFT 0
-
-#define GNPTXFSIZ HSOTG_REG(0x028)
-/* Use FIFOSIZE_* constants to access this register */
-
-#define GNPTXSTS HSOTG_REG(0x02C)
-#define GNPTXSTS_NP_TXQ_TOP_MASK (0x7f << 24)
-#define GNPTXSTS_NP_TXQ_TOP_SHIFT 24
-#define GNPTXSTS_NP_TXQ_SPC_AVAIL_MASK (0xff << 16)
-#define GNPTXSTS_NP_TXQ_SPC_AVAIL_SHIFT 16
-#define GNPTXSTS_NP_TXQ_SPC_AVAIL_GET(_v) (((_v) >> 16) & 0xff)
-#define GNPTXSTS_NP_TXF_SPC_AVAIL_MASK (0xffff << 0)
-#define GNPTXSTS_NP_TXF_SPC_AVAIL_SHIFT 0
-#define GNPTXSTS_NP_TXF_SPC_AVAIL_GET(_v) (((_v) >> 0) & 0xffff)
-
-#define GI2CCTL HSOTG_REG(0x0030)
-#define GI2CCTL_BSYDNE BIT(31)
-#define GI2CCTL_RW BIT(30)
-#define GI2CCTL_I2CDATSE0 BIT(28)
-#define GI2CCTL_I2CDEVADDR_MASK (0x3 << 26)
-#define GI2CCTL_I2CDEVADDR_SHIFT 26
-#define GI2CCTL_I2CSUSPCTL BIT(25)
-#define GI2CCTL_ACK BIT(24)
-#define GI2CCTL_I2CEN BIT(23)
-#define GI2CCTL_ADDR_MASK (0x7f << 16)
-#define GI2CCTL_ADDR_SHIFT 16
-#define GI2CCTL_REGADDR_MASK (0xff << 8)
-#define GI2CCTL_REGADDR_SHIFT 8
-#define GI2CCTL_RWDATA_MASK (0xff << 0)
-#define GI2CCTL_RWDATA_SHIFT 0
-
-#define GPVNDCTL HSOTG_REG(0x0034)
-#define GGPIO HSOTG_REG(0x0038)
-#define GGPIO_STM32_OTG_GCCFG_PWRDWN BIT(16)
-
-#define GUID HSOTG_REG(0x003c)
-#define GSNPSID HSOTG_REG(0x0040)
-#define GHWCFG1 HSOTG_REG(0x0044)
-#define GSNPSID_ID_MASK GENMASK(31, 16)
-
-#define GHWCFG2 HSOTG_REG(0x0048)
-#define GHWCFG2_OTG_ENABLE_IC_USB BIT(31)
-#define GHWCFG2_DEV_TOKEN_Q_DEPTH_MASK (0x1f << 26)
-#define GHWCFG2_DEV_TOKEN_Q_DEPTH_SHIFT 26
-#define GHWCFG2_HOST_PERIO_TX_Q_DEPTH_MASK (0x3 << 24)
-#define GHWCFG2_HOST_PERIO_TX_Q_DEPTH_SHIFT 24
-#define GHWCFG2_NONPERIO_TX_Q_DEPTH_MASK (0x3 << 22)
-#define GHWCFG2_NONPERIO_TX_Q_DEPTH_SHIFT 22
-#define GHWCFG2_MULTI_PROC_INT BIT(20)
-#define GHWCFG2_DYNAMIC_FIFO BIT(19)
-#define GHWCFG2_PERIO_EP_SUPPORTED BIT(18)
-#define GHWCFG2_NUM_HOST_CHAN_MASK (0xf << 14)
-#define GHWCFG2_NUM_HOST_CHAN_SHIFT 14
-#define GHWCFG2_NUM_DEV_EP_MASK (0xf << 10)
-#define GHWCFG2_NUM_DEV_EP_SHIFT 10
-#define GHWCFG2_FS_PHY_TYPE_MASK (0x3 << 8)
-#define GHWCFG2_FS_PHY_TYPE_SHIFT 8
-#define GHWCFG2_FS_PHY_TYPE_NOT_SUPPORTED 0
-#define GHWCFG2_FS_PHY_TYPE_DEDICATED 1
-#define GHWCFG2_FS_PHY_TYPE_SHARED_UTMI 2
-#define GHWCFG2_FS_PHY_TYPE_SHARED_ULPI 3
-#define GHWCFG2_HS_PHY_TYPE_MASK (0x3 << 6)
-#define GHWCFG2_HS_PHY_TYPE_SHIFT 6
-#define GHWCFG2_HS_PHY_TYPE_NOT_SUPPORTED 0
-#define GHWCFG2_HS_PHY_TYPE_UTMI 1
-#define GHWCFG2_HS_PHY_TYPE_ULPI 2
-#define GHWCFG2_HS_PHY_TYPE_UTMI_ULPI 3
-#define GHWCFG2_POINT2POINT BIT(5)
-#define GHWCFG2_ARCHITECTURE_MASK (0x3 << 3)
-#define GHWCFG2_ARCHITECTURE_SHIFT 3
-#define GHWCFG2_SLAVE_ONLY_ARCH 0
-#define GHWCFG2_EXT_DMA_ARCH 1
-#define GHWCFG2_INT_DMA_ARCH 2
-#define GHWCFG2_OP_MODE_MASK (0x7 << 0)
-#define GHWCFG2_OP_MODE_SHIFT 0
-#define GHWCFG2_OP_MODE_HNP_SRP_CAPABLE 0
-#define GHWCFG2_OP_MODE_SRP_ONLY_CAPABLE 1
-#define GHWCFG2_OP_MODE_NO_HNP_SRP_CAPABLE 2
-#define GHWCFG2_OP_MODE_SRP_CAPABLE_DEVICE 3
-#define GHWCFG2_OP_MODE_NO_SRP_CAPABLE_DEVICE 4
-#define GHWCFG2_OP_MODE_SRP_CAPABLE_HOST 5
-#define GHWCFG2_OP_MODE_NO_SRP_CAPABLE_HOST 6
-#define GHWCFG2_OP_MODE_UNDEFINED 7
-
-#define GHWCFG3 HSOTG_REG(0x004c)
-#define GHWCFG3_DFIFO_DEPTH_MASK (0xffff << 16)
-#define GHWCFG3_DFIFO_DEPTH_SHIFT 16
-#define GHWCFG3_OTG_LPM_EN BIT(15)
-#define GHWCFG3_BC_SUPPORT BIT(14)
-#define GHWCFG3_OTG_ENABLE_HSIC BIT(13)
-#define GHWCFG3_ADP_SUPP BIT(12)
-#define GHWCFG3_SYNCH_RESET_TYPE BIT(11)
-#define GHWCFG3_OPTIONAL_FEATURES BIT(10)
-#define GHWCFG3_VENDOR_CTRL_IF BIT(9)
-#define GHWCFG3_I2C BIT(8)
-#define GHWCFG3_OTG_FUNC BIT(7)
-#define GHWCFG3_PACKET_SIZE_CNTR_WIDTH_MASK (0x7 << 4)
-#define GHWCFG3_PACKET_SIZE_CNTR_WIDTH_SHIFT 4
-#define GHWCFG3_XFER_SIZE_CNTR_WIDTH_MASK (0xf << 0)
-#define GHWCFG3_XFER_SIZE_CNTR_WIDTH_SHIFT 0
-
-#define GHWCFG4 HSOTG_REG(0x0050)
-#define GHWCFG4_DESC_DMA_DYN BIT(31)
-#define GHWCFG4_DESC_DMA BIT(30)
-#define GHWCFG4_NUM_IN_EPS_MASK (0xf << 26)
-#define GHWCFG4_NUM_IN_EPS_SHIFT 26
-#define GHWCFG4_DED_FIFO_EN BIT(25)
-#define GHWCFG4_DED_FIFO_SHIFT 25
-#define GHWCFG4_SESSION_END_FILT_EN BIT(24)
-#define GHWCFG4_B_VALID_FILT_EN BIT(23)
-#define GHWCFG4_A_VALID_FILT_EN BIT(22)
-#define GHWCFG4_VBUS_VALID_FILT_EN BIT(21)
-#define GHWCFG4_IDDIG_FILT_EN BIT(20)
-#define GHWCFG4_NUM_DEV_MODE_CTRL_EP_MASK (0xf << 16)
-#define GHWCFG4_NUM_DEV_MODE_CTRL_EP_SHIFT 16
-#define GHWCFG4_UTMI_PHY_DATA_WIDTH_MASK (0x3 << 14)
-#define GHWCFG4_UTMI_PHY_DATA_WIDTH_SHIFT 14
-#define GHWCFG4_UTMI_PHY_DATA_WIDTH_8 0
-#define GHWCFG4_UTMI_PHY_DATA_WIDTH_16 1
-#define GHWCFG4_UTMI_PHY_DATA_WIDTH_8_OR_16 2
-#define GHWCFG4_ACG_SUPPORTED BIT(12)
-#define GHWCFG4_IPG_ISOC_SUPPORTED BIT(11)
-#define GHWCFG4_SERVICE_INTERVAL_SUPPORTED BIT(10)
-#define GHWCFG4_XHIBER BIT(7)
-#define GHWCFG4_HIBER BIT(6)
-#define GHWCFG4_MIN_AHB_FREQ BIT(5)
-#define GHWCFG4_POWER_OPTIMIZ BIT(4)
-#define GHWCFG4_NUM_DEV_PERIO_IN_EP_MASK (0xf << 0)
-#define GHWCFG4_NUM_DEV_PERIO_IN_EP_SHIFT 0
-
-#define GLPMCFG HSOTG_REG(0x0054)
-#define GLPMCFG_INVSELHSIC BIT(31)
-#define GLPMCFG_HSICCON BIT(30)
-#define GLPMCFG_RSTRSLPSTS BIT(29)
-#define GLPMCFG_ENBESL BIT(28)
-#define GLPMCFG_LPM_RETRYCNT_STS_MASK (0x7 << 25)
-#define GLPMCFG_LPM_RETRYCNT_STS_SHIFT 25
-#define GLPMCFG_SNDLPM BIT(24)
-#define GLPMCFG_RETRY_CNT_MASK (0x7 << 21)
-#define GLPMCFG_RETRY_CNT_SHIFT 21
-#define GLPMCFG_LPM_REJECT_CTRL_CONTROL BIT(21)
-#define GLPMCFG_LPM_ACCEPT_CTRL_ISOC BIT(22)
-#define GLPMCFG_LPM_CHNL_INDX_MASK (0xf << 17)
-#define GLPMCFG_LPM_CHNL_INDX_SHIFT 17
-#define GLPMCFG_L1RESUMEOK BIT(16)
-#define GLPMCFG_SLPSTS BIT(15)
-#define GLPMCFG_COREL1RES_MASK (0x3 << 13)
-#define GLPMCFG_COREL1RES_SHIFT 13
-#define GLPMCFG_HIRD_THRES_MASK (0x1f << 8)
-#define GLPMCFG_HIRD_THRES_SHIFT 8
-#define GLPMCFG_HIRD_THRES_EN (0x10 << 8)
-#define GLPMCFG_ENBLSLPM BIT(7)
-#define GLPMCFG_BREMOTEWAKE BIT(6)
-#define GLPMCFG_HIRD_MASK (0xf << 2)
-#define GLPMCFG_HIRD_SHIFT 2
-#define GLPMCFG_APPL1RES BIT(1)
-#define GLPMCFG_LPMCAP BIT(0)
-
-#define GPWRDN HSOTG_REG(0x0058)
-#define GPWRDN_MULT_VAL_ID_BC_MASK (0x1f << 24)
-#define GPWRDN_MULT_VAL_ID_BC_SHIFT 24
-#define GPWRDN_ADP_INT BIT(23)
-#define GPWRDN_BSESSVLD BIT(22)
-#define GPWRDN_IDSTS BIT(21)
-#define GPWRDN_LINESTATE_MASK (0x3 << 19)
-#define GPWRDN_LINESTATE_SHIFT 19
-#define GPWRDN_STS_CHGINT_MSK BIT(18)
-#define GPWRDN_STS_CHGINT BIT(17)
-#define GPWRDN_SRP_DET_MSK BIT(16)
-#define GPWRDN_SRP_DET BIT(15)
-#define GPWRDN_CONNECT_DET_MSK BIT(14)
-#define GPWRDN_CONNECT_DET BIT(13)
-#define GPWRDN_DISCONN_DET_MSK BIT(12)
-#define GPWRDN_DISCONN_DET BIT(11)
-#define GPWRDN_RST_DET_MSK BIT(10)
-#define GPWRDN_RST_DET BIT(9)
-#define GPWRDN_LNSTSCHG_MSK BIT(8)
-#define GPWRDN_LNSTSCHG BIT(7)
-#define GPWRDN_DIS_VBUS BIT(6)
-#define GPWRDN_PWRDNSWTCH BIT(5)
-#define GPWRDN_PWRDNRSTN BIT(4)
-#define GPWRDN_PWRDNCLMP BIT(3)
-#define GPWRDN_RESTORE BIT(2)
-#define GPWRDN_PMUACTV BIT(1)
-#define GPWRDN_PMUINTSEL BIT(0)
-
-#define GDFIFOCFG HSOTG_REG(0x005c)
-#define GDFIFOCFG_EPINFOBASE_MASK (0xffff << 16)
-#define GDFIFOCFG_EPINFOBASE_SHIFT 16
-#define GDFIFOCFG_GDFIFOCFG_MASK (0xffff << 0)
-#define GDFIFOCFG_GDFIFOCFG_SHIFT 0
-
-#define ADPCTL HSOTG_REG(0x0060)
-#define ADPCTL_AR_MASK (0x3 << 27)
-#define ADPCTL_AR_SHIFT 27
-#define ADPCTL_ADP_TMOUT_INT_MSK BIT(26)
-#define ADPCTL_ADP_SNS_INT_MSK BIT(25)
-#define ADPCTL_ADP_PRB_INT_MSK BIT(24)
-#define ADPCTL_ADP_TMOUT_INT BIT(23)
-#define ADPCTL_ADP_SNS_INT BIT(22)
-#define ADPCTL_ADP_PRB_INT BIT(21)
-#define ADPCTL_ADPENA BIT(20)
-#define ADPCTL_ADPRES BIT(19)
-#define ADPCTL_ENASNS BIT(18)
-#define ADPCTL_ENAPRB BIT(17)
-#define ADPCTL_RTIM_MASK (0x7ff << 6)
-#define ADPCTL_RTIM_SHIFT 6
-#define ADPCTL_PRB_PER_MASK (0x3 << 4)
-#define ADPCTL_PRB_PER_SHIFT 4
-#define ADPCTL_PRB_DELTA_MASK (0x3 << 2)
-#define ADPCTL_PRB_DELTA_SHIFT 2
-#define ADPCTL_PRB_DSCHRG_MASK (0x3 << 0)
-#define ADPCTL_PRB_DSCHRG_SHIFT 0
-
-#define GREFCLK HSOTG_REG(0x0064)
-#define GREFCLK_REFCLKPER_MASK (0x1ffff << 15)
-#define GREFCLK_REFCLKPER_SHIFT 15
-#define GREFCLK_REF_CLK_MODE BIT(14)
-#define GREFCLK_SOF_CNT_WKUP_ALERT_MASK (0x3ff)
-#define GREFCLK_SOF_CNT_WKUP_ALERT_SHIFT 0
-
-#define GINTMSK2 HSOTG_REG(0x0068)
-#define GINTMSK2_WKUP_ALERT_INT_MSK BIT(0)
-
-#define GINTSTS2 HSOTG_REG(0x006c)
-#define GINTSTS2_WKUP_ALERT_INT BIT(0)
-
-#define HPTXFSIZ HSOTG_REG(0x100)
-/* Use FIFOSIZE_* constants to access this register */
-
-#define DPTXFSIZN(_a) HSOTG_REG(0x104 + (((_a) - 1) * 4))
-/* Use FIFOSIZE_* constants to access this register */
-
-/* These apply to the GNPTXFSIZ, HPTXFSIZ and DPTXFSIZN registers */
-#define FIFOSIZE_DEPTH_MASK (0xffff << 16)
-#define FIFOSIZE_DEPTH_SHIFT 16
-#define FIFOSIZE_STARTADDR_MASK (0xffff << 0)
-#define FIFOSIZE_STARTADDR_SHIFT 0
-#define FIFOSIZE_DEPTH_GET(_x) (((_x) >> 16) & 0xffff)
-
-/* Device mode registers */
-
-#define DCFG HSOTG_REG(0x800)
-#define DCFG_DESCDMA_EN BIT(23)
-#define DCFG_EPMISCNT_MASK (0x1f << 18)
-#define DCFG_EPMISCNT_SHIFT 18
-#define DCFG_EPMISCNT_LIMIT 0x1f
-#define DCFG_EPMISCNT(_x) ((_x) << 18)
-#define DCFG_IPG_ISOC_SUPPORDED BIT(17)
-#define DCFG_PERFRINT_MASK (0x3 << 11)
-#define DCFG_PERFRINT_SHIFT 11
-#define DCFG_PERFRINT_LIMIT 0x3
-#define DCFG_PERFRINT(_x) ((_x) << 11)
-#define DCFG_DEVADDR_MASK (0x7f << 4)
-#define DCFG_DEVADDR_SHIFT 4
-#define DCFG_DEVADDR_LIMIT 0x7f
-#define DCFG_DEVADDR(_x) ((_x) << 4)
-#define DCFG_NZ_STS_OUT_HSHK BIT(2)
-#define DCFG_DEVSPD_MASK (0x3 << 0)
-#define DCFG_DEVSPD_SHIFT 0
-#define DCFG_DEVSPD_HS 0
-#define DCFG_DEVSPD_FS 1
-#define DCFG_DEVSPD_LS 2
-#define DCFG_DEVSPD_FS48 3
-
-#define DCTL HSOTG_REG(0x804)
-#define DCTL_SERVICE_INTERVAL_SUPPORTED BIT(19)
-#define DCTL_PWRONPRGDONE BIT(11)
-#define DCTL_CGOUTNAK BIT(10)
-#define DCTL_SGOUTNAK BIT(9)
-#define DCTL_CGNPINNAK BIT(8)
-#define DCTL_SGNPINNAK BIT(7)
-#define DCTL_TSTCTL_MASK (0x7 << 4)
-#define DCTL_TSTCTL_SHIFT 4
-#define DCTL_GOUTNAKSTS BIT(3)
-#define DCTL_GNPINNAKSTS BIT(2)
-#define DCTL_SFTDISCON BIT(1)
-#define DCTL_RMTWKUPSIG BIT(0)
-
-#define DSTS HSOTG_REG(0x808)
-#define DSTS_SOFFN_MASK (0x3fff << 8)
-#define DSTS_SOFFN_SHIFT 8
-#define DSTS_SOFFN_LIMIT 0x3fff
-#define DSTS_SOFFN(_x) ((_x) << 8)
-#define DSTS_ERRATICERR BIT(3)
-#define DSTS_ENUMSPD_MASK (0x3 << 1)
-#define DSTS_ENUMSPD_SHIFT 1
-#define DSTS_ENUMSPD_HS 0
-#define DSTS_ENUMSPD_FS 1
-#define DSTS_ENUMSPD_LS 2
-#define DSTS_ENUMSPD_FS48 3
-#define DSTS_SUSPSTS BIT(0)
-
-#define DIEPMSK HSOTG_REG(0x810)
-#define DIEPMSK_NAKMSK BIT(13)
-#define DIEPMSK_BNAININTRMSK BIT(9)
-#define DIEPMSK_TXFIFOUNDRNMSK BIT(8)
-#define DIEPMSK_TXFIFOEMPTY BIT(7)
-#define DIEPMSK_INEPNAKEFFMSK BIT(6)
-#define DIEPMSK_INTKNEPMISMSK BIT(5)
-#define DIEPMSK_INTKNTXFEMPMSK BIT(4)
-#define DIEPMSK_TIMEOUTMSK BIT(3)
-#define DIEPMSK_AHBERRMSK BIT(2)
-#define DIEPMSK_EPDISBLDMSK BIT(1)
-#define DIEPMSK_XFERCOMPLMSK BIT(0)
-
-#define DOEPMSK HSOTG_REG(0x814)
-#define DOEPMSK_BNAMSK BIT(9)
-#define DOEPMSK_BACK2BACKSETUP BIT(6)
-#define DOEPMSK_STSPHSERCVDMSK BIT(5)
-#define DOEPMSK_OUTTKNEPDISMSK BIT(4)
-#define DOEPMSK_SETUPMSK BIT(3)
-#define DOEPMSK_AHBERRMSK BIT(2)
-#define DOEPMSK_EPDISBLDMSK BIT(1)
-#define DOEPMSK_XFERCOMPLMSK BIT(0)
-
-#define DAINT HSOTG_REG(0x818)
-#define DAINTMSK HSOTG_REG(0x81C)
-#define DAINT_OUTEP_SHIFT 16
-#define DAINT_OUTEP(_x) (1 << ((_x) + 16))
-#define DAINT_INEP(_x) (1 << (_x))
-
-#define DTKNQR1 HSOTG_REG(0x820)
-#define DTKNQR2 HSOTG_REG(0x824)
-#define DTKNQR3 HSOTG_REG(0x830)
-#define DTKNQR4 HSOTG_REG(0x834)
-#define DIEPEMPMSK HSOTG_REG(0x834)
-
-#define DVBUSDIS HSOTG_REG(0x828)
-#define DVBUSPULSE HSOTG_REG(0x82C)
-
-#define DIEPCTL0 HSOTG_REG(0x900)
-#define DIEPCTL(_a) HSOTG_REG(0x900 + ((_a) * 0x20))
-
-#define DOEPCTL0 HSOTG_REG(0xB00)
-#define DOEPCTL(_a) HSOTG_REG(0xB00 + ((_a) * 0x20))
-
-/* EP0 specialness:
- * bits[29..28] - reserved (no SetD0PID, SetD1PID)
- * bits[25..22] - should always be zero, this isn't a periodic endpoint
- * bits[10..0] - MPS setting different for EP0
- */
-#define D0EPCTL_MPS_MASK (0x3 << 0)
-#define D0EPCTL_MPS_SHIFT 0
-#define D0EPCTL_MPS_64 0
-#define D0EPCTL_MPS_32 1
-#define D0EPCTL_MPS_16 2
-#define D0EPCTL_MPS_8 3
-
-#define DXEPCTL_EPENA BIT(31)
-#define DXEPCTL_EPDIS BIT(30)
-#define DXEPCTL_SETD1PID BIT(29)
-#define DXEPCTL_SETODDFR BIT(29)
-#define DXEPCTL_SETD0PID BIT(28)
-#define DXEPCTL_SETEVENFR BIT(28)
-#define DXEPCTL_SNAK BIT(27)
-#define DXEPCTL_CNAK BIT(26)
-#define DXEPCTL_TXFNUM_MASK (0xf << 22)
-#define DXEPCTL_TXFNUM_SHIFT 22
-#define DXEPCTL_TXFNUM_LIMIT 0xf
-#define DXEPCTL_TXFNUM(_x) ((_x) << 22)
-#define DXEPCTL_STALL BIT(21)
-#define DXEPCTL_SNP BIT(20)
-#define DXEPCTL_EPTYPE_MASK (0x3 << 18)
-#define DXEPCTL_EPTYPE_CONTROL (0x0 << 18)
-#define DXEPCTL_EPTYPE_ISO (0x1 << 18)
-#define DXEPCTL_EPTYPE_BULK (0x2 << 18)
-#define DXEPCTL_EPTYPE_INTERRUPT (0x3 << 18)
-
-#define DXEPCTL_NAKSTS BIT(17)
-#define DXEPCTL_DPID BIT(16)
-#define DXEPCTL_EOFRNUM BIT(16)
-#define DXEPCTL_USBACTEP BIT(15)
-#define DXEPCTL_NEXTEP_MASK (0xf << 11)
-#define DXEPCTL_NEXTEP_SHIFT 11
-#define DXEPCTL_NEXTEP_LIMIT 0xf
-#define DXEPCTL_NEXTEP(_x) ((_x) << 11)
-#define DXEPCTL_MPS_MASK (0x7ff << 0)
-#define DXEPCTL_MPS_SHIFT 0
-#define DXEPCTL_MPS_LIMIT 0x7ff
-#define DXEPCTL_MPS(_x) ((_x) << 0)
-
-#define DIEPINT(_a) HSOTG_REG(0x908 + ((_a) * 0x20))
-#define DOEPINT(_a) HSOTG_REG(0xB08 + ((_a) * 0x20))
-#define DXEPINT_SETUP_RCVD BIT(15)
-#define DXEPINT_NYETINTRPT BIT(14)
-#define DXEPINT_NAKINTRPT BIT(13)
-#define DXEPINT_BBLEERRINTRPT BIT(12)
-#define DXEPINT_PKTDRPSTS BIT(11)
-#define DXEPINT_BNAINTR BIT(9)
-#define DXEPINT_TXFIFOUNDRN BIT(8)
-#define DXEPINT_OUTPKTERR BIT(8)
-#define DXEPINT_TXFEMP BIT(7)
-#define DXEPINT_INEPNAKEFF BIT(6)
-#define DXEPINT_BACK2BACKSETUP BIT(6)
-#define DXEPINT_INTKNEPMIS BIT(5)
-#define DXEPINT_STSPHSERCVD BIT(5)
-#define DXEPINT_INTKNTXFEMP BIT(4)
-#define DXEPINT_OUTTKNEPDIS BIT(4)
-#define DXEPINT_TIMEOUT BIT(3)
-#define DXEPINT_SETUP BIT(3)
-#define DXEPINT_AHBERR BIT(2)
-#define DXEPINT_EPDISBLD BIT(1)
-#define DXEPINT_XFERCOMPL BIT(0)
-
-#define DIEPTSIZ0 HSOTG_REG(0x910)
-#define DIEPTSIZ0_PKTCNT_MASK (0x3 << 19)
-#define DIEPTSIZ0_PKTCNT_SHIFT 19
-#define DIEPTSIZ0_PKTCNT_LIMIT 0x3
-#define DIEPTSIZ0_PKTCNT(_x) ((_x) << 19)
-#define DIEPTSIZ0_XFERSIZE_MASK (0x7f << 0)
-#define DIEPTSIZ0_XFERSIZE_SHIFT 0
-#define DIEPTSIZ0_XFERSIZE_LIMIT 0x7f
-#define DIEPTSIZ0_XFERSIZE(_x) ((_x) << 0)
-
-#define DOEPTSIZ0 HSOTG_REG(0xB10)
-#define DOEPTSIZ0_SUPCNT_MASK (0x3 << 29)
-#define DOEPTSIZ0_SUPCNT_SHIFT 29
-#define DOEPTSIZ0_SUPCNT_LIMIT 0x3
-#define DOEPTSIZ0_SUPCNT(_x) ((_x) << 29)
-#define DOEPTSIZ0_PKTCNT BIT(19)
-#define DOEPTSIZ0_XFERSIZE_MASK (0x7f << 0)
-#define DOEPTSIZ0_XFERSIZE_SHIFT 0
-
-#define DIEPTSIZ(_a) HSOTG_REG(0x910 + ((_a) * 0x20))
-#define DOEPTSIZ(_a) HSOTG_REG(0xB10 + ((_a) * 0x20))
-#define DXEPTSIZ_MC_MASK (0x3 << 29)
-#define DXEPTSIZ_MC_SHIFT 29
-#define DXEPTSIZ_MC_LIMIT 0x3
-#define DXEPTSIZ_MC(_x) ((_x) << 29)
-#define DXEPTSIZ_PKTCNT_MASK (0x3ff << 19)
-#define DXEPTSIZ_PKTCNT_SHIFT 19
-#define DXEPTSIZ_PKTCNT_LIMIT 0x3ff
-#define DXEPTSIZ_PKTCNT_GET(_v) (((_v) >> 19) & 0x3ff)
-#define DXEPTSIZ_PKTCNT(_x) ((_x) << 19)
-#define DXEPTSIZ_XFERSIZE_MASK (0x7ffff << 0)
-#define DXEPTSIZ_XFERSIZE_SHIFT 0
-#define DXEPTSIZ_XFERSIZE_LIMIT 0x7ffff
-#define DXEPTSIZ_XFERSIZE_GET(_v) (((_v) >> 0) & 0x7ffff)
-#define DXEPTSIZ_XFERSIZE(_x) ((_x) << 0)
-
-#define DIEPDMA(_a) HSOTG_REG(0x914 + ((_a) * 0x20))
-#define DOEPDMA(_a) HSOTG_REG(0xB14 + ((_a) * 0x20))
-
-#define DTXFSTS(_a) HSOTG_REG(0x918 + ((_a) * 0x20))
-
-#define PCGCTL HSOTG_REG(0x0e00)
-#define PCGCTL_IF_DEV_MODE BIT(31)
-#define PCGCTL_P2HD_PRT_SPD_MASK (0x3 << 29)
-#define PCGCTL_P2HD_PRT_SPD_SHIFT 29
-#define PCGCTL_P2HD_DEV_ENUM_SPD_MASK (0x3 << 27)
-#define PCGCTL_P2HD_DEV_ENUM_SPD_SHIFT 27
-#define PCGCTL_MAC_DEV_ADDR_MASK (0x7f << 20)
-#define PCGCTL_MAC_DEV_ADDR_SHIFT 20
-#define PCGCTL_MAX_TERMSEL BIT(19)
-#define PCGCTL_MAX_XCVRSELECT_MASK (0x3 << 17)
-#define PCGCTL_MAX_XCVRSELECT_SHIFT 17
-#define PCGCTL_PORT_POWER BIT(16)
-#define PCGCTL_PRT_CLK_SEL_MASK (0x3 << 14)
-#define PCGCTL_PRT_CLK_SEL_SHIFT 14
-#define PCGCTL_ESS_REG_RESTORED BIT(13)
-#define PCGCTL_EXTND_HIBER_SWITCH BIT(12)
-#define PCGCTL_EXTND_HIBER_PWRCLMP BIT(11)
-#define PCGCTL_ENBL_EXTND_HIBER BIT(10)
-#define PCGCTL_RESTOREMODE BIT(9)
-#define PCGCTL_RESETAFTSUSP BIT(8)
-#define PCGCTL_DEEP_SLEEP BIT(7)
-#define PCGCTL_PHY_IN_SLEEP BIT(6)
-#define PCGCTL_ENBL_SLEEP_GATING BIT(5)
-#define PCGCTL_RSTPDWNMODULE BIT(3)
-#define PCGCTL_PWRCLMP BIT(2)
-#define PCGCTL_GATEHCLK BIT(1)
-#define PCGCTL_STOPPCLK BIT(0)
-
-#define PCGCCTL1 HSOTG_REG(0xe04)
-#define PCGCCTL1_TIMER (0x3 << 1)
-#define PCGCCTL1_GATEEN BIT(0)
-
-#define EPFIFO(_a) HSOTG_REG(0x1000 + ((_a) * 0x1000))
-
-/* Host Mode Registers */
-
-#define HCFG HSOTG_REG(0x0400)
-#define HCFG_MODECHTIMEN BIT(31)
-#define HCFG_PERSCHEDENA BIT(26)
-#define HCFG_FRLISTEN_MASK (0x3 << 24)
-#define HCFG_FRLISTEN_SHIFT 24
-#define HCFG_FRLISTEN_8 (0 << 24)
-#define FRLISTEN_8_SIZE 8
-#define HCFG_FRLISTEN_16 BIT(24)
-#define FRLISTEN_16_SIZE 16
-#define HCFG_FRLISTEN_32 (2 << 24)
-#define FRLISTEN_32_SIZE 32
-#define HCFG_FRLISTEN_64 (3 << 24)
-#define FRLISTEN_64_SIZE 64
-#define HCFG_DESCDMA BIT(23)
-#define HCFG_RESVALID_MASK (0xff << 8)
-#define HCFG_RESVALID_SHIFT 8
-#define HCFG_ENA32KHZ BIT(7)
-#define HCFG_FSLSSUPP BIT(2)
-#define HCFG_FSLSPCLKSEL_MASK (0x3 << 0)
-#define HCFG_FSLSPCLKSEL_SHIFT 0
-#define HCFG_FSLSPCLKSEL_30_60_MHZ 0
-#define HCFG_FSLSPCLKSEL_48_MHZ 1
-#define HCFG_FSLSPCLKSEL_6_MHZ 2
-
-#define HFIR HSOTG_REG(0x0404)
-#define HFIR_FRINT_MASK (0xffff << 0)
-#define HFIR_FRINT_SHIFT 0
-#define HFIR_RLDCTRL BIT(16)
-
-#define HFNUM HSOTG_REG(0x0408)
-#define HFNUM_FRREM_MASK (0xffff << 16)
-#define HFNUM_FRREM_SHIFT 16
-#define HFNUM_FRNUM_MASK (0xffff << 0)
-#define HFNUM_FRNUM_SHIFT 0
-#define HFNUM_MAX_FRNUM 0x3fff
-
-#define HPTXSTS HSOTG_REG(0x0410)
-#define TXSTS_QTOP_ODD BIT(31)
-#define TXSTS_QTOP_CHNEP_MASK (0xf << 27)
-#define TXSTS_QTOP_CHNEP_SHIFT 27
-#define TXSTS_QTOP_TOKEN_MASK (0x3 << 25)
-#define TXSTS_QTOP_TOKEN_SHIFT 25
-#define TXSTS_QTOP_TERMINATE BIT(24)
-#define TXSTS_QSPCAVAIL_MASK (0xff << 16)
-#define TXSTS_QSPCAVAIL_SHIFT 16
-#define TXSTS_FSPCAVAIL_MASK (0xffff << 0)
-#define TXSTS_FSPCAVAIL_SHIFT 0
-
-#define HAINT HSOTG_REG(0x0414)
-#define HAINTMSK HSOTG_REG(0x0418)
-#define HFLBADDR HSOTG_REG(0x041c)
-
-#define HPRT0 HSOTG_REG(0x0440)
-#define HPRT0_SPD_MASK (0x3 << 17)
-#define HPRT0_SPD_SHIFT 17
-#define HPRT0_SPD_HIGH_SPEED 0
-#define HPRT0_SPD_FULL_SPEED 1
-#define HPRT0_SPD_LOW_SPEED 2
-#define HPRT0_TSTCTL_MASK (0xf << 13)
-#define HPRT0_TSTCTL_SHIFT 13
-#define HPRT0_PWR BIT(12)
-#define HPRT0_LNSTS_MASK (0x3 << 10)
-#define HPRT0_LNSTS_SHIFT 10
-#define HPRT0_RST BIT(8)
-#define HPRT0_SUSP BIT(7)
-#define HPRT0_RES BIT(6)
-#define HPRT0_OVRCURRCHG BIT(5)
-#define HPRT0_OVRCURRACT BIT(4)
-#define HPRT0_ENACHG BIT(3)
-#define HPRT0_ENA BIT(2)
-#define HPRT0_CONNDET BIT(1)
-#define HPRT0_CONNSTS BIT(0)
-
-#define HCCHAR(_ch) HSOTG_REG(0x0500 + 0x20 * (_ch))
-#define HCCHAR_CHENA BIT(31)
-#define HCCHAR_CHDIS BIT(30)
-#define HCCHAR_ODDFRM BIT(29)
-#define HCCHAR_DEVADDR_MASK (0x7f << 22)
-#define HCCHAR_DEVADDR_SHIFT 22
-#define HCCHAR_MULTICNT_MASK (0x3 << 20)
-#define HCCHAR_MULTICNT_SHIFT 20
-#define HCCHAR_EPTYPE_MASK (0x3 << 18)
-#define HCCHAR_EPTYPE_SHIFT 18
-#define HCCHAR_LSPDDEV BIT(17)
-#define HCCHAR_EPDIR BIT(15)
-#define HCCHAR_EPNUM_MASK (0xf << 11)
-#define HCCHAR_EPNUM_SHIFT 11
-#define HCCHAR_MPS_MASK (0x7ff << 0)
-#define HCCHAR_MPS_SHIFT 0
-
-#define HCSPLT(_ch) HSOTG_REG(0x0504 + 0x20 * (_ch))
-#define HCSPLT_SPLTENA BIT(31)
-#define HCSPLT_COMPSPLT BIT(16)
-#define HCSPLT_XACTPOS_MASK (0x3 << 14)
-#define HCSPLT_XACTPOS_SHIFT 14
-#define HCSPLT_XACTPOS_MID 0
-#define HCSPLT_XACTPOS_END 1
-#define HCSPLT_XACTPOS_BEGIN 2
-#define HCSPLT_XACTPOS_ALL 3
-#define HCSPLT_HUBADDR_MASK (0x7f << 7)
-#define HCSPLT_HUBADDR_SHIFT 7
-#define HCSPLT_PRTADDR_MASK (0x7f << 0)
-#define HCSPLT_PRTADDR_SHIFT 0
-
-#define HCINT(_ch) HSOTG_REG(0x0508 + 0x20 * (_ch))
-#define HCINTMSK(_ch) HSOTG_REG(0x050c + 0x20 * (_ch))
-#define HCINTMSK_RESERVED14_31 (0x3ffff << 14)
-#define HCINTMSK_FRM_LIST_ROLL BIT(13)
-#define HCINTMSK_XCS_XACT BIT(12)
-#define HCINTMSK_BNA BIT(11)
-#define HCINTMSK_DATATGLERR BIT(10)
-#define HCINTMSK_FRMOVRUN BIT(9)
-#define HCINTMSK_BBLERR BIT(8)
-#define HCINTMSK_XACTERR BIT(7)
-#define HCINTMSK_NYET BIT(6)
-#define HCINTMSK_ACK BIT(5)
-#define HCINTMSK_NAK BIT(4)
-#define HCINTMSK_STALL BIT(3)
-#define HCINTMSK_AHBERR BIT(2)
-#define HCINTMSK_CHHLTD BIT(1)
-#define HCINTMSK_XFERCOMPL BIT(0)
-
-#define HCTSIZ(_ch) HSOTG_REG(0x0510 + 0x20 * (_ch))
-#define TSIZ_DOPNG BIT(31)
-#define TSIZ_SC_MC_PID_MASK (0x3 << 29)
-#define TSIZ_SC_MC_PID_SHIFT 29
-#define TSIZ_SC_MC_PID_DATA0 0
-#define TSIZ_SC_MC_PID_DATA2 1
-#define TSIZ_SC_MC_PID_DATA1 2
-#define TSIZ_SC_MC_PID_MDATA 3
-#define TSIZ_SC_MC_PID_SETUP 3
-#define TSIZ_PKTCNT_MASK (0x3ff << 19)
-#define TSIZ_PKTCNT_SHIFT 19
-#define TSIZ_NTD_MASK (0xff << 8)
-#define TSIZ_NTD_SHIFT 8
-#define TSIZ_SCHINFO_MASK (0xff << 0)
-#define TSIZ_SCHINFO_SHIFT 0
-#define TSIZ_XFERSIZE_MASK (0x7ffff << 0)
-#define TSIZ_XFERSIZE_SHIFT 0
-
-#define HCDMA(_ch) HSOTG_REG(0x0514 + 0x20 * (_ch))
-
-#define HCDMAB(_ch) HSOTG_REG(0x051c + 0x20 * (_ch))
-
-#define HCFIFO(_ch) HSOTG_REG(0x1000 + 0x1000 * (_ch))
-
-/**
- * struct dwc2_dma_desc - DMA descriptor structure,
- * used for both host and gadget modes
- *
- * @status: DMA descriptor status quadlet
- * @buf: DMA descriptor data buffer pointer
- *
- * DMA Descriptor structure contains two quadlets:
- * Status quadlet and Data buffer pointer.
- */
-struct dwc2_dma_desc {
- uint32_t status;
- uint32_t buf;
-} __packed;
-
-/* Host Mode DMA descriptor status quadlet */
-
-#define HOST_DMA_A BIT(31)
-#define HOST_DMA_STS_MASK (0x3 << 28)
-#define HOST_DMA_STS_SHIFT 28
-#define HOST_DMA_STS_PKTERR BIT(28)
-#define HOST_DMA_EOL BIT(26)
-#define HOST_DMA_IOC BIT(25)
-#define HOST_DMA_SUP BIT(24)
-#define HOST_DMA_ALT_QTD BIT(23)
-#define HOST_DMA_QTD_OFFSET_MASK (0x3f << 17)
-#define HOST_DMA_QTD_OFFSET_SHIFT 17
-#define HOST_DMA_ISOC_NBYTES_MASK (0xfff << 0)
-#define HOST_DMA_ISOC_NBYTES_SHIFT 0
-#define HOST_DMA_NBYTES_MASK (0x1ffff << 0)
-#define HOST_DMA_NBYTES_SHIFT 0
-#define HOST_DMA_NBYTES_LIMIT 131071
-
-/* Device Mode DMA descriptor status quadlet */
-
-#define DEV_DMA_BUFF_STS_MASK (0x3 << 30)
-#define DEV_DMA_BUFF_STS_SHIFT 30
-#define DEV_DMA_BUFF_STS_HREADY 0
-#define DEV_DMA_BUFF_STS_DMABUSY 1
-#define DEV_DMA_BUFF_STS_DMADONE 2
-#define DEV_DMA_BUFF_STS_HBUSY 3
-#define DEV_DMA_STS_MASK (0x3 << 28)
-#define DEV_DMA_STS_SHIFT 28
-#define DEV_DMA_STS_SUCC 0
-#define DEV_DMA_STS_BUFF_FLUSH 1
-#define DEV_DMA_STS_BUFF_ERR 3
-#define DEV_DMA_L BIT(27)
-#define DEV_DMA_SHORT BIT(26)
-#define DEV_DMA_IOC BIT(25)
-#define DEV_DMA_SR BIT(24)
-#define DEV_DMA_MTRF BIT(23)
-#define DEV_DMA_ISOC_PID_MASK (0x3 << 23)
-#define DEV_DMA_ISOC_PID_SHIFT 23
-#define DEV_DMA_ISOC_PID_DATA0 0
-#define DEV_DMA_ISOC_PID_DATA2 1
-#define DEV_DMA_ISOC_PID_DATA1 2
-#define DEV_DMA_ISOC_PID_MDATA 3
-#define DEV_DMA_ISOC_FRNUM_MASK (0x7ff << 12)
-#define DEV_DMA_ISOC_FRNUM_SHIFT 12
-#define DEV_DMA_ISOC_TX_NBYTES_MASK (0xfff << 0)
-#define DEV_DMA_ISOC_TX_NBYTES_LIMIT 0xfff
-#define DEV_DMA_ISOC_RX_NBYTES_MASK (0x7ff << 0)
-#define DEV_DMA_ISOC_RX_NBYTES_LIMIT 0x7ff
-#define DEV_DMA_ISOC_NBYTES_SHIFT 0
-#define DEV_DMA_NBYTES_MASK (0xffff << 0)
-#define DEV_DMA_NBYTES_SHIFT 0
-#define DEV_DMA_NBYTES_LIMIT 0xffff
-
-#define MAX_DMA_DESC_NUM_GENERIC 64
-#define MAX_DMA_DESC_NUM_HS_ISOC 256
-
-#endif /* __DWC2_HW_H__ */
+++ /dev/null
-#ifndef HW_USB_EHCI_REGS_H
-#define HW_USB_EHCI_REGS_H
-
-/* Capability Registers Base Address - section 2.2 */
-#define CAPLENGTH 0x0000 /* 1-byte, 0x0001 reserved */
-#define HCIVERSION 0x0002 /* 2-bytes, i/f version # */
-#define HCSPARAMS 0x0004 /* 4-bytes, structural params */
-#define HCCPARAMS 0x0008 /* 4-bytes, capability params */
-#define EECP HCCPARAMS + 1
-#define HCSPPORTROUTE1 0x000c
-#define HCSPPORTROUTE2 0x0010
-
-#define USBCMD 0x0000
-#define USBCMD_RUNSTOP (1 << 0) // run / Stop
-#define USBCMD_HCRESET (1 << 1) // HC Reset
-#define USBCMD_FLS (3 << 2) // Frame List Size
-#define USBCMD_FLS_SH 2 // Frame List Size Shift
-#define USBCMD_PSE (1 << 4) // Periodic Schedule Enable
-#define USBCMD_ASE (1 << 5) // Asynch Schedule Enable
-#define USBCMD_IAAD (1 << 6) // Int Asynch Advance Doorbell
-#define USBCMD_LHCR (1 << 7) // Light Host Controller Reset
-#define USBCMD_ASPMC (3 << 8) // Async Sched Park Mode Count
-#define USBCMD_ASPME (1 << 11) // Async Sched Park Mode Enable
-#define USBCMD_ITC (0x7f << 16) // Int Threshold Control
-#define USBCMD_ITC_SH 16 // Int Threshold Control Shift
-
-#define USBSTS 0x0004
-#define USBSTS_RO_MASK 0x0000003f
-#define USBSTS_INT (1 << 0) // USB Interrupt
-#define USBSTS_ERRINT (1 << 1) // Error Interrupt
-#define USBSTS_PCD (1 << 2) // Port Change Detect
-#define USBSTS_FLR (1 << 3) // Frame List Rollover
-#define USBSTS_HSE (1 << 4) // Host System Error
-#define USBSTS_IAA (1 << 5) // Interrupt on Async Advance
-#define USBSTS_HALT (1 << 12) // HC Halted
-#define USBSTS_REC (1 << 13) // Reclamation
-#define USBSTS_PSS (1 << 14) // Periodic Schedule Status
-#define USBSTS_ASS (1 << 15) // Asynchronous Schedule Status
-
-/*
- * Interrupt enable bits correspond to the interrupt active bits in USBSTS
- * so no need to redefine here.
- */
-#define USBINTR 0x0008
-#define USBINTR_MASK 0x0000003f
-
-#define FRINDEX 0x000c
-#define CTRLDSSEGMENT 0x0010
-#define PERIODICLISTBASE 0x0014
-#define ASYNCLISTADDR 0x0018
-#define ASYNCLISTADDR_MASK 0xffffffe0
-
-#define CONFIGFLAG 0x0040
-
-/*
- * Bits that are reserved or are read-only are masked out of values
- * written to us by software
- */
-#define PORTSC_RO_MASK 0x007001c0
-#define PORTSC_RWC_MASK 0x0000002a
-#define PORTSC_WKOC_E (1 << 22) // Wake on Over Current Enable
-#define PORTSC_WKDS_E (1 << 21) // Wake on Disconnect Enable
-#define PORTSC_WKCN_E (1 << 20) // Wake on Connect Enable
-#define PORTSC_PTC (15 << 16) // Port Test Control
-#define PORTSC_PTC_SH 16 // Port Test Control shift
-#define PORTSC_PIC (3 << 14) // Port Indicator Control
-#define PORTSC_PIC_SH 14 // Port Indicator Control Shift
-#define PORTSC_POWNER (1 << 13) // Port Owner
-#define PORTSC_PPOWER (1 << 12) // Port Power
-#define PORTSC_LINESTAT (3 << 10) // Port Line Status
-#define PORTSC_LINESTAT_SH 10 // Port Line Status Shift
-#define PORTSC_PRESET (1 << 8) // Port Reset
-#define PORTSC_SUSPEND (1 << 7) // Port Suspend
-#define PORTSC_FPRES (1 << 6) // Force Port Resume
-#define PORTSC_OCC (1 << 5) // Over Current Change
-#define PORTSC_OCA (1 << 4) // Over Current Active
-#define PORTSC_PEDC (1 << 3) // Port Enable/Disable Change
-#define PORTSC_PED (1 << 2) // Port Enable/Disable
-#define PORTSC_CSC (1 << 1) // Connect Status Change
-#define PORTSC_CONNECT (1 << 0) // Current Connect Status
-
-#endif /* HW_USB_EHCI_REGS_H */
+++ /dev/null
-/*
- * "Inventra" High-speed Dual-Role Controller (MUSB-HDRC), Mentor Graphics,
- * USB2.0 OTG compliant core used in various chips.
- *
- * Only host-mode and non-DMA accesses are currently supported.
- *
- * Copyright (C) 2008 Nokia Corporation
- * Written by Andrzej Zaborowski <balrog@zabor.org>
- *
- * SPDX-License-Identifier: GPL-2.0-or-later
- */
-
-#ifndef HW_USB_MUSB_H
-#define HW_USB_MUSB_H
-
-enum musb_irq_source_e {
- musb_irq_suspend = 0,
- musb_irq_resume,
- musb_irq_rst_babble,
- musb_irq_sof,
- musb_irq_connect,
- musb_irq_disconnect,
- musb_irq_vbus_request,
- musb_irq_vbus_error,
- musb_irq_rx,
- musb_irq_tx,
- musb_set_vbus,
- musb_set_session,
- /* Add new interrupts here */
- musb_irq_max /* total number of interrupts defined */
-};
-
-/* TODO convert hcd-musb to QOM/qdev and remove MUSBReadFunc/MUSBWriteFunc */
-typedef void MUSBWriteFunc(void *opaque, hwaddr addr, uint32_t value);
-typedef uint32_t MUSBReadFunc(void *opaque, hwaddr addr);
-extern MUSBReadFunc * const musb_read[];
-extern MUSBWriteFunc * const musb_write[];
-
-typedef struct MUSBState MUSBState;
-
-MUSBState *musb_init(DeviceState *parent_device, int gpio_base);
-void musb_reset(MUSBState *s);
-uint32_t musb_core_intr_get(MUSBState *s);
-void musb_core_intr_clear(MUSBState *s, uint32_t mask);
-void musb_set_size(MUSBState *s, int epnum, int size, int is_tx);
-
-#endif
+++ /dev/null
-#ifndef HW_USB_HID_H
-#define HW_USB_HID_H
-
-/* HID interface requests */
-#define HID_GET_REPORT 0xa101
-#define HID_GET_IDLE 0xa102
-#define HID_GET_PROTOCOL 0xa103
-#define HID_SET_REPORT 0x2109
-#define HID_SET_IDLE 0x210a
-#define HID_SET_PROTOCOL 0x210b
-
-/* HID descriptor types */
-#define USB_DT_HID 0x21
-#define USB_DT_REPORT 0x22
-#define USB_DT_PHY 0x23
-
-#endif
+++ /dev/null
-#ifndef IMX_USB_PHY_H
-#define IMX_USB_PHY_H
-
-#include "hw/sysbus.h"
-#include "qemu/bitops.h"
-#include "qom/object.h"
-
-enum IMXUsbPhyRegisters {
- USBPHY_PWD,
- USBPHY_PWD_SET,
- USBPHY_PWD_CLR,
- USBPHY_PWD_TOG,
- USBPHY_TX,
- USBPHY_TX_SET,
- USBPHY_TX_CLR,
- USBPHY_TX_TOG,
- USBPHY_RX,
- USBPHY_RX_SET,
- USBPHY_RX_CLR,
- USBPHY_RX_TOG,
- USBPHY_CTRL,
- USBPHY_CTRL_SET,
- USBPHY_CTRL_CLR,
- USBPHY_CTRL_TOG,
- USBPHY_STATUS,
- USBPHY_DEBUG = 0x14,
- USBPHY_DEBUG_SET,
- USBPHY_DEBUG_CLR,
- USBPHY_DEBUG_TOG,
- USBPHY_DEBUG0_STATUS,
- USBPHY_DEBUG1 = 0x1c,
- USBPHY_DEBUG1_SET,
- USBPHY_DEBUG1_CLR,
- USBPHY_DEBUG1_TOG,
- USBPHY_VERSION,
- USBPHY_MAX
-};
-
-#define USBPHY_CTRL_SFTRST BIT(31)
-
-#define TYPE_IMX_USBPHY "imx.usbphy"
-OBJECT_DECLARE_SIMPLE_TYPE(IMXUSBPHYState, IMX_USBPHY)
-
-struct IMXUSBPHYState {
- /* <private> */
- SysBusDevice parent_obj;
-
- /* <public> */
- MemoryRegion iomem;
-
- uint32_t usbphy[USBPHY_MAX];
-};
-
-#endif /* IMX_USB_PHY_H */
+++ /dev/null
-#ifndef HW_USB_UHCI_REGS_H
-#define HW_USB_UHCI_REGS_H
-
-#define UHCI_CMD_FGR (1 << 4)
-#define UHCI_CMD_EGSM (1 << 3)
-#define UHCI_CMD_GRESET (1 << 2)
-#define UHCI_CMD_HCRESET (1 << 1)
-#define UHCI_CMD_RS (1 << 0)
-
-#define UHCI_STS_HCHALTED (1 << 5)
-#define UHCI_STS_HCPERR (1 << 4)
-#define UHCI_STS_HSERR (1 << 3)
-#define UHCI_STS_RD (1 << 2)
-#define UHCI_STS_USBERR (1 << 1)
-#define UHCI_STS_USBINT (1 << 0)
-
-#define TD_CTRL_SPD (1 << 29)
-#define TD_CTRL_ERROR_SHIFT 27
-#define TD_CTRL_IOS (1 << 25)
-#define TD_CTRL_IOC (1 << 24)
-#define TD_CTRL_ACTIVE (1 << 23)
-#define TD_CTRL_STALL (1 << 22)
-#define TD_CTRL_BABBLE (1 << 20)
-#define TD_CTRL_NAK (1 << 19)
-#define TD_CTRL_TIMEOUT (1 << 18)
-
-#define UHCI_PORT_SUSPEND (1 << 12)
-#define UHCI_PORT_RESET (1 << 9)
-#define UHCI_PORT_LSDA (1 << 8)
-#define UHCI_PORT_RSVD1 (1 << 7)
-#define UHCI_PORT_RD (1 << 6)
-#define UHCI_PORT_ENC (1 << 3)
-#define UHCI_PORT_EN (1 << 2)
-#define UHCI_PORT_CSC (1 << 1)
-#define UHCI_PORT_CCS (1 << 0)
-
-#define UHCI_PORT_READ_ONLY (0x1bb)
-#define UHCI_PORT_WRITE_CLEAR (UHCI_PORT_CSC | UHCI_PORT_ENC)
-
-#endif /* HW_USB_UHCI_REGS_H */
+++ /dev/null
-#ifndef HW_USB_XHCI_H
-#define HW_USB_XHCI_H
-
-#define TYPE_XHCI "base-xhci"
-#define TYPE_NEC_XHCI "nec-usb-xhci"
-#define TYPE_QEMU_XHCI "qemu-xhci"
-#define TYPE_XHCI_SYSBUS "sysbus-xhci"
-
-#define XHCI_MAXPORTS_2 15
-#define XHCI_MAXPORTS_3 15
-
-#define XHCI_MAXPORTS (XHCI_MAXPORTS_2 + XHCI_MAXPORTS_3)
-#define XHCI_MAXSLOTS 64
-#define XHCI_MAXINTRS 16
-
-/* must be power of 2 */
-#define XHCI_LEN_REGS 0x4000
-
-void xhci_sysbus_build_aml(Aml *scope, uint32_t mmio, unsigned int irq);
-
-#endif
+++ /dev/null
-/*
- * VFIO AMD XGBE device
- *
- * Copyright Linaro Limited, 2015
- *
- * Authors:
- * Eric Auger <eric.auger@linaro.org>
- *
- * This work is licensed under the terms of the GNU GPL, version 2. See
- * the COPYING file in the top-level directory.
- *
- */
-
-#ifndef HW_VFIO_VFIO_AMD_XGBE_H
-#define HW_VFIO_VFIO_AMD_XGBE_H
-
-#include "hw/vfio/vfio-platform.h"
-#include "qom/object.h"
-
-#define TYPE_VFIO_AMD_XGBE "vfio-amd-xgbe"
-
-/**
- * This device exposes:
- * - 5 MMIO regions: MAC, PCS, SerDes Rx/Tx regs,
- SerDes Integration Registers 1/2 & 2/2
- * - 2 level sensitive IRQs and optional DMA channel IRQs
- */
-struct VFIOAmdXgbeDevice {
- VFIOPlatformDevice vdev;
-};
-
-typedef struct VFIOAmdXgbeDevice VFIOAmdXgbeDevice;
-
-struct VFIOAmdXgbeDeviceClass {
- /*< private >*/
- VFIOPlatformDeviceClass parent_class;
- /*< public >*/
- DeviceRealize parent_realize;
-};
-
-typedef struct VFIOAmdXgbeDeviceClass VFIOAmdXgbeDeviceClass;
-
-DECLARE_OBJ_CHECKERS(VFIOAmdXgbeDevice, VFIOAmdXgbeDeviceClass,
- VFIO_AMD_XGBE_DEVICE, TYPE_VFIO_AMD_XGBE)
-
-#endif
+++ /dev/null
-/*
- * VFIO calxeda xgmac device
- *
- * Copyright Linaro Limited, 2014
- *
- * Authors:
- * Eric Auger <eric.auger@linaro.org>
- *
- * This work is licensed under the terms of the GNU GPL, version 2. See
- * the COPYING file in the top-level directory.
- *
- */
-
-#ifndef HW_VFIO_VFIO_CALXEDA_XGMAC_H
-#define HW_VFIO_VFIO_CALXEDA_XGMAC_H
-
-#include "hw/vfio/vfio-platform.h"
-#include "qom/object.h"
-
-#define TYPE_VFIO_CALXEDA_XGMAC "vfio-calxeda-xgmac"
-
-/**
- * This device exposes:
- * - a single MMIO region corresponding to its register space
- * - 3 IRQS (main and 2 power related IRQs)
- */
-struct VFIOCalxedaXgmacDevice {
- VFIOPlatformDevice vdev;
-};
-typedef struct VFIOCalxedaXgmacDevice VFIOCalxedaXgmacDevice;
-
-struct VFIOCalxedaXgmacDeviceClass {
- /*< private >*/
- VFIOPlatformDeviceClass parent_class;
- /*< public >*/
- DeviceRealize parent_realize;
-};
-typedef struct VFIOCalxedaXgmacDeviceClass VFIOCalxedaXgmacDeviceClass;
-
-DECLARE_OBJ_CHECKERS(VFIOCalxedaXgmacDevice, VFIOCalxedaXgmacDeviceClass,
- VFIO_CALXEDA_XGMAC_DEVICE, TYPE_VFIO_CALXEDA_XGMAC)
-
-#endif
+++ /dev/null
-/*
- * common header for vfio based device assignment support
- *
- * Copyright Red Hat, Inc. 2012
- *
- * Authors:
- * Alex Williamson <alex.williamson@redhat.com>
- *
- * This work is licensed under the terms of the GNU GPL, version 2. See
- * the COPYING file in the top-level directory.
- *
- * Based on qemu-kvm device-assignment:
- * Adapted for KVM by Qumranet.
- * Copyright (c) 2007, Neocleus, Alex Novik (alex@neocleus.com)
- * Copyright (c) 2007, Neocleus, Guy Zana (guy@neocleus.com)
- * Copyright (C) 2008, Qumranet, Amit Shah (amit.shah@qumranet.com)
- * Copyright (C) 2008, Red Hat, Amit Shah (amit.shah@redhat.com)
- * Copyright (C) 2008, IBM, Muli Ben-Yehuda (muli@il.ibm.com)
- */
-
-#ifndef HW_VFIO_VFIO_COMMON_H
-#define HW_VFIO_VFIO_COMMON_H
-
-#include "exec/memory.h"
-#include "qemu/queue.h"
-#include "qemu/notify.h"
-#include "ui/console.h"
-#include "hw/display/ramfb.h"
-#ifdef CONFIG_LINUX
-#include <linux/vfio.h>
-#endif
-#include "sysemu/sysemu.h"
-
-#define VFIO_MSG_PREFIX "vfio %s: "
-
-enum {
- VFIO_DEVICE_TYPE_PCI = 0,
- VFIO_DEVICE_TYPE_PLATFORM = 1,
- VFIO_DEVICE_TYPE_CCW = 2,
- VFIO_DEVICE_TYPE_AP = 3,
-};
-
-typedef struct VFIOMmap {
- MemoryRegion mem;
- void *mmap;
- off_t offset;
- size_t size;
-} VFIOMmap;
-
-typedef struct VFIORegion {
- struct VFIODevice *vbasedev;
- off_t fd_offset; /* offset of region within device fd */
- MemoryRegion *mem; /* slow, read/write access */
- size_t size;
- uint32_t flags; /* VFIO region flags (rd/wr/mmap) */
- uint32_t nr_mmaps;
- VFIOMmap *mmaps;
- uint8_t nr; /* cache the region number for debug */
-} VFIORegion;
-
-typedef struct VFIOMigration {
- struct VFIODevice *vbasedev;
- VMChangeStateEntry *vm_state;
- VFIORegion region;
- uint32_t device_state;
- int vm_running;
- Notifier migration_state;
- uint64_t pending_bytes;
-} VFIOMigration;
-
-typedef struct VFIOAddressSpace {
- AddressSpace *as;
- QLIST_HEAD(, VFIOContainer) containers;
- QLIST_ENTRY(VFIOAddressSpace) list;
-} VFIOAddressSpace;
-
-struct VFIOGroup;
-
-typedef struct VFIOContainer {
- VFIOAddressSpace *space;
- int fd; /* /dev/vfio/vfio, empowered by the attached groups */
- MemoryListener listener;
- MemoryListener prereg_listener;
- unsigned iommu_type;
- Error *error;
- bool initialized;
- bool dirty_pages_supported;
- uint64_t dirty_pgsizes;
- uint64_t max_dirty_bitmap_size;
- unsigned long pgsizes;
- QLIST_HEAD(, VFIOGuestIOMMU) giommu_list;
- QLIST_HEAD(, VFIOHostDMAWindow) hostwin_list;
- QLIST_HEAD(, VFIOGroup) group_list;
- QLIST_ENTRY(VFIOContainer) next;
-} VFIOContainer;
-
-typedef struct VFIOGuestIOMMU {
- VFIOContainer *container;
- IOMMUMemoryRegion *iommu;
- hwaddr iommu_offset;
- IOMMUNotifier n;
- QLIST_ENTRY(VFIOGuestIOMMU) giommu_next;
-} VFIOGuestIOMMU;
-
-typedef struct VFIOHostDMAWindow {
- hwaddr min_iova;
- hwaddr max_iova;
- uint64_t iova_pgsizes;
- QLIST_ENTRY(VFIOHostDMAWindow) hostwin_next;
-} VFIOHostDMAWindow;
-
-typedef struct VFIODeviceOps VFIODeviceOps;
-
-typedef struct VFIODevice {
- QLIST_ENTRY(VFIODevice) next;
- struct VFIOGroup *group;
- char *sysfsdev;
- char *name;
- DeviceState *dev;
- int fd;
- int type;
- bool reset_works;
- bool needs_reset;
- bool no_mmap;
- bool ram_block_discard_allowed;
- bool enable_migration;
- VFIODeviceOps *ops;
- unsigned int num_irqs;
- unsigned int num_regions;
- unsigned int flags;
- VFIOMigration *migration;
- Error *migration_blocker;
- OnOffAuto pre_copy_dirty_page_tracking;
-} VFIODevice;
-
-struct VFIODeviceOps {
- void (*vfio_compute_needs_reset)(VFIODevice *vdev);
- int (*vfio_hot_reset_multi)(VFIODevice *vdev);
- void (*vfio_eoi)(VFIODevice *vdev);
- Object *(*vfio_get_object)(VFIODevice *vdev);
- void (*vfio_save_config)(VFIODevice *vdev, QEMUFile *f);
- int (*vfio_load_config)(VFIODevice *vdev, QEMUFile *f);
-};
-
-typedef struct VFIOGroup {
- int fd;
- int groupid;
- VFIOContainer *container;
- QLIST_HEAD(, VFIODevice) device_list;
- QLIST_ENTRY(VFIOGroup) next;
- QLIST_ENTRY(VFIOGroup) container_next;
- bool ram_block_discard_allowed;
-} VFIOGroup;
-
-typedef struct VFIODMABuf {
- QemuDmaBuf buf;
- uint32_t pos_x, pos_y, pos_updates;
- uint32_t hot_x, hot_y, hot_updates;
- int dmabuf_id;
- QTAILQ_ENTRY(VFIODMABuf) next;
-} VFIODMABuf;
-
-typedef struct VFIODisplay {
- QemuConsole *con;
- RAMFBState *ramfb;
- struct vfio_region_info *edid_info;
- struct vfio_region_gfx_edid *edid_regs;
- uint8_t *edid_blob;
- QEMUTimer *edid_link_timer;
- struct {
- VFIORegion buffer;
- DisplaySurface *surface;
- } region;
- struct {
- QTAILQ_HEAD(, VFIODMABuf) bufs;
- VFIODMABuf *primary;
- VFIODMABuf *cursor;
- } dmabuf;
-} VFIODisplay;
-
-void vfio_put_base_device(VFIODevice *vbasedev);
-void vfio_disable_irqindex(VFIODevice *vbasedev, int index);
-void vfio_unmask_single_irqindex(VFIODevice *vbasedev, int index);
-void vfio_mask_single_irqindex(VFIODevice *vbasedev, int index);
-int vfio_set_irq_signaling(VFIODevice *vbasedev, int index, int subindex,
- int action, int fd, Error **errp);
-void vfio_region_write(void *opaque, hwaddr addr,
- uint64_t data, unsigned size);
-uint64_t vfio_region_read(void *opaque,
- hwaddr addr, unsigned size);
-int vfio_region_setup(Object *obj, VFIODevice *vbasedev, VFIORegion *region,
- int index, const char *name);
-int vfio_region_mmap(VFIORegion *region);
-void vfio_region_mmaps_set_enabled(VFIORegion *region, bool enabled);
-void vfio_region_unmap(VFIORegion *region);
-void vfio_region_exit(VFIORegion *region);
-void vfio_region_finalize(VFIORegion *region);
-void vfio_reset_handler(void *opaque);
-VFIOGroup *vfio_get_group(int groupid, AddressSpace *as, Error **errp);
-void vfio_put_group(VFIOGroup *group);
-int vfio_get_device(VFIOGroup *group, const char *name,
- VFIODevice *vbasedev, Error **errp);
-
-extern const MemoryRegionOps vfio_region_ops;
-typedef QLIST_HEAD(VFIOGroupList, VFIOGroup) VFIOGroupList;
-extern VFIOGroupList vfio_group_list;
-
-bool vfio_mig_active(void);
-int64_t vfio_mig_bytes_transferred(void);
-
-#ifdef CONFIG_LINUX
-int vfio_get_region_info(VFIODevice *vbasedev, int index,
- struct vfio_region_info **info);
-int vfio_get_dev_region_info(VFIODevice *vbasedev, uint32_t type,
- uint32_t subtype, struct vfio_region_info **info);
-bool vfio_has_region_cap(VFIODevice *vbasedev, int region, uint16_t cap_type);
-struct vfio_info_cap_header *
-vfio_get_region_info_cap(struct vfio_region_info *info, uint16_t id);
-bool vfio_get_info_dma_avail(struct vfio_iommu_type1_info *info,
- unsigned int *avail);
-struct vfio_info_cap_header *
-vfio_get_device_info_cap(struct vfio_device_info *info, uint16_t id);
-#endif
-extern const MemoryListener vfio_prereg_listener;
-
-int vfio_spapr_create_window(VFIOContainer *container,
- MemoryRegionSection *section,
- hwaddr *pgsize);
-int vfio_spapr_remove_window(VFIOContainer *container,
- hwaddr offset_within_address_space);
-
-int vfio_migration_probe(VFIODevice *vbasedev, Error **errp);
-void vfio_migration_finalize(VFIODevice *vbasedev);
-
-#endif /* HW_VFIO_VFIO_COMMON_H */
+++ /dev/null
-/*
- * vfio based device assignment support - platform devices
- *
- * Copyright Linaro Limited, 2014
- *
- * Authors:
- * Kim Phillips <kim.phillips@linaro.org>
- *
- * This work is licensed under the terms of the GNU GPL, version 2. See
- * the COPYING file in the top-level directory.
- *
- * Based on vfio based PCI device assignment support:
- * Copyright Red Hat, Inc. 2012
- */
-
-#ifndef HW_VFIO_VFIO_PLATFORM_H
-#define HW_VFIO_VFIO_PLATFORM_H
-
-#include "hw/sysbus.h"
-#include "hw/vfio/vfio-common.h"
-#include "qemu/event_notifier.h"
-#include "qemu/queue.h"
-#include "qom/object.h"
-
-#define TYPE_VFIO_PLATFORM "vfio-platform"
-
-enum {
- VFIO_IRQ_INACTIVE = 0,
- VFIO_IRQ_PENDING = 1,
- VFIO_IRQ_ACTIVE = 2,
- /* VFIO_IRQ_ACTIVE_AND_PENDING cannot happen with VFIO */
-};
-
-typedef struct VFIOINTp {
- QLIST_ENTRY(VFIOINTp) next; /* entry for IRQ list */
- QSIMPLEQ_ENTRY(VFIOINTp) pqnext; /* entry for pending IRQ queue */
- EventNotifier *interrupt; /* eventfd triggered on interrupt */
- EventNotifier *unmask; /* eventfd for unmask on QEMU bypass */
- qemu_irq qemuirq;
- struct VFIOPlatformDevice *vdev; /* back pointer to device */
- int state; /* inactive, pending, active */
- uint8_t pin; /* index */
- uint32_t flags; /* IRQ info flags */
- bool kvm_accel; /* set when QEMU bypass through KVM enabled */
-} VFIOINTp;
-
-/* function type for user side eventfd handler */
-typedef void (*eventfd_user_side_handler_t)(VFIOINTp *intp);
-
-struct VFIOPlatformDevice {
- SysBusDevice sbdev;
- VFIODevice vbasedev; /* not a QOM object */
- VFIORegion **regions;
- QLIST_HEAD(, VFIOINTp) intp_list; /* list of IRQs */
- /* queue of pending IRQs */
- QSIMPLEQ_HEAD(, VFIOINTp) pending_intp_queue;
- char *compat; /* DT compatible values, separated by NUL */
- unsigned int num_compat; /* number of compatible values */
- uint32_t mmap_timeout; /* delay to re-enable mmaps after interrupt */
- QEMUTimer *mmap_timer; /* allows fast-path resume after IRQ hit */
- QemuMutex intp_mutex; /* protect the intp_list IRQ state */
- bool irqfd_allowed; /* debug option to force irqfd on/off */
-};
-typedef struct VFIOPlatformDevice VFIOPlatformDevice;
-
-struct VFIOPlatformDeviceClass {
- /*< private >*/
- SysBusDeviceClass parent_class;
- /*< public >*/
-};
-typedef struct VFIOPlatformDeviceClass VFIOPlatformDeviceClass;
-
-DECLARE_OBJ_CHECKERS(VFIOPlatformDevice, VFIOPlatformDeviceClass,
- VFIO_PLATFORM_DEVICE, TYPE_VFIO_PLATFORM)
-
-#endif /* HW_VFIO_VFIO_PLATFORM_H */
+++ /dev/null
-#ifndef HW_VFIO_H
-#define HW_VFIO_H
-
-bool vfio_eeh_as_ok(AddressSpace *as);
-int vfio_eeh_as_op(AddressSpace *as, uint32_t op);
-
-#endif
+++ /dev/null
-/*
- * vhost-backend
- *
- * Copyright (c) 2013 Virtual Open Systems Sarl.
- *
- * This work is licensed under the terms of the GNU GPL, version 2 or later.
- * See the COPYING file in the top-level directory.
- *
- */
-
-#ifndef VHOST_BACKEND_H
-#define VHOST_BACKEND_H
-
-#include "exec/memory.h"
-
-typedef enum VhostBackendType {
- VHOST_BACKEND_TYPE_NONE = 0,
- VHOST_BACKEND_TYPE_KERNEL = 1,
- VHOST_BACKEND_TYPE_USER = 2,
- VHOST_BACKEND_TYPE_VDPA = 3,
- VHOST_BACKEND_TYPE_MAX = 4,
-} VhostBackendType;
-
-typedef enum VhostSetConfigType {
- VHOST_SET_CONFIG_TYPE_MASTER = 0,
- VHOST_SET_CONFIG_TYPE_MIGRATION = 1,
-} VhostSetConfigType;
-
-struct vhost_inflight;
-struct vhost_dev;
-struct vhost_log;
-struct vhost_memory;
-struct vhost_vring_file;
-struct vhost_vring_state;
-struct vhost_vring_addr;
-struct vhost_scsi_target;
-struct vhost_iotlb_msg;
-struct vhost_virtqueue;
-
-typedef int (*vhost_backend_init)(struct vhost_dev *dev, void *opaque);
-typedef int (*vhost_backend_cleanup)(struct vhost_dev *dev);
-typedef int (*vhost_backend_memslots_limit)(struct vhost_dev *dev);
-
-typedef int (*vhost_net_set_backend_op)(struct vhost_dev *dev,
- struct vhost_vring_file *file);
-typedef int (*vhost_net_set_mtu_op)(struct vhost_dev *dev, uint16_t mtu);
-typedef int (*vhost_scsi_set_endpoint_op)(struct vhost_dev *dev,
- struct vhost_scsi_target *target);
-typedef int (*vhost_scsi_clear_endpoint_op)(struct vhost_dev *dev,
- struct vhost_scsi_target *target);
-typedef int (*vhost_scsi_get_abi_version_op)(struct vhost_dev *dev,
- int *version);
-typedef int (*vhost_set_log_base_op)(struct vhost_dev *dev, uint64_t base,
- struct vhost_log *log);
-typedef int (*vhost_set_mem_table_op)(struct vhost_dev *dev,
- struct vhost_memory *mem);
-typedef int (*vhost_set_vring_addr_op)(struct vhost_dev *dev,
- struct vhost_vring_addr *addr);
-typedef int (*vhost_set_vring_endian_op)(struct vhost_dev *dev,
- struct vhost_vring_state *ring);
-typedef int (*vhost_set_vring_num_op)(struct vhost_dev *dev,
- struct vhost_vring_state *ring);
-typedef int (*vhost_set_vring_base_op)(struct vhost_dev *dev,
- struct vhost_vring_state *ring);
-typedef int (*vhost_get_vring_base_op)(struct vhost_dev *dev,
- struct vhost_vring_state *ring);
-typedef int (*vhost_set_vring_kick_op)(struct vhost_dev *dev,
- struct vhost_vring_file *file);
-typedef int (*vhost_set_vring_call_op)(struct vhost_dev *dev,
- struct vhost_vring_file *file);
-typedef int (*vhost_set_vring_busyloop_timeout_op)(struct vhost_dev *dev,
- struct vhost_vring_state *r);
-typedef int (*vhost_set_features_op)(struct vhost_dev *dev,
- uint64_t features);
-typedef int (*vhost_get_features_op)(struct vhost_dev *dev,
- uint64_t *features);
-typedef int (*vhost_set_backend_cap_op)(struct vhost_dev *dev);
-typedef int (*vhost_set_owner_op)(struct vhost_dev *dev);
-typedef int (*vhost_reset_device_op)(struct vhost_dev *dev);
-typedef int (*vhost_get_vq_index_op)(struct vhost_dev *dev, int idx);
-typedef int (*vhost_set_vring_enable_op)(struct vhost_dev *dev,
- int enable);
-typedef bool (*vhost_requires_shm_log_op)(struct vhost_dev *dev);
-typedef int (*vhost_migration_done_op)(struct vhost_dev *dev,
- char *mac_addr);
-typedef bool (*vhost_backend_can_merge_op)(struct vhost_dev *dev,
- uint64_t start1, uint64_t size1,
- uint64_t start2, uint64_t size2);
-typedef int (*vhost_vsock_set_guest_cid_op)(struct vhost_dev *dev,
- uint64_t guest_cid);
-typedef int (*vhost_vsock_set_running_op)(struct vhost_dev *dev, int start);
-typedef void (*vhost_set_iotlb_callback_op)(struct vhost_dev *dev,
- int enabled);
-typedef int (*vhost_send_device_iotlb_msg_op)(struct vhost_dev *dev,
- struct vhost_iotlb_msg *imsg);
-typedef int (*vhost_set_config_op)(struct vhost_dev *dev, const uint8_t *data,
- uint32_t offset, uint32_t size,
- uint32_t flags);
-typedef int (*vhost_get_config_op)(struct vhost_dev *dev, uint8_t *config,
- uint32_t config_len);
-
-typedef int (*vhost_crypto_create_session_op)(struct vhost_dev *dev,
- void *session_info,
- uint64_t *session_id);
-typedef int (*vhost_crypto_close_session_op)(struct vhost_dev *dev,
- uint64_t session_id);
-
-typedef bool (*vhost_backend_mem_section_filter_op)(struct vhost_dev *dev,
- MemoryRegionSection *section);
-
-typedef int (*vhost_get_inflight_fd_op)(struct vhost_dev *dev,
- uint16_t queue_size,
- struct vhost_inflight *inflight);
-
-typedef int (*vhost_set_inflight_fd_op)(struct vhost_dev *dev,
- struct vhost_inflight *inflight);
-
-typedef int (*vhost_dev_start_op)(struct vhost_dev *dev, bool started);
-
-typedef int (*vhost_vq_get_addr_op)(struct vhost_dev *dev,
- struct vhost_vring_addr *addr,
- struct vhost_virtqueue *vq);
-
-typedef int (*vhost_get_device_id_op)(struct vhost_dev *dev, uint32_t *dev_id);
-
-typedef bool (*vhost_force_iommu_op)(struct vhost_dev *dev);
-
-typedef struct VhostOps {
- VhostBackendType backend_type;
- vhost_backend_init vhost_backend_init;
- vhost_backend_cleanup vhost_backend_cleanup;
- vhost_backend_memslots_limit vhost_backend_memslots_limit;
- vhost_net_set_backend_op vhost_net_set_backend;
- vhost_net_set_mtu_op vhost_net_set_mtu;
- vhost_scsi_set_endpoint_op vhost_scsi_set_endpoint;
- vhost_scsi_clear_endpoint_op vhost_scsi_clear_endpoint;
- vhost_scsi_get_abi_version_op vhost_scsi_get_abi_version;
- vhost_set_log_base_op vhost_set_log_base;
- vhost_set_mem_table_op vhost_set_mem_table;
- vhost_set_vring_addr_op vhost_set_vring_addr;
- vhost_set_vring_endian_op vhost_set_vring_endian;
- vhost_set_vring_num_op vhost_set_vring_num;
- vhost_set_vring_base_op vhost_set_vring_base;
- vhost_get_vring_base_op vhost_get_vring_base;
- vhost_set_vring_kick_op vhost_set_vring_kick;
- vhost_set_vring_call_op vhost_set_vring_call;
- vhost_set_vring_busyloop_timeout_op vhost_set_vring_busyloop_timeout;
- vhost_set_features_op vhost_set_features;
- vhost_get_features_op vhost_get_features;
- vhost_set_backend_cap_op vhost_set_backend_cap;
- vhost_set_owner_op vhost_set_owner;
- vhost_reset_device_op vhost_reset_device;
- vhost_get_vq_index_op vhost_get_vq_index;
- vhost_set_vring_enable_op vhost_set_vring_enable;
- vhost_requires_shm_log_op vhost_requires_shm_log;
- vhost_migration_done_op vhost_migration_done;
- vhost_backend_can_merge_op vhost_backend_can_merge;
- vhost_vsock_set_guest_cid_op vhost_vsock_set_guest_cid;
- vhost_vsock_set_running_op vhost_vsock_set_running;
- vhost_set_iotlb_callback_op vhost_set_iotlb_callback;
- vhost_send_device_iotlb_msg_op vhost_send_device_iotlb_msg;
- vhost_get_config_op vhost_get_config;
- vhost_set_config_op vhost_set_config;
- vhost_crypto_create_session_op vhost_crypto_create_session;
- vhost_crypto_close_session_op vhost_crypto_close_session;
- vhost_backend_mem_section_filter_op vhost_backend_mem_section_filter;
- vhost_get_inflight_fd_op vhost_get_inflight_fd;
- vhost_set_inflight_fd_op vhost_set_inflight_fd;
- vhost_dev_start_op vhost_dev_start;
- vhost_vq_get_addr_op vhost_vq_get_addr;
- vhost_get_device_id_op vhost_get_device_id;
- vhost_force_iommu_op vhost_force_iommu;
-} VhostOps;
-
-extern const VhostOps user_ops;
-extern const VhostOps vdpa_ops;
-
-int vhost_set_backend_type(struct vhost_dev *dev,
- VhostBackendType backend_type);
-
-int vhost_backend_update_device_iotlb(struct vhost_dev *dev,
- uint64_t iova, uint64_t uaddr,
- uint64_t len,
- IOMMUAccessFlags perm);
-
-int vhost_backend_invalidate_device_iotlb(struct vhost_dev *dev,
- uint64_t iova, uint64_t len);
-
-int vhost_backend_handle_iotlb_msg(struct vhost_dev *dev,
- struct vhost_iotlb_msg *imsg);
-
-int vhost_user_gpu_set_socket(struct vhost_dev *dev, int fd);
-
-#endif /* VHOST_BACKEND_H */
+++ /dev/null
-/*
- * vhost_scsi host device
- *
- * Copyright (c) 2016 Nutanix Inc. All rights reserved.
- *
- * Author:
- * Felipe Franciosi <felipe@nutanix.com>
- *
- * This work is licensed under the terms of the GNU LGPL, version 2 or later.
- * See the COPYING.LIB file in the top-level directory.
- *
- */
-
-#ifndef VHOST_SCSI_COMMON_H
-#define VHOST_SCSI_COMMON_H
-
-#include "hw/virtio/virtio-scsi.h"
-#include "hw/virtio/vhost.h"
-#include "hw/fw-path-provider.h"
-#include "qom/object.h"
-
-#define TYPE_VHOST_SCSI_COMMON "vhost-scsi-common"
-OBJECT_DECLARE_SIMPLE_TYPE(VHostSCSICommon, VHOST_SCSI_COMMON)
-
-struct VHostSCSICommon {
- VirtIOSCSICommon parent_obj;
-
- Error *migration_blocker;
-
- struct vhost_dev dev;
- const int *feature_bits;
- int32_t bootindex;
- int channel;
- int target;
- int lun;
- uint64_t host_features;
- bool migratable;
-
- struct vhost_inflight *inflight;
-};
-
-int vhost_scsi_common_start(VHostSCSICommon *vsc);
-void vhost_scsi_common_stop(VHostSCSICommon *vsc);
-char *vhost_scsi_common_get_fw_dev_path(FWPathProvider *p, BusState *bus,
- DeviceState *dev);
-void vhost_scsi_common_set_config(VirtIODevice *vdev, const uint8_t *config);
-uint64_t vhost_scsi_common_get_features(VirtIODevice *vdev, uint64_t features,
- Error **errp);
-
-#endif /* VHOST_SCSI_COMMON_H */
+++ /dev/null
-/*
- * vhost_scsi host device
- *
- * Copyright IBM, Corp. 2011
- *
- * Authors:
- * Stefan Hajnoczi <stefanha@linux.vnet.ibm.com>
- *
- * This work is licensed under the terms of the GNU LGPL, version 2 or later.
- * See the COPYING.LIB file in the top-level directory.
- *
- */
-
-#ifndef VHOST_SCSI_H
-#define VHOST_SCSI_H
-
-#include "hw/virtio/virtio-scsi.h"
-#include "hw/virtio/vhost.h"
-#include "hw/virtio/vhost-scsi-common.h"
-#include "qom/object.h"
-
-enum vhost_scsi_vq_list {
- VHOST_SCSI_VQ_CONTROL = 0,
- VHOST_SCSI_VQ_EVENT = 1,
- VHOST_SCSI_VQ_NUM_FIXED = 2,
-};
-
-#define TYPE_VHOST_SCSI "vhost-scsi"
-OBJECT_DECLARE_SIMPLE_TYPE(VHostSCSI, VHOST_SCSI)
-
-struct VHostSCSI {
- VHostSCSICommon parent_obj;
-};
-
-#endif
+++ /dev/null
-/*
- * vhost-user-blk host device
- * Copyright(C) 2017 Intel Corporation.
- *
- * Authors:
- * Changpeng Liu <changpeng.liu@intel.com>
- *
- * Based on vhost-scsi.h, Copyright IBM, Corp. 2011
- *
- * This work is licensed under the terms of the GNU LGPL, version 2 or later.
- * See the COPYING.LIB file in the top-level directory.
- *
- */
-
-#ifndef VHOST_USER_BLK_H
-#define VHOST_USER_BLK_H
-
-#include "standard-headers/linux/virtio_blk.h"
-#include "hw/block/block.h"
-#include "chardev/char-fe.h"
-#include "hw/virtio/vhost.h"
-#include "hw/virtio/vhost-user.h"
-#include "qom/object.h"
-
-#define TYPE_VHOST_USER_BLK "vhost-user-blk"
-OBJECT_DECLARE_SIMPLE_TYPE(VHostUserBlk, VHOST_USER_BLK)
-
-#define VHOST_USER_BLK_AUTO_NUM_QUEUES UINT16_MAX
-
-struct VHostUserBlk {
- VirtIODevice parent_obj;
- CharBackend chardev;
- int32_t bootindex;
- struct virtio_blk_config blkcfg;
- uint16_t num_queues;
- uint32_t queue_size;
- uint32_t config_wce;
- struct vhost_dev dev;
- struct vhost_inflight *inflight;
- VhostUserState vhost_user;
- struct vhost_virtqueue *vhost_vqs;
- VirtQueue **virtqs;
-
- /*
- * There are at least two steps of initialization of the
- * vhost-user device. The first is a "connect" step and
- * second is a "start" step. Make a separation between
- * those initialization phases by using two fields.
- */
- /* vhost_user_blk_connect/vhost_user_blk_disconnect */
- bool connected;
- /* vhost_user_blk_start/vhost_user_blk_stop */
- bool started_vu;
-};
-
-#endif
+++ /dev/null
-/*
- * Vhost-user filesystem virtio device
- *
- * Copyright 2018-2019 Red Hat, Inc.
- *
- * Authors:
- * Stefan Hajnoczi <stefanha@redhat.com>
- *
- * This work is licensed under the terms of the GNU GPL, version 2 or
- * (at your option) any later version. See the COPYING file in the
- * top-level directory.
- */
-
-#ifndef _QEMU_VHOST_USER_FS_H
-#define _QEMU_VHOST_USER_FS_H
-
-#include "hw/virtio/virtio.h"
-#include "hw/virtio/vhost.h"
-#include "hw/virtio/vhost-user.h"
-#include "chardev/char-fe.h"
-#include "qom/object.h"
-
-#define TYPE_VHOST_USER_FS "vhost-user-fs-device"
-OBJECT_DECLARE_SIMPLE_TYPE(VHostUserFS, VHOST_USER_FS)
-
-typedef struct {
- CharBackend chardev;
- char *tag;
- uint16_t num_request_queues;
- uint16_t queue_size;
-} VHostUserFSConf;
-
-struct VHostUserFS {
- /*< private >*/
- VirtIODevice parent;
- VHostUserFSConf conf;
- struct vhost_virtqueue *vhost_vqs;
- struct vhost_dev vhost_dev;
- VhostUserState vhost_user;
- VirtQueue **req_vqs;
- VirtQueue *hiprio_vq;
-
- /*< public >*/
-};
-
-#endif /* _QEMU_VHOST_USER_FS_H */
+++ /dev/null
-/*
- * vhost-user-scsi host device
- *
- * Copyright (c) 2016 Nutanix Inc. All rights reserved.
- *
- * Author:
- * Felipe Franciosi <felipe@nutanix.com>
- *
- * This file is largely based on "vhost-scsi.h" by:
- * Stefan Hajnoczi <stefanha@linux.vnet.ibm.com>
- *
- * This work is licensed under the terms of the GNU LGPL, version 2 or later.
- * See the COPYING.LIB file in the top-level directory.
- *
- */
-
-#ifndef VHOST_USER_SCSI_H
-#define VHOST_USER_SCSI_H
-
-#include "hw/virtio/virtio-scsi.h"
-#include "hw/virtio/vhost.h"
-#include "hw/virtio/vhost-user.h"
-#include "hw/virtio/vhost-scsi-common.h"
-#include "qom/object.h"
-
-#define TYPE_VHOST_USER_SCSI "vhost-user-scsi"
-OBJECT_DECLARE_SIMPLE_TYPE(VHostUserSCSI, VHOST_USER_SCSI)
-
-struct VHostUserSCSI {
- VHostSCSICommon parent_obj;
- VhostUserState vhost_user;
-};
-
-#endif /* VHOST_USER_SCSI_H */
+++ /dev/null
-/*
- * Vhost-user vsock virtio device
- *
- * Copyright 2020 Red Hat, Inc.
- *
- * This work is licensed under the terms of the GNU GPL, version 2 or
- * (at your option) any later version. See the COPYING file in the
- * top-level directory.
- */
-
-#ifndef _QEMU_VHOST_USER_VSOCK_H
-#define _QEMU_VHOST_USER_VSOCK_H
-
-#include "hw/virtio/vhost-vsock-common.h"
-#include "hw/virtio/vhost-user.h"
-#include "standard-headers/linux/virtio_vsock.h"
-#include "qom/object.h"
-
-#define TYPE_VHOST_USER_VSOCK "vhost-user-vsock-device"
-OBJECT_DECLARE_SIMPLE_TYPE(VHostUserVSock, VHOST_USER_VSOCK)
-
-typedef struct {
- CharBackend chardev;
-} VHostUserVSockConf;
-
-struct VHostUserVSock {
- /*< private >*/
- VHostVSockCommon parent;
- VhostUserState vhost_user;
- VHostUserVSockConf conf;
- struct virtio_vsock_config vsockcfg;
-
- /*< public >*/
-};
-
-#endif /* _QEMU_VHOST_USER_VSOCK_H */
+++ /dev/null
-/*
- * Copyright (c) 2017-2018 Intel Corporation
- *
- * This work is licensed under the terms of the GNU GPL, version 2.
- * See the COPYING file in the top-level directory.
- */
-
-#ifndef HW_VIRTIO_VHOST_USER_H
-#define HW_VIRTIO_VHOST_USER_H
-
-#include "chardev/char-fe.h"
-#include "hw/virtio/virtio.h"
-
-typedef struct VhostUserHostNotifier {
- MemoryRegion mr;
- void *addr;
- bool set;
-} VhostUserHostNotifier;
-
-typedef struct VhostUserState {
- CharBackend *chr;
- VhostUserHostNotifier notifier[VIRTIO_QUEUE_MAX];
- int memory_slots;
-} VhostUserState;
-
-bool vhost_user_init(VhostUserState *user, CharBackend *chr, Error **errp);
-void vhost_user_cleanup(VhostUserState *user);
-
-#endif
+++ /dev/null
-/*
- * vhost-vdpa.h
- *
- * Copyright(c) 2017-2018 Intel Corporation.
- * Copyright(c) 2020 Red Hat, Inc.
- *
- * This work is licensed under the terms of the GNU GPL, version 2 or later.
- * See the COPYING file in the top-level directory.
- *
- */
-
-#ifndef HW_VIRTIO_VHOST_VDPA_H
-#define HW_VIRTIO_VHOST_VDPA_H
-
-#include "hw/virtio/virtio.h"
-
-typedef struct vhost_vdpa {
- int device_fd;
- uint32_t msg_type;
- MemoryListener listener;
- struct vhost_dev *dev;
-} VhostVDPA;
-
-extern AddressSpace address_space_memory;
-extern int vhost_vdpa_get_device_id(struct vhost_dev *dev,
- uint32_t *device_id);
-#endif
+++ /dev/null
-/*
- * Parent class for vhost-vsock devices
- *
- * Copyright 2015-2020 Red Hat, Inc.
- *
- * This work is licensed under the terms of the GNU GPL, version 2 or
- * (at your option) any later version. See the COPYING file in the
- * top-level directory.
- */
-
-#ifndef _QEMU_VHOST_VSOCK_COMMON_H
-#define _QEMU_VHOST_VSOCK_COMMON_H
-
-#include "hw/virtio/virtio.h"
-#include "hw/virtio/vhost.h"
-#include "qom/object.h"
-
-#define TYPE_VHOST_VSOCK_COMMON "vhost-vsock-common"
-OBJECT_DECLARE_SIMPLE_TYPE(VHostVSockCommon, VHOST_VSOCK_COMMON)
-
-enum {
- VHOST_VSOCK_SAVEVM_VERSION = 0,
-
- VHOST_VSOCK_QUEUE_SIZE = 128,
-};
-
-struct VHostVSockCommon {
- VirtIODevice parent;
-
- struct vhost_virtqueue vhost_vqs[2];
- struct vhost_dev vhost_dev;
-
- VirtQueue *event_vq;
- VirtQueue *recv_vq;
- VirtQueue *trans_vq;
-
- QEMUTimer *post_load_timer;
-};
-
-int vhost_vsock_common_start(VirtIODevice *vdev);
-void vhost_vsock_common_stop(VirtIODevice *vdev);
-int vhost_vsock_common_pre_save(void *opaque);
-int vhost_vsock_common_post_load(void *opaque, int version_id);
-void vhost_vsock_common_realize(VirtIODevice *vdev, const char *name);
-void vhost_vsock_common_unrealize(VirtIODevice *vdev);
-
-#endif /* _QEMU_VHOST_VSOCK_COMMON_H */
+++ /dev/null
-/*
- * Vhost vsock virtio device
- *
- * Copyright 2015 Red Hat, Inc.
- *
- * Authors:
- * Stefan Hajnoczi <stefanha@redhat.com>
- *
- * This work is licensed under the terms of the GNU GPL, version 2 or
- * (at your option) any later version. See the COPYING file in the
- * top-level directory.
- */
-
-#ifndef QEMU_VHOST_VSOCK_H
-#define QEMU_VHOST_VSOCK_H
-
-#include "hw/virtio/vhost-vsock-common.h"
-#include "qom/object.h"
-
-#define TYPE_VHOST_VSOCK "vhost-vsock-device"
-OBJECT_DECLARE_SIMPLE_TYPE(VHostVSock, VHOST_VSOCK)
-
-typedef struct {
- uint64_t guest_cid;
- char *vhostfd;
-} VHostVSockConf;
-
-struct VHostVSock {
- /*< private >*/
- VHostVSockCommon parent;
- VHostVSockConf conf;
-
- /*< public >*/
-};
-
-#endif /* QEMU_VHOST_VSOCK_H */
+++ /dev/null
-#ifndef VHOST_H
-#define VHOST_H
-
-#include "hw/virtio/vhost-backend.h"
-#include "hw/virtio/virtio.h"
-#include "exec/memory.h"
-
-/* Generic structures common for any vhost based device. */
-
-struct vhost_inflight {
- int fd;
- void *addr;
- uint64_t size;
- uint64_t offset;
- uint16_t queue_size;
-};
-
-struct vhost_virtqueue {
- int kick;
- int call;
- void *desc;
- void *avail;
- void *used;
- int num;
- unsigned long long desc_phys;
- unsigned desc_size;
- unsigned long long avail_phys;
- unsigned avail_size;
- unsigned long long used_phys;
- unsigned used_size;
- EventNotifier masked_notifier;
- struct vhost_dev *dev;
-};
-
-typedef unsigned long vhost_log_chunk_t;
-#define VHOST_LOG_PAGE 0x1000
-#define VHOST_LOG_BITS (8 * sizeof(vhost_log_chunk_t))
-#define VHOST_LOG_CHUNK (VHOST_LOG_PAGE * VHOST_LOG_BITS)
-#define VHOST_INVALID_FEATURE_BIT (0xff)
-
-struct vhost_log {
- unsigned long long size;
- int refcnt;
- int fd;
- vhost_log_chunk_t *log;
-};
-
-struct vhost_dev;
-struct vhost_iommu {
- struct vhost_dev *hdev;
- MemoryRegion *mr;
- hwaddr iommu_offset;
- IOMMUNotifier n;
- QLIST_ENTRY(vhost_iommu) iommu_next;
-};
-
-typedef struct VhostDevConfigOps {
- /* Vhost device config space changed callback
- */
- int (*vhost_dev_config_notifier)(struct vhost_dev *dev);
-} VhostDevConfigOps;
-
-struct vhost_memory;
-struct vhost_dev {
- VirtIODevice *vdev;
- MemoryListener memory_listener;
- MemoryListener iommu_listener;
- struct vhost_memory *mem;
- int n_mem_sections;
- MemoryRegionSection *mem_sections;
- int n_tmp_sections;
- MemoryRegionSection *tmp_sections;
- struct vhost_virtqueue *vqs;
- int nvqs;
- /* the first virtqueue which would be used by this vhost dev */
- int vq_index;
- uint64_t features;
- uint64_t acked_features;
- uint64_t backend_features;
- uint64_t protocol_features;
- uint64_t max_queues;
- uint64_t backend_cap;
- bool started;
- bool log_enabled;
- uint64_t log_size;
- Error *migration_blocker;
- const VhostOps *vhost_ops;
- void *opaque;
- struct vhost_log *log;
- QLIST_ENTRY(vhost_dev) entry;
- QLIST_HEAD(, vhost_iommu) iommu_list;
- IOMMUNotifier n;
- const VhostDevConfigOps *config_ops;
-};
-
-struct vhost_net {
- struct vhost_dev dev;
- struct vhost_virtqueue vqs[2];
- int backend;
- NetClientState *nc;
-};
-
-int vhost_dev_init(struct vhost_dev *hdev, void *opaque,
- VhostBackendType backend_type,
- uint32_t busyloop_timeout);
-void vhost_dev_cleanup(struct vhost_dev *hdev);
-int vhost_dev_start(struct vhost_dev *hdev, VirtIODevice *vdev);
-void vhost_dev_stop(struct vhost_dev *hdev, VirtIODevice *vdev);
-int vhost_dev_enable_notifiers(struct vhost_dev *hdev, VirtIODevice *vdev);
-void vhost_dev_disable_notifiers(struct vhost_dev *hdev, VirtIODevice *vdev);
-
-/* Test and clear masked event pending status.
- * Should be called after unmask to avoid losing events.
- */
-bool vhost_virtqueue_pending(struct vhost_dev *hdev, int n);
-
-/* Mask/unmask events from this vq.
- */
-void vhost_virtqueue_mask(struct vhost_dev *hdev, VirtIODevice *vdev, int n,
- bool mask);
-uint64_t vhost_get_features(struct vhost_dev *hdev, const int *feature_bits,
- uint64_t features);
-void vhost_ack_features(struct vhost_dev *hdev, const int *feature_bits,
- uint64_t features);
-bool vhost_has_free_slot(void);
-
-int vhost_net_set_backend(struct vhost_dev *hdev,
- struct vhost_vring_file *file);
-
-int vhost_device_iotlb_miss(struct vhost_dev *dev, uint64_t iova, int write);
-int vhost_dev_get_config(struct vhost_dev *dev, uint8_t *config,
- uint32_t config_len);
-int vhost_dev_set_config(struct vhost_dev *dev, const uint8_t *data,
- uint32_t offset, uint32_t size, uint32_t flags);
-/* notifier callback in case vhost device config space changed
- */
-void vhost_dev_set_config_notifier(struct vhost_dev *dev,
- const VhostDevConfigOps *ops);
-
-void vhost_dev_reset_inflight(struct vhost_inflight *inflight);
-void vhost_dev_free_inflight(struct vhost_inflight *inflight);
-void vhost_dev_save_inflight(struct vhost_inflight *inflight, QEMUFile *f);
-int vhost_dev_load_inflight(struct vhost_inflight *inflight, QEMUFile *f);
-int vhost_dev_prepare_inflight(struct vhost_dev *hdev, VirtIODevice *vdev);
-int vhost_dev_set_inflight(struct vhost_dev *dev,
- struct vhost_inflight *inflight);
-int vhost_dev_get_inflight(struct vhost_dev *dev, uint16_t queue_size,
- struct vhost_inflight *inflight);
-#endif
+++ /dev/null
-/*
- * Virtio Accessor Support: In case your target can change endian.
- *
- * Copyright IBM, Corp. 2013
- *
- * Authors:
- * Rusty Russell <rusty@au.ibm.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation, either version 2 of the License, or
- * (at your option) any later version.
- *
- */
-
-#ifndef QEMU_VIRTIO_ACCESS_H
-#define QEMU_VIRTIO_ACCESS_H
-
-#include "exec/hwaddr.h"
-#include "hw/virtio/virtio.h"
-#include "hw/virtio/virtio-bus.h"
-
-#if defined(TARGET_PPC64) || defined(TARGET_ARM)
-#define LEGACY_VIRTIO_IS_BIENDIAN 1
-#endif
-
-static inline bool virtio_access_is_big_endian(VirtIODevice *vdev)
-{
-#if defined(LEGACY_VIRTIO_IS_BIENDIAN)
- return virtio_is_big_endian(vdev);
-#elif defined(TARGET_WORDS_BIGENDIAN)
- if (virtio_vdev_has_feature(vdev, VIRTIO_F_VERSION_1)) {
- /* Devices conforming to VIRTIO 1.0 or later are always LE. */
- return false;
- }
- return true;
-#else
- return false;
-#endif
-}
-
-static inline uint16_t virtio_lduw_phys(VirtIODevice *vdev, hwaddr pa)
-{
- AddressSpace *dma_as = vdev->dma_as;
-
- if (virtio_access_is_big_endian(vdev)) {
- return lduw_be_phys(dma_as, pa);
- }
- return lduw_le_phys(dma_as, pa);
-}
-
-static inline uint32_t virtio_ldl_phys(VirtIODevice *vdev, hwaddr pa)
-{
- AddressSpace *dma_as = vdev->dma_as;
-
- if (virtio_access_is_big_endian(vdev)) {
- return ldl_be_phys(dma_as, pa);
- }
- return ldl_le_phys(dma_as, pa);
-}
-
-static inline uint64_t virtio_ldq_phys(VirtIODevice *vdev, hwaddr pa)
-{
- AddressSpace *dma_as = vdev->dma_as;
-
- if (virtio_access_is_big_endian(vdev)) {
- return ldq_be_phys(dma_as, pa);
- }
- return ldq_le_phys(dma_as, pa);
-}
-
-static inline void virtio_stw_phys(VirtIODevice *vdev, hwaddr pa,
- uint16_t value)
-{
- AddressSpace *dma_as = vdev->dma_as;
-
- if (virtio_access_is_big_endian(vdev)) {
- stw_be_phys(dma_as, pa, value);
- } else {
- stw_le_phys(dma_as, pa, value);
- }
-}
-
-static inline void virtio_stl_phys(VirtIODevice *vdev, hwaddr pa,
- uint32_t value)
-{
- AddressSpace *dma_as = vdev->dma_as;
-
- if (virtio_access_is_big_endian(vdev)) {
- stl_be_phys(dma_as, pa, value);
- } else {
- stl_le_phys(dma_as, pa, value);
- }
-}
-
-static inline void virtio_stw_p(VirtIODevice *vdev, void *ptr, uint16_t v)
-{
- if (virtio_access_is_big_endian(vdev)) {
- stw_be_p(ptr, v);
- } else {
- stw_le_p(ptr, v);
- }
-}
-
-static inline void virtio_stl_p(VirtIODevice *vdev, void *ptr, uint32_t v)
-{
- if (virtio_access_is_big_endian(vdev)) {
- stl_be_p(ptr, v);
- } else {
- stl_le_p(ptr, v);
- }
-}
-
-static inline void virtio_stq_p(VirtIODevice *vdev, void *ptr, uint64_t v)
-{
- if (virtio_access_is_big_endian(vdev)) {
- stq_be_p(ptr, v);
- } else {
- stq_le_p(ptr, v);
- }
-}
-
-static inline int virtio_lduw_p(VirtIODevice *vdev, const void *ptr)
-{
- if (virtio_access_is_big_endian(vdev)) {
- return lduw_be_p(ptr);
- } else {
- return lduw_le_p(ptr);
- }
-}
-
-static inline int virtio_ldl_p(VirtIODevice *vdev, const void *ptr)
-{
- if (virtio_access_is_big_endian(vdev)) {
- return ldl_be_p(ptr);
- } else {
- return ldl_le_p(ptr);
- }
-}
-
-static inline uint64_t virtio_ldq_p(VirtIODevice *vdev, const void *ptr)
-{
- if (virtio_access_is_big_endian(vdev)) {
- return ldq_be_p(ptr);
- } else {
- return ldq_le_p(ptr);
- }
-}
-
-static inline uint16_t virtio_tswap16(VirtIODevice *vdev, uint16_t s)
-{
-#ifdef HOST_WORDS_BIGENDIAN
- return virtio_access_is_big_endian(vdev) ? s : bswap16(s);
-#else
- return virtio_access_is_big_endian(vdev) ? bswap16(s) : s;
-#endif
-}
-
-static inline uint16_t virtio_lduw_phys_cached(VirtIODevice *vdev,
- MemoryRegionCache *cache,
- hwaddr pa)
-{
- if (virtio_access_is_big_endian(vdev)) {
- return lduw_be_phys_cached(cache, pa);
- }
- return lduw_le_phys_cached(cache, pa);
-}
-
-static inline uint32_t virtio_ldl_phys_cached(VirtIODevice *vdev,
- MemoryRegionCache *cache,
- hwaddr pa)
-{
- if (virtio_access_is_big_endian(vdev)) {
- return ldl_be_phys_cached(cache, pa);
- }
- return ldl_le_phys_cached(cache, pa);
-}
-
-static inline uint64_t virtio_ldq_phys_cached(VirtIODevice *vdev,
- MemoryRegionCache *cache,
- hwaddr pa)
-{
- if (virtio_access_is_big_endian(vdev)) {
- return ldq_be_phys_cached(cache, pa);
- }
- return ldq_le_phys_cached(cache, pa);
-}
-
-static inline void virtio_stw_phys_cached(VirtIODevice *vdev,
- MemoryRegionCache *cache,
- hwaddr pa, uint16_t value)
-{
- if (virtio_access_is_big_endian(vdev)) {
- stw_be_phys_cached(cache, pa, value);
- } else {
- stw_le_phys_cached(cache, pa, value);
- }
-}
-
-static inline void virtio_stl_phys_cached(VirtIODevice *vdev,
- MemoryRegionCache *cache,
- hwaddr pa, uint32_t value)
-{
- if (virtio_access_is_big_endian(vdev)) {
- stl_be_phys_cached(cache, pa, value);
- } else {
- stl_le_phys_cached(cache, pa, value);
- }
-}
-
-static inline void virtio_tswap16s(VirtIODevice *vdev, uint16_t *s)
-{
- *s = virtio_tswap16(vdev, *s);
-}
-
-static inline uint32_t virtio_tswap32(VirtIODevice *vdev, uint32_t s)
-{
-#ifdef HOST_WORDS_BIGENDIAN
- return virtio_access_is_big_endian(vdev) ? s : bswap32(s);
-#else
- return virtio_access_is_big_endian(vdev) ? bswap32(s) : s;
-#endif
-}
-
-static inline void virtio_tswap32s(VirtIODevice *vdev, uint32_t *s)
-{
- *s = virtio_tswap32(vdev, *s);
-}
-
-static inline uint64_t virtio_tswap64(VirtIODevice *vdev, uint64_t s)
-{
-#ifdef HOST_WORDS_BIGENDIAN
- return virtio_access_is_big_endian(vdev) ? s : bswap64(s);
-#else
- return virtio_access_is_big_endian(vdev) ? bswap64(s) : s;
-#endif
-}
-
-static inline void virtio_tswap64s(VirtIODevice *vdev, uint64_t *s)
-{
- *s = virtio_tswap64(vdev, *s);
-}
-#endif /* QEMU_VIRTIO_ACCESS_H */
+++ /dev/null
-/*
- * Virtio Support
- *
- * Copyright IBM, Corp. 2007-2008
- *
- * Authors:
- * Anthony Liguori <aliguori@us.ibm.com>
- * Rusty Russell <rusty@rustcorp.com.au>
- *
- * This work is licensed under the terms of the GNU GPL, version 2. See
- * the COPYING file in the top-level directory.
- *
- */
-
-#ifndef QEMU_VIRTIO_BALLOON_H
-#define QEMU_VIRTIO_BALLOON_H
-
-#include "standard-headers/linux/virtio_balloon.h"
-#include "hw/virtio/virtio.h"
-#include "sysemu/iothread.h"
-#include "qom/object.h"
-
-#define TYPE_VIRTIO_BALLOON "virtio-balloon-device"
-OBJECT_DECLARE_SIMPLE_TYPE(VirtIOBalloon, VIRTIO_BALLOON)
-
-#define VIRTIO_BALLOON_FREE_PAGE_HINT_CMD_ID_MIN 0x80000000
-
-typedef struct virtio_balloon_stat VirtIOBalloonStat;
-
-typedef struct virtio_balloon_stat_modern {
- uint16_t tag;
- uint8_t reserved[6];
- uint64_t val;
-} VirtIOBalloonStatModern;
-
-enum virtio_balloon_free_page_hint_status {
- FREE_PAGE_HINT_S_STOP = 0,
- FREE_PAGE_HINT_S_REQUESTED = 1,
- FREE_PAGE_HINT_S_START = 2,
- FREE_PAGE_HINT_S_DONE = 3,
-};
-
-struct VirtIOBalloon {
- VirtIODevice parent_obj;
- VirtQueue *ivq, *dvq, *svq, *free_page_vq, *reporting_vq;
- uint32_t free_page_hint_status;
- uint32_t num_pages;
- uint32_t actual;
- uint32_t free_page_hint_cmd_id;
- uint64_t stats[VIRTIO_BALLOON_S_NR];
- VirtQueueElement *stats_vq_elem;
- size_t stats_vq_offset;
- QEMUTimer *stats_timer;
- IOThread *iothread;
- QEMUBH *free_page_bh;
- /*
- * Lock to synchronize threads to access the free page reporting related
- * fields (e.g. free_page_hint_status).
- */
- QemuMutex free_page_lock;
- QemuCond free_page_cond;
- /*
- * Set to block iothread to continue reading free page hints as the VM is
- * stopped.
- */
- bool block_iothread;
- NotifierWithReturn free_page_hint_notify;
- int64_t stats_last_update;
- int64_t stats_poll_interval;
- uint32_t host_features;
-
- bool qemu_4_0_config_size;
- uint32_t poison_val;
-};
-
-#endif
+++ /dev/null
-/*
- * Virtio Block Device
- *
- * Copyright IBM, Corp. 2007
- *
- * Authors:
- * Anthony Liguori <aliguori@us.ibm.com>
- *
- * This work is licensed under the terms of the GNU GPL, version 2. See
- * the COPYING file in the top-level directory.
- *
- */
-
-#ifndef QEMU_VIRTIO_BLK_H
-#define QEMU_VIRTIO_BLK_H
-
-#include "standard-headers/linux/virtio_blk.h"
-#include "hw/virtio/virtio.h"
-#include "hw/block/block.h"
-#include "sysemu/iothread.h"
-#include "sysemu/block-backend.h"
-#include "qom/object.h"
-
-#define TYPE_VIRTIO_BLK "virtio-blk-device"
-OBJECT_DECLARE_SIMPLE_TYPE(VirtIOBlock, VIRTIO_BLK)
-
-/* This is the last element of the write scatter-gather list */
-struct virtio_blk_inhdr
-{
- unsigned char status;
-};
-
-#define VIRTIO_BLK_AUTO_NUM_QUEUES UINT16_MAX
-
-struct VirtIOBlkConf
-{
- BlockConf conf;
- IOThread *iothread;
- char *serial;
- uint32_t request_merging;
- uint16_t num_queues;
- uint16_t queue_size;
- bool seg_max_adjust;
- uint32_t max_discard_sectors;
- uint32_t max_write_zeroes_sectors;
- bool x_enable_wce_if_config_wce;
-};
-
-struct VirtIOBlockDataPlane;
-
-struct VirtIOBlockReq;
-struct VirtIOBlock {
- VirtIODevice parent_obj;
- BlockBackend *blk;
- void *rq;
- QEMUBH *bh;
- VirtIOBlkConf conf;
- unsigned short sector_mask;
- bool original_wce;
- VMChangeStateEntry *change;
- bool dataplane_disabled;
- bool dataplane_started;
- struct VirtIOBlockDataPlane *dataplane;
- uint64_t host_features;
- size_t config_size;
-};
-
-typedef struct VirtIOBlockReq {
- VirtQueueElement elem;
- int64_t sector_num;
- VirtIOBlock *dev;
- VirtQueue *vq;
- IOVDiscardUndo inhdr_undo;
- IOVDiscardUndo outhdr_undo;
- struct virtio_blk_inhdr *in;
- struct virtio_blk_outhdr out;
- QEMUIOVector qiov;
- size_t in_len;
- struct VirtIOBlockReq *next;
- struct VirtIOBlockReq *mr_next;
- BlockAcctCookie acct;
-} VirtIOBlockReq;
-
-#define VIRTIO_BLK_MAX_MERGE_REQS 32
-
-typedef struct MultiReqBuffer {
- VirtIOBlockReq *reqs[VIRTIO_BLK_MAX_MERGE_REQS];
- unsigned int num_reqs;
- bool is_write;
-} MultiReqBuffer;
-
-bool virtio_blk_handle_vq(VirtIOBlock *s, VirtQueue *vq);
-void virtio_blk_process_queued_requests(VirtIOBlock *s, bool is_bh);
-
-#endif
+++ /dev/null
-/*
- * VirtioBus
- *
- * Copyright (C) 2012 : GreenSocs Ltd
- * http://www.greensocs.com/ , email: info@greensocs.com
- *
- * Developed by :
- * Frederic Konrad <fred.konrad@greensocs.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation, either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License along
- * with this program; if not, see <http://www.gnu.org/licenses/>.
- *
- */
-
-#ifndef VIRTIO_BUS_H
-#define VIRTIO_BUS_H
-
-#include "hw/qdev-core.h"
-#include "hw/virtio/virtio.h"
-#include "qom/object.h"
-
-#define TYPE_VIRTIO_BUS "virtio-bus"
-typedef struct VirtioBusClass VirtioBusClass;
-typedef struct VirtioBusState VirtioBusState;
-DECLARE_OBJ_CHECKERS(VirtioBusState, VirtioBusClass,
- VIRTIO_BUS, TYPE_VIRTIO_BUS)
-
-
-struct VirtioBusClass {
- /* This is what a VirtioBus must implement */
- BusClass parent;
- void (*notify)(DeviceState *d, uint16_t vector);
- void (*save_config)(DeviceState *d, QEMUFile *f);
- void (*save_queue)(DeviceState *d, int n, QEMUFile *f);
- void (*save_extra_state)(DeviceState *d, QEMUFile *f);
- int (*load_config)(DeviceState *d, QEMUFile *f);
- int (*load_queue)(DeviceState *d, int n, QEMUFile *f);
- int (*load_done)(DeviceState *d, QEMUFile *f);
- int (*load_extra_state)(DeviceState *d, QEMUFile *f);
- bool (*has_extra_state)(DeviceState *d);
- bool (*query_guest_notifiers)(DeviceState *d);
- int (*set_guest_notifiers)(DeviceState *d, int nvqs, bool assign);
- int (*set_host_notifier_mr)(DeviceState *d, int n,
- MemoryRegion *mr, bool assign);
- void (*vmstate_change)(DeviceState *d, bool running);
- /*
- * Expose the features the transport layer supports before
- * the negotiation takes place.
- */
- void (*pre_plugged)(DeviceState *d, Error **errp);
- /*
- * transport independent init function.
- * This is called by virtio-bus just after the device is plugged.
- */
- void (*device_plugged)(DeviceState *d, Error **errp);
- /*
- * transport independent exit function.
- * This is called by virtio-bus just before the device is unplugged.
- */
- void (*device_unplugged)(DeviceState *d);
- int (*query_nvectors)(DeviceState *d);
- /*
- * ioeventfd handling: if the transport implements ioeventfd_assign,
- * it must implement ioeventfd_enabled as well.
- */
- /* Returns true if the ioeventfd is enabled for the device. */
- bool (*ioeventfd_enabled)(DeviceState *d);
- /*
- * Assigns/deassigns the ioeventfd backing for the transport on
- * the device for queue number n. Returns an error value on
- * failure.
- */
- int (*ioeventfd_assign)(DeviceState *d, EventNotifier *notifier,
- int n, bool assign);
- /*
- * Whether queue number n is enabled.
- */
- bool (*queue_enabled)(DeviceState *d, int n);
- /*
- * Does the transport have variable vring alignment?
- * (ie can it ever call virtio_queue_set_align()?)
- * Note that changing this will break migration for this transport.
- */
- bool has_variable_vring_alignment;
- AddressSpace *(*get_dma_as)(DeviceState *d);
-};
-
-struct VirtioBusState {
- BusState parent_obj;
-
- /*
- * Set if ioeventfd has been started.
- */
- bool ioeventfd_started;
-
- /*
- * Set if ioeventfd has been grabbed by vhost. When ioeventfd
- * is grabbed by vhost, we track its started/stopped state (which
- * depends in turn on the virtio status register), but do not
- * register a handler for the ioeventfd. When ioeventfd is
- * released, if ioeventfd_started is true we finally register
- * the handler so that QEMU's device model can use ioeventfd.
- */
- int ioeventfd_grabbed;
-};
-
-void virtio_bus_device_plugged(VirtIODevice *vdev, Error **errp);
-void virtio_bus_reset(VirtioBusState *bus);
-void virtio_bus_device_unplugged(VirtIODevice *bus);
-/* Get the device id of the plugged device. */
-uint16_t virtio_bus_get_vdev_id(VirtioBusState *bus);
-/* Get the config_len field of the plugged device. */
-size_t virtio_bus_get_vdev_config_len(VirtioBusState *bus);
-/* Get bad features of the plugged device. */
-uint32_t virtio_bus_get_vdev_bad_features(VirtioBusState *bus);
-/* Get config of the plugged device. */
-void virtio_bus_get_vdev_config(VirtioBusState *bus, uint8_t *config);
-/* Set config of the plugged device. */
-void virtio_bus_set_vdev_config(VirtioBusState *bus, uint8_t *config);
-
-static inline VirtIODevice *virtio_bus_get_device(VirtioBusState *bus)
-{
- BusState *qbus = &bus->parent_obj;
- BusChild *kid = QTAILQ_FIRST(&qbus->children);
- DeviceState *qdev = kid ? kid->child : NULL;
-
- /* This is used on the data path, the cast is guaranteed
- * to succeed by the qdev machinery.
- */
- return (VirtIODevice *)qdev;
-}
-
-/* Return whether the proxy allows ioeventfd. */
-bool virtio_bus_ioeventfd_enabled(VirtioBusState *bus);
-/* Start the ioeventfd. */
-int virtio_bus_start_ioeventfd(VirtioBusState *bus);
-/* Stop the ioeventfd. */
-void virtio_bus_stop_ioeventfd(VirtioBusState *bus);
-/* Tell the bus that vhost is grabbing the ioeventfd. */
-int virtio_bus_grab_ioeventfd(VirtioBusState *bus);
-/* bus that vhost is not using the ioeventfd anymore. */
-void virtio_bus_release_ioeventfd(VirtioBusState *bus);
-/* Switch from/to the generic ioeventfd handler */
-int virtio_bus_set_host_notifier(VirtioBusState *bus, int n, bool assign);
-/* Tell the bus that the ioeventfd handler is no longer required. */
-void virtio_bus_cleanup_host_notifier(VirtioBusState *bus, int n);
-
-#endif /* VIRTIO_BUS_H */
+++ /dev/null
-/*
- * Virtio crypto Support
- *
- * Copyright (c) 2016 HUAWEI TECHNOLOGIES CO., LTD.
- *
- * Authors:
- * Gonglei <arei.gonglei@huawei.com>
- *
- * This work is licensed under the terms of the GNU GPL, version 2 or
- * (at your option) any later version. See the COPYING file in the
- * top-level directory.
- */
-
-#ifndef QEMU_VIRTIO_CRYPTO_H
-#define QEMU_VIRTIO_CRYPTO_H
-
-#include "standard-headers/linux/virtio_crypto.h"
-#include "hw/virtio/virtio.h"
-#include "sysemu/iothread.h"
-#include "sysemu/cryptodev.h"
-#include "qom/object.h"
-
-
-#define DEBUG_VIRTIO_CRYPTO 0
-
-#define DPRINTF(fmt, ...) \
-do { \
- if (DEBUG_VIRTIO_CRYPTO) { \
- fprintf(stderr, "virtio_crypto: " fmt, ##__VA_ARGS__); \
- } \
-} while (0)
-
-
-#define TYPE_VIRTIO_CRYPTO "virtio-crypto-device"
-OBJECT_DECLARE_SIMPLE_TYPE(VirtIOCrypto, VIRTIO_CRYPTO)
-#define VIRTIO_CRYPTO_GET_PARENT_CLASS(obj) \
- OBJECT_GET_PARENT_CLASS(obj, TYPE_VIRTIO_CRYPTO)
-
-
-typedef struct VirtIOCryptoConf {
- CryptoDevBackend *cryptodev;
-
- /* Supported service mask */
- uint32_t crypto_services;
-
- /* Detailed algorithms mask */
- uint32_t cipher_algo_l;
- uint32_t cipher_algo_h;
- uint32_t hash_algo;
- uint32_t mac_algo_l;
- uint32_t mac_algo_h;
- uint32_t aead_algo;
-
- /* Maximum length of cipher key */
- uint32_t max_cipher_key_len;
- /* Maximum length of authenticated key */
- uint32_t max_auth_key_len;
- /* Maximum size of each crypto request's content */
- uint64_t max_size;
-} VirtIOCryptoConf;
-
-struct VirtIOCrypto;
-
-typedef struct VirtIOCryptoReq {
- VirtQueueElement elem;
- /* flags of operation, such as type of algorithm */
- uint32_t flags;
- struct virtio_crypto_inhdr *in;
- struct iovec *in_iov; /* Head address of dest iovec */
- unsigned int in_num; /* Number of dest iovec */
- size_t in_len;
- VirtQueue *vq;
- struct VirtIOCrypto *vcrypto;
- union {
- CryptoDevBackendSymOpInfo *sym_op_info;
- } u;
-} VirtIOCryptoReq;
-
-typedef struct VirtIOCryptoQueue {
- VirtQueue *dataq;
- QEMUBH *dataq_bh;
- struct VirtIOCrypto *vcrypto;
-} VirtIOCryptoQueue;
-
-struct VirtIOCrypto {
- VirtIODevice parent_obj;
-
- VirtQueue *ctrl_vq;
- VirtIOCryptoQueue *vqs;
- VirtIOCryptoConf conf;
- CryptoDevBackend *cryptodev;
-
- uint32_t max_queues;
- uint32_t status;
-
- int multiqueue;
- uint32_t curr_queues;
- size_t config_size;
- uint8_t vhost_started;
-};
-
-#endif /* QEMU_VIRTIO_CRYPTO_H */
+++ /dev/null
-/*
- * Virtio GPU Device
- *
- * Copyright Red Hat, Inc. 2013-2014
- *
- * Authors:
- * Dave Airlie <airlied@redhat.com>
- * Gerd Hoffmann <kraxel@redhat.com>
- *
- * This work is licensed under the terms of the GNU GPL, version 2 or later.
- * See the COPYING file in the top-level directory.
- */
-
-#ifndef HW_VIRTIO_GPU_BSWAP_H
-#define HW_VIRTIO_GPU_BSWAP_H
-
-#include "qemu/bswap.h"
-#include "standard-headers/linux/virtio_gpu.h"
-
-static inline void
-virtio_gpu_ctrl_hdr_bswap(struct virtio_gpu_ctrl_hdr *hdr)
-{
- le32_to_cpus(&hdr->type);
- le32_to_cpus(&hdr->flags);
- le64_to_cpus(&hdr->fence_id);
- le32_to_cpus(&hdr->ctx_id);
- le32_to_cpus(&hdr->padding);
-}
-
-static inline void
-virtio_gpu_bswap_32(void *ptr, size_t size)
-{
-#ifdef HOST_WORDS_BIGENDIAN
-
- size_t i;
- struct virtio_gpu_ctrl_hdr *hdr = (struct virtio_gpu_ctrl_hdr *) ptr;
-
- virtio_gpu_ctrl_hdr_bswap(hdr);
-
- i = sizeof(struct virtio_gpu_ctrl_hdr);
- while (i < size) {
- le32_to_cpus((uint32_t *)(ptr + i));
- i = i + sizeof(uint32_t);
- }
-
-#endif
-}
-
-static inline void
-virtio_gpu_t2d_bswap(struct virtio_gpu_transfer_to_host_2d *t2d)
-{
- virtio_gpu_ctrl_hdr_bswap(&t2d->hdr);
- le32_to_cpus(&t2d->r.x);
- le32_to_cpus(&t2d->r.y);
- le32_to_cpus(&t2d->r.width);
- le32_to_cpus(&t2d->r.height);
- le64_to_cpus(&t2d->offset);
- le32_to_cpus(&t2d->resource_id);
- le32_to_cpus(&t2d->padding);
-}
-
-#endif
+++ /dev/null
-/*
- * Virtio GPU PCI Device
- *
- * Copyright Red Hat, Inc. 2013-2014
- *
- * Authors:
- * Dave Airlie <airlied@redhat.com>
- * Gerd Hoffmann <kraxel@redhat.com>
- *
- * This work is licensed under the terms of the GNU GPL, version 2.
- * See the COPYING file in the top-level directory.
- */
-
-#ifndef HW_VIRTIO_GPU_PCI_H
-#define HW_VIRTIO_GPU_PCI_H
-
-#include "hw/virtio/virtio-pci.h"
-#include "hw/virtio/virtio-gpu.h"
-#include "qom/object.h"
-
-
-/*
- * virtio-gpu-pci-base: This extends VirtioPCIProxy.
- */
-#define TYPE_VIRTIO_GPU_PCI_BASE "virtio-gpu-pci-base"
-OBJECT_DECLARE_SIMPLE_TYPE(VirtIOGPUPCIBase, VIRTIO_GPU_PCI_BASE)
-
-struct VirtIOGPUPCIBase {
- VirtIOPCIProxy parent_obj;
- VirtIOGPUBase *vgpu;
-};
-
-/* to share between PCI and VGA */
-#define DEFINE_VIRTIO_GPU_PCI_PROPERTIES(_state) \
- DEFINE_PROP_BIT("ioeventfd", _state, flags, \
- VIRTIO_PCI_FLAG_USE_IOEVENTFD_BIT, false), \
- DEFINE_PROP_UINT32("vectors", _state, nvectors, 3)
-
-#endif /* HW_VIRTIO_GPU_PCI_H */
+++ /dev/null
-/*
- * Virtio GPU Device
- *
- * Copyright Red Hat, Inc. 2013-2014
- *
- * Authors:
- * Dave Airlie <airlied@redhat.com>
- * Gerd Hoffmann <kraxel@redhat.com>
- *
- * This work is licensed under the terms of the GNU GPL, version 2 or later.
- * See the COPYING file in the top-level directory.
- */
-
-#ifndef HW_VIRTIO_GPU_PIXMAN_H
-#define HW_VIRTIO_GPU_PIXMAN_H
-
-#include "ui/qemu-pixman.h"
-#include "standard-headers/linux/virtio_gpu.h"
-
-static inline pixman_format_code_t
-virtio_gpu_get_pixman_format(uint32_t virtio_gpu_format)
-{
- switch (virtio_gpu_format) {
- case VIRTIO_GPU_FORMAT_B8G8R8X8_UNORM:
- return PIXMAN_BE_b8g8r8x8;
- case VIRTIO_GPU_FORMAT_B8G8R8A8_UNORM:
- return PIXMAN_BE_b8g8r8a8;
- case VIRTIO_GPU_FORMAT_X8R8G8B8_UNORM:
- return PIXMAN_BE_x8r8g8b8;
- case VIRTIO_GPU_FORMAT_A8R8G8B8_UNORM:
- return PIXMAN_BE_a8r8g8b8;
- case VIRTIO_GPU_FORMAT_R8G8B8X8_UNORM:
- return PIXMAN_BE_r8g8b8x8;
- case VIRTIO_GPU_FORMAT_R8G8B8A8_UNORM:
- return PIXMAN_BE_r8g8b8a8;
- case VIRTIO_GPU_FORMAT_X8B8G8R8_UNORM:
- return PIXMAN_BE_x8b8g8r8;
- case VIRTIO_GPU_FORMAT_A8B8G8R8_UNORM:
- return PIXMAN_BE_a8b8g8r8;
- default:
- return 0;
- }
-}
-
-#endif
+++ /dev/null
-/*
- * Virtio GPU Device
- *
- * Copyright Red Hat, Inc. 2013-2014
- *
- * Authors:
- * Dave Airlie <airlied@redhat.com>
- * Gerd Hoffmann <kraxel@redhat.com>
- *
- * This work is licensed under the terms of the GNU GPL, version 2.
- * See the COPYING file in the top-level directory.
- */
-
-#ifndef HW_VIRTIO_GPU_H
-#define HW_VIRTIO_GPU_H
-
-#include "qemu/queue.h"
-#include "ui/qemu-pixman.h"
-#include "ui/console.h"
-#include "hw/virtio/virtio.h"
-#include "qemu/log.h"
-#include "sysemu/vhost-user-backend.h"
-
-#include "standard-headers/linux/virtio_gpu.h"
-#include "qom/object.h"
-
-#define TYPE_VIRTIO_GPU_BASE "virtio-gpu-base"
-OBJECT_DECLARE_TYPE(VirtIOGPUBase, VirtIOGPUBaseClass,
- VIRTIO_GPU_BASE)
-
-#define TYPE_VIRTIO_GPU "virtio-gpu-device"
-OBJECT_DECLARE_SIMPLE_TYPE(VirtIOGPU, VIRTIO_GPU)
-
-#define TYPE_VHOST_USER_GPU "vhost-user-gpu"
-OBJECT_DECLARE_SIMPLE_TYPE(VhostUserGPU, VHOST_USER_GPU)
-
-#define VIRTIO_ID_GPU 16
-
-struct virtio_gpu_simple_resource {
- uint32_t resource_id;
- uint32_t width;
- uint32_t height;
- uint32_t format;
- uint64_t *addrs;
- struct iovec *iov;
- unsigned int iov_cnt;
- uint32_t scanout_bitmask;
- pixman_image_t *image;
- uint64_t hostmem;
- QTAILQ_ENTRY(virtio_gpu_simple_resource) next;
-};
-
-struct virtio_gpu_scanout {
- QemuConsole *con;
- DisplaySurface *ds;
- uint32_t width, height;
- int x, y;
- int invalidate;
- uint32_t resource_id;
- struct virtio_gpu_update_cursor cursor;
- QEMUCursor *current_cursor;
-};
-
-struct virtio_gpu_requested_state {
- uint16_t width_mm, height_mm;
- uint32_t width, height;
- int x, y;
-};
-
-enum virtio_gpu_base_conf_flags {
- VIRTIO_GPU_FLAG_VIRGL_ENABLED = 1,
- VIRTIO_GPU_FLAG_STATS_ENABLED,
- VIRTIO_GPU_FLAG_EDID_ENABLED,
-};
-
-#define virtio_gpu_virgl_enabled(_cfg) \
- (_cfg.flags & (1 << VIRTIO_GPU_FLAG_VIRGL_ENABLED))
-#define virtio_gpu_stats_enabled(_cfg) \
- (_cfg.flags & (1 << VIRTIO_GPU_FLAG_STATS_ENABLED))
-#define virtio_gpu_edid_enabled(_cfg) \
- (_cfg.flags & (1 << VIRTIO_GPU_FLAG_EDID_ENABLED))
-
-struct virtio_gpu_base_conf {
- uint32_t max_outputs;
- uint32_t flags;
- uint32_t xres;
- uint32_t yres;
-};
-
-struct virtio_gpu_ctrl_command {
- VirtQueueElement elem;
- VirtQueue *vq;
- struct virtio_gpu_ctrl_hdr cmd_hdr;
- uint32_t error;
- bool finished;
- QTAILQ_ENTRY(virtio_gpu_ctrl_command) next;
-};
-
-struct VirtIOGPUBase {
- VirtIODevice parent_obj;
-
- Error *migration_blocker;
-
- struct virtio_gpu_base_conf conf;
- struct virtio_gpu_config virtio_config;
- const GraphicHwOps *hw_ops;
-
- bool use_virgl_renderer;
- int renderer_blocked;
- int enable;
-
- struct virtio_gpu_scanout scanout[VIRTIO_GPU_MAX_SCANOUTS];
-
- int enabled_output_bitmask;
- struct virtio_gpu_requested_state req_state[VIRTIO_GPU_MAX_SCANOUTS];
-};
-
-struct VirtIOGPUBaseClass {
- VirtioDeviceClass parent;
-
- void (*gl_unblock)(VirtIOGPUBase *g);
-};
-
-#define VIRTIO_GPU_BASE_PROPERTIES(_state, _conf) \
- DEFINE_PROP_UINT32("max_outputs", _state, _conf.max_outputs, 1), \
- DEFINE_PROP_BIT("edid", _state, _conf.flags, \
- VIRTIO_GPU_FLAG_EDID_ENABLED, true), \
- DEFINE_PROP_UINT32("xres", _state, _conf.xres, 1024), \
- DEFINE_PROP_UINT32("yres", _state, _conf.yres, 768)
-
-struct VirtIOGPU {
- VirtIOGPUBase parent_obj;
-
- uint64_t conf_max_hostmem;
-
- VirtQueue *ctrl_vq;
- VirtQueue *cursor_vq;
-
- QEMUBH *ctrl_bh;
- QEMUBH *cursor_bh;
-
- QTAILQ_HEAD(, virtio_gpu_simple_resource) reslist;
- QTAILQ_HEAD(, virtio_gpu_ctrl_command) cmdq;
- QTAILQ_HEAD(, virtio_gpu_ctrl_command) fenceq;
-
- uint64_t hostmem;
-
- bool renderer_inited;
- bool renderer_reset;
- QEMUTimer *fence_poll;
- QEMUTimer *print_stats;
-
- uint32_t inflight;
- struct {
- uint32_t max_inflight;
- uint32_t requests;
- uint32_t req_3d;
- uint32_t bytes_3d;
- } stats;
-};
-
-struct VhostUserGPU {
- VirtIOGPUBase parent_obj;
-
- VhostUserBackend *vhost;
- int vhost_gpu_fd; /* closed by the chardev */
- CharBackend vhost_chr;
- QemuDmaBuf dmabuf[VIRTIO_GPU_MAX_SCANOUTS];
- bool backend_blocked;
-};
-
-#define VIRTIO_GPU_FILL_CMD(out) do { \
- size_t s; \
- s = iov_to_buf(cmd->elem.out_sg, cmd->elem.out_num, 0, \
- &out, sizeof(out)); \
- if (s != sizeof(out)) { \
- qemu_log_mask(LOG_GUEST_ERROR, \
- "%s: command size incorrect %zu vs %zu\n", \
- __func__, s, sizeof(out)); \
- return; \
- } \
- } while (0)
-
-/* virtio-gpu-base.c */
-bool virtio_gpu_base_device_realize(DeviceState *qdev,
- VirtIOHandleOutput ctrl_cb,
- VirtIOHandleOutput cursor_cb,
- Error **errp);
-void virtio_gpu_base_reset(VirtIOGPUBase *g);
-void virtio_gpu_base_fill_display_info(VirtIOGPUBase *g,
- struct virtio_gpu_resp_display_info *dpy_info);
-
-/* virtio-gpu.c */
-void virtio_gpu_ctrl_response(VirtIOGPU *g,
- struct virtio_gpu_ctrl_command *cmd,
- struct virtio_gpu_ctrl_hdr *resp,
- size_t resp_len);
-void virtio_gpu_ctrl_response_nodata(VirtIOGPU *g,
- struct virtio_gpu_ctrl_command *cmd,
- enum virtio_gpu_ctrl_type type);
-void virtio_gpu_get_display_info(VirtIOGPU *g,
- struct virtio_gpu_ctrl_command *cmd);
-void virtio_gpu_get_edid(VirtIOGPU *g,
- struct virtio_gpu_ctrl_command *cmd);
-int virtio_gpu_create_mapping_iov(VirtIOGPU *g,
- struct virtio_gpu_resource_attach_backing *ab,
- struct virtio_gpu_ctrl_command *cmd,
- uint64_t **addr, struct iovec **iov);
-void virtio_gpu_cleanup_mapping_iov(VirtIOGPU *g,
- struct iovec *iov, uint32_t count);
-void virtio_gpu_process_cmdq(VirtIOGPU *g);
-
-/* virtio-gpu-3d.c */
-void virtio_gpu_virgl_process_cmd(VirtIOGPU *g,
- struct virtio_gpu_ctrl_command *cmd);
-void virtio_gpu_virgl_fence_poll(VirtIOGPU *g);
-void virtio_gpu_virgl_reset(VirtIOGPU *g);
-int virtio_gpu_virgl_init(VirtIOGPU *g);
-int virtio_gpu_virgl_get_num_capsets(VirtIOGPU *g);
-
-#endif
+++ /dev/null
-#ifndef QEMU_VIRTIO_INPUT_H
-#define QEMU_VIRTIO_INPUT_H
-
-#include "ui/input.h"
-#include "sysemu/vhost-user-backend.h"
-
-/* ----------------------------------------------------------------- */
-/* virtio input protocol */
-
-#include "standard-headers/linux/virtio_ids.h"
-#include "standard-headers/linux/virtio_input.h"
-#include "qom/object.h"
-
-typedef struct virtio_input_absinfo virtio_input_absinfo;
-typedef struct virtio_input_config virtio_input_config;
-typedef struct virtio_input_event virtio_input_event;
-
-/* ----------------------------------------------------------------- */
-/* qemu internals */
-
-#define TYPE_VIRTIO_INPUT "virtio-input-device"
-OBJECT_DECLARE_TYPE(VirtIOInput, VirtIOInputClass,
- VIRTIO_INPUT)
-#define VIRTIO_INPUT_GET_PARENT_CLASS(obj) \
- OBJECT_GET_PARENT_CLASS(obj, TYPE_VIRTIO_INPUT)
-
-#define TYPE_VIRTIO_INPUT_HID "virtio-input-hid-device"
-#define TYPE_VIRTIO_KEYBOARD "virtio-keyboard-device"
-#define TYPE_VIRTIO_MOUSE "virtio-mouse-device"
-#define TYPE_VIRTIO_TABLET "virtio-tablet-device"
-
-OBJECT_DECLARE_SIMPLE_TYPE(VirtIOInputHID, VIRTIO_INPUT_HID)
-#define VIRTIO_INPUT_HID_GET_PARENT_CLASS(obj) \
- OBJECT_GET_PARENT_CLASS(obj, TYPE_VIRTIO_INPUT_HID)
-
-#define TYPE_VIRTIO_INPUT_HOST "virtio-input-host-device"
-OBJECT_DECLARE_SIMPLE_TYPE(VirtIOInputHost, VIRTIO_INPUT_HOST)
-#define VIRTIO_INPUT_HOST_GET_PARENT_CLASS(obj) \
- OBJECT_GET_PARENT_CLASS(obj, TYPE_VIRTIO_INPUT_HOST)
-
-#define TYPE_VHOST_USER_INPUT "vhost-user-input"
-OBJECT_DECLARE_SIMPLE_TYPE(VHostUserInput, VHOST_USER_INPUT)
-#define VHOST_USER_INPUT_GET_PARENT_CLASS(obj) \
- OBJECT_GET_PARENT_CLASS(obj, TYPE_VHOST_USER_INPUT)
-
-typedef struct VirtIOInputConfig VirtIOInputConfig;
-
-struct VirtIOInputConfig {
- virtio_input_config config;
- QTAILQ_ENTRY(VirtIOInputConfig) node;
-};
-
-struct VirtIOInput {
- VirtIODevice parent_obj;
- uint8_t cfg_select;
- uint8_t cfg_subsel;
- uint32_t cfg_size;
- QTAILQ_HEAD(, VirtIOInputConfig) cfg_list;
- VirtQueue *evt, *sts;
- char *serial;
-
- struct {
- virtio_input_event event;
- VirtQueueElement *elem;
- } *queue;
- uint32_t qindex, qsize;
-
- bool active;
-};
-
-struct VirtIOInputClass {
- /*< private >*/
- VirtioDeviceClass parent;
- /*< public >*/
-
- DeviceRealize realize;
- DeviceUnrealize unrealize;
- void (*change_active)(VirtIOInput *vinput);
- void (*handle_status)(VirtIOInput *vinput, virtio_input_event *event);
-};
-
-struct VirtIOInputHID {
- VirtIOInput parent_obj;
- char *display;
- uint32_t head;
- QemuInputHandler *handler;
- QemuInputHandlerState *hs;
- int ledstate;
- bool wheel_axis;
-};
-
-struct VirtIOInputHost {
- VirtIOInput parent_obj;
- char *evdev;
- int fd;
-};
-
-struct VHostUserInput {
- VirtIOInput parent_obj;
-
- VhostUserBackend *vhost;
-};
-
-void virtio_input_send(VirtIOInput *vinput, virtio_input_event *event);
-void virtio_input_init_config(VirtIOInput *vinput,
- virtio_input_config *config);
-virtio_input_config *virtio_input_find_config(VirtIOInput *vinput,
- uint8_t select,
- uint8_t subsel);
-void virtio_input_add_config(VirtIOInput *vinput,
- virtio_input_config *config);
-void virtio_input_idstr_config(VirtIOInput *vinput,
- uint8_t select, const char *string);
-
-#endif /* QEMU_VIRTIO_INPUT_H */
+++ /dev/null
-/*
- * virtio-iommu device
- *
- * Copyright (c) 2020 Red Hat, Inc.
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms and conditions of the GNU General Public License,
- * version 2 or later, as published by the Free Software Foundation.
- *
- * This program is distributed in the hope it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License along with
- * this program. If not, see <http://www.gnu.org/licenses/>.
- *
- */
-
-#ifndef QEMU_VIRTIO_IOMMU_H
-#define QEMU_VIRTIO_IOMMU_H
-
-#include "standard-headers/linux/virtio_iommu.h"
-#include "hw/virtio/virtio.h"
-#include "hw/pci/pci.h"
-#include "qom/object.h"
-
-#define TYPE_VIRTIO_IOMMU "virtio-iommu-device"
-#define TYPE_VIRTIO_IOMMU_PCI "virtio-iommu-device-base"
-OBJECT_DECLARE_SIMPLE_TYPE(VirtIOIOMMU, VIRTIO_IOMMU)
-
-#define TYPE_VIRTIO_IOMMU_MEMORY_REGION "virtio-iommu-memory-region"
-
-typedef struct IOMMUDevice {
- void *viommu;
- PCIBus *bus;
- int devfn;
- IOMMUMemoryRegion iommu_mr;
- AddressSpace as;
-} IOMMUDevice;
-
-typedef struct IOMMUPciBus {
- PCIBus *bus;
- IOMMUDevice *pbdev[]; /* Parent array is sparse, so dynamically alloc */
-} IOMMUPciBus;
-
-struct VirtIOIOMMU {
- VirtIODevice parent_obj;
- VirtQueue *req_vq;
- VirtQueue *event_vq;
- struct virtio_iommu_config config;
- uint64_t features;
- GHashTable *as_by_busptr;
- IOMMUPciBus *iommu_pcibus_by_bus_num[PCI_BUS_MAX];
- PCIBus *primary_bus;
- ReservedRegion *reserved_regions;
- uint32_t nb_reserved_regions;
- GTree *domains;
- QemuMutex mutex;
- GTree *endpoints;
-};
-
-#endif
+++ /dev/null
-/*
- * Virtio MEM device
- *
- * Copyright (C) 2020 Red Hat, Inc.
- *
- * Authors:
- * David Hildenbrand <david@redhat.com>
- *
- * This work is licensed under the terms of the GNU GPL, version 2.
- * See the COPYING file in the top-level directory.
- */
-
-#ifndef HW_VIRTIO_MEM_H
-#define HW_VIRTIO_MEM_H
-
-#include "standard-headers/linux/virtio_mem.h"
-#include "hw/virtio/virtio.h"
-#include "qapi/qapi-types-misc.h"
-#include "sysemu/hostmem.h"
-#include "qom/object.h"
-
-#define TYPE_VIRTIO_MEM "virtio-mem"
-
-OBJECT_DECLARE_TYPE(VirtIOMEM, VirtIOMEMClass,
- VIRTIO_MEM)
-
-#define VIRTIO_MEM_MEMDEV_PROP "memdev"
-#define VIRTIO_MEM_NODE_PROP "node"
-#define VIRTIO_MEM_SIZE_PROP "size"
-#define VIRTIO_MEM_REQUESTED_SIZE_PROP "requested-size"
-#define VIRTIO_MEM_BLOCK_SIZE_PROP "block-size"
-#define VIRTIO_MEM_ADDR_PROP "memaddr"
-
-struct VirtIOMEM {
- VirtIODevice parent_obj;
-
- /* guest -> host request queue */
- VirtQueue *vq;
-
- /* bitmap used to track unplugged memory */
- int32_t bitmap_size;
- unsigned long *bitmap;
-
- /* assigned memory backend and memory region */
- HostMemoryBackend *memdev;
-
- /* NUMA node */
- uint32_t node;
-
- /* assigned address of the region in guest physical memory */
- uint64_t addr;
-
- /* usable region size (<= region_size) */
- uint64_t usable_region_size;
-
- /* actual size (how much the guest plugged) */
- uint64_t size;
-
- /* requested size */
- uint64_t requested_size;
-
- /* block size and alignment */
- uint64_t block_size;
-
- /* notifiers to notify when "size" changes */
- NotifierList size_change_notifiers;
-
- /* don't migrate unplugged memory */
- NotifierWithReturn precopy_notifier;
-};
-
-struct VirtIOMEMClass {
- /* private */
- VirtIODevice parent;
-
- /* public */
- void (*fill_device_info)(const VirtIOMEM *vmen, VirtioMEMDeviceInfo *vi);
- MemoryRegion *(*get_memory_region)(VirtIOMEM *vmem, Error **errp);
- void (*add_size_change_notifier)(VirtIOMEM *vmem, Notifier *notifier);
- void (*remove_size_change_notifier)(VirtIOMEM *vmem, Notifier *notifier);
-};
-
-#endif
+++ /dev/null
-/*
- * Virtio MMIO bindings
- *
- * Copyright (c) 2011 Linaro Limited
- *
- * Author:
- * Peter Maydell <peter.maydell@linaro.org>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License; either version 2
- * of the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License along
- * with this program; if not, see <http://www.gnu.org/licenses/>.
- */
-
-#ifndef HW_VIRTIO_MMIO_H
-#define HW_VIRTIO_MMIO_H
-
-#include "hw/virtio/virtio-bus.h"
-#include "qom/object.h"
-
-/* QOM macros */
-/* virtio-mmio-bus */
-#define TYPE_VIRTIO_MMIO_BUS "virtio-mmio-bus"
-/* This is reusing the VirtioBusState typedef from TYPE_VIRTIO_BUS */
-DECLARE_OBJ_CHECKERS(VirtioBusState, VirtioBusClass,
- VIRTIO_MMIO_BUS, TYPE_VIRTIO_MMIO_BUS)
-
-/* virtio-mmio */
-#define TYPE_VIRTIO_MMIO "virtio-mmio"
-OBJECT_DECLARE_SIMPLE_TYPE(VirtIOMMIOProxy, VIRTIO_MMIO)
-
-#define VIRT_MAGIC 0x74726976 /* 'virt' */
-#define VIRT_VERSION 2
-#define VIRT_VERSION_LEGACY 1
-#define VIRT_VENDOR 0x554D4551 /* 'QEMU' */
-
-typedef struct VirtIOMMIOQueue {
- uint16_t num;
- bool enabled;
- uint32_t desc[2];
- uint32_t avail[2];
- uint32_t used[2];
-} VirtIOMMIOQueue;
-
-struct VirtIOMMIOProxy {
- /* Generic */
- SysBusDevice parent_obj;
- MemoryRegion iomem;
- qemu_irq irq;
- bool legacy;
- /* Guest accessible state needing migration and reset */
- uint32_t host_features_sel;
- uint32_t guest_features_sel;
- uint32_t guest_page_shift;
- /* virtio-bus */
- VirtioBusState bus;
- bool format_transport_address;
- /* Fields only used for non-legacy (v2) devices */
- uint32_t guest_features[2];
- VirtIOMMIOQueue vqs[VIRTIO_QUEUE_MAX];
-};
-
-#endif
+++ /dev/null
-/*
- * Virtio Network Device
- *
- * Copyright IBM, Corp. 2007
- *
- * Authors:
- * Anthony Liguori <aliguori@us.ibm.com>
- *
- * This work is licensed under the terms of the GNU GPL, version 2. See
- * the COPYING file in the top-level directory.
- *
- */
-
-#ifndef QEMU_VIRTIO_NET_H
-#define QEMU_VIRTIO_NET_H
-
-#include "qemu/units.h"
-#include "standard-headers/linux/virtio_net.h"
-#include "hw/virtio/virtio.h"
-#include "net/announce.h"
-#include "qemu/option_int.h"
-#include "qom/object.h"
-
-#define TYPE_VIRTIO_NET "virtio-net-device"
-OBJECT_DECLARE_SIMPLE_TYPE(VirtIONet, VIRTIO_NET)
-
-#define TX_TIMER_INTERVAL 150000 /* 150 us */
-
-/* Limit the number of packets that can be sent via a single flush
- * of the TX queue. This gives us a guaranteed exit condition and
- * ensures fairness in the io path. 256 conveniently matches the
- * length of the TX queue and shows a good balance of performance
- * and latency. */
-#define TX_BURST 256
-
-typedef struct virtio_net_conf
-{
- uint32_t txtimer;
- int32_t txburst;
- char *tx;
- uint16_t rx_queue_size;
- uint16_t tx_queue_size;
- uint16_t mtu;
- int32_t speed;
- char *duplex_str;
- uint8_t duplex;
- char *primary_id_str;
-} virtio_net_conf;
-
-/* Coalesced packets type & status */
-typedef enum {
- RSC_COALESCE, /* Data been coalesced */
- RSC_FINAL, /* Will terminate current connection */
- RSC_NO_MATCH, /* No matched in the buffer pool */
- RSC_BYPASS, /* Packet to be bypass, not tcp, tcp ctrl, etc */
- RSC_CANDIDATE /* Data want to be coalesced */
-} CoalesceStatus;
-
-typedef struct VirtioNetRscStat {
- uint32_t received;
- uint32_t coalesced;
- uint32_t over_size;
- uint32_t cache;
- uint32_t empty_cache;
- uint32_t no_match_cache;
- uint32_t win_update;
- uint32_t no_match;
- uint32_t tcp_syn;
- uint32_t tcp_ctrl_drain;
- uint32_t dup_ack;
- uint32_t dup_ack1;
- uint32_t dup_ack2;
- uint32_t pure_ack;
- uint32_t ack_out_of_win;
- uint32_t data_out_of_win;
- uint32_t data_out_of_order;
- uint32_t data_after_pure_ack;
- uint32_t bypass_not_tcp;
- uint32_t tcp_option;
- uint32_t tcp_all_opt;
- uint32_t ip_frag;
- uint32_t ip_ecn;
- uint32_t ip_hacked;
- uint32_t ip_option;
- uint32_t purge_failed;
- uint32_t drain_failed;
- uint32_t final_failed;
- int64_t timer;
-} VirtioNetRscStat;
-
-/* Rsc unit general info used to checking if can coalescing */
-typedef struct VirtioNetRscUnit {
- void *ip; /* ip header */
- uint16_t *ip_plen; /* data len pointer in ip header field */
- struct tcp_header *tcp; /* tcp header */
- uint16_t tcp_hdrlen; /* tcp header len */
- uint16_t payload; /* pure payload without virtio/eth/ip/tcp */
-} VirtioNetRscUnit;
-
-/* Coalesced segment */
-typedef struct VirtioNetRscSeg {
- QTAILQ_ENTRY(VirtioNetRscSeg) next;
- void *buf;
- size_t size;
- uint16_t packets;
- uint16_t dup_ack;
- bool is_coalesced; /* need recal ipv4 header checksum, mark here */
- VirtioNetRscUnit unit;
- NetClientState *nc;
-} VirtioNetRscSeg;
-
-
-/* Chain is divided by protocol(ipv4/v6) and NetClientInfo */
-typedef struct VirtioNetRscChain {
- QTAILQ_ENTRY(VirtioNetRscChain) next;
- VirtIONet *n; /* VirtIONet */
- uint16_t proto;
- uint8_t gso_type;
- uint16_t max_payload;
- QEMUTimer *drain_timer;
- QTAILQ_HEAD(, VirtioNetRscSeg) buffers;
- VirtioNetRscStat stat;
-} VirtioNetRscChain;
-
-/* Maximum packet size we can receive from tap device: header + 64k */
-#define VIRTIO_NET_MAX_BUFSIZE (sizeof(struct virtio_net_hdr) + (64 * KiB))
-
-#define VIRTIO_NET_RSS_MAX_KEY_SIZE 40
-#define VIRTIO_NET_RSS_MAX_TABLE_LEN 128
-
-typedef struct VirtioNetRssData {
- bool enabled;
- bool redirect;
- bool populate_hash;
- uint32_t hash_types;
- uint8_t key[VIRTIO_NET_RSS_MAX_KEY_SIZE];
- uint16_t indirections_len;
- uint16_t *indirections_table;
- uint16_t default_queue;
-} VirtioNetRssData;
-
-typedef struct VirtIONetQueue {
- VirtQueue *rx_vq;
- VirtQueue *tx_vq;
- QEMUTimer *tx_timer;
- QEMUBH *tx_bh;
- uint32_t tx_waiting;
- struct {
- VirtQueueElement *elem;
- } async_tx;
- struct VirtIONet *n;
-} VirtIONetQueue;
-
-struct VirtIONet {
- VirtIODevice parent_obj;
- uint8_t mac[ETH_ALEN];
- uint16_t status;
- VirtIONetQueue *vqs;
- VirtQueue *ctrl_vq;
- NICState *nic;
- /* RSC Chains - temporary storage of coalesced data,
- all these data are lost in case of migration */
- QTAILQ_HEAD(, VirtioNetRscChain) rsc_chains;
- uint32_t tx_timeout;
- int32_t tx_burst;
- uint32_t has_vnet_hdr;
- size_t host_hdr_len;
- size_t guest_hdr_len;
- uint64_t host_features;
- uint32_t rsc_timeout;
- uint8_t rsc4_enabled;
- uint8_t rsc6_enabled;
- uint8_t has_ufo;
- uint32_t mergeable_rx_bufs;
- uint8_t promisc;
- uint8_t allmulti;
- uint8_t alluni;
- uint8_t nomulti;
- uint8_t nouni;
- uint8_t nobcast;
- uint8_t vhost_started;
- struct {
- uint32_t in_use;
- uint32_t first_multi;
- uint8_t multi_overflow;
- uint8_t uni_overflow;
- uint8_t *macs;
- } mac_table;
- uint32_t *vlans;
- virtio_net_conf net_conf;
- NICConf nic_conf;
- DeviceState *qdev;
- int multiqueue;
- uint16_t max_queues;
- uint16_t curr_queues;
- size_t config_size;
- char *netclient_name;
- char *netclient_type;
- uint64_t curr_guest_offloads;
- /* used on saved state restore phase to preserve the curr_guest_offloads */
- uint64_t saved_guest_offloads;
- AnnounceTimer announce_timer;
- bool needs_vnet_hdr_swap;
- bool mtu_bypass_backend;
- QemuOpts *primary_device_opts;
- QDict *primary_device_dict;
- DeviceState *primary_dev;
- BusState *primary_bus;
- char *primary_device_id;
- char *standby_id;
- bool primary_should_be_hidden;
- bool failover;
- DeviceListener primary_listener;
- Notifier migration_state;
- VirtioNetRssData rss_data;
- struct NetRxPkt *rx_pkt;
-};
-
-void virtio_net_set_netclient_name(VirtIONet *n, const char *name,
- const char *type);
-
-#endif
+++ /dev/null
-/*
- * Virtio PMEM device
- *
- * Copyright (C) 2018-2019 Red Hat, Inc.
- *
- * Authors:
- * Pankaj Gupta <pagupta@redhat.com>
- * David Hildenbrand <david@redhat.com>
- *
- * This work is licensed under the terms of the GNU GPL, version 2.
- * See the COPYING file in the top-level directory.
- */
-
-#ifndef HW_VIRTIO_PMEM_H
-#define HW_VIRTIO_PMEM_H
-
-#include "hw/virtio/virtio.h"
-#include "qapi/qapi-types-machine.h"
-#include "qom/object.h"
-
-#define TYPE_VIRTIO_PMEM "virtio-pmem"
-
-OBJECT_DECLARE_TYPE(VirtIOPMEM, VirtIOPMEMClass,
- VIRTIO_PMEM)
-
-#define VIRTIO_PMEM_ADDR_PROP "memaddr"
-#define VIRTIO_PMEM_MEMDEV_PROP "memdev"
-
-struct VirtIOPMEM {
- VirtIODevice parent_obj;
-
- VirtQueue *rq_vq;
- uint64_t start;
- HostMemoryBackend *memdev;
-};
-
-struct VirtIOPMEMClass {
- /* private */
- VirtIODevice parent;
-
- /* public */
- void (*fill_device_info)(const VirtIOPMEM *pmem, VirtioPMEMDeviceInfo *vi);
- MemoryRegion *(*get_memory_region)(VirtIOPMEM *pmem, Error **errp);
-};
-
-#endif
+++ /dev/null
-/*
- * Virtio RNG Support
- *
- * Copyright Red Hat, Inc. 2012
- * Copyright Amit Shah <amit.shah@redhat.com>
- *
- * This work is licensed under the terms of the GNU GPL, version 2 or
- * (at your option) any later version. See the COPYING file in the
- * top-level directory.
- */
-
-#ifndef QEMU_VIRTIO_RNG_H
-#define QEMU_VIRTIO_RNG_H
-
-#include "hw/virtio/virtio.h"
-#include "sysemu/rng.h"
-#include "standard-headers/linux/virtio_rng.h"
-#include "qom/object.h"
-
-#define TYPE_VIRTIO_RNG "virtio-rng-device"
-OBJECT_DECLARE_SIMPLE_TYPE(VirtIORNG, VIRTIO_RNG)
-#define VIRTIO_RNG_GET_PARENT_CLASS(obj) \
- OBJECT_GET_PARENT_CLASS(obj, TYPE_VIRTIO_RNG)
-
-struct VirtIORNGConf {
- RngBackend *rng;
- uint64_t max_bytes;
- uint32_t period_ms;
-};
-
-struct VirtIORNG {
- VirtIODevice parent_obj;
-
- /* Only one vq - guest puts buffer(s) on it when it needs entropy */
- VirtQueue *vq;
-
- VirtIORNGConf conf;
-
- RngBackend *rng;
-
- /* We purposefully don't migrate this state. The quota will reset on the
- * destination as a result. Rate limiting is host state, not guest state.
- */
- QEMUTimer *rate_limit_timer;
- int64_t quota_remaining;
- bool activate_timer;
-
- VMChangeStateEntry *vmstate;
-};
-
-#endif
+++ /dev/null
-/*
- * Virtio SCSI HBA
- *
- * Copyright IBM, Corp. 2010
- *
- * Authors:
- * Stefan Hajnoczi <stefanha@linux.vnet.ibm.com>
- *
- * This work is licensed under the terms of the GNU GPL, version 2. See
- * the COPYING file in the top-level directory.
- *
- */
-
-#ifndef QEMU_VIRTIO_SCSI_H
-#define QEMU_VIRTIO_SCSI_H
-#include "qom/object.h"
-
-/* Override CDB/sense data size: they are dynamic (guest controlled) in QEMU */
-#define VIRTIO_SCSI_CDB_SIZE 0
-#define VIRTIO_SCSI_SENSE_SIZE 0
-#include "standard-headers/linux/virtio_scsi.h"
-#include "hw/virtio/virtio.h"
-#include "hw/pci/pci.h"
-#include "hw/scsi/scsi.h"
-#include "chardev/char-fe.h"
-#include "sysemu/iothread.h"
-
-#define TYPE_VIRTIO_SCSI_COMMON "virtio-scsi-common"
-OBJECT_DECLARE_SIMPLE_TYPE(VirtIOSCSICommon, VIRTIO_SCSI_COMMON)
-
-#define TYPE_VIRTIO_SCSI "virtio-scsi-device"
-OBJECT_DECLARE_SIMPLE_TYPE(VirtIOSCSI, VIRTIO_SCSI)
-
-#define VIRTIO_SCSI_MAX_CHANNEL 0
-#define VIRTIO_SCSI_MAX_TARGET 255
-#define VIRTIO_SCSI_MAX_LUN 16383
-
-/* Number of virtqueues that are always present */
-#define VIRTIO_SCSI_VQ_NUM_FIXED 2
-
-#define VIRTIO_SCSI_AUTO_NUM_QUEUES UINT32_MAX
-
-typedef struct virtio_scsi_cmd_req VirtIOSCSICmdReq;
-typedef struct virtio_scsi_cmd_resp VirtIOSCSICmdResp;
-typedef struct virtio_scsi_ctrl_tmf_req VirtIOSCSICtrlTMFReq;
-typedef struct virtio_scsi_ctrl_tmf_resp VirtIOSCSICtrlTMFResp;
-typedef struct virtio_scsi_ctrl_an_req VirtIOSCSICtrlANReq;
-typedef struct virtio_scsi_ctrl_an_resp VirtIOSCSICtrlANResp;
-typedef struct virtio_scsi_event VirtIOSCSIEvent;
-typedef struct virtio_scsi_config VirtIOSCSIConfig;
-
-struct VirtIOSCSIConf {
- uint32_t num_queues;
- uint32_t virtqueue_size;
- bool seg_max_adjust;
- uint32_t max_sectors;
- uint32_t cmd_per_lun;
-#ifdef CONFIG_VHOST_SCSI
- char *vhostfd;
- char *wwpn;
-#endif
- CharBackend chardev;
- uint32_t boot_tpgt;
- IOThread *iothread;
-};
-
-struct VirtIOSCSI;
-
-struct VirtIOSCSICommon {
- VirtIODevice parent_obj;
- VirtIOSCSIConf conf;
-
- uint32_t sense_size;
- uint32_t cdb_size;
- VirtQueue *ctrl_vq;
- VirtQueue *event_vq;
- VirtQueue **cmd_vqs;
-};
-
-struct VirtIOSCSI {
- VirtIOSCSICommon parent_obj;
-
- SCSIBus bus;
- int resetting;
- bool events_dropped;
-
- /* Fields for dataplane below */
- AioContext *ctx; /* one iothread per virtio-scsi-pci for now */
-
- bool dataplane_started;
- bool dataplane_starting;
- bool dataplane_stopping;
- bool dataplane_fenced;
- uint32_t host_features;
-};
-
-typedef struct VirtIOSCSIReq {
- /* Note:
- * - fields up to resp_iov are initialized by virtio_scsi_init_req;
- * - fields starting at vring are zeroed by virtio_scsi_init_req.
- * */
- VirtQueueElement elem;
-
- VirtIOSCSI *dev;
- VirtQueue *vq;
- QEMUSGList qsgl;
- QEMUIOVector resp_iov;
-
- union {
- /* Used for two-stage request submission */
- QTAILQ_ENTRY(VirtIOSCSIReq) next;
-
- /* Used for cancellation of request during TMFs */
- int remaining;
- };
-
- SCSIRequest *sreq;
- size_t resp_size;
- enum SCSIXferMode mode;
- union {
- VirtIOSCSICmdResp cmd;
- VirtIOSCSICtrlTMFResp tmf;
- VirtIOSCSICtrlANResp an;
- VirtIOSCSIEvent event;
- } resp;
- union {
- VirtIOSCSICmdReq cmd;
- VirtIOSCSICtrlTMFReq tmf;
- VirtIOSCSICtrlANReq an;
- } req;
-} VirtIOSCSIReq;
-
-static inline void virtio_scsi_acquire(VirtIOSCSI *s)
-{
- if (s->ctx) {
- aio_context_acquire(s->ctx);
- }
-}
-
-static inline void virtio_scsi_release(VirtIOSCSI *s)
-{
- if (s->ctx) {
- aio_context_release(s->ctx);
- }
-}
-
-void virtio_scsi_common_realize(DeviceState *dev,
- VirtIOHandleOutput ctrl,
- VirtIOHandleOutput evt,
- VirtIOHandleOutput cmd,
- Error **errp);
-
-void virtio_scsi_common_unrealize(DeviceState *dev);
-bool virtio_scsi_handle_event_vq(VirtIOSCSI *s, VirtQueue *vq);
-bool virtio_scsi_handle_cmd_vq(VirtIOSCSI *s, VirtQueue *vq);
-bool virtio_scsi_handle_ctrl_vq(VirtIOSCSI *s, VirtQueue *vq);
-void virtio_scsi_init_req(VirtIOSCSI *s, VirtQueue *vq, VirtIOSCSIReq *req);
-void virtio_scsi_free_req(VirtIOSCSIReq *req);
-void virtio_scsi_push_event(VirtIOSCSI *s, SCSIDevice *dev,
- uint32_t event, uint32_t reason);
-
-void virtio_scsi_dataplane_setup(VirtIOSCSI *s, Error **errp);
-int virtio_scsi_dataplane_start(VirtIODevice *s);
-void virtio_scsi_dataplane_stop(VirtIODevice *s);
-
-#endif /* QEMU_VIRTIO_SCSI_H */
+++ /dev/null
-/*
- * Virtio Serial / Console Support
- *
- * Copyright IBM, Corp. 2008
- * Copyright Red Hat, Inc. 2009, 2010
- *
- * Authors:
- * Christian Ehrhardt <ehrhardt@linux.vnet.ibm.com>
- * Amit Shah <amit.shah@redhat.com>
- *
- * This work is licensed under the terms of the GNU GPL, version 2. See
- * the COPYING file in the top-level directory.
- *
- */
-
-#ifndef QEMU_VIRTIO_SERIAL_H
-#define QEMU_VIRTIO_SERIAL_H
-
-#include "standard-headers/linux/virtio_console.h"
-#include "hw/virtio/virtio.h"
-#include "qom/object.h"
-
-struct virtio_serial_conf {
- /* Max. number of ports we can have for a virtio-serial device */
- uint32_t max_virtserial_ports;
-};
-
-#define TYPE_VIRTIO_SERIAL_PORT "virtio-serial-port"
-OBJECT_DECLARE_TYPE(VirtIOSerialPort, VirtIOSerialPortClass,
- VIRTIO_SERIAL_PORT)
-
-typedef struct VirtIOSerial VirtIOSerial;
-
-#define TYPE_VIRTIO_SERIAL_BUS "virtio-serial-bus"
-OBJECT_DECLARE_SIMPLE_TYPE(VirtIOSerialBus, VIRTIO_SERIAL_BUS)
-
-
-struct VirtIOSerialPortClass {
- DeviceClass parent_class;
-
- /* Is this a device that binds with hvc in the guest? */
- bool is_console;
-
- /*
- * The per-port (or per-app) realize function that's called when a
- * new device is found on the bus.
- */
- DeviceRealize realize;
- /*
- * Per-port unrealize function that's called when a port gets
- * hot-unplugged or removed.
- */
- DeviceUnrealize unrealize;
-
- /* Callbacks for guest events */
- /* Guest opened/closed device. */
- void (*set_guest_connected)(VirtIOSerialPort *port, int guest_connected);
-
- /* Enable/disable backend for virtio serial port */
- void (*enable_backend)(VirtIOSerialPort *port, bool enable);
-
- /* Guest is now ready to accept data (virtqueues set up). */
- void (*guest_ready)(VirtIOSerialPort *port);
-
- /*
- * Guest has enqueued a buffer for the host to write into.
- * Called each time a buffer is enqueued by the guest;
- * irrespective of whether there already were free buffers the
- * host could have consumed.
- *
- * This is dependent on both the guest and host end being
- * connected.
- */
- void (*guest_writable)(VirtIOSerialPort *port);
-
- /*
- * Guest wrote some data to the port. This data is handed over to
- * the app via this callback. The app can return a size less than
- * 'len'. In this case, throttling will be enabled for this port.
- */
- ssize_t (*have_data)(VirtIOSerialPort *port, const uint8_t *buf,
- ssize_t len);
-};
-
-/*
- * This is the state that's shared between all the ports. Some of the
- * state is configurable via command-line options. Some of it can be
- * set by individual devices in their initfn routines. Some of the
- * state is set by the generic qdev device init routine.
- */
-struct VirtIOSerialPort {
- DeviceState dev;
-
- QTAILQ_ENTRY(VirtIOSerialPort) next;
-
- /*
- * This field gives us the virtio device as well as the qdev bus
- * that we are associated with
- */
- VirtIOSerial *vser;
-
- VirtQueue *ivq, *ovq;
-
- /*
- * This name is sent to the guest and exported via sysfs.
- * The guest could create symlinks based on this information.
- * The name is in the reverse fqdn format, like org.qemu.console.0
- */
- char *name;
-
- /*
- * This id helps identify ports between the guest and the host.
- * The guest sends a "header" with this id with each data packet
- * that it sends and the host can then find out which associated
- * device to send out this data to
- */
- uint32_t id;
-
- /*
- * This is the elem that we pop from the virtqueue. A slow
- * backend that consumes guest data (e.g. the file backend for
- * qemu chardevs) can cause the guest to block till all the output
- * is flushed. This isn't desired, so we keep a note of the last
- * element popped and continue consuming it once the backend
- * becomes writable again.
- */
- VirtQueueElement *elem;
-
- /*
- * The index and the offset into the iov buffer that was popped in
- * elem above.
- */
- uint32_t iov_idx;
- uint64_t iov_offset;
-
- /*
- * When unthrottling we use a bottom-half to call flush_queued_data.
- */
- QEMUBH *bh;
-
- /* Is the corresponding guest device open? */
- bool guest_connected;
- /* Is this device open for IO on the host? */
- bool host_connected;
- /* Do apps not want to receive data? */
- bool throttled;
-};
-
-/* The virtio-serial bus on top of which the ports will ride as devices */
-struct VirtIOSerialBus {
- BusState qbus;
-
- /* This is the parent device that provides the bus for ports. */
- VirtIOSerial *vser;
-
- /* The maximum number of ports that can ride on top of this bus */
- uint32_t max_nr_ports;
-};
-
-typedef struct VirtIOSerialPostLoad {
- QEMUTimer *timer;
- uint32_t nr_active_ports;
- struct {
- VirtIOSerialPort *port;
- uint8_t host_connected;
- } *connected;
-} VirtIOSerialPostLoad;
-
-struct VirtIOSerial {
- VirtIODevice parent_obj;
-
- VirtQueue *c_ivq, *c_ovq;
- /* Arrays of ivqs and ovqs: one per port */
- VirtQueue **ivqs, **ovqs;
-
- VirtIOSerialBus bus;
-
- QTAILQ_HEAD(, VirtIOSerialPort) ports;
-
- QLIST_ENTRY(VirtIOSerial) next;
-
- /* bitmap for identifying active ports */
- uint32_t *ports_map;
-
- struct VirtIOSerialPostLoad *post_load;
-
- virtio_serial_conf serial;
-
- uint64_t host_features;
-};
-
-/* Interface to the virtio-serial bus */
-
-/*
- * Open a connection to the port
- * Returns 0 on success (always).
- */
-int virtio_serial_open(VirtIOSerialPort *port);
-
-/*
- * Close the connection to the port
- * Returns 0 on success (always).
- */
-int virtio_serial_close(VirtIOSerialPort *port);
-
-/*
- * Send data to Guest
- */
-ssize_t virtio_serial_write(VirtIOSerialPort *port, const uint8_t *buf,
- size_t size);
-
-/*
- * Query whether a guest is ready to receive data.
- */
-size_t virtio_serial_guest_ready(VirtIOSerialPort *port);
-
-/*
- * Flow control: Ports can signal to the virtio-serial core to stop
- * sending data or re-start sending data, depending on the 'throttle'
- * value here.
- */
-void virtio_serial_throttle_port(VirtIOSerialPort *port, bool throttle);
-
-#define TYPE_VIRTIO_SERIAL "virtio-serial-device"
-OBJECT_DECLARE_SIMPLE_TYPE(VirtIOSerial, VIRTIO_SERIAL)
-
-#endif
+++ /dev/null
-/*
- * Virtio Support
- *
- * Copyright IBM, Corp. 2007
- *
- * Authors:
- * Anthony Liguori <aliguori@us.ibm.com>
- *
- * This work is licensed under the terms of the GNU GPL, version 2. See
- * the COPYING file in the top-level directory.
- *
- */
-
-#ifndef QEMU_VIRTIO_H
-#define QEMU_VIRTIO_H
-
-#include "exec/memory.h"
-#include "hw/qdev-core.h"
-#include "net/net.h"
-#include "migration/vmstate.h"
-#include "qemu/event_notifier.h"
-#include "standard-headers/linux/virtio_config.h"
-#include "standard-headers/linux/virtio_ring.h"
-#include "qom/object.h"
-
-/* A guest should never accept this. It implies negotiation is broken. */
-#define VIRTIO_F_BAD_FEATURE 30
-
-#define VIRTIO_LEGACY_FEATURES ((0x1ULL << VIRTIO_F_BAD_FEATURE) | \
- (0x1ULL << VIRTIO_F_NOTIFY_ON_EMPTY) | \
- (0x1ULL << VIRTIO_F_ANY_LAYOUT))
-
-struct VirtQueue;
-
-static inline hwaddr vring_align(hwaddr addr,
- unsigned long align)
-{
- return QEMU_ALIGN_UP(addr, align);
-}
-
-typedef struct VirtIOFeature {
- uint64_t flags;
- size_t end;
-} VirtIOFeature;
-
-size_t virtio_feature_get_config_size(VirtIOFeature *features,
- uint64_t host_features);
-
-typedef struct VirtQueue VirtQueue;
-
-#define VIRTQUEUE_MAX_SIZE 1024
-
-typedef struct VirtQueueElement
-{
- unsigned int index;
- unsigned int len;
- unsigned int ndescs;
- unsigned int out_num;
- unsigned int in_num;
- hwaddr *in_addr;
- hwaddr *out_addr;
- struct iovec *in_sg;
- struct iovec *out_sg;
-} VirtQueueElement;
-
-#define VIRTIO_QUEUE_MAX 1024
-
-#define VIRTIO_NO_VECTOR 0xffff
-
-#define TYPE_VIRTIO_DEVICE "virtio-device"
-OBJECT_DECLARE_TYPE(VirtIODevice, VirtioDeviceClass, VIRTIO_DEVICE)
-
-enum virtio_device_endian {
- VIRTIO_DEVICE_ENDIAN_UNKNOWN,
- VIRTIO_DEVICE_ENDIAN_LITTLE,
- VIRTIO_DEVICE_ENDIAN_BIG,
-};
-
-struct VirtIODevice
-{
- DeviceState parent_obj;
- const char *name;
- uint8_t status;
- uint8_t isr;
- uint16_t queue_sel;
- uint64_t guest_features;
- uint64_t host_features;
- uint64_t backend_features;
- size_t config_len;
- void *config;
- uint16_t config_vector;
- uint32_t generation;
- int nvectors;
- VirtQueue *vq;
- MemoryListener listener;
- uint16_t device_id;
- bool vm_running;
- bool broken; /* device in invalid state, needs reset */
- bool use_disabled_flag; /* allow use of 'disable' flag when needed */
- bool disabled; /* device in temporarily disabled state */
- bool use_started;
- bool started;
- bool start_on_kick; /* when virtio 1.0 feature has not been negotiated */
- bool disable_legacy_check;
- VMChangeStateEntry *vmstate;
- char *bus_name;
- uint8_t device_endian;
- bool use_guest_notifier_mask;
- AddressSpace *dma_as;
- QLIST_HEAD(, VirtQueue) *vector_queues;
-};
-
-struct VirtioDeviceClass {
- /*< private >*/
- DeviceClass parent;
- /*< public >*/
-
- /* This is what a VirtioDevice must implement */
- DeviceRealize realize;
- DeviceUnrealize unrealize;
- uint64_t (*get_features)(VirtIODevice *vdev,
- uint64_t requested_features,
- Error **errp);
- uint64_t (*bad_features)(VirtIODevice *vdev);
- void (*set_features)(VirtIODevice *vdev, uint64_t val);
- int (*validate_features)(VirtIODevice *vdev);
- void (*get_config)(VirtIODevice *vdev, uint8_t *config);
- void (*set_config)(VirtIODevice *vdev, const uint8_t *config);
- void (*reset)(VirtIODevice *vdev);
- void (*set_status)(VirtIODevice *vdev, uint8_t val);
- /* For transitional devices, this is a bitmap of features
- * that are only exposed on the legacy interface but not
- * the modern one.
- */
- uint64_t legacy_features;
- /* Test and clear event pending status.
- * Should be called after unmask to avoid losing events.
- * If backend does not support masking,
- * must check in frontend instead.
- */
- bool (*guest_notifier_pending)(VirtIODevice *vdev, int n);
- /* Mask/unmask events from this vq. Any events reported
- * while masked will become pending.
- * If backend does not support masking,
- * must mask in frontend instead.
- */
- void (*guest_notifier_mask)(VirtIODevice *vdev, int n, bool mask);
- int (*start_ioeventfd)(VirtIODevice *vdev);
- void (*stop_ioeventfd)(VirtIODevice *vdev);
- /* Saving and loading of a device; trying to deprecate save/load
- * use vmsd for new devices.
- */
- void (*save)(VirtIODevice *vdev, QEMUFile *f);
- int (*load)(VirtIODevice *vdev, QEMUFile *f, int version_id);
- /* Post load hook in vmsd is called early while device is processed, and
- * when VirtIODevice isn't fully initialized. Devices should use this instead,
- * unless they specifically want to verify the migration stream as it's
- * processed, e.g. for bounds checking.
- */
- int (*post_load)(VirtIODevice *vdev);
- const VMStateDescription *vmsd;
- bool (*primary_unplug_pending)(void *opaque);
-};
-
-void virtio_instance_init_common(Object *proxy_obj, void *data,
- size_t vdev_size, const char *vdev_name);
-
-void virtio_init(VirtIODevice *vdev, const char *name,
- uint16_t device_id, size_t config_size);
-void virtio_cleanup(VirtIODevice *vdev);
-
-void virtio_error(VirtIODevice *vdev, const char *fmt, ...) GCC_FMT_ATTR(2, 3);
-
-/* Set the child bus name. */
-void virtio_device_set_child_bus_name(VirtIODevice *vdev, char *bus_name);
-
-typedef void (*VirtIOHandleOutput)(VirtIODevice *, VirtQueue *);
-typedef bool (*VirtIOHandleAIOOutput)(VirtIODevice *, VirtQueue *);
-
-VirtQueue *virtio_add_queue(VirtIODevice *vdev, int queue_size,
- VirtIOHandleOutput handle_output);
-
-void virtio_del_queue(VirtIODevice *vdev, int n);
-
-void virtio_delete_queue(VirtQueue *vq);
-
-void virtqueue_push(VirtQueue *vq, const VirtQueueElement *elem,
- unsigned int len);
-void virtqueue_flush(VirtQueue *vq, unsigned int count);
-void virtqueue_detach_element(VirtQueue *vq, const VirtQueueElement *elem,
- unsigned int len);
-void virtqueue_unpop(VirtQueue *vq, const VirtQueueElement *elem,
- unsigned int len);
-bool virtqueue_rewind(VirtQueue *vq, unsigned int num);
-void virtqueue_fill(VirtQueue *vq, const VirtQueueElement *elem,
- unsigned int len, unsigned int idx);
-
-void virtqueue_map(VirtIODevice *vdev, VirtQueueElement *elem);
-void *virtqueue_pop(VirtQueue *vq, size_t sz);
-unsigned int virtqueue_drop_all(VirtQueue *vq);
-void *qemu_get_virtqueue_element(VirtIODevice *vdev, QEMUFile *f, size_t sz);
-void qemu_put_virtqueue_element(VirtIODevice *vdev, QEMUFile *f,
- VirtQueueElement *elem);
-int virtqueue_avail_bytes(VirtQueue *vq, unsigned int in_bytes,
- unsigned int out_bytes);
-void virtqueue_get_avail_bytes(VirtQueue *vq, unsigned int *in_bytes,
- unsigned int *out_bytes,
- unsigned max_in_bytes, unsigned max_out_bytes);
-
-void virtio_notify_irqfd(VirtIODevice *vdev, VirtQueue *vq);
-void virtio_notify(VirtIODevice *vdev, VirtQueue *vq);
-
-int virtio_save(VirtIODevice *vdev, QEMUFile *f);
-
-extern const VMStateInfo virtio_vmstate_info;
-
-#define VMSTATE_VIRTIO_DEVICE \
- { \
- .name = "virtio", \
- .info = &virtio_vmstate_info, \
- .flags = VMS_SINGLE, \
- }
-
-int virtio_load(VirtIODevice *vdev, QEMUFile *f, int version_id);
-
-void virtio_notify_config(VirtIODevice *vdev);
-
-bool virtio_queue_get_notification(VirtQueue *vq);
-void virtio_queue_set_notification(VirtQueue *vq, int enable);
-
-int virtio_queue_ready(VirtQueue *vq);
-
-int virtio_queue_empty(VirtQueue *vq);
-
-/* Host binding interface. */
-
-uint32_t virtio_config_readb(VirtIODevice *vdev, uint32_t addr);
-uint32_t virtio_config_readw(VirtIODevice *vdev, uint32_t addr);
-uint32_t virtio_config_readl(VirtIODevice *vdev, uint32_t addr);
-void virtio_config_writeb(VirtIODevice *vdev, uint32_t addr, uint32_t data);
-void virtio_config_writew(VirtIODevice *vdev, uint32_t addr, uint32_t data);
-void virtio_config_writel(VirtIODevice *vdev, uint32_t addr, uint32_t data);
-uint32_t virtio_config_modern_readb(VirtIODevice *vdev, uint32_t addr);
-uint32_t virtio_config_modern_readw(VirtIODevice *vdev, uint32_t addr);
-uint32_t virtio_config_modern_readl(VirtIODevice *vdev, uint32_t addr);
-void virtio_config_modern_writeb(VirtIODevice *vdev,
- uint32_t addr, uint32_t data);
-void virtio_config_modern_writew(VirtIODevice *vdev,
- uint32_t addr, uint32_t data);
-void virtio_config_modern_writel(VirtIODevice *vdev,
- uint32_t addr, uint32_t data);
-void virtio_queue_set_addr(VirtIODevice *vdev, int n, hwaddr addr);
-hwaddr virtio_queue_get_addr(VirtIODevice *vdev, int n);
-void virtio_queue_set_num(VirtIODevice *vdev, int n, int num);
-int virtio_queue_get_num(VirtIODevice *vdev, int n);
-int virtio_queue_get_max_num(VirtIODevice *vdev, int n);
-int virtio_get_num_queues(VirtIODevice *vdev);
-void virtio_queue_set_rings(VirtIODevice *vdev, int n, hwaddr desc,
- hwaddr avail, hwaddr used);
-void virtio_queue_update_rings(VirtIODevice *vdev, int n);
-void virtio_queue_set_align(VirtIODevice *vdev, int n, int align);
-void virtio_queue_notify(VirtIODevice *vdev, int n);
-uint16_t virtio_queue_vector(VirtIODevice *vdev, int n);
-void virtio_queue_set_vector(VirtIODevice *vdev, int n, uint16_t vector);
-int virtio_queue_set_host_notifier_mr(VirtIODevice *vdev, int n,
- MemoryRegion *mr, bool assign);
-int virtio_set_status(VirtIODevice *vdev, uint8_t val);
-void virtio_reset(void *opaque);
-void virtio_update_irq(VirtIODevice *vdev);
-int virtio_set_features(VirtIODevice *vdev, uint64_t val);
-
-/* Base devices. */
-typedef struct VirtIOBlkConf VirtIOBlkConf;
-struct virtio_net_conf;
-typedef struct virtio_serial_conf virtio_serial_conf;
-typedef struct virtio_input_conf virtio_input_conf;
-typedef struct VirtIOSCSIConf VirtIOSCSIConf;
-typedef struct VirtIORNGConf VirtIORNGConf;
-
-#define DEFINE_VIRTIO_COMMON_FEATURES(_state, _field) \
- DEFINE_PROP_BIT64("indirect_desc", _state, _field, \
- VIRTIO_RING_F_INDIRECT_DESC, true), \
- DEFINE_PROP_BIT64("event_idx", _state, _field, \
- VIRTIO_RING_F_EVENT_IDX, true), \
- DEFINE_PROP_BIT64("notify_on_empty", _state, _field, \
- VIRTIO_F_NOTIFY_ON_EMPTY, true), \
- DEFINE_PROP_BIT64("any_layout", _state, _field, \
- VIRTIO_F_ANY_LAYOUT, true), \
- DEFINE_PROP_BIT64("iommu_platform", _state, _field, \
- VIRTIO_F_IOMMU_PLATFORM, false), \
- DEFINE_PROP_BIT64("packed", _state, _field, \
- VIRTIO_F_RING_PACKED, false)
-
-hwaddr virtio_queue_get_desc_addr(VirtIODevice *vdev, int n);
-bool virtio_queue_enabled_legacy(VirtIODevice *vdev, int n);
-bool virtio_queue_enabled(VirtIODevice *vdev, int n);
-hwaddr virtio_queue_get_avail_addr(VirtIODevice *vdev, int n);
-hwaddr virtio_queue_get_used_addr(VirtIODevice *vdev, int n);
-hwaddr virtio_queue_get_desc_size(VirtIODevice *vdev, int n);
-hwaddr virtio_queue_get_avail_size(VirtIODevice *vdev, int n);
-hwaddr virtio_queue_get_used_size(VirtIODevice *vdev, int n);
-unsigned int virtio_queue_get_last_avail_idx(VirtIODevice *vdev, int n);
-void virtio_queue_set_last_avail_idx(VirtIODevice *vdev, int n,
- unsigned int idx);
-void virtio_queue_restore_last_avail_idx(VirtIODevice *vdev, int n);
-void virtio_queue_invalidate_signalled_used(VirtIODevice *vdev, int n);
-void virtio_queue_update_used_idx(VirtIODevice *vdev, int n);
-VirtQueue *virtio_get_queue(VirtIODevice *vdev, int n);
-uint16_t virtio_get_queue_index(VirtQueue *vq);
-EventNotifier *virtio_queue_get_guest_notifier(VirtQueue *vq);
-void virtio_queue_set_guest_notifier_fd_handler(VirtQueue *vq, bool assign,
- bool with_irqfd);
-int virtio_device_start_ioeventfd(VirtIODevice *vdev);
-int virtio_device_grab_ioeventfd(VirtIODevice *vdev);
-void virtio_device_release_ioeventfd(VirtIODevice *vdev);
-bool virtio_device_ioeventfd_enabled(VirtIODevice *vdev);
-EventNotifier *virtio_queue_get_host_notifier(VirtQueue *vq);
-void virtio_queue_set_host_notifier_enabled(VirtQueue *vq, bool enabled);
-void virtio_queue_host_notifier_read(EventNotifier *n);
-void virtio_queue_aio_set_host_notifier_handler(VirtQueue *vq, AioContext *ctx,
- VirtIOHandleAIOOutput handle_output);
-VirtQueue *virtio_vector_first_queue(VirtIODevice *vdev, uint16_t vector);
-VirtQueue *virtio_vector_next_queue(VirtQueue *vq);
-
-static inline void virtio_add_feature(uint64_t *features, unsigned int fbit)
-{
- assert(fbit < 64);
- *features |= (1ULL << fbit);
-}
-
-static inline void virtio_clear_feature(uint64_t *features, unsigned int fbit)
-{
- assert(fbit < 64);
- *features &= ~(1ULL << fbit);
-}
-
-static inline bool virtio_has_feature(uint64_t features, unsigned int fbit)
-{
- assert(fbit < 64);
- return !!(features & (1ULL << fbit));
-}
-
-static inline bool virtio_vdev_has_feature(VirtIODevice *vdev,
- unsigned int fbit)
-{
- return virtio_has_feature(vdev->guest_features, fbit);
-}
-
-static inline bool virtio_host_has_feature(VirtIODevice *vdev,
- unsigned int fbit)
-{
- return virtio_has_feature(vdev->host_features, fbit);
-}
-
-static inline bool virtio_is_big_endian(VirtIODevice *vdev)
-{
- if (!virtio_vdev_has_feature(vdev, VIRTIO_F_VERSION_1)) {
- assert(vdev->device_endian != VIRTIO_DEVICE_ENDIAN_UNKNOWN);
- return vdev->device_endian == VIRTIO_DEVICE_ENDIAN_BIG;
- }
- /* Devices conforming to VIRTIO 1.0 or later are always LE. */
- return false;
-}
-
-static inline bool virtio_device_started(VirtIODevice *vdev, uint8_t status)
-{
- if (vdev->use_started) {
- return vdev->started;
- }
-
- return status & VIRTIO_CONFIG_S_DRIVER_OK;
-}
-
-static inline void virtio_set_started(VirtIODevice *vdev, bool started)
-{
- if (started) {
- vdev->start_on_kick = false;
- }
-
- if (vdev->use_started) {
- vdev->started = started;
- }
-}
-
-static inline void virtio_set_disabled(VirtIODevice *vdev, bool disable)
-{
- if (vdev->use_disabled_flag) {
- vdev->disabled = disable;
- }
-}
-
-static inline bool virtio_device_disabled(VirtIODevice *vdev)
-{
- return unlikely(vdev->disabled || vdev->broken);
-}
-
-bool virtio_legacy_allowed(VirtIODevice *vdev);
-bool virtio_legacy_check_disabled(VirtIODevice *vdev);
-
-#endif
+++ /dev/null
-/*
- * ARM CMSDK APB watchdog emulation
- *
- * Copyright (c) 2018 Linaro Limited
- * Written by Peter Maydell
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 or
- * (at your option) any later version.
- */
-
-/*
- * This is a model of the "APB watchdog" which is part of the Cortex-M
- * System Design Kit (CMSDK) and documented in the Cortex-M System
- * Design Kit Technical Reference Manual (ARM DDI0479C):
- * https://developer.arm.com/products/system-design/system-design-kits/cortex-m-system-design-kit
- *
- * QEMU interface:
- * + QOM property "wdogclk-frq": frequency at which the watchdog is clocked
- * + sysbus MMIO region 0: the register bank
- * + sysbus IRQ 0: watchdog interrupt
- *
- * In real hardware the watchdog's reset output is just a GPIO line
- * which can then be masked by the board or treated as a simple interrupt.
- * (For instance the IoTKit does this with the non-secure watchdog, so that
- * secure code can control whether non-secure code can perform a system
- * reset via its watchdog.) In QEMU, we just wire up the watchdog reset
- * to watchdog_perform_action(), at least for the moment.
- */
-
-#ifndef CMSDK_APB_WATCHDOG_H
-#define CMSDK_APB_WATCHDOG_H
-
-#include "hw/sysbus.h"
-#include "hw/ptimer.h"
-#include "qom/object.h"
-
-#define TYPE_CMSDK_APB_WATCHDOG "cmsdk-apb-watchdog"
-OBJECT_DECLARE_SIMPLE_TYPE(CMSDKAPBWatchdog, CMSDK_APB_WATCHDOG)
-
-/*
- * This shares the same struct (and cast macro) as the base
- * cmsdk-apb-watchdog device.
- */
-#define TYPE_LUMINARY_WATCHDOG "luminary-watchdog"
-
-struct CMSDKAPBWatchdog {
- /*< private >*/
- SysBusDevice parent_obj;
-
- /*< public >*/
- MemoryRegion iomem;
- qemu_irq wdogint;
- uint32_t wdogclk_frq;
- bool is_luminary;
- struct ptimer_state *timer;
-
- uint32_t control;
- uint32_t intstatus;
- uint32_t lock;
- uint32_t itcr;
- uint32_t itop;
- uint32_t resetstatus;
- const uint32_t *id;
-};
-
-#endif
+++ /dev/null
-/*
- * Copyright (c) 2020 Linaro Limited
- *
- * Authors:
- * Shashi Mallela <shashi.mallela@linaro.org>
- *
- * This work is licensed under the terms of the GNU GPL, version 2 or (at your
- * option) any later version. See the COPYING file in the top-level directory.
- *
- */
-
-#ifndef WDT_SBSA_GWDT_H
-#define WDT_SBSA_GWDT_H
-
-#include "qemu/bitops.h"
-#include "hw/sysbus.h"
-#include "hw/irq.h"
-
-#define TYPE_WDT_SBSA "sbsa_gwdt"
-#define SBSA_GWDT(obj) \
- OBJECT_CHECK(SBSA_GWDTState, (obj), TYPE_WDT_SBSA)
-#define SBSA_GWDT_CLASS(klass) \
- OBJECT_CLASS_CHECK(SBSA_GWDTClass, (klass), TYPE_WDT_SBSA)
-#define SBSA_GWDT_GET_CLASS(obj) \
- OBJECT_GET_CLASS(SBSA_GWDTClass, (obj), TYPE_WDT_SBSA)
-
-/* SBSA Generic Watchdog register definitions */
-/* refresh frame */
-#define SBSA_GWDT_WRR 0x000
-
-/* control frame */
-#define SBSA_GWDT_WCS 0x000
-#define SBSA_GWDT_WOR 0x008
-#define SBSA_GWDT_WORU 0x00C
-#define SBSA_GWDT_WCV 0x010
-#define SBSA_GWDT_WCVU 0x014
-
-/* Watchdog Interface Identification Register */
-#define SBSA_GWDT_W_IIDR 0xFCC
-
-/* Watchdog Control and Status Register Bits */
-#define SBSA_GWDT_WCS_EN BIT(0)
-#define SBSA_GWDT_WCS_WS0 BIT(1)
-#define SBSA_GWDT_WCS_WS1 BIT(2)
-
-#define SBSA_GWDT_WOR_MASK 0x0000FFFF
-
-/*
- * Watchdog Interface Identification Register definition
- * considering JEP106 code for ARM in Bits [11:0]
- */
-#define SBSA_GWDT_ID 0x1043B
-
-/* 2 Separate memory regions for each of refresh & control register frames */
-#define SBSA_GWDT_RMMIO_SIZE 0x1000
-#define SBSA_GWDT_CMMIO_SIZE 0x1000
-
-#define SBSA_TIMER_FREQ 62500000 /* Hz */
-
-typedef struct SBSA_GWDTState {
- /* <private> */
- SysBusDevice parent_obj;
-
- /*< public >*/
- MemoryRegion rmmio;
- MemoryRegion cmmio;
- qemu_irq irq;
-
- QEMUTimer *timer;
-
- uint32_t id;
- uint32_t wcs;
- uint32_t worl;
- uint32_t woru;
- uint32_t wcvl;
- uint32_t wcvu;
-} SBSA_GWDTState;
-
-#endif /* WDT_SBSA_GWDT_H */
+++ /dev/null
-/*
- * ASPEED Watchdog Controller
- *
- * Copyright (C) 2016-2017 IBM Corp.
- *
- * This code is licensed under the GPL version 2 or later. See the
- * COPYING file in the top-level directory.
- */
-
-#ifndef WDT_ASPEED_H
-#define WDT_ASPEED_H
-
-#include "hw/misc/aspeed_scu.h"
-#include "hw/sysbus.h"
-#include "qom/object.h"
-
-#define TYPE_ASPEED_WDT "aspeed.wdt"
-OBJECT_DECLARE_TYPE(AspeedWDTState, AspeedWDTClass, ASPEED_WDT)
-#define TYPE_ASPEED_2400_WDT TYPE_ASPEED_WDT "-ast2400"
-#define TYPE_ASPEED_2500_WDT TYPE_ASPEED_WDT "-ast2500"
-#define TYPE_ASPEED_2600_WDT TYPE_ASPEED_WDT "-ast2600"
-
-#define ASPEED_WDT_REGS_MAX (0x20 / 4)
-
-struct AspeedWDTState {
- /*< private >*/
- SysBusDevice parent_obj;
- QEMUTimer *timer;
-
- /*< public >*/
- MemoryRegion iomem;
- uint32_t regs[ASPEED_WDT_REGS_MAX];
-
- AspeedSCUState *scu;
- uint32_t pclk_freq;
-};
-
-
-struct AspeedWDTClass {
- SysBusDeviceClass parent_class;
-
- uint32_t offset;
- uint32_t ext_pulse_width_mask;
- uint32_t reset_ctrl_reg;
- void (*reset_pulse)(AspeedWDTState *s, uint32_t property);
- void (*wdt_reload)(AspeedWDTState *s);
-};
-
-#endif /* WDT_ASPEED_H */
+++ /dev/null
-#ifndef WDT_DIAG288_H
-#define WDT_DIAG288_H
-
-#include "hw/qdev-core.h"
-#include "qom/object.h"
-
-#define TYPE_WDT_DIAG288 "diag288"
-typedef struct DIAG288Class DIAG288Class;
-typedef struct DIAG288State DIAG288State;
-DECLARE_OBJ_CHECKERS(DIAG288State, DIAG288Class,
- DIAG288, TYPE_WDT_DIAG288)
-
-#define WDT_DIAG288_INIT 0
-#define WDT_DIAG288_CHANGE 1
-#define WDT_DIAG288_CANCEL 2
-
-struct DIAG288State {
- /*< private >*/
- DeviceState parent_obj;
- QEMUTimer *timer;
- bool enabled;
-
- /*< public >*/
-};
-
-struct DIAG288Class {
- /*< private >*/
- DeviceClass parent_class;
-
- /*< public >*/
- int (*handle_timer)(DIAG288State *dev,
- uint64_t func, uint64_t timeout);
-};
-
-#endif /* WDT_DIAG288_H */
+++ /dev/null
-/*
- * Copyright (c) 2017, Impinj, Inc.
- *
- * i.MX2 Watchdog IP block
- *
- * Author: Andrey Smirnov <andrew.smirnov@gmail.com>
- *
- * This work is licensed under the terms of the GNU GPL, version 2 or later.
- * See the COPYING file in the top-level directory.
- */
-
-#ifndef IMX2_WDT_H
-#define IMX2_WDT_H
-
-#include "qemu/bitops.h"
-#include "hw/sysbus.h"
-#include "hw/irq.h"
-#include "hw/ptimer.h"
-#include "qom/object.h"
-
-#define TYPE_IMX2_WDT "imx2.wdt"
-OBJECT_DECLARE_SIMPLE_TYPE(IMX2WdtState, IMX2_WDT)
-
-enum IMX2WdtRegisters {
- IMX2_WDT_WCR = 0x0000, /* Control Register */
- IMX2_WDT_WSR = 0x0002, /* Service Register */
- IMX2_WDT_WRSR = 0x0004, /* Reset Status Register */
- IMX2_WDT_WICR = 0x0006, /* Interrupt Control Register */
- IMX2_WDT_WMCR = 0x0008, /* Misc Register */
-};
-
-#define IMX2_WDT_MMIO_SIZE 0x000a
-
-/* Control Register definitions */
-#define IMX2_WDT_WCR_WT (0xFF << 8) /* Watchdog Timeout Field */
-#define IMX2_WDT_WCR_WDW BIT(7) /* WDOG Disable for Wait */
-#define IMX2_WDT_WCR_WDA BIT(5) /* WDOG Assertion */
-#define IMX2_WDT_WCR_SRS BIT(4) /* Software Reset Signal */
-#define IMX2_WDT_WCR_WDT BIT(3) /* WDOG Timeout Assertion */
-#define IMX2_WDT_WCR_WDE BIT(2) /* Watchdog Enable */
-#define IMX2_WDT_WCR_WDBG BIT(1) /* Watchdog Debug Enable */
-#define IMX2_WDT_WCR_WDZST BIT(0) /* Watchdog Timer Suspend */
-
-#define IMX2_WDT_WCR_LOCK_MASK (IMX2_WDT_WCR_WDZST | IMX2_WDT_WCR_WDBG \
- | IMX2_WDT_WCR_WDW)
-
-/* Service Register definitions */
-#define IMX2_WDT_SEQ1 0x5555 /* service sequence 1 */
-#define IMX2_WDT_SEQ2 0xAAAA /* service sequence 2 */
-
-/* Reset Status Register definitions */
-#define IMX2_WDT_WRSR_TOUT BIT(1) /* Reset due to Timeout */
-#define IMX2_WDT_WRSR_SFTW BIT(0) /* Reset due to software reset */
-
-/* Interrupt Control Register definitions */
-#define IMX2_WDT_WICR_WIE BIT(15) /* Interrupt Enable */
-#define IMX2_WDT_WICR_WTIS BIT(14) /* Interrupt Status */
-#define IMX2_WDT_WICR_WICT 0xff /* Interrupt Timeout */
-#define IMX2_WDT_WICR_WICT_DEF 0x04 /* Default interrupt timeout (2s) */
-
-#define IMX2_WDT_WICR_LOCK_MASK (IMX2_WDT_WICR_WIE | IMX2_WDT_WICR_WICT)
-
-/* Misc Control Register definitions */
-#define IMX2_WDT_WMCR_PDE BIT(0) /* Power-Down Enable */
-
-struct IMX2WdtState {
- /* <private> */
- SysBusDevice parent_obj;
-
- /*< public >*/
- MemoryRegion mmio;
- qemu_irq irq;
-
- struct ptimer_state *timer;
- struct ptimer_state *itimer;
-
- bool pretimeout_support;
- bool wicr_locked;
-
- uint16_t wcr;
- uint16_t wsr;
- uint16_t wrsr;
- uint16_t wicr;
- uint16_t wmcr;
-
- bool wcr_locked; /* affects WDZST, WDBG, and WDW */
- bool wcr_wde_locked; /* affects WDE */
- bool wcr_wdt_locked; /* affects WDT (never cleared) */
-};
-
-#endif /* IMX2_WDT_H */
+++ /dev/null
-/******************************************************************************
- * grant_table.h
- *
- * Interface for granting foreign access to page frames, and receiving
- * page-ownership transfers.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to
- * deal in the Software without restriction, including without limitation the
- * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
- * sell copies of the Software, and to permit persons to whom the Software is
- * furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
- * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
- * DEALINGS IN THE SOFTWARE.
- *
- * Copyright (c) 2004, K A Fraser
- */
-
-#ifndef __XEN_PUBLIC_GRANT_TABLE_H__
-#define __XEN_PUBLIC_GRANT_TABLE_H__
-
-/*
- * Reference to a grant entry in a specified domain's grant table.
- */
-typedef uint32_t grant_ref_t;
-
-#endif /* __XEN_PUBLIC_GRANT_TABLE_H__ */
+++ /dev/null
-/******************************************************************************
- * blkif.h
- *
- * Unified block-device I/O interface for Xen guest OSes.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to
- * deal in the Software without restriction, including without limitation the
- * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
- * sell copies of the Software, and to permit persons to whom the Software is
- * furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
- * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
- * DEALINGS IN THE SOFTWARE.
- *
- * Copyright (c) 2003-2004, Keir Fraser
- * Copyright (c) 2012, Spectra Logic Corporation
- */
-
-#ifndef __XEN_PUBLIC_IO_BLKIF_H__
-#define __XEN_PUBLIC_IO_BLKIF_H__
-
-#include "ring.h"
-#include "../grant_table.h"
-
-/*
- * Front->back notifications: When enqueuing a new request, sending a
- * notification can be made conditional on req_event (i.e., the generic
- * hold-off mechanism provided by the ring macros). Backends must set
- * req_event appropriately (e.g., using RING_FINAL_CHECK_FOR_REQUESTS()).
- *
- * Back->front notifications: When enqueuing a new response, sending a
- * notification can be made conditional on rsp_event (i.e., the generic
- * hold-off mechanism provided by the ring macros). Frontends must set
- * rsp_event appropriately (e.g., using RING_FINAL_CHECK_FOR_RESPONSES()).
- */
-
-#ifndef blkif_vdev_t
-#define blkif_vdev_t uint16_t
-#endif
-#define blkif_sector_t uint64_t
-
-/*
- * Feature and Parameter Negotiation
- * =================================
- * The two halves of a Xen block driver utilize nodes within the XenStore to
- * communicate capabilities and to negotiate operating parameters. This
- * section enumerates these nodes which reside in the respective front and
- * backend portions of the XenStore, following the XenBus convention.
- *
- * All data in the XenStore is stored as strings. Nodes specifying numeric
- * values are encoded in decimal. Integer value ranges listed below are
- * expressed as fixed sized integer types capable of storing the conversion
- * of a properly formated node string, without loss of information.
- *
- * Any specified default value is in effect if the corresponding XenBus node
- * is not present in the XenStore.
- *
- * XenStore nodes in sections marked "PRIVATE" are solely for use by the
- * driver side whose XenBus tree contains them.
- *
- * XenStore nodes marked "DEPRECATED" in their notes section should only be
- * used to provide interoperability with legacy implementations.
- *
- * See the XenBus state transition diagram below for details on when XenBus
- * nodes must be published and when they can be queried.
- *
- *****************************************************************************
- * Backend XenBus Nodes
- *****************************************************************************
- *
- *------------------ Backend Device Identification (PRIVATE) ------------------
- *
- * mode
- * Values: "r" (read only), "w" (writable)
- *
- * The read or write access permissions to the backing store to be
- * granted to the frontend.
- *
- * params
- * Values: string
- *
- * A free formatted string providing sufficient information for the
- * hotplug script to attach the device and provide a suitable
- * handler (ie: a block device) for blkback to use.
- *
- * physical-device
- * Values: "MAJOR:MINOR"
- * Notes: 11
- *
- * MAJOR and MINOR are the major number and minor number of the
- * backing device respectively.
- *
- * physical-device-path
- * Values: path string
- *
- * A string that contains the absolute path to the disk image. On
- * NetBSD and Linux this is always a block device, while on FreeBSD
- * it can be either a block device or a regular file.
- *
- * type
- * Values: "file", "phy", "tap"
- *
- * The type of the backing device/object.
- *
- *
- * direct-io-safe
- * Values: 0/1 (boolean)
- * Default Value: 0
- *
- * The underlying storage is not affected by the direct IO memory
- * lifetime bug. See:
- * http://lists.xen.org/archives/html/xen-devel/2012-12/msg01154.html
- *
- * Therefore this option gives the backend permission to use
- * O_DIRECT, notwithstanding that bug.
- *
- * That is, if this option is enabled, use of O_DIRECT is safe,
- * in circumstances where we would normally have avoided it as a
- * workaround for that bug. This option is not relevant for all
- * backends, and even not necessarily supported for those for
- * which it is relevant. A backend which knows that it is not
- * affected by the bug can ignore this option.
- *
- * This option doesn't require a backend to use O_DIRECT, so it
- * should not be used to try to control the caching behaviour.
- *
- *--------------------------------- Features ---------------------------------
- *
- * feature-barrier
- * Values: 0/1 (boolean)
- * Default Value: 0
- *
- * A value of "1" indicates that the backend can process requests
- * containing the BLKIF_OP_WRITE_BARRIER request opcode. Requests
- * of this type may still be returned at any time with the
- * BLKIF_RSP_EOPNOTSUPP result code.
- *
- * feature-flush-cache
- * Values: 0/1 (boolean)
- * Default Value: 0
- *
- * A value of "1" indicates that the backend can process requests
- * containing the BLKIF_OP_FLUSH_DISKCACHE request opcode. Requests
- * of this type may still be returned at any time with the
- * BLKIF_RSP_EOPNOTSUPP result code.
- *
- * feature-discard
- * Values: 0/1 (boolean)
- * Default Value: 0
- *
- * A value of "1" indicates that the backend can process requests
- * containing the BLKIF_OP_DISCARD request opcode. Requests
- * of this type may still be returned at any time with the
- * BLKIF_RSP_EOPNOTSUPP result code.
- *
- * feature-persistent
- * Values: 0/1 (boolean)
- * Default Value: 0
- * Notes: 7
- *
- * A value of "1" indicates that the backend can keep the grants used
- * by the frontend driver mapped, so the same set of grants should be
- * used in all transactions. The maximum number of grants the backend
- * can map persistently depends on the implementation, but ideally it
- * should be RING_SIZE * BLKIF_MAX_SEGMENTS_PER_REQUEST. Using this
- * feature the backend doesn't need to unmap each grant, preventing
- * costly TLB flushes. The backend driver should only map grants
- * persistently if the frontend supports it. If a backend driver chooses
- * to use the persistent protocol when the frontend doesn't support it,
- * it will probably hit the maximum number of persistently mapped grants
- * (due to the fact that the frontend won't be reusing the same grants),
- * and fall back to non-persistent mode. Backend implementations may
- * shrink or expand the number of persistently mapped grants without
- * notifying the frontend depending on memory constraints (this might
- * cause a performance degradation).
- *
- * If a backend driver wants to limit the maximum number of persistently
- * mapped grants to a value less than RING_SIZE *
- * BLKIF_MAX_SEGMENTS_PER_REQUEST a LRU strategy should be used to
- * discard the grants that are less commonly used. Using a LRU in the
- * backend driver paired with a LIFO queue in the frontend will
- * allow us to have better performance in this scenario.
- *
- *----------------------- Request Transport Parameters ------------------------
- *
- * max-ring-page-order
- * Values: <uint32_t>
- * Default Value: 0
- * Notes: 1, 3
- *
- * The maximum supported size of the request ring buffer in units of
- * lb(machine pages). (e.g. 0 == 1 page, 1 = 2 pages, 2 == 4 pages,
- * etc.).
- *
- * max-ring-pages
- * Values: <uint32_t>
- * Default Value: 1
- * Notes: DEPRECATED, 2, 3
- *
- * The maximum supported size of the request ring buffer in units of
- * machine pages. The value must be a power of 2.
- *
- *------------------------- Backend Device Properties -------------------------
- *
- * discard-enable
- * Values: 0/1 (boolean)
- * Default Value: 1
- *
- * This optional property, set by the toolstack, instructs the backend
- * to offer (or not to offer) discard to the frontend. If the property
- * is missing the backend should offer discard if the backing storage
- * actually supports it.
- *
- * discard-alignment
- * Values: <uint32_t>
- * Default Value: 0
- * Notes: 4, 5
- *
- * The offset, in bytes from the beginning of the virtual block device,
- * to the first, addressable, discard extent on the underlying device.
- *
- * discard-granularity
- * Values: <uint32_t>
- * Default Value: <"sector-size">
- * Notes: 4
- *
- * The size, in bytes, of the individually addressable discard extents
- * of the underlying device.
- *
- * discard-secure
- * Values: 0/1 (boolean)
- * Default Value: 0
- * Notes: 10
- *
- * A value of "1" indicates that the backend can process BLKIF_OP_DISCARD
- * requests with the BLKIF_DISCARD_SECURE flag set.
- *
- * info
- * Values: <uint32_t> (bitmap)
- *
- * A collection of bit flags describing attributes of the backing
- * device. The VDISK_* macros define the meaning of each bit
- * location.
- *
- * sector-size
- * Values: <uint32_t>
- *
- * The logical block size, in bytes, of the underlying storage. This
- * must be a power of two with a minimum value of 512.
- *
- * NOTE: Because of implementation bugs in some frontends this must be
- * set to 512, unless the frontend advertizes a non-zero value
- * in its "feature-large-sector-size" xenbus node. (See below).
- *
- * physical-sector-size
- * Values: <uint32_t>
- * Default Value: <"sector-size">
- *
- * The physical block size, in bytes, of the backend storage. This
- * must be an integer multiple of "sector-size".
- *
- * sectors
- * Values: <uint64_t>
- *
- * The size of the backend device, expressed in units of "sector-size".
- * The product of "sector-size" and "sectors" must also be an integer
- * multiple of "physical-sector-size", if that node is present.
- *
- *****************************************************************************
- * Frontend XenBus Nodes
- *****************************************************************************
- *
- *----------------------- Request Transport Parameters -----------------------
- *
- * event-channel
- * Values: <uint32_t>
- *
- * The identifier of the Xen event channel used to signal activity
- * in the ring buffer.
- *
- * ring-ref
- * Values: <uint32_t>
- * Notes: 6
- *
- * The Xen grant reference granting permission for the backend to map
- * the sole page in a single page sized ring buffer.
- *
- * ring-ref%u
- * Values: <uint32_t>
- * Notes: 6
- *
- * For a frontend providing a multi-page ring, a "number of ring pages"
- * sized list of nodes, each containing a Xen grant reference granting
- * permission for the backend to map the page of the ring located
- * at page index "%u". Page indexes are zero based.
- *
- * protocol
- * Values: string (XEN_IO_PROTO_ABI_*)
- * Default Value: XEN_IO_PROTO_ABI_NATIVE
- *
- * The machine ABI rules governing the format of all ring request and
- * response structures.
- *
- * ring-page-order
- * Values: <uint32_t>
- * Default Value: 0
- * Maximum Value: MAX(ffs(max-ring-pages) - 1, max-ring-page-order)
- * Notes: 1, 3
- *
- * The size of the frontend allocated request ring buffer in units
- * of lb(machine pages). (e.g. 0 == 1 page, 1 = 2 pages, 2 == 4 pages,
- * etc.).
- *
- * num-ring-pages
- * Values: <uint32_t>
- * Default Value: 1
- * Maximum Value: MAX(max-ring-pages,(0x1 << max-ring-page-order))
- * Notes: DEPRECATED, 2, 3
- *
- * The size of the frontend allocated request ring buffer in units of
- * machine pages. The value must be a power of 2.
- *
- *--------------------------------- Features ---------------------------------
- *
- * feature-persistent
- * Values: 0/1 (boolean)
- * Default Value: 0
- * Notes: 7, 8, 9
- *
- * A value of "1" indicates that the frontend will reuse the same grants
- * for all transactions, allowing the backend to map them with write
- * access (even when it should be read-only). If the frontend hits the
- * maximum number of allowed persistently mapped grants, it can fallback
- * to non persistent mode. This will cause a performance degradation,
- * since the backend driver will still try to map those grants
- * persistently. Since the persistent grants protocol is compatible with
- * the previous protocol, a frontend driver can choose to work in
- * persistent mode even when the backend doesn't support it.
- *
- * It is recommended that the frontend driver stores the persistently
- * mapped grants in a LIFO queue, so a subset of all persistently mapped
- * grants gets used commonly. This is done in case the backend driver
- * decides to limit the maximum number of persistently mapped grants
- * to a value less than RING_SIZE * BLKIF_MAX_SEGMENTS_PER_REQUEST.
- *
- * feature-large-sector-size
- * Values: 0/1 (boolean)
- * Default Value: 0
- *
- * A value of "1" indicates that the frontend will correctly supply and
- * interpret all sector-based quantities in terms of the "sector-size"
- * value supplied in the backend info, whatever that may be set to.
- * If this node is not present or its value is "0" then it is assumed
- * that the frontend requires that the logical block size is 512 as it
- * is hardcoded (which is the case in some frontend implementations).
- *
- *------------------------- Virtual Device Properties -------------------------
- *
- * device-type
- * Values: "disk", "cdrom", "floppy", etc.
- *
- * virtual-device
- * Values: <uint32_t>
- *
- * A value indicating the physical device to virtualize within the
- * frontend's domain. (e.g. "The first ATA disk", "The third SCSI
- * disk", etc.)
- *
- * See docs/misc/vbd-interface.txt for details on the format of this
- * value.
- *
- * Notes
- * -----
- * (1) Multi-page ring buffer scheme first developed in the Citrix XenServer
- * PV drivers.
- * (2) Multi-page ring buffer scheme first used in some RedHat distributions
- * including a distribution deployed on certain nodes of the Amazon
- * EC2 cluster.
- * (3) Support for multi-page ring buffers was implemented independently,
- * in slightly different forms, by both Citrix and RedHat/Amazon.
- * For full interoperability, block front and backends should publish
- * identical ring parameters, adjusted for unit differences, to the
- * XenStore nodes used in both schemes.
- * (4) Devices that support discard functionality may internally allocate space
- * (discardable extents) in units that are larger than the exported logical
- * block size. If the backing device has such discardable extents the
- * backend should provide both discard-granularity and discard-alignment.
- * Providing just one of the two may be considered an error by the frontend.
- * Backends supporting discard should include discard-granularity and
- * discard-alignment even if it supports discarding individual sectors.
- * Frontends should assume discard-alignment == 0 and discard-granularity
- * == sector size if these keys are missing.
- * (5) The discard-alignment parameter allows a physical device to be
- * partitioned into virtual devices that do not necessarily begin or
- * end on a discardable extent boundary.
- * (6) When there is only a single page allocated to the request ring,
- * 'ring-ref' is used to communicate the grant reference for this
- * page to the backend. When using a multi-page ring, the 'ring-ref'
- * node is not created. Instead 'ring-ref0' - 'ring-refN' are used.
- * (7) When using persistent grants data has to be copied from/to the page
- * where the grant is currently mapped. The overhead of doing this copy
- * however doesn't suppress the speed improvement of not having to unmap
- * the grants.
- * (8) The frontend driver has to allow the backend driver to map all grants
- * with write access, even when they should be mapped read-only, since
- * further requests may reuse these grants and require write permissions.
- * (9) Linux implementation doesn't have a limit on the maximum number of
- * grants that can be persistently mapped in the frontend driver, but
- * due to the frontent driver implementation it should never be bigger
- * than RING_SIZE * BLKIF_MAX_SEGMENTS_PER_REQUEST.
- *(10) The discard-secure property may be present and will be set to 1 if the
- * backing device supports secure discard.
- *(11) Only used by Linux and NetBSD.
- */
-
-/*
- * Multiple hardware queues/rings:
- * If supported, the backend will write the key "multi-queue-max-queues" to
- * the directory for that vbd, and set its value to the maximum supported
- * number of queues.
- * Frontends that are aware of this feature and wish to use it can write the
- * key "multi-queue-num-queues" with the number they wish to use, which must be
- * greater than zero, and no more than the value reported by the backend in
- * "multi-queue-max-queues".
- *
- * For frontends requesting just one queue, the usual event-channel and
- * ring-ref keys are written as before, simplifying the backend processing
- * to avoid distinguishing between a frontend that doesn't understand the
- * multi-queue feature, and one that does, but requested only one queue.
- *
- * Frontends requesting two or more queues must not write the toplevel
- * event-channel and ring-ref keys, instead writing those keys under sub-keys
- * having the name "queue-N" where N is the integer ID of the queue/ring for
- * which those keys belong. Queues are indexed from zero.
- * For example, a frontend with two queues must write the following set of
- * queue-related keys:
- *
- * /local/domain/1/device/vbd/0/multi-queue-num-queues = "2"
- * /local/domain/1/device/vbd/0/queue-0 = ""
- * /local/domain/1/device/vbd/0/queue-0/ring-ref = "<ring-ref#0>"
- * /local/domain/1/device/vbd/0/queue-0/event-channel = "<evtchn#0>"
- * /local/domain/1/device/vbd/0/queue-1 = ""
- * /local/domain/1/device/vbd/0/queue-1/ring-ref = "<ring-ref#1>"
- * /local/domain/1/device/vbd/0/queue-1/event-channel = "<evtchn#1>"
- *
- * It is also possible to use multiple queues/rings together with
- * feature multi-page ring buffer.
- * For example, a frontend requests two queues/rings and the size of each ring
- * buffer is two pages must write the following set of related keys:
- *
- * /local/domain/1/device/vbd/0/multi-queue-num-queues = "2"
- * /local/domain/1/device/vbd/0/ring-page-order = "1"
- * /local/domain/1/device/vbd/0/queue-0 = ""
- * /local/domain/1/device/vbd/0/queue-0/ring-ref0 = "<ring-ref#0>"
- * /local/domain/1/device/vbd/0/queue-0/ring-ref1 = "<ring-ref#1>"
- * /local/domain/1/device/vbd/0/queue-0/event-channel = "<evtchn#0>"
- * /local/domain/1/device/vbd/0/queue-1 = ""
- * /local/domain/1/device/vbd/0/queue-1/ring-ref0 = "<ring-ref#2>"
- * /local/domain/1/device/vbd/0/queue-1/ring-ref1 = "<ring-ref#3>"
- * /local/domain/1/device/vbd/0/queue-1/event-channel = "<evtchn#1>"
- *
- */
-
-/*
- * STATE DIAGRAMS
- *
- *****************************************************************************
- * Startup *
- *****************************************************************************
- *
- * Tool stack creates front and back nodes with state XenbusStateInitialising.
- *
- * Front Back
- * ================================= =====================================
- * XenbusStateInitialising XenbusStateInitialising
- * o Query virtual device o Query backend device identification
- * properties. data.
- * o Setup OS device instance. o Open and validate backend device.
- * o Publish backend features and
- * transport parameters.
- * |
- * |
- * V
- * XenbusStateInitWait
- *
- * o Query backend features and
- * transport parameters.
- * o Allocate and initialize the
- * request ring.
- * o Publish transport parameters
- * that will be in effect during
- * this connection.
- * |
- * |
- * V
- * XenbusStateInitialised
- *
- * o Query frontend transport parameters.
- * o Connect to the request ring and
- * event channel.
- * o Publish backend device properties.
- * |
- * |
- * V
- * XenbusStateConnected
- *
- * o Query backend device properties.
- * o Finalize OS virtual device
- * instance.
- * |
- * |
- * V
- * XenbusStateConnected
- *
- * Note: Drivers that do not support any optional features, or the negotiation
- * of transport parameters, can skip certain states in the state machine:
- *
- * o A frontend may transition to XenbusStateInitialised without
- * waiting for the backend to enter XenbusStateInitWait. In this
- * case, default transport parameters are in effect and any
- * transport parameters published by the frontend must contain
- * their default values.
- *
- * o A backend may transition to XenbusStateInitialised, bypassing
- * XenbusStateInitWait, without waiting for the frontend to first
- * enter the XenbusStateInitialised state. In this case, default
- * transport parameters are in effect and any transport parameters
- * published by the backend must contain their default values.
- *
- * Drivers that support optional features and/or transport parameter
- * negotiation must tolerate these additional state transition paths.
- * In general this means performing the work of any skipped state
- * transition, if it has not already been performed, in addition to the
- * work associated with entry into the current state.
- */
-
-/*
- * REQUEST CODES.
- */
-#define BLKIF_OP_READ 0
-#define BLKIF_OP_WRITE 1
-/*
- * All writes issued prior to a request with the BLKIF_OP_WRITE_BARRIER
- * operation code ("barrier request") must be completed prior to the
- * execution of the barrier request. All writes issued after the barrier
- * request must not execute until after the completion of the barrier request.
- *
- * Optional. See "feature-barrier" XenBus node documentation above.
- */
-#define BLKIF_OP_WRITE_BARRIER 2
-/*
- * Commit any uncommitted contents of the backing device's volatile cache
- * to stable storage.
- *
- * Optional. See "feature-flush-cache" XenBus node documentation above.
- */
-#define BLKIF_OP_FLUSH_DISKCACHE 3
-/*
- * Used in SLES sources for device specific command packet
- * contained within the request. Reserved for that purpose.
- */
-#define BLKIF_OP_RESERVED_1 4
-/*
- * Indicate to the backend device that a region of storage is no longer in
- * use, and may be discarded at any time without impact to the client. If
- * the BLKIF_DISCARD_SECURE flag is set on the request, all copies of the
- * discarded region on the device must be rendered unrecoverable before the
- * command returns.
- *
- * This operation is analogous to performing a trim (ATA) or unamp (SCSI),
- * command on a native device.
- *
- * More information about trim/unmap operations can be found at:
- * http://t13.org/Documents/UploadedDocuments/docs2008/
- * e07154r6-Data_Set_Management_Proposal_for_ATA-ACS2.doc
- * http://www.seagate.com/staticfiles/support/disc/manuals/
- * Interface%20manuals/100293068c.pdf
- *
- * Optional. See "feature-discard", "discard-alignment",
- * "discard-granularity", and "discard-secure" in the XenBus node
- * documentation above.
- */
-#define BLKIF_OP_DISCARD 5
-
-/*
- * Recognized if "feature-max-indirect-segments" in present in the backend
- * xenbus info. The "feature-max-indirect-segments" node contains the maximum
- * number of segments allowed by the backend per request. If the node is
- * present, the frontend might use blkif_request_indirect structs in order to
- * issue requests with more than BLKIF_MAX_SEGMENTS_PER_REQUEST (11). The
- * maximum number of indirect segments is fixed by the backend, but the
- * frontend can issue requests with any number of indirect segments as long as
- * it's less than the number provided by the backend. The indirect_grefs field
- * in blkif_request_indirect should be filled by the frontend with the
- * grant references of the pages that are holding the indirect segments.
- * These pages are filled with an array of blkif_request_segment that hold the
- * information about the segments. The number of indirect pages to use is
- * determined by the number of segments an indirect request contains. Every
- * indirect page can contain a maximum of
- * (PAGE_SIZE / sizeof(struct blkif_request_segment)) segments, so to
- * calculate the number of indirect pages to use we have to do
- * ceil(indirect_segments / (PAGE_SIZE / sizeof(struct blkif_request_segment))).
- *
- * If a backend does not recognize BLKIF_OP_INDIRECT, it should *not*
- * create the "feature-max-indirect-segments" node!
- */
-#define BLKIF_OP_INDIRECT 6
-
-/*
- * Maximum scatter/gather segments per request.
- * This is carefully chosen so that sizeof(blkif_ring_t) <= PAGE_SIZE.
- * NB. This could be 12 if the ring indexes weren't stored in the same page.
- */
-#define BLKIF_MAX_SEGMENTS_PER_REQUEST 11
-
-/*
- * Maximum number of indirect pages to use per request.
- */
-#define BLKIF_MAX_INDIRECT_PAGES_PER_REQUEST 8
-
-/*
- * NB. 'first_sect' and 'last_sect' in blkif_request_segment, as well as
- * 'sector_number' in blkif_request, blkif_request_discard and
- * blkif_request_indirect are sector-based quantities. See the description
- * of the "feature-large-sector-size" frontend xenbus node above for
- * more information.
- */
-struct blkif_request_segment {
- grant_ref_t gref; /* reference to I/O buffer frame */
- /* @first_sect: first sector in frame to transfer (inclusive). */
- /* @last_sect: last sector in frame to transfer (inclusive). */
- uint8_t first_sect, last_sect;
-};
-
-/*
- * Starting ring element for any I/O request.
- */
-struct blkif_request {
- uint8_t operation; /* BLKIF_OP_??? */
- uint8_t nr_segments; /* number of segments */
- blkif_vdev_t handle; /* only for read/write requests */
- uint64_t id; /* private guest value, echoed in resp */
- blkif_sector_t sector_number;/* start sector idx on disk (r/w only) */
- struct blkif_request_segment seg[BLKIF_MAX_SEGMENTS_PER_REQUEST];
-};
-typedef struct blkif_request blkif_request_t;
-
-/*
- * Cast to this structure when blkif_request.operation == BLKIF_OP_DISCARD
- * sizeof(struct blkif_request_discard) <= sizeof(struct blkif_request)
- */
-struct blkif_request_discard {
- uint8_t operation; /* BLKIF_OP_DISCARD */
- uint8_t flag; /* BLKIF_DISCARD_SECURE or zero */
-#define BLKIF_DISCARD_SECURE (1<<0) /* ignored if discard-secure=0 */
- blkif_vdev_t handle; /* same as for read/write requests */
- uint64_t id; /* private guest value, echoed in resp */
- blkif_sector_t sector_number;/* start sector idx on disk */
- uint64_t nr_sectors; /* number of contiguous sectors to discard*/
-};
-typedef struct blkif_request_discard blkif_request_discard_t;
-
-struct blkif_request_indirect {
- uint8_t operation; /* BLKIF_OP_INDIRECT */
- uint8_t indirect_op; /* BLKIF_OP_{READ/WRITE} */
- uint16_t nr_segments; /* number of segments */
- uint64_t id; /* private guest value, echoed in resp */
- blkif_sector_t sector_number;/* start sector idx on disk (r/w only) */
- blkif_vdev_t handle; /* same as for read/write requests */
- grant_ref_t indirect_grefs[BLKIF_MAX_INDIRECT_PAGES_PER_REQUEST];
-#ifdef __i386__
- uint64_t pad; /* Make it 64 byte aligned on i386 */
-#endif
-};
-typedef struct blkif_request_indirect blkif_request_indirect_t;
-
-struct blkif_response {
- uint64_t id; /* copied from request */
- uint8_t operation; /* copied from request */
- int16_t status; /* BLKIF_RSP_??? */
-};
-typedef struct blkif_response blkif_response_t;
-
-/*
- * STATUS RETURN CODES.
- */
- /* Operation not supported (only happens on barrier writes). */
-#define BLKIF_RSP_EOPNOTSUPP -2
- /* Operation failed for some unspecified reason (-EIO). */
-#define BLKIF_RSP_ERROR -1
- /* Operation completed successfully. */
-#define BLKIF_RSP_OKAY 0
-
-/*
- * Generate blkif ring structures and types.
- */
-DEFINE_RING_TYPES(blkif, struct blkif_request, struct blkif_response);
-
-#define VDISK_CDROM 0x1
-#define VDISK_REMOVABLE 0x2
-#define VDISK_READONLY 0x4
-
-#endif /* __XEN_PUBLIC_IO_BLKIF_H__ */
+++ /dev/null
-/******************************************************************************
- * console.h
- *
- * Console I/O interface for Xen guest OSes.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to
- * deal in the Software without restriction, including without limitation the
- * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
- * sell copies of the Software, and to permit persons to whom the Software is
- * furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
- * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
- * DEALINGS IN THE SOFTWARE.
- *
- * Copyright (c) 2005, Keir Fraser
- */
-
-#ifndef __XEN_PUBLIC_IO_CONSOLE_H__
-#define __XEN_PUBLIC_IO_CONSOLE_H__
-
-typedef uint32_t XENCONS_RING_IDX;
-
-#define MASK_XENCONS_IDX(idx, ring) ((idx) & (sizeof(ring)-1))
-
-struct xencons_interface {
- char in[1024];
- char out[2048];
- XENCONS_RING_IDX in_cons, in_prod;
- XENCONS_RING_IDX out_cons, out_prod;
-};
-
-#ifdef XEN_WANT_FLEX_CONSOLE_RING
-#include "ring.h"
-DEFINE_XEN_FLEX_RING(xencons);
-#endif
-
-#endif /* __XEN_PUBLIC_IO_CONSOLE_H__ */
+++ /dev/null
-/*
- * fbif.h -- Xen virtual frame buffer device
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to
- * deal in the Software without restriction, including without limitation the
- * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
- * sell copies of the Software, and to permit persons to whom the Software is
- * furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
- * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
- * DEALINGS IN THE SOFTWARE.
- *
- * Copyright (C) 2005 Anthony Liguori <aliguori@us.ibm.com>
- * Copyright (C) 2006 Red Hat, Inc., Markus Armbruster <armbru@redhat.com>
- */
-
-#ifndef __XEN_PUBLIC_IO_FBIF_H__
-#define __XEN_PUBLIC_IO_FBIF_H__
-
-/* Out events (frontend -> backend) */
-
-/*
- * Out events may be sent only when requested by backend, and receipt
- * of an unknown out event is an error.
- */
-
-/* Event type 1 currently not used */
-/*
- * Framebuffer update notification event
- * Capable frontend sets feature-update in xenstore.
- * Backend requests it by setting request-update in xenstore.
- */
-#define XENFB_TYPE_UPDATE 2
-
-struct xenfb_update
-{
- uint8_t type; /* XENFB_TYPE_UPDATE */
- int32_t x; /* source x */
- int32_t y; /* source y */
- int32_t width; /* rect width */
- int32_t height; /* rect height */
-};
-
-/*
- * Framebuffer resize notification event
- * Capable backend sets feature-resize in xenstore.
- */
-#define XENFB_TYPE_RESIZE 3
-
-struct xenfb_resize
-{
- uint8_t type; /* XENFB_TYPE_RESIZE */
- int32_t width; /* width in pixels */
- int32_t height; /* height in pixels */
- int32_t stride; /* stride in bytes */
- int32_t depth; /* depth in bits */
- int32_t offset; /* offset of the framebuffer in bytes */
-};
-
-#define XENFB_OUT_EVENT_SIZE 40
-
-union xenfb_out_event
-{
- uint8_t type;
- struct xenfb_update update;
- struct xenfb_resize resize;
- char pad[XENFB_OUT_EVENT_SIZE];
-};
-
-/* In events (backend -> frontend) */
-
-/*
- * Frontends should ignore unknown in events.
- */
-
-/*
- * Framebuffer refresh period advice
- * Backend sends it to advise the frontend their preferred period of
- * refresh. Frontends that keep the framebuffer constantly up-to-date
- * just ignore it. Frontends that use the advice should immediately
- * refresh the framebuffer (and send an update notification event if
- * those have been requested), then use the update frequency to guide
- * their periodical refreshs.
- */
-#define XENFB_TYPE_REFRESH_PERIOD 1
-#define XENFB_NO_REFRESH 0
-
-struct xenfb_refresh_period
-{
- uint8_t type; /* XENFB_TYPE_UPDATE_PERIOD */
- uint32_t period; /* period of refresh, in ms,
- * XENFB_NO_REFRESH if no refresh is needed */
-};
-
-#define XENFB_IN_EVENT_SIZE 40
-
-union xenfb_in_event
-{
- uint8_t type;
- struct xenfb_refresh_period refresh_period;
- char pad[XENFB_IN_EVENT_SIZE];
-};
-
-/* shared page */
-
-#define XENFB_IN_RING_SIZE 1024
-#define XENFB_IN_RING_LEN (XENFB_IN_RING_SIZE / XENFB_IN_EVENT_SIZE)
-#define XENFB_IN_RING_OFFS 1024
-#define XENFB_IN_RING(page) \
- ((union xenfb_in_event *)((char *)(page) + XENFB_IN_RING_OFFS))
-#define XENFB_IN_RING_REF(page, idx) \
- (XENFB_IN_RING((page))[(idx) % XENFB_IN_RING_LEN])
-
-#define XENFB_OUT_RING_SIZE 2048
-#define XENFB_OUT_RING_LEN (XENFB_OUT_RING_SIZE / XENFB_OUT_EVENT_SIZE)
-#define XENFB_OUT_RING_OFFS (XENFB_IN_RING_OFFS + XENFB_IN_RING_SIZE)
-#define XENFB_OUT_RING(page) \
- ((union xenfb_out_event *)((char *)(page) + XENFB_OUT_RING_OFFS))
-#define XENFB_OUT_RING_REF(page, idx) \
- (XENFB_OUT_RING((page))[(idx) % XENFB_OUT_RING_LEN])
-
-struct xenfb_page
-{
- uint32_t in_cons, in_prod;
- uint32_t out_cons, out_prod;
-
- int32_t width; /* the width of the framebuffer (in pixels) */
- int32_t height; /* the height of the framebuffer (in pixels) */
- uint32_t line_length; /* the length of a row of pixels (in bytes) */
- uint32_t mem_length; /* the length of the framebuffer (in bytes) */
- uint8_t depth; /* the depth of a pixel (in bits) */
-
- /*
- * Framebuffer page directory
- *
- * Each directory page holds PAGE_SIZE / sizeof(*pd)
- * framebuffer pages, and can thus map up to PAGE_SIZE *
- * PAGE_SIZE / sizeof(*pd) bytes. With PAGE_SIZE == 4096 and
- * sizeof(unsigned long) == 4/8, that's 4 Megs 32 bit and 2 Megs
- * 64 bit. 256 directories give enough room for a 512 Meg
- * framebuffer with a max resolution of 12,800x10,240. Should
- * be enough for a while with room leftover for expansion.
- */
- unsigned long pd[256];
-};
-
-#endif
+++ /dev/null
-/*
- * kbdif.h -- Xen virtual keyboard/mouse
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to
- * deal in the Software without restriction, including without limitation the
- * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
- * sell copies of the Software, and to permit persons to whom the Software is
- * furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
- * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
- * DEALINGS IN THE SOFTWARE.
- *
- * Copyright (C) 2005 Anthony Liguori <aliguori@us.ibm.com>
- * Copyright (C) 2006 Red Hat, Inc., Markus Armbruster <armbru@redhat.com>
- */
-
-#ifndef __XEN_PUBLIC_IO_KBDIF_H__
-#define __XEN_PUBLIC_IO_KBDIF_H__
-
-/*
- *****************************************************************************
- * Feature and Parameter Negotiation
- *****************************************************************************
- *
- * The two halves of a para-virtual driver utilize nodes within
- * XenStore to communicate capabilities and to negotiate operating parameters.
- * This section enumerates these nodes which reside in the respective front and
- * backend portions of XenStore, following XenBus convention.
- *
- * All data in XenStore is stored as strings. Nodes specifying numeric
- * values are encoded in decimal. Integer value ranges listed below are
- * expressed as fixed sized integer types capable of storing the conversion
- * of a properly formated node string, without loss of information.
- *
- *****************************************************************************
- * Backend XenBus Nodes
- *****************************************************************************
- *
- *---------------------------- Features supported ----------------------------
- *
- * Capable backend advertises supported features by publishing
- * corresponding entries in XenStore and puts 1 as the value of the entry.
- * If a feature is not supported then 0 must be set or feature entry omitted.
- *
- * feature-disable-keyboard
- * Values: <uint>
- *
- * If there is no need to expose a virtual keyboard device by the
- * frontend then this must be set to 1.
- *
- * feature-disable-pointer
- * Values: <uint>
- *
- * If there is no need to expose a virtual pointer device by the
- * frontend then this must be set to 1.
- *
- * feature-abs-pointer
- * Values: <uint>
- *
- * Backends, which support reporting of absolute coordinates for pointer
- * device should set this to 1.
- *
- * feature-multi-touch
- * Values: <uint>
- *
- * Backends, which support reporting of multi-touch events
- * should set this to 1.
- *
- * feature-raw-pointer
- * Values: <uint>
- *
- * Backends, which support reporting raw (unscaled) absolute coordinates
- * for pointer devices should set this to 1. Raw (unscaled) values have
- * a range of [0, 0x7fff].
- *
- *----------------------- Device Instance Parameters ------------------------
- *
- * unique-id
- * Values: <string>
- *
- * After device instance initialization it is assigned a unique ID,
- * so every instance of the frontend can be identified by the backend
- * by this ID. This can be UUID or such.
- *
- *------------------------- Pointer Device Parameters ------------------------
- *
- * width
- * Values: <uint>
- *
- * Maximum X coordinate (width) to be used by the frontend
- * while reporting input events, pixels, [0; UINT32_MAX].
- *
- * height
- * Values: <uint>
- *
- * Maximum Y coordinate (height) to be used by the frontend
- * while reporting input events, pixels, [0; UINT32_MAX].
- *
- *----------------------- Multi-touch Device Parameters ----------------------
- *
- * multi-touch-num-contacts
- * Values: <uint>
- *
- * Number of simultaneous touches reported.
- *
- * multi-touch-width
- * Values: <uint>
- *
- * Width of the touch area to be used by the frontend
- * while reporting input events, pixels, [0; UINT32_MAX].
- *
- * multi-touch-height
- * Values: <uint>
- *
- * Height of the touch area to be used by the frontend
- * while reporting input events, pixels, [0; UINT32_MAX].
- *
- *****************************************************************************
- * Frontend XenBus Nodes
- *****************************************************************************
- *
- *------------------------------ Feature request -----------------------------
- *
- * Capable frontend requests features from backend via setting corresponding
- * entries to 1 in XenStore. Requests for features not advertised as supported
- * by the backend have no effect.
- *
- * request-abs-pointer
- * Values: <uint>
- *
- * Request backend to report absolute pointer coordinates
- * (XENKBD_TYPE_POS) instead of relative ones (XENKBD_TYPE_MOTION).
- *
- * request-multi-touch
- * Values: <uint>
- *
- * Request backend to report multi-touch events.
- *
- * request-raw-pointer
- * Values: <uint>
- *
- * Request backend to report raw unscaled absolute pointer coordinates.
- * This option is only valid if request-abs-pointer is also set.
- * Raw unscaled coordinates have the range [0, 0x7fff]
- *
- *----------------------- Request Transport Parameters -----------------------
- *
- * event-channel
- * Values: <uint>
- *
- * The identifier of the Xen event channel used to signal activity
- * in the ring buffer.
- *
- * page-gref
- * Values: <uint>
- *
- * The Xen grant reference granting permission for the backend to map
- * a sole page in a single page sized event ring buffer.
- *
- * page-ref
- * Values: <uint>
- *
- * OBSOLETE, not recommended for use.
- * PFN of the shared page.
- */
-
-/*
- * EVENT CODES.
- */
-
-#define XENKBD_TYPE_MOTION 1
-#define XENKBD_TYPE_RESERVED 2
-#define XENKBD_TYPE_KEY 3
-#define XENKBD_TYPE_POS 4
-#define XENKBD_TYPE_MTOUCH 5
-
-/* Multi-touch event sub-codes */
-
-#define XENKBD_MT_EV_DOWN 0
-#define XENKBD_MT_EV_UP 1
-#define XENKBD_MT_EV_MOTION 2
-#define XENKBD_MT_EV_SYN 3
-#define XENKBD_MT_EV_SHAPE 4
-#define XENKBD_MT_EV_ORIENT 5
-
-/*
- * CONSTANTS, XENSTORE FIELD AND PATH NAME STRINGS, HELPERS.
- */
-
-#define XENKBD_DRIVER_NAME "vkbd"
-
-#define XENKBD_FIELD_FEAT_DSBL_KEYBRD "feature-disable-keyboard"
-#define XENKBD_FIELD_FEAT_DSBL_POINTER "feature-disable-pointer"
-#define XENKBD_FIELD_FEAT_ABS_POINTER "feature-abs-pointer"
-#define XENKBD_FIELD_FEAT_RAW_POINTER "feature-raw-pointer"
-#define XENKBD_FIELD_FEAT_MTOUCH "feature-multi-touch"
-#define XENKBD_FIELD_REQ_ABS_POINTER "request-abs-pointer"
-#define XENKBD_FIELD_REQ_RAW_POINTER "request-raw-pointer"
-#define XENKBD_FIELD_REQ_MTOUCH "request-multi-touch"
-#define XENKBD_FIELD_RING_GREF "page-gref"
-#define XENKBD_FIELD_EVT_CHANNEL "event-channel"
-#define XENKBD_FIELD_WIDTH "width"
-#define XENKBD_FIELD_HEIGHT "height"
-#define XENKBD_FIELD_MT_WIDTH "multi-touch-width"
-#define XENKBD_FIELD_MT_HEIGHT "multi-touch-height"
-#define XENKBD_FIELD_MT_NUM_CONTACTS "multi-touch-num-contacts"
-#define XENKBD_FIELD_UNIQUE_ID "unique-id"
-
-/* OBSOLETE, not recommended for use */
-#define XENKBD_FIELD_RING_REF "page-ref"
-
-/*
- *****************************************************************************
- * Description of the protocol between frontend and backend driver.
- *****************************************************************************
- *
- * The two halves of a Para-virtual driver communicate with
- * each other using a shared page and an event channel.
- * Shared page contains a ring with event structures.
- *
- * All reserved fields in the structures below must be 0.
- *
- *****************************************************************************
- * Backend to frontend events
- *****************************************************************************
- *
- * Frontends should ignore unknown in events.
- * All event packets have the same length (40 octets)
- * All event packets have common header:
- *
- * 0 octet
- * +-----------------+
- * | type |
- * +-----------------+
- * type - uint8_t, event code, XENKBD_TYPE_???
- *
- *
- * Pointer relative movement event
- * 0 1 2 3 octet
- * +----------------+----------------+----------------+----------------+
- * | _TYPE_MOTION | reserved | 4
- * +----------------+----------------+----------------+----------------+
- * | rel_x | 8
- * +----------------+----------------+----------------+----------------+
- * | rel_y | 12
- * +----------------+----------------+----------------+----------------+
- * | rel_z | 16
- * +----------------+----------------+----------------+----------------+
- * | reserved | 20
- * +----------------+----------------+----------------+----------------+
- * |/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/|
- * +----------------+----------------+----------------+----------------+
- * | reserved | 40
- * +----------------+----------------+----------------+----------------+
- *
- * rel_x - int32_t, relative X motion
- * rel_y - int32_t, relative Y motion
- * rel_z - int32_t, relative Z motion (wheel)
- */
-
-struct xenkbd_motion
-{
- uint8_t type;
- int32_t rel_x;
- int32_t rel_y;
- int32_t rel_z;
-};
-
-/*
- * Key event (includes pointer buttons)
- * 0 1 2 3 octet
- * +----------------+----------------+----------------+----------------+
- * | _TYPE_KEY | pressed | reserved | 4
- * +----------------+----------------+----------------+----------------+
- * | keycode | 8
- * +----------------+----------------+----------------+----------------+
- * | reserved | 12
- * +----------------+----------------+----------------+----------------+
- * |/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/|
- * +----------------+----------------+----------------+----------------+
- * | reserved | 40
- * +----------------+----------------+----------------+----------------+
- *
- * pressed - uint8_t, 1 if pressed; 0 otherwise
- * keycode - uint32_t, KEY_* from linux/input.h
- */
-
-struct xenkbd_key
-{
- uint8_t type;
- uint8_t pressed;
- uint32_t keycode;
-};
-
-/*
- * Pointer absolute position event
- * 0 1 2 3 octet
- * +----------------+----------------+----------------+----------------+
- * | _TYPE_POS | reserved | 4
- * +----------------+----------------+----------------+----------------+
- * | abs_x | 8
- * +----------------+----------------+----------------+----------------+
- * | abs_y | 12
- * +----------------+----------------+----------------+----------------+
- * | rel_z | 16
- * +----------------+----------------+----------------+----------------+
- * | reserved | 20
- * +----------------+----------------+----------------+----------------+
- * |/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/|
- * +----------------+----------------+----------------+----------------+
- * | reserved | 40
- * +----------------+----------------+----------------+----------------+
- *
- * abs_x - int32_t, absolute X position (in FB pixels)
- * abs_y - int32_t, absolute Y position (in FB pixels)
- * rel_z - int32_t, relative Z motion (wheel)
- */
-
-struct xenkbd_position
-{
- uint8_t type;
- int32_t abs_x;
- int32_t abs_y;
- int32_t rel_z;
-};
-
-/*
- * Multi-touch event and its sub-types
- *
- * All multi-touch event packets have common header:
- *
- * 0 1 2 3 octet
- * +----------------+----------------+----------------+----------------+
- * | _TYPE_MTOUCH | event_type | contact_id | reserved | 4
- * +----------------+----------------+----------------+----------------+
- * | reserved | 8
- * +----------------+----------------+----------------+----------------+
- *
- * event_type - unt8_t, multi-touch event sub-type, XENKBD_MT_EV_???
- * contact_id - unt8_t, ID of the contact
- *
- * Touch interactions can consist of one or more contacts.
- * For each contact, a series of events is generated, starting
- * with a down event, followed by zero or more motion events,
- * and ending with an up event. Events relating to the same
- * contact point can be identified by the ID of the sequence: contact ID.
- * Contact ID may be reused after XENKBD_MT_EV_UP event and
- * is in the [0; XENKBD_FIELD_NUM_CONTACTS - 1] range.
- *
- * For further information please refer to documentation on Wayland [1],
- * Linux [2] and Windows [3] multi-touch support.
- *
- * [1] https://cgit.freedesktop.org/wayland/wayland/tree/protocol/wayland.xml
- * [2] https://www.kernel.org/doc/Documentation/input/multi-touch-protocol.txt
- * [3] https://msdn.microsoft.com/en-us/library/jj151564(v=vs.85).aspx
- *
- *
- * Multi-touch down event - sent when a new touch is made: touch is assigned
- * a unique contact ID, sent with this and consequent events related
- * to this touch.
- * 0 1 2 3 octet
- * +----------------+----------------+----------------+----------------+
- * | _TYPE_MTOUCH | _MT_EV_DOWN | contact_id | reserved | 4
- * +----------------+----------------+----------------+----------------+
- * | reserved | 8
- * +----------------+----------------+----------------+----------------+
- * | abs_x | 12
- * +----------------+----------------+----------------+----------------+
- * | abs_y | 16
- * +----------------+----------------+----------------+----------------+
- * | reserved | 20
- * +----------------+----------------+----------------+----------------+
- * |/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/|
- * +----------------+----------------+----------------+----------------+
- * | reserved | 40
- * +----------------+----------------+----------------+----------------+
- *
- * abs_x - int32_t, absolute X position, in pixels
- * abs_y - int32_t, absolute Y position, in pixels
- *
- * Multi-touch contact release event
- * 0 1 2 3 octet
- * +----------------+----------------+----------------+----------------+
- * | _TYPE_MTOUCH | _MT_EV_UP | contact_id | reserved | 4
- * +----------------+----------------+----------------+----------------+
- * | reserved | 8
- * +----------------+----------------+----------------+----------------+
- * |/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/|
- * +----------------+----------------+----------------+----------------+
- * | reserved | 40
- * +----------------+----------------+----------------+----------------+
- *
- * Multi-touch motion event
- * 0 1 2 3 octet
- * +----------------+----------------+----------------+----------------+
- * | _TYPE_MTOUCH | _MT_EV_MOTION | contact_id | reserved | 4
- * +----------------+----------------+----------------+----------------+
- * | reserved | 8
- * +----------------+----------------+----------------+----------------+
- * | abs_x | 12
- * +----------------+----------------+----------------+----------------+
- * | abs_y | 16
- * +----------------+----------------+----------------+----------------+
- * | reserved | 20
- * +----------------+----------------+----------------+----------------+
- * |/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/|
- * +----------------+----------------+----------------+----------------+
- * | reserved | 40
- * +----------------+----------------+----------------+----------------+
- *
- * abs_x - int32_t, absolute X position, in pixels,
- * abs_y - int32_t, absolute Y position, in pixels,
- *
- * Multi-touch input synchronization event - shows end of a set of events
- * which logically belong together.
- * 0 1 2 3 octet
- * +----------------+----------------+----------------+----------------+
- * | _TYPE_MTOUCH | _MT_EV_SYN | contact_id | reserved | 4
- * +----------------+----------------+----------------+----------------+
- * | reserved | 8
- * +----------------+----------------+----------------+----------------+
- * |/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/|
- * +----------------+----------------+----------------+----------------+
- * | reserved | 40
- * +----------------+----------------+----------------+----------------+
- *
- * Multi-touch shape event - touch point's shape has changed its shape.
- * Shape is approximated by an ellipse through the major and minor axis
- * lengths: major is the longer diameter of the ellipse and minor is the
- * shorter one. Center of the ellipse is reported via
- * XENKBD_MT_EV_DOWN/XENKBD_MT_EV_MOTION events.
- * 0 1 2 3 octet
- * +----------------+----------------+----------------+----------------+
- * | _TYPE_MTOUCH | _MT_EV_SHAPE | contact_id | reserved | 4
- * +----------------+----------------+----------------+----------------+
- * | reserved | 8
- * +----------------+----------------+----------------+----------------+
- * | major | 12
- * +----------------+----------------+----------------+----------------+
- * | minor | 16
- * +----------------+----------------+----------------+----------------+
- * | reserved | 20
- * +----------------+----------------+----------------+----------------+
- * |/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/|
- * +----------------+----------------+----------------+----------------+
- * | reserved | 40
- * +----------------+----------------+----------------+----------------+
- *
- * major - unt32_t, length of the major axis, pixels
- * minor - unt32_t, length of the minor axis, pixels
- *
- * Multi-touch orientation event - touch point's shape has changed
- * its orientation: calculated as a clockwise angle between the major axis
- * of the ellipse and positive Y axis in degrees, [-180; +180].
- * 0 1 2 3 octet
- * +----------------+----------------+----------------+----------------+
- * | _TYPE_MTOUCH | _MT_EV_ORIENT | contact_id | reserved | 4
- * +----------------+----------------+----------------+----------------+
- * | reserved | 8
- * +----------------+----------------+----------------+----------------+
- * | orientation | reserved | 12
- * +----------------+----------------+----------------+----------------+
- * | reserved | 16
- * +----------------+----------------+----------------+----------------+
- * |/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/|
- * +----------------+----------------+----------------+----------------+
- * | reserved | 40
- * +----------------+----------------+----------------+----------------+
- *
- * orientation - int16_t, clockwise angle of the major axis
- */
-
-struct xenkbd_mtouch {
- uint8_t type; /* XENKBD_TYPE_MTOUCH */
- uint8_t event_type; /* XENKBD_MT_EV_??? */
- uint8_t contact_id;
- uint8_t reserved[5]; /* reserved for the future use */
- union {
- struct {
- int32_t abs_x; /* absolute X position, pixels */
- int32_t abs_y; /* absolute Y position, pixels */
- } pos;
- struct {
- uint32_t major; /* length of the major axis, pixels */
- uint32_t minor; /* length of the minor axis, pixels */
- } shape;
- int16_t orientation; /* clockwise angle of the major axis */
- } u;
-};
-
-#define XENKBD_IN_EVENT_SIZE 40
-
-union xenkbd_in_event
-{
- uint8_t type;
- struct xenkbd_motion motion;
- struct xenkbd_key key;
- struct xenkbd_position pos;
- struct xenkbd_mtouch mtouch;
- char pad[XENKBD_IN_EVENT_SIZE];
-};
-
-/*
- *****************************************************************************
- * Frontend to backend events
- *****************************************************************************
- *
- * Out events may be sent only when requested by backend, and receipt
- * of an unknown out event is an error.
- * No out events currently defined.
-
- * All event packets have the same length (40 octets)
- * All event packets have common header:
- * 0 octet
- * +-----------------+
- * | type |
- * +-----------------+
- * type - uint8_t, event code
- */
-
-#define XENKBD_OUT_EVENT_SIZE 40
-
-union xenkbd_out_event
-{
- uint8_t type;
- char pad[XENKBD_OUT_EVENT_SIZE];
-};
-
-/*
- *****************************************************************************
- * Shared page
- *****************************************************************************
- */
-
-#define XENKBD_IN_RING_SIZE 2048
-#define XENKBD_IN_RING_LEN (XENKBD_IN_RING_SIZE / XENKBD_IN_EVENT_SIZE)
-#define XENKBD_IN_RING_OFFS 1024
-#define XENKBD_IN_RING(page) \
- ((union xenkbd_in_event *)((char *)(page) + XENKBD_IN_RING_OFFS))
-#define XENKBD_IN_RING_REF(page, idx) \
- (XENKBD_IN_RING((page))[(idx) % XENKBD_IN_RING_LEN])
-
-#define XENKBD_OUT_RING_SIZE 1024
-#define XENKBD_OUT_RING_LEN (XENKBD_OUT_RING_SIZE / XENKBD_OUT_EVENT_SIZE)
-#define XENKBD_OUT_RING_OFFS (XENKBD_IN_RING_OFFS + XENKBD_IN_RING_SIZE)
-#define XENKBD_OUT_RING(page) \
- ((union xenkbd_out_event *)((char *)(page) + XENKBD_OUT_RING_OFFS))
-#define XENKBD_OUT_RING_REF(page, idx) \
- (XENKBD_OUT_RING((page))[(idx) % XENKBD_OUT_RING_LEN])
-
-struct xenkbd_page
-{
- uint32_t in_cons, in_prod;
- uint32_t out_cons, out_prod;
-};
-
-#endif /* __XEN_PUBLIC_IO_KBDIF_H__ */
+++ /dev/null
-/******************************************************************************
- * netif.h
- *
- * Unified network-device I/O interface for Xen guest OSes.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to
- * deal in the Software without restriction, including without limitation the
- * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
- * sell copies of the Software, and to permit persons to whom the Software is
- * furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
- * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
- * DEALINGS IN THE SOFTWARE.
- *
- * Copyright (c) 2003-2004, Keir Fraser
- */
-
-#ifndef __XEN_PUBLIC_IO_NETIF_H__
-#define __XEN_PUBLIC_IO_NETIF_H__
-
-#include "ring.h"
-#include "../grant_table.h"
-
-/*
- * Older implementation of Xen network frontend / backend has an
- * implicit dependency on the MAX_SKB_FRAGS as the maximum number of
- * ring slots a skb can use. Netfront / netback may not work as
- * expected when frontend and backend have different MAX_SKB_FRAGS.
- *
- * A better approach is to add mechanism for netfront / netback to
- * negotiate this value. However we cannot fix all possible
- * frontends, so we need to define a value which states the minimum
- * slots backend must support.
- *
- * The minimum value derives from older Linux kernel's MAX_SKB_FRAGS
- * (18), which is proved to work with most frontends. Any new backend
- * which doesn't negotiate with frontend should expect frontend to
- * send a valid packet using slots up to this value.
- */
-#define XEN_NETIF_NR_SLOTS_MIN 18
-
-/*
- * Notifications after enqueuing any type of message should be conditional on
- * the appropriate req_event or rsp_event field in the shared ring.
- * If the client sends notification for rx requests then it should specify
- * feature 'feature-rx-notify' via xenbus. Otherwise the backend will assume
- * that it cannot safely queue packets (as it may not be kicked to send them).
- */
-
-/*
- * "feature-split-event-channels" is introduced to separate guest TX
- * and RX notification. Backend either doesn't support this feature or
- * advertises it via xenstore as 0 (disabled) or 1 (enabled).
- *
- * To make use of this feature, frontend should allocate two event
- * channels for TX and RX, advertise them to backend as
- * "event-channel-tx" and "event-channel-rx" respectively. If frontend
- * doesn't want to use this feature, it just writes "event-channel"
- * node as before.
- */
-
-/*
- * Multiple transmit and receive queues:
- * If supported, the backend will write the key "multi-queue-max-queues" to
- * the directory for that vif, and set its value to the maximum supported
- * number of queues.
- * Frontends that are aware of this feature and wish to use it can write the
- * key "multi-queue-num-queues", set to the number they wish to use, which
- * must be greater than zero, and no more than the value reported by the backend
- * in "multi-queue-max-queues".
- *
- * Queues replicate the shared rings and event channels.
- * "feature-split-event-channels" may optionally be used when using
- * multiple queues, but is not mandatory.
- *
- * Each queue consists of one shared ring pair, i.e. there must be the same
- * number of tx and rx rings.
- *
- * For frontends requesting just one queue, the usual event-channel and
- * ring-ref keys are written as before, simplifying the backend processing
- * to avoid distinguishing between a frontend that doesn't understand the
- * multi-queue feature, and one that does, but requested only one queue.
- *
- * Frontends requesting two or more queues must not write the toplevel
- * event-channel (or event-channel-{tx,rx}) and {tx,rx}-ring-ref keys,
- * instead writing those keys under sub-keys having the name "queue-N" where
- * N is the integer ID of the queue for which those keys belong. Queues
- * are indexed from zero. For example, a frontend with two queues and split
- * event channels must write the following set of queue-related keys:
- *
- * /local/domain/1/device/vif/0/multi-queue-num-queues = "2"
- * /local/domain/1/device/vif/0/queue-0 = ""
- * /local/domain/1/device/vif/0/queue-0/tx-ring-ref = "<ring-ref-tx0>"
- * /local/domain/1/device/vif/0/queue-0/rx-ring-ref = "<ring-ref-rx0>"
- * /local/domain/1/device/vif/0/queue-0/event-channel-tx = "<evtchn-tx0>"
- * /local/domain/1/device/vif/0/queue-0/event-channel-rx = "<evtchn-rx0>"
- * /local/domain/1/device/vif/0/queue-1 = ""
- * /local/domain/1/device/vif/0/queue-1/tx-ring-ref = "<ring-ref-tx1>"
- * /local/domain/1/device/vif/0/queue-1/rx-ring-ref = "<ring-ref-rx1"
- * /local/domain/1/device/vif/0/queue-1/event-channel-tx = "<evtchn-tx1>"
- * /local/domain/1/device/vif/0/queue-1/event-channel-rx = "<evtchn-rx1>"
- *
- * If there is any inconsistency in the XenStore data, the backend may
- * choose not to connect any queues, instead treating the request as an
- * error. This includes scenarios where more (or fewer) queues were
- * requested than the frontend provided details for.
- *
- * Mapping of packets to queues is considered to be a function of the
- * transmitting system (backend or frontend) and is not negotiated
- * between the two. Guests are free to transmit packets on any queue
- * they choose, provided it has been set up correctly. Guests must be
- * prepared to receive packets on any queue they have requested be set up.
- */
-
-/*
- * "feature-no-csum-offload" should be used to turn IPv4 TCP/UDP checksum
- * offload off or on. If it is missing then the feature is assumed to be on.
- * "feature-ipv6-csum-offload" should be used to turn IPv6 TCP/UDP checksum
- * offload on or off. If it is missing then the feature is assumed to be off.
- */
-
-/*
- * "feature-gso-tcpv4" and "feature-gso-tcpv6" advertise the capability to
- * handle large TCP packets (in IPv4 or IPv6 form respectively). Neither
- * frontends nor backends are assumed to be capable unless the flags are
- * present.
- */
-
-/*
- * "feature-multicast-control" and "feature-dynamic-multicast-control"
- * advertise the capability to filter ethernet multicast packets in the
- * backend. If the frontend wishes to take advantage of this feature then
- * it may set "request-multicast-control". If the backend only advertises
- * "feature-multicast-control" then "request-multicast-control" must be set
- * before the frontend moves into the connected state. The backend will
- * sample the value on this state transition and any subsequent change in
- * value will have no effect. However, if the backend also advertises
- * "feature-dynamic-multicast-control" then "request-multicast-control"
- * may be set by the frontend at any time. In this case, the backend will
- * watch the value and re-sample on watch events.
- *
- * If the sampled value of "request-multicast-control" is set then the
- * backend transmit side should no longer flood multicast packets to the
- * frontend, it should instead drop any multicast packet that does not
- * match in a filter list.
- * The list is amended by the frontend by sending dummy transmit requests
- * containing XEN_NETIF_EXTRA_TYPE_MCAST_{ADD,DEL} extra-info fragments as
- * specified below.
- * Note that the filter list may be amended even if the sampled value of
- * "request-multicast-control" is not set, however the filter should only
- * be applied if it is set.
- */
-
-/*
- * Control ring
- * ============
- *
- * Some features, such as hashing (detailed below), require a
- * significant amount of out-of-band data to be passed from frontend to
- * backend. Use of xenstore is not suitable for large quantities of data
- * because of quota limitations and so a dedicated 'control ring' is used.
- * The ability of the backend to use a control ring is advertised by
- * setting:
- *
- * /local/domain/X/backend/<domid>/<vif>/feature-ctrl-ring = "1"
- *
- * The frontend provides a control ring to the backend by setting:
- *
- * /local/domain/<domid>/device/vif/<vif>/ctrl-ring-ref = <gref>
- * /local/domain/<domid>/device/vif/<vif>/event-channel-ctrl = <port>
- *
- * where <gref> is the grant reference of the shared page used to
- * implement the control ring and <port> is an event channel to be used
- * as a mailbox interrupt. These keys must be set before the frontend
- * moves into the connected state.
- *
- * The control ring uses a fixed request/response message size and is
- * balanced (i.e. one request to one response), so operationally it is much
- * the same as a transmit or receive ring.
- * Note that there is no requirement that responses are issued in the same
- * order as requests.
- */
-
-/*
- * Hash types
- * ==========
- *
- * For the purposes of the definitions below, 'Packet[]' is an array of
- * octets containing an IP packet without options, 'Array[X..Y]' means a
- * sub-array of 'Array' containing bytes X thru Y inclusive, and '+' is
- * used to indicate concatenation of arrays.
- */
-
-/*
- * A hash calculated over an IP version 4 header as follows:
- *
- * Buffer[0..8] = Packet[12..15] (source address) +
- * Packet[16..19] (destination address)
- *
- * Result = Hash(Buffer, 8)
- */
-#define _XEN_NETIF_CTRL_HASH_TYPE_IPV4 0
-#define XEN_NETIF_CTRL_HASH_TYPE_IPV4 \
- (1 << _XEN_NETIF_CTRL_HASH_TYPE_IPV4)
-
-/*
- * A hash calculated over an IP version 4 header and TCP header as
- * follows:
- *
- * Buffer[0..12] = Packet[12..15] (source address) +
- * Packet[16..19] (destination address) +
- * Packet[20..21] (source port) +
- * Packet[22..23] (destination port)
- *
- * Result = Hash(Buffer, 12)
- */
-#define _XEN_NETIF_CTRL_HASH_TYPE_IPV4_TCP 1
-#define XEN_NETIF_CTRL_HASH_TYPE_IPV4_TCP \
- (1 << _XEN_NETIF_CTRL_HASH_TYPE_IPV4_TCP)
-
-/*
- * A hash calculated over an IP version 6 header as follows:
- *
- * Buffer[0..32] = Packet[8..23] (source address ) +
- * Packet[24..39] (destination address)
- *
- * Result = Hash(Buffer, 32)
- */
-#define _XEN_NETIF_CTRL_HASH_TYPE_IPV6 2
-#define XEN_NETIF_CTRL_HASH_TYPE_IPV6 \
- (1 << _XEN_NETIF_CTRL_HASH_TYPE_IPV6)
-
-/*
- * A hash calculated over an IP version 6 header and TCP header as
- * follows:
- *
- * Buffer[0..36] = Packet[8..23] (source address) +
- * Packet[24..39] (destination address) +
- * Packet[40..41] (source port) +
- * Packet[42..43] (destination port)
- *
- * Result = Hash(Buffer, 36)
- */
-#define _XEN_NETIF_CTRL_HASH_TYPE_IPV6_TCP 3
-#define XEN_NETIF_CTRL_HASH_TYPE_IPV6_TCP \
- (1 << _XEN_NETIF_CTRL_HASH_TYPE_IPV6_TCP)
-
-/*
- * Hash algorithms
- * ===============
- */
-
-#define XEN_NETIF_CTRL_HASH_ALGORITHM_NONE 0
-
-/*
- * Toeplitz hash:
- */
-
-#define XEN_NETIF_CTRL_HASH_ALGORITHM_TOEPLITZ 1
-
-/*
- * Control requests (struct xen_netif_ctrl_request)
- * ================================================
- *
- * All requests have the following format:
- *
- * 0 1 2 3 4 5 6 7 octet
- * +-----+-----+-----+-----+-----+-----+-----+-----+
- * | id | type | data[0] |
- * +-----+-----+-----+-----+-----+-----+-----+-----+
- * | data[1] | data[2] |
- * +-----+-----+-----+-----+-----------------------+
- *
- * id: the request identifier, echoed in response.
- * type: the type of request (see below)
- * data[]: any data associated with the request (determined by type)
- */
-
-struct xen_netif_ctrl_request {
- uint16_t id;
- uint16_t type;
-
-#define XEN_NETIF_CTRL_TYPE_INVALID 0
-#define XEN_NETIF_CTRL_TYPE_GET_HASH_FLAGS 1
-#define XEN_NETIF_CTRL_TYPE_SET_HASH_FLAGS 2
-#define XEN_NETIF_CTRL_TYPE_SET_HASH_KEY 3
-#define XEN_NETIF_CTRL_TYPE_GET_HASH_MAPPING_SIZE 4
-#define XEN_NETIF_CTRL_TYPE_SET_HASH_MAPPING_SIZE 5
-#define XEN_NETIF_CTRL_TYPE_SET_HASH_MAPPING 6
-#define XEN_NETIF_CTRL_TYPE_SET_HASH_ALGORITHM 7
-#define XEN_NETIF_CTRL_TYPE_GET_GREF_MAPPING_SIZE 8
-#define XEN_NETIF_CTRL_TYPE_ADD_GREF_MAPPING 9
-#define XEN_NETIF_CTRL_TYPE_DEL_GREF_MAPPING 10
-
- uint32_t data[3];
-};
-
-/*
- * Control responses (struct xen_netif_ctrl_response)
- * ==================================================
- *
- * All responses have the following format:
- *
- * 0 1 2 3 4 5 6 7 octet
- * +-----+-----+-----+-----+-----+-----+-----+-----+
- * | id | type | status |
- * +-----+-----+-----+-----+-----+-----+-----+-----+
- * | data |
- * +-----+-----+-----+-----+
- *
- * id: the corresponding request identifier
- * type: the type of the corresponding request
- * status: the status of request processing
- * data: any data associated with the response (determined by type and
- * status)
- */
-
-struct xen_netif_ctrl_response {
- uint16_t id;
- uint16_t type;
- uint32_t status;
-
-#define XEN_NETIF_CTRL_STATUS_SUCCESS 0
-#define XEN_NETIF_CTRL_STATUS_NOT_SUPPORTED 1
-#define XEN_NETIF_CTRL_STATUS_INVALID_PARAMETER 2
-#define XEN_NETIF_CTRL_STATUS_BUFFER_OVERFLOW 3
-
- uint32_t data;
-};
-
-/*
- * Static Grants (struct xen_netif_gref)
- * =====================================
- *
- * A frontend may provide a fixed set of grant references to be mapped on
- * the backend. The message of type XEN_NETIF_CTRL_TYPE_ADD_GREF_MAPPING
- * prior its usage in the command ring allows for creation of these mappings.
- * The backend will maintain a fixed amount of these mappings.
- *
- * XEN_NETIF_CTRL_TYPE_GET_GREF_MAPPING_SIZE lets a frontend query how many
- * of these mappings can be kept.
- *
- * Each entry in the XEN_NETIF_CTRL_TYPE_{ADD,DEL}_GREF_MAPPING input table has
- * the following format:
- *
- * 0 1 2 3 4 5 6 7 octet
- * +-----+-----+-----+-----+-----+-----+-----+-----+
- * | grant ref | flags | status |
- * +-----+-----+-----+-----+-----+-----+-----+-----+
- *
- * grant ref: grant reference (IN)
- * flags: flags describing the control operation (IN)
- * status: XEN_NETIF_CTRL_STATUS_* (OUT)
- *
- * 'status' is an output parameter which does not require to be set to zero
- * prior to its usage in the corresponding control messages.
- */
-
-struct xen_netif_gref {
- grant_ref_t ref;
- uint16_t flags;
-
-#define _XEN_NETIF_CTRLF_GREF_readonly 0
-#define XEN_NETIF_CTRLF_GREF_readonly (1U<<_XEN_NETIF_CTRLF_GREF_readonly)
-
- uint16_t status;
-};
-
-/*
- * Control messages
- * ================
- *
- * XEN_NETIF_CTRL_TYPE_SET_HASH_ALGORITHM
- * --------------------------------------
- *
- * This is sent by the frontend to set the desired hash algorithm.
- *
- * Request:
- *
- * type = XEN_NETIF_CTRL_TYPE_SET_HASH_ALGORITHM
- * data[0] = a XEN_NETIF_CTRL_HASH_ALGORITHM_* value
- * data[1] = 0
- * data[2] = 0
- *
- * Response:
- *
- * status = XEN_NETIF_CTRL_STATUS_NOT_SUPPORTED - Operation not
- * supported
- * XEN_NETIF_CTRL_STATUS_INVALID_PARAMETER - The algorithm is not
- * supported
- * XEN_NETIF_CTRL_STATUS_SUCCESS - Operation successful
- *
- * NOTE: Setting data[0] to XEN_NETIF_CTRL_HASH_ALGORITHM_NONE disables
- * hashing and the backend is free to choose how it steers packets
- * to queues (which is the default behaviour).
- *
- * XEN_NETIF_CTRL_TYPE_GET_HASH_FLAGS
- * ----------------------------------
- *
- * This is sent by the frontend to query the types of hash supported by
- * the backend.
- *
- * Request:
- *
- * type = XEN_NETIF_CTRL_TYPE_GET_HASH_FLAGS
- * data[0] = 0
- * data[1] = 0
- * data[2] = 0
- *
- * Response:
- *
- * status = XEN_NETIF_CTRL_STATUS_NOT_SUPPORTED - Operation not supported
- * XEN_NETIF_CTRL_STATUS_SUCCESS - Operation successful
- * data = supported hash types (if operation was successful)
- *
- * NOTE: A valid hash algorithm must be selected before this operation can
- * succeed.
- *
- * XEN_NETIF_CTRL_TYPE_SET_HASH_FLAGS
- * ----------------------------------
- *
- * This is sent by the frontend to set the types of hash that the backend
- * should calculate. (See above for hash type definitions).
- * Note that the 'maximal' type of hash should always be chosen. For
- * example, if the frontend sets both IPV4 and IPV4_TCP hash types then
- * the latter hash type should be calculated for any TCP packet and the
- * former only calculated for non-TCP packets.
- *
- * Request:
- *
- * type = XEN_NETIF_CTRL_TYPE_SET_HASH_FLAGS
- * data[0] = bitwise OR of XEN_NETIF_CTRL_HASH_TYPE_* values
- * data[1] = 0
- * data[2] = 0
- *
- * Response:
- *
- * status = XEN_NETIF_CTRL_STATUS_NOT_SUPPORTED - Operation not
- * supported
- * XEN_NETIF_CTRL_STATUS_INVALID_PARAMETER - One or more flag
- * value is invalid or
- * unsupported
- * XEN_NETIF_CTRL_STATUS_SUCCESS - Operation successful
- * data = 0
- *
- * NOTE: A valid hash algorithm must be selected before this operation can
- * succeed.
- * Also, setting data[0] to zero disables hashing and the backend
- * is free to choose how it steers packets to queues.
- *
- * XEN_NETIF_CTRL_TYPE_SET_HASH_KEY
- * --------------------------------
- *
- * This is sent by the frontend to set the key of the hash if the algorithm
- * requires it. (See hash algorithms above).
- *
- * Request:
- *
- * type = XEN_NETIF_CTRL_TYPE_SET_HASH_KEY
- * data[0] = grant reference of page containing the key (assumed to
- * start at beginning of grant)
- * data[1] = size of key in octets
- * data[2] = 0
- *
- * Response:
- *
- * status = XEN_NETIF_CTRL_STATUS_NOT_SUPPORTED - Operation not
- * supported
- * XEN_NETIF_CTRL_STATUS_INVALID_PARAMETER - Key size is invalid
- * XEN_NETIF_CTRL_STATUS_BUFFER_OVERFLOW - Key size is larger
- * than the backend
- * supports
- * XEN_NETIF_CTRL_STATUS_SUCCESS - Operation successful
- * data = 0
- *
- * NOTE: Any key octets not specified are assumed to be zero (the key
- * is assumed to be empty by default) and specifying a new key
- * invalidates any previous key, hence specifying a key size of
- * zero will clear the key (which ensures that the calculated hash
- * will always be zero).
- * The maximum size of key is algorithm and backend specific, but
- * is also limited by the single grant reference.
- * The grant reference may be read-only and must remain valid until
- * the response has been processed.
- *
- * XEN_NETIF_CTRL_TYPE_GET_HASH_MAPPING_SIZE
- * -----------------------------------------
- *
- * This is sent by the frontend to query the maximum size of mapping
- * table supported by the backend. The size is specified in terms of
- * table entries.
- *
- * Request:
- *
- * type = XEN_NETIF_CTRL_TYPE_GET_HASH_MAPPING_SIZE
- * data[0] = 0
- * data[1] = 0
- * data[2] = 0
- *
- * Response:
- *
- * status = XEN_NETIF_CTRL_STATUS_NOT_SUPPORTED - Operation not supported
- * XEN_NETIF_CTRL_STATUS_SUCCESS - Operation successful
- * data = maximum number of entries allowed in the mapping table
- * (if operation was successful) or zero if a mapping table is
- * not supported (i.e. hash mapping is done only by modular
- * arithmetic).
- *
- * XEN_NETIF_CTRL_TYPE_SET_HASH_MAPPING_SIZE
- * -------------------------------------
- *
- * This is sent by the frontend to set the actual size of the mapping
- * table to be used by the backend. The size is specified in terms of
- * table entries.
- * Any previous table is invalidated by this message and any new table
- * is assumed to be zero filled.
- *
- * Request:
- *
- * type = XEN_NETIF_CTRL_TYPE_SET_HASH_MAPPING_SIZE
- * data[0] = number of entries in mapping table
- * data[1] = 0
- * data[2] = 0
- *
- * Response:
- *
- * status = XEN_NETIF_CTRL_STATUS_NOT_SUPPORTED - Operation not
- * supported
- * XEN_NETIF_CTRL_STATUS_INVALID_PARAMETER - Table size is invalid
- * XEN_NETIF_CTRL_STATUS_SUCCESS - Operation successful
- * data = 0
- *
- * NOTE: Setting data[0] to 0 means that hash mapping should be done
- * using modular arithmetic.
- *
- * XEN_NETIF_CTRL_TYPE_SET_HASH_MAPPING
- * ------------------------------------
- *
- * This is sent by the frontend to set the content of the table mapping
- * hash value to queue number. The backend should calculate the hash from
- * the packet header, use it as an index into the table (modulo the size
- * of the table) and then steer the packet to the queue number found at
- * that index.
- *
- * Request:
- *
- * type = XEN_NETIF_CTRL_TYPE_SET_HASH_MAPPING
- * data[0] = grant reference of page containing the mapping (sub-)table
- * (assumed to start at beginning of grant)
- * data[1] = size of (sub-)table in entries
- * data[2] = offset, in entries, of sub-table within overall table
- *
- * Response:
- *
- * status = XEN_NETIF_CTRL_STATUS_NOT_SUPPORTED - Operation not
- * supported
- * XEN_NETIF_CTRL_STATUS_INVALID_PARAMETER - Table size or content
- * is invalid
- * XEN_NETIF_CTRL_STATUS_BUFFER_OVERFLOW - Table size is larger
- * than the backend
- * supports
- * XEN_NETIF_CTRL_STATUS_SUCCESS - Operation successful
- * data = 0
- *
- * NOTE: The overall table has the following format:
- *
- * 0 1 2 3 4 5 6 7 octet
- * +-----+-----+-----+-----+-----+-----+-----+-----+
- * | mapping[0] | mapping[1] |
- * +-----+-----+-----+-----+-----+-----+-----+-----+
- * | . |
- * | . |
- * | . |
- * +-----+-----+-----+-----+-----+-----+-----+-----+
- * | mapping[N-2] | mapping[N-1] |
- * +-----+-----+-----+-----+-----+-----+-----+-----+
- *
- * where N is specified by a XEN_NETIF_CTRL_TYPE_SET_HASH_MAPPING_SIZE
- * message and each mapping must specifies a queue between 0 and
- * "multi-queue-num-queues" (see above).
- * The backend may support a mapping table larger than can be
- * mapped by a single grant reference. Thus sub-tables within a
- * larger table can be individually set by sending multiple messages
- * with differing offset values. Specifying a new sub-table does not
- * invalidate any table data outside that range.
- * The grant reference may be read-only and must remain valid until
- * the response has been processed.
- *
- * XEN_NETIF_CTRL_TYPE_GET_GREF_MAPPING_SIZE
- * -----------------------------------------
- *
- * This is sent by the frontend to fetch the number of grefs that can be kept
- * mapped in the backend.
- *
- * Request:
- *
- * type = XEN_NETIF_CTRL_TYPE_GET_GREF_MAPPING_SIZE
- * data[0] = queue index (assumed 0 for single queue)
- * data[1] = 0
- * data[2] = 0
- *
- * Response:
- *
- * status = XEN_NETIF_CTRL_STATUS_NOT_SUPPORTED - Operation not
- * supported
- * XEN_NETIF_CTRL_STATUS_INVALID_PARAMETER - The queue index is
- * out of range
- * XEN_NETIF_CTRL_STATUS_SUCCESS - Operation successful
- * data = maximum number of entries allowed in the gref mapping table
- * (if operation was successful) or zero if it is not supported.
- *
- * XEN_NETIF_CTRL_TYPE_ADD_GREF_MAPPING
- * ------------------------------------
- *
- * This is sent by the frontend for backend to map a list of grant
- * references.
- *
- * Request:
- *
- * type = XEN_NETIF_CTRL_TYPE_ADD_GREF_MAPPING
- * data[0] = queue index
- * data[1] = grant reference of page containing the mapping list
- * (r/w and assumed to start at beginning of page)
- * data[2] = size of list in entries
- *
- * Response:
- *
- * status = XEN_NETIF_CTRL_STATUS_NOT_SUPPORTED - Operation not
- * supported
- * XEN_NETIF_CTRL_STATUS_INVALID_PARAMETER - Operation failed
- * XEN_NETIF_CTRL_STATUS_SUCCESS - Operation successful
- *
- * NOTE: Each entry in the input table has the format outlined
- * in struct xen_netif_gref.
- * Contrary to XEN_NETIF_CTRL_TYPE_DEL_GREF_MAPPING, the struct
- * xen_netif_gref 'status' field is not used and therefore the response
- * 'status' determines the success of this operation. In case of
- * failure none of grants mappings get added in the backend.
- *
- * XEN_NETIF_CTRL_TYPE_DEL_GREF_MAPPING
- * ------------------------------------
- *
- * This is sent by the frontend for backend to unmap a list of grant
- * references.
- *
- * Request:
- *
- * type = XEN_NETIF_CTRL_TYPE_DEL_GREF_MAPPING
- * data[0] = queue index
- * data[1] = grant reference of page containing the mapping list
- * (r/w and assumed to start at beginning of page)
- * data[2] = size of list in entries
- *
- * Response:
- *
- * status = XEN_NETIF_CTRL_STATUS_NOT_SUPPORTED - Operation not
- * supported
- * XEN_NETIF_CTRL_STATUS_INVALID_PARAMETER - Operation failed
- * XEN_NETIF_CTRL_STATUS_SUCCESS - Operation successful
- * data = number of entries that were unmapped
- *
- * NOTE: Each entry in the input table has the format outlined in struct
- * xen_netif_gref.
- * The struct xen_netif_gref 'status' field determines if the entry
- * was successfully removed.
- * The entries used are only the ones representing grant references that
- * were previously the subject of a XEN_NETIF_CTRL_TYPE_ADD_GREF_MAPPING
- * operation. Any other entries will have their status set to
- * XEN_NETIF_CTRL_STATUS_INVALID_PARAMETER upon completion.
- */
-
-DEFINE_RING_TYPES(xen_netif_ctrl,
- struct xen_netif_ctrl_request,
- struct xen_netif_ctrl_response);
-
-/*
- * Guest transmit
- * ==============
- *
- * This is the 'wire' format for transmit (frontend -> backend) packets:
- *
- * Fragment 1: netif_tx_request_t - flags = NETTXF_*
- * size = total packet size
- * [Extra 1: netif_extra_info_t] - (only if fragment 1 flags include
- * NETTXF_extra_info)
- * ...
- * [Extra N: netif_extra_info_t] - (only if extra N-1 flags include
- * XEN_NETIF_EXTRA_MORE)
- * ...
- * Fragment N: netif_tx_request_t - (only if fragment N-1 flags include
- * NETTXF_more_data - flags on preceding
- * extras are not relevant here)
- * flags = 0
- * size = fragment size
- *
- * NOTE:
- *
- * This format slightly is different from that used for receive
- * (backend -> frontend) packets. Specifically, in a multi-fragment
- * packet the actual size of fragment 1 can only be determined by
- * subtracting the sizes of fragments 2..N from the total packet size.
- *
- * Ring slot size is 12 octets, however not all request/response
- * structs use the full size.
- *
- * tx request data (netif_tx_request_t)
- * ------------------------------------
- *
- * 0 1 2 3 4 5 6 7 octet
- * +-----+-----+-----+-----+-----+-----+-----+-----+
- * | grant ref | offset | flags |
- * +-----+-----+-----+-----+-----+-----+-----+-----+
- * | id | size |
- * +-----+-----+-----+-----+
- *
- * grant ref: Reference to buffer page.
- * offset: Offset within buffer page.
- * flags: NETTXF_*.
- * id: request identifier, echoed in response.
- * size: packet size in bytes.
- *
- * tx response (netif_tx_response_t)
- * ---------------------------------
- *
- * 0 1 2 3 4 5 6 7 octet
- * +-----+-----+-----+-----+-----+-----+-----+-----+
- * | id | status | unused |
- * +-----+-----+-----+-----+-----+-----+-----+-----+
- * | unused |
- * +-----+-----+-----+-----+
- *
- * id: reflects id in transmit request
- * status: NETIF_RSP_*
- *
- * Guest receive
- * =============
- *
- * This is the 'wire' format for receive (backend -> frontend) packets:
- *
- * Fragment 1: netif_rx_request_t - flags = NETRXF_*
- * size = fragment size
- * [Extra 1: netif_extra_info_t] - (only if fragment 1 flags include
- * NETRXF_extra_info)
- * ...
- * [Extra N: netif_extra_info_t] - (only if extra N-1 flags include
- * XEN_NETIF_EXTRA_MORE)
- * ...
- * Fragment N: netif_rx_request_t - (only if fragment N-1 flags include
- * NETRXF_more_data - flags on preceding
- * extras are not relevant here)
- * flags = 0
- * size = fragment size
- *
- * NOTE:
- *
- * This format slightly is different from that used for transmit
- * (frontend -> backend) packets. Specifically, in a multi-fragment
- * packet the size of the packet can only be determined by summing the
- * sizes of fragments 1..N.
- *
- * Ring slot size is 8 octets.
- *
- * rx request (netif_rx_request_t)
- * -------------------------------
- *
- * 0 1 2 3 4 5 6 7 octet
- * +-----+-----+-----+-----+-----+-----+-----+-----+
- * | id | pad | gref |
- * +-----+-----+-----+-----+-----+-----+-----+-----+
- *
- * id: request identifier, echoed in response.
- * gref: reference to incoming granted frame.
- *
- * rx response (netif_rx_response_t)
- * ---------------------------------
- *
- * 0 1 2 3 4 5 6 7 octet
- * +-----+-----+-----+-----+-----+-----+-----+-----+
- * | id | offset | flags | status |
- * +-----+-----+-----+-----+-----+-----+-----+-----+
- *
- * id: reflects id in receive request
- * offset: offset in page of start of received packet
- * flags: NETRXF_*
- * status: -ve: NETIF_RSP_*; +ve: Rx'ed pkt size.
- *
- * NOTE: Historically, to support GSO on the frontend receive side, Linux
- * netfront does not make use of the rx response id (because, as
- * described below, extra info structures overlay the id field).
- * Instead it assumes that responses always appear in the same ring
- * slot as their corresponding request. Thus, to maintain
- * compatibility, backends must make sure this is the case.
- *
- * Extra Info
- * ==========
- *
- * Can be present if initial request or response has NET{T,R}XF_extra_info,
- * or previous extra request has XEN_NETIF_EXTRA_MORE.
- *
- * The struct therefore needs to fit into either a tx or rx slot and
- * is therefore limited to 8 octets.
- *
- * NOTE: Because extra info data overlays the usual request/response
- * structures, there is no id information in the opposite direction.
- * So, if an extra info overlays an rx response the frontend can
- * assume that it is in the same ring slot as the request that was
- * consumed to make the slot available, and the backend must ensure
- * this assumption is true.
- *
- * extra info (netif_extra_info_t)
- * -------------------------------
- *
- * General format:
- *
- * 0 1 2 3 4 5 6 7 octet
- * +-----+-----+-----+-----+-----+-----+-----+-----+
- * |type |flags| type specific data |
- * +-----+-----+-----+-----+-----+-----+-----+-----+
- * | padding for tx |
- * +-----+-----+-----+-----+
- *
- * type: XEN_NETIF_EXTRA_TYPE_*
- * flags: XEN_NETIF_EXTRA_FLAG_*
- * padding for tx: present only in the tx case due to 8 octet limit
- * from rx case. Not shown in type specific entries
- * below.
- *
- * XEN_NETIF_EXTRA_TYPE_GSO:
- *
- * 0 1 2 3 4 5 6 7 octet
- * +-----+-----+-----+-----+-----+-----+-----+-----+
- * |type |flags| size |type | pad | features |
- * +-----+-----+-----+-----+-----+-----+-----+-----+
- *
- * type: Must be XEN_NETIF_EXTRA_TYPE_GSO
- * flags: XEN_NETIF_EXTRA_FLAG_*
- * size: Maximum payload size of each segment. For example,
- * for TCP this is just the path MSS.
- * type: XEN_NETIF_GSO_TYPE_*: This determines the protocol of
- * the packet and any extra features required to segment the
- * packet properly.
- * features: EN_NETIF_GSO_FEAT_*: This specifies any extra GSO
- * features required to process this packet, such as ECN
- * support for TCPv4.
- *
- * XEN_NETIF_EXTRA_TYPE_MCAST_{ADD,DEL}:
- *
- * 0 1 2 3 4 5 6 7 octet
- * +-----+-----+-----+-----+-----+-----+-----+-----+
- * |type |flags| addr |
- * +-----+-----+-----+-----+-----+-----+-----+-----+
- *
- * type: Must be XEN_NETIF_EXTRA_TYPE_MCAST_{ADD,DEL}
- * flags: XEN_NETIF_EXTRA_FLAG_*
- * addr: address to add/remove
- *
- * XEN_NETIF_EXTRA_TYPE_HASH:
- *
- * A backend that supports teoplitz hashing is assumed to accept
- * this type of extra info in transmit packets.
- * A frontend that enables hashing is assumed to accept
- * this type of extra info in receive packets.
- *
- * 0 1 2 3 4 5 6 7 octet
- * +-----+-----+-----+-----+-----+-----+-----+-----+
- * |type |flags|htype| alg |LSB ---- value ---- MSB|
- * +-----+-----+-----+-----+-----+-----+-----+-----+
- *
- * type: Must be XEN_NETIF_EXTRA_TYPE_HASH
- * flags: XEN_NETIF_EXTRA_FLAG_*
- * htype: Hash type (one of _XEN_NETIF_CTRL_HASH_TYPE_* - see above)
- * alg: The algorithm used to calculate the hash (one of
- * XEN_NETIF_CTRL_HASH_TYPE_ALGORITHM_* - see above)
- * value: Hash value
- */
-
-/* Protocol checksum field is blank in the packet (hardware offload)? */
-#define _NETTXF_csum_blank (0)
-#define NETTXF_csum_blank (1U<<_NETTXF_csum_blank)
-
-/* Packet data has been validated against protocol checksum. */
-#define _NETTXF_data_validated (1)
-#define NETTXF_data_validated (1U<<_NETTXF_data_validated)
-
-/* Packet continues in the next request descriptor. */
-#define _NETTXF_more_data (2)
-#define NETTXF_more_data (1U<<_NETTXF_more_data)
-
-/* Packet to be followed by extra descriptor(s). */
-#define _NETTXF_extra_info (3)
-#define NETTXF_extra_info (1U<<_NETTXF_extra_info)
-
-#define XEN_NETIF_MAX_TX_SIZE 0xFFFF
-struct netif_tx_request {
- grant_ref_t gref;
- uint16_t offset;
- uint16_t flags;
- uint16_t id;
- uint16_t size;
-};
-typedef struct netif_tx_request netif_tx_request_t;
-
-/* Types of netif_extra_info descriptors. */
-#define XEN_NETIF_EXTRA_TYPE_NONE (0) /* Never used - invalid */
-#define XEN_NETIF_EXTRA_TYPE_GSO (1) /* u.gso */
-#define XEN_NETIF_EXTRA_TYPE_MCAST_ADD (2) /* u.mcast */
-#define XEN_NETIF_EXTRA_TYPE_MCAST_DEL (3) /* u.mcast */
-#define XEN_NETIF_EXTRA_TYPE_HASH (4) /* u.hash */
-#define XEN_NETIF_EXTRA_TYPE_MAX (5)
-
-/* netif_extra_info_t flags. */
-#define _XEN_NETIF_EXTRA_FLAG_MORE (0)
-#define XEN_NETIF_EXTRA_FLAG_MORE (1U<<_XEN_NETIF_EXTRA_FLAG_MORE)
-
-/* GSO types */
-#define XEN_NETIF_GSO_TYPE_NONE (0)
-#define XEN_NETIF_GSO_TYPE_TCPV4 (1)
-#define XEN_NETIF_GSO_TYPE_TCPV6 (2)
-
-/*
- * This structure needs to fit within both netif_tx_request_t and
- * netif_rx_response_t for compatibility.
- */
-struct netif_extra_info {
- uint8_t type;
- uint8_t flags;
- union {
- struct {
- uint16_t size;
- uint8_t type;
- uint8_t pad;
- uint16_t features;
- } gso;
- struct {
- uint8_t addr[6];
- } mcast;
- struct {
- uint8_t type;
- uint8_t algorithm;
- uint8_t value[4];
- } hash;
- uint16_t pad[3];
- } u;
-};
-typedef struct netif_extra_info netif_extra_info_t;
-
-struct netif_tx_response {
- uint16_t id;
- int16_t status;
-};
-typedef struct netif_tx_response netif_tx_response_t;
-
-struct netif_rx_request {
- uint16_t id; /* Echoed in response message. */
- uint16_t pad;
- grant_ref_t gref;
-};
-typedef struct netif_rx_request netif_rx_request_t;
-
-/* Packet data has been validated against protocol checksum. */
-#define _NETRXF_data_validated (0)
-#define NETRXF_data_validated (1U<<_NETRXF_data_validated)
-
-/* Protocol checksum field is blank in the packet (hardware offload)? */
-#define _NETRXF_csum_blank (1)
-#define NETRXF_csum_blank (1U<<_NETRXF_csum_blank)
-
-/* Packet continues in the next request descriptor. */
-#define _NETRXF_more_data (2)
-#define NETRXF_more_data (1U<<_NETRXF_more_data)
-
-/* Packet to be followed by extra descriptor(s). */
-#define _NETRXF_extra_info (3)
-#define NETRXF_extra_info (1U<<_NETRXF_extra_info)
-
-/* Packet has GSO prefix. Deprecated but included for compatibility */
-#define _NETRXF_gso_prefix (4)
-#define NETRXF_gso_prefix (1U<<_NETRXF_gso_prefix)
-
-struct netif_rx_response {
- uint16_t id;
- uint16_t offset;
- uint16_t flags;
- int16_t status;
-};
-typedef struct netif_rx_response netif_rx_response_t;
-
-/*
- * Generate netif ring structures and types.
- */
-
-DEFINE_RING_TYPES(netif_tx, struct netif_tx_request, struct netif_tx_response);
-DEFINE_RING_TYPES(netif_rx, struct netif_rx_request, struct netif_rx_response);
-
-#define NETIF_RSP_DROPPED -2
-#define NETIF_RSP_ERROR -1
-#define NETIF_RSP_OKAY 0
-/* No response: used for auxiliary requests (e.g., netif_extra_info_t). */
-#define NETIF_RSP_NULL 1
-
-#endif
+++ /dev/null
-/******************************************************************************
- * protocols.h
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to
- * deal in the Software without restriction, including without limitation the
- * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
- * sell copies of the Software, and to permit persons to whom the Software is
- * furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
- * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
- * DEALINGS IN THE SOFTWARE.
- *
- * Copyright (c) 2008, Keir Fraser
- */
-
-#ifndef __XEN_PROTOCOLS_H__
-#define __XEN_PROTOCOLS_H__
-
-#define XEN_IO_PROTO_ABI_X86_32 "x86_32-abi"
-#define XEN_IO_PROTO_ABI_X86_64 "x86_64-abi"
-#define XEN_IO_PROTO_ABI_ARM "arm-abi"
-
-#if defined(__i386__)
-# define XEN_IO_PROTO_ABI_NATIVE XEN_IO_PROTO_ABI_X86_32
-#elif defined(__x86_64__)
-# define XEN_IO_PROTO_ABI_NATIVE XEN_IO_PROTO_ABI_X86_64
-#elif defined(__arm__) || defined(__aarch64__)
-# define XEN_IO_PROTO_ABI_NATIVE XEN_IO_PROTO_ABI_ARM
-#else
-# error arch fixup needed here
-#endif
-
-#endif
+++ /dev/null
-/******************************************************************************
- * ring.h
- *
- * Shared producer-consumer ring macros.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to
- * deal in the Software without restriction, including without limitation the
- * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
- * sell copies of the Software, and to permit persons to whom the Software is
- * furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
- * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
- * DEALINGS IN THE SOFTWARE.
- *
- * Tim Deegan and Andrew Warfield November 2004.
- */
-
-#ifndef __XEN_PUBLIC_IO_RING_H__
-#define __XEN_PUBLIC_IO_RING_H__
-
-/*
- * When #include'ing this header, you need to provide the following
- * declaration upfront:
- * - standard integers types (uint8_t, uint16_t, etc)
- * They are provided by stdint.h of the standard headers.
- *
- * Before using the different macros, you need to provide the following
- * macros:
- * - xen_mb() a memory barrier
- * - xen_rmb() a read memory barrier
- * - xen_wmb() a write memory barrier
- * Example of those can be found in xenctrl.h.
- *
- * In addition, if you intend to use the FLEX macros, you also need to
- * provide the following, before invoking the FLEX macros:
- * - size_t
- * - memcpy
- * - grant_ref_t
- * These declarations are provided by string.h of the standard headers,
- * and grant_table.h from the Xen public headers.
- */
-
-typedef unsigned int RING_IDX;
-
-/* Round a 32-bit unsigned constant down to the nearest power of two. */
-#define __RD2(_x) (((_x) & 0x00000002) ? 0x2 : ((_x) & 0x1))
-#define __RD4(_x) (((_x) & 0x0000000c) ? __RD2((_x)>>2)<<2 : __RD2(_x))
-#define __RD8(_x) (((_x) & 0x000000f0) ? __RD4((_x)>>4)<<4 : __RD4(_x))
-#define __RD16(_x) (((_x) & 0x0000ff00) ? __RD8((_x)>>8)<<8 : __RD8(_x))
-#define __RD32(_x) (((_x) & 0xffff0000) ? __RD16((_x)>>16)<<16 : __RD16(_x))
-
-/*
- * Calculate size of a shared ring, given the total available space for the
- * ring and indexes (_sz), and the name tag of the request/response structure.
- * A ring contains as many entries as will fit, rounded down to the nearest
- * power of two (so we can mask with (size-1) to loop around).
- */
-#define __CONST_RING_SIZE(_s, _sz) \
- (__RD32(((_sz) - offsetof(struct _s##_sring, ring)) / \
- sizeof_field(struct _s##_sring, ring[0])))
-/*
- * The same for passing in an actual pointer instead of a name tag.
- */
-#define __RING_SIZE(_s, _sz) \
- (__RD32(((_sz) - (long)(_s)->ring + (long)(_s)) / sizeof((_s)->ring[0])))
-
-/*
- * Macros to make the correct C datatypes for a new kind of ring.
- *
- * To make a new ring datatype, you need to have two message structures,
- * let's say request_t, and response_t already defined.
- *
- * In a header where you want the ring datatype declared, you then do:
- *
- * DEFINE_RING_TYPES(mytag, request_t, response_t);
- *
- * These expand out to give you a set of types, as you can see below.
- * The most important of these are:
- *
- * mytag_sring_t - The shared ring.
- * mytag_front_ring_t - The 'front' half of the ring.
- * mytag_back_ring_t - The 'back' half of the ring.
- *
- * To initialize a ring in your code you need to know the location and size
- * of the shared memory area (PAGE_SIZE, for instance). To initialise
- * the front half:
- *
- * mytag_front_ring_t front_ring;
- * SHARED_RING_INIT((mytag_sring_t *)shared_page);
- * FRONT_RING_INIT(&front_ring, (mytag_sring_t *)shared_page, PAGE_SIZE);
- *
- * Initializing the back follows similarly (note that only the front
- * initializes the shared ring):
- *
- * mytag_back_ring_t back_ring;
- * BACK_RING_INIT(&back_ring, (mytag_sring_t *)shared_page, PAGE_SIZE);
- */
-
-#define DEFINE_RING_TYPES(__name, __req_t, __rsp_t) \
- \
-/* Shared ring entry */ \
-union __name##_sring_entry { \
- __req_t req; \
- __rsp_t rsp; \
-}; \
- \
-/* Shared ring page */ \
-struct __name##_sring { \
- RING_IDX req_prod, req_event; \
- RING_IDX rsp_prod, rsp_event; \
- union { \
- struct { \
- uint8_t smartpoll_active; \
- } netif; \
- struct { \
- uint8_t msg; \
- } tapif_user; \
- uint8_t pvt_pad[4]; \
- } pvt; \
- uint8_t __pad[44]; \
- union __name##_sring_entry ring[1]; /* variable-length */ \
-}; \
- \
-/* "Front" end's private variables */ \
-struct __name##_front_ring { \
- RING_IDX req_prod_pvt; \
- RING_IDX rsp_cons; \
- unsigned int nr_ents; \
- struct __name##_sring *sring; \
-}; \
- \
-/* "Back" end's private variables */ \
-struct __name##_back_ring { \
- RING_IDX rsp_prod_pvt; \
- RING_IDX req_cons; \
- unsigned int nr_ents; \
- struct __name##_sring *sring; \
-}; \
- \
-/* Syntactic sugar */ \
-typedef struct __name##_sring __name##_sring_t; \
-typedef struct __name##_front_ring __name##_front_ring_t; \
-typedef struct __name##_back_ring __name##_back_ring_t
-
-/*
- * Macros for manipulating rings.
- *
- * FRONT_RING_whatever works on the "front end" of a ring: here
- * requests are pushed on to the ring and responses taken off it.
- *
- * BACK_RING_whatever works on the "back end" of a ring: here
- * requests are taken off the ring and responses put on.
- *
- * N.B. these macros do NO INTERLOCKS OR FLOW CONTROL.
- * This is OK in 1-for-1 request-response situations where the
- * requestor (front end) never has more than RING_SIZE()-1
- * outstanding requests.
- */
-
-/* Initialising empty rings */
-#define SHARED_RING_INIT(_s) do { \
- (_s)->req_prod = (_s)->rsp_prod = 0; \
- (_s)->req_event = (_s)->rsp_event = 1; \
- (void)memset((_s)->pvt.pvt_pad, 0, sizeof((_s)->pvt.pvt_pad)); \
- (void)memset((_s)->__pad, 0, sizeof((_s)->__pad)); \
-} while(0)
-
-#define FRONT_RING_INIT(_r, _s, __size) do { \
- (_r)->req_prod_pvt = 0; \
- (_r)->rsp_cons = 0; \
- (_r)->nr_ents = __RING_SIZE(_s, __size); \
- (_r)->sring = (_s); \
-} while (0)
-
-#define BACK_RING_INIT(_r, _s, __size) do { \
- (_r)->rsp_prod_pvt = 0; \
- (_r)->req_cons = 0; \
- (_r)->nr_ents = __RING_SIZE(_s, __size); \
- (_r)->sring = (_s); \
-} while (0)
-
-/* How big is this ring? */
-#define RING_SIZE(_r) \
- ((_r)->nr_ents)
-
-/* Number of free requests (for use on front side only). */
-#define RING_FREE_REQUESTS(_r) \
- (RING_SIZE(_r) - ((_r)->req_prod_pvt - (_r)->rsp_cons))
-
-/* Test if there is an empty slot available on the front ring.
- * (This is only meaningful from the front. )
- */
-#define RING_FULL(_r) \
- (RING_FREE_REQUESTS(_r) == 0)
-
-/* Test if there are outstanding messages to be processed on a ring. */
-#define RING_HAS_UNCONSUMED_RESPONSES(_r) \
- ((_r)->sring->rsp_prod - (_r)->rsp_cons)
-
-#ifdef __GNUC__
-#define RING_HAS_UNCONSUMED_REQUESTS(_r) ({ \
- unsigned int req = (_r)->sring->req_prod - (_r)->req_cons; \
- unsigned int rsp = RING_SIZE(_r) - \
- ((_r)->req_cons - (_r)->rsp_prod_pvt); \
- req < rsp ? req : rsp; \
-})
-#else
-/* Same as above, but without the nice GCC ({ ... }) syntax. */
-#define RING_HAS_UNCONSUMED_REQUESTS(_r) \
- ((((_r)->sring->req_prod - (_r)->req_cons) < \
- (RING_SIZE(_r) - ((_r)->req_cons - (_r)->rsp_prod_pvt))) ? \
- ((_r)->sring->req_prod - (_r)->req_cons) : \
- (RING_SIZE(_r) - ((_r)->req_cons - (_r)->rsp_prod_pvt)))
-#endif
-
-/* Direct access to individual ring elements, by index. */
-#define RING_GET_REQUEST(_r, _idx) \
- (&((_r)->sring->ring[((_idx) & (RING_SIZE(_r) - 1))].req))
-
-/*
- * Get a local copy of a request.
- *
- * Use this in preference to RING_GET_REQUEST() so all processing is
- * done on a local copy that cannot be modified by the other end.
- *
- * Note that https://gcc.gnu.org/bugzilla/show_bug.cgi?id=58145 may cause this
- * to be ineffective where _req is a struct which consists of only bitfields.
- */
-#define RING_COPY_REQUEST(_r, _idx, _req) do { \
- /* Use volatile to force the copy into _req. */ \
- *(_req) = *(volatile typeof(_req))RING_GET_REQUEST(_r, _idx); \
-} while (0)
-
-#define RING_GET_RESPONSE(_r, _idx) \
- (&((_r)->sring->ring[((_idx) & (RING_SIZE(_r) - 1))].rsp))
-
-/* Loop termination condition: Would the specified index overflow the ring? */
-#define RING_REQUEST_CONS_OVERFLOW(_r, _cons) \
- (((_cons) - (_r)->rsp_prod_pvt) >= RING_SIZE(_r))
-
-/* Ill-behaved frontend determination: Can there be this many requests? */
-#define RING_REQUEST_PROD_OVERFLOW(_r, _prod) \
- (((_prod) - (_r)->rsp_prod_pvt) > RING_SIZE(_r))
-
-#define RING_PUSH_REQUESTS(_r) do { \
- xen_wmb(); /* back sees requests /before/ updated producer index */ \
- (_r)->sring->req_prod = (_r)->req_prod_pvt; \
-} while (0)
-
-#define RING_PUSH_RESPONSES(_r) do { \
- xen_wmb(); /* front sees resps /before/ updated producer index */ \
- (_r)->sring->rsp_prod = (_r)->rsp_prod_pvt; \
-} while (0)
-
-/*
- * Notification hold-off (req_event and rsp_event):
- *
- * When queueing requests or responses on a shared ring, it may not always be
- * necessary to notify the remote end. For example, if requests are in flight
- * in a backend, the front may be able to queue further requests without
- * notifying the back (if the back checks for new requests when it queues
- * responses).
- *
- * When enqueuing requests or responses:
- *
- * Use RING_PUSH_{REQUESTS,RESPONSES}_AND_CHECK_NOTIFY(). The second argument
- * is a boolean return value. True indicates that the receiver requires an
- * asynchronous notification.
- *
- * After dequeuing requests or responses (before sleeping the connection):
- *
- * Use RING_FINAL_CHECK_FOR_REQUESTS() or RING_FINAL_CHECK_FOR_RESPONSES().
- * The second argument is a boolean return value. True indicates that there
- * are pending messages on the ring (i.e., the connection should not be put
- * to sleep).
- *
- * These macros will set the req_event/rsp_event field to trigger a
- * notification on the very next message that is enqueued. If you want to
- * create batches of work (i.e., only receive a notification after several
- * messages have been enqueued) then you will need to create a customised
- * version of the FINAL_CHECK macro in your own code, which sets the event
- * field appropriately.
- */
-
-#define RING_PUSH_REQUESTS_AND_CHECK_NOTIFY(_r, _notify) do { \
- RING_IDX __old = (_r)->sring->req_prod; \
- RING_IDX __new = (_r)->req_prod_pvt; \
- xen_wmb(); /* back sees requests /before/ updated producer index */ \
- (_r)->sring->req_prod = __new; \
- xen_mb(); /* back sees new requests /before/ we check req_event */ \
- (_notify) = ((RING_IDX)(__new - (_r)->sring->req_event) < \
- (RING_IDX)(__new - __old)); \
-} while (0)
-
-#define RING_PUSH_RESPONSES_AND_CHECK_NOTIFY(_r, _notify) do { \
- RING_IDX __old = (_r)->sring->rsp_prod; \
- RING_IDX __new = (_r)->rsp_prod_pvt; \
- xen_wmb(); /* front sees resps /before/ updated producer index */ \
- (_r)->sring->rsp_prod = __new; \
- xen_mb(); /* front sees new resps /before/ we check rsp_event */ \
- (_notify) = ((RING_IDX)(__new - (_r)->sring->rsp_event) < \
- (RING_IDX)(__new - __old)); \
-} while (0)
-
-#define RING_FINAL_CHECK_FOR_REQUESTS(_r, _work_to_do) do { \
- (_work_to_do) = RING_HAS_UNCONSUMED_REQUESTS(_r); \
- if (_work_to_do) break; \
- (_r)->sring->req_event = (_r)->req_cons + 1; \
- xen_mb(); \
- (_work_to_do) = RING_HAS_UNCONSUMED_REQUESTS(_r); \
-} while (0)
-
-#define RING_FINAL_CHECK_FOR_RESPONSES(_r, _work_to_do) do { \
- (_work_to_do) = RING_HAS_UNCONSUMED_RESPONSES(_r); \
- if (_work_to_do) break; \
- (_r)->sring->rsp_event = (_r)->rsp_cons + 1; \
- xen_mb(); \
- (_work_to_do) = RING_HAS_UNCONSUMED_RESPONSES(_r); \
-} while (0)
-
-
-/*
- * DEFINE_XEN_FLEX_RING_AND_INTF defines two monodirectional rings and
- * functions to check if there is data on the ring, and to read and
- * write to them.
- *
- * DEFINE_XEN_FLEX_RING is similar to DEFINE_XEN_FLEX_RING_AND_INTF, but
- * does not define the indexes page. As different protocols can have
- * extensions to the basic format, this macro allow them to define their
- * own struct.
- *
- * XEN_FLEX_RING_SIZE
- * Convenience macro to calculate the size of one of the two rings
- * from the overall order.
- *
- * $NAME_mask
- * Function to apply the size mask to an index, to reduce the index
- * within the range [0-size].
- *
- * $NAME_read_packet
- * Function to read data from the ring. The amount of data to read is
- * specified by the "size" argument.
- *
- * $NAME_write_packet
- * Function to write data to the ring. The amount of data to write is
- * specified by the "size" argument.
- *
- * $NAME_get_ring_ptr
- * Convenience function that returns a pointer to read/write to the
- * ring at the right location.
- *
- * $NAME_data_intf
- * Indexes page, shared between frontend and backend. It also
- * contains the array of grant refs.
- *
- * $NAME_queued
- * Function to calculate how many bytes are currently on the ring,
- * ready to be read. It can also be used to calculate how much free
- * space is currently on the ring (XEN_FLEX_RING_SIZE() -
- * $NAME_queued()).
- */
-
-#ifndef XEN_PAGE_SHIFT
-/* The PAGE_SIZE for ring protocols and hypercall interfaces is always
- * 4K, regardless of the architecture, and page granularity chosen by
- * operating systems.
- */
-#define XEN_PAGE_SHIFT 12
-#endif
-#define XEN_FLEX_RING_SIZE(order) \
- (1UL << ((order) + XEN_PAGE_SHIFT - 1))
-
-#define DEFINE_XEN_FLEX_RING(name) \
-static inline RING_IDX name##_mask(RING_IDX idx, RING_IDX ring_size) \
-{ \
- return idx & (ring_size - 1); \
-} \
- \
-static inline unsigned char *name##_get_ring_ptr(unsigned char *buf, \
- RING_IDX idx, \
- RING_IDX ring_size) \
-{ \
- return buf + name##_mask(idx, ring_size); \
-} \
- \
-static inline void name##_read_packet(void *opaque, \
- const unsigned char *buf, \
- size_t size, \
- RING_IDX masked_prod, \
- RING_IDX *masked_cons, \
- RING_IDX ring_size) \
-{ \
- if (*masked_cons < masked_prod || \
- size <= ring_size - *masked_cons) { \
- memcpy(opaque, buf + *masked_cons, size); \
- } else { \
- memcpy(opaque, buf + *masked_cons, ring_size - *masked_cons); \
- memcpy((unsigned char *)opaque + ring_size - *masked_cons, buf, \
- size - (ring_size - *masked_cons)); \
- } \
- *masked_cons = name##_mask(*masked_cons + size, ring_size); \
-} \
- \
-static inline void name##_write_packet(unsigned char *buf, \
- const void *opaque, \
- size_t size, \
- RING_IDX *masked_prod, \
- RING_IDX masked_cons, \
- RING_IDX ring_size) \
-{ \
- if (*masked_prod < masked_cons || \
- size <= ring_size - *masked_prod) { \
- memcpy(buf + *masked_prod, opaque, size); \
- } else { \
- memcpy(buf + *masked_prod, opaque, ring_size - *masked_prod); \
- memcpy(buf, (unsigned char *)opaque + (ring_size - *masked_prod), \
- size - (ring_size - *masked_prod)); \
- } \
- *masked_prod = name##_mask(*masked_prod + size, ring_size); \
-} \
- \
-static inline RING_IDX name##_queued(RING_IDX prod, \
- RING_IDX cons, \
- RING_IDX ring_size) \
-{ \
- RING_IDX size; \
- \
- if (prod == cons) \
- return 0; \
- \
- prod = name##_mask(prod, ring_size); \
- cons = name##_mask(cons, ring_size); \
- \
- if (prod == cons) \
- return ring_size; \
- \
- if (prod > cons) \
- size = prod - cons; \
- else \
- size = ring_size - (cons - prod); \
- return size; \
-} \
- \
-struct name##_data { \
- unsigned char *in; /* half of the allocation */ \
- unsigned char *out; /* half of the allocation */ \
-}
-
-#define DEFINE_XEN_FLEX_RING_AND_INTF(name) \
-struct name##_data_intf { \
- RING_IDX in_cons, in_prod; \
- \
- uint8_t pad1[56]; \
- \
- RING_IDX out_cons, out_prod; \
- \
- uint8_t pad2[56]; \
- \
- RING_IDX ring_order; \
- grant_ref_t ref[]; \
-}; \
-DEFINE_XEN_FLEX_RING(name)
-
-#endif /* __XEN_PUBLIC_IO_RING_H__ */
-
-/*
- * Local variables:
- * mode: C
- * c-file-style: "BSD"
- * c-basic-offset: 4
- * tab-width: 4
- * indent-tabs-mode: nil
- * End:
- */
+++ /dev/null
-/*
- * usbif.h
- *
- * USB I/O interface for Xen guest OSes.
- *
- * Copyright (C) 2009, FUJITSU LABORATORIES LTD.
- * Author: Noboru Iwamatsu <n_iwamatsu@jp.fujitsu.com>
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to
- * deal in the Software without restriction, including without limitation the
- * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
- * sell copies of the Software, and to permit persons to whom the Software is
- * furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
- * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
- * DEALINGS IN THE SOFTWARE.
- */
-
-#ifndef __XEN_PUBLIC_IO_USBIF_H__
-#define __XEN_PUBLIC_IO_USBIF_H__
-
-#include "ring.h"
-#include "../grant_table.h"
-
-/*
- * Feature and Parameter Negotiation
- * =================================
- * The two halves of a Xen pvUSB driver utilize nodes within the XenStore to
- * communicate capabilities and to negotiate operating parameters. This
- * section enumerates these nodes which reside in the respective front and
- * backend portions of the XenStore, following the XenBus convention.
- *
- * Any specified default value is in effect if the corresponding XenBus node
- * is not present in the XenStore.
- *
- * XenStore nodes in sections marked "PRIVATE" are solely for use by the
- * driver side whose XenBus tree contains them.
- *
- *****************************************************************************
- * Backend XenBus Nodes
- *****************************************************************************
- *
- *------------------ Backend Device Identification (PRIVATE) ------------------
- *
- * num-ports
- * Values: unsigned [1...31]
- *
- * Number of ports for this (virtual) USB host connector.
- *
- * usb-ver
- * Values: unsigned [1...2]
- *
- * USB version of this host connector: 1 = USB 1.1, 2 = USB 2.0.
- *
- * port/[1...31]
- * Values: string
- *
- * Physical USB device connected to the given port, e.g. "3-1.5".
- *
- *****************************************************************************
- * Frontend XenBus Nodes
- *****************************************************************************
- *
- *----------------------- Request Transport Parameters -----------------------
- *
- * event-channel
- * Values: unsigned
- *
- * The identifier of the Xen event channel used to signal activity
- * in the ring buffer.
- *
- * urb-ring-ref
- * Values: unsigned
- *
- * The Xen grant reference granting permission for the backend to map
- * the sole page in a single page sized ring buffer. This is the ring
- * buffer for urb requests.
- *
- * conn-ring-ref
- * Values: unsigned
- *
- * The Xen grant reference granting permission for the backend to map
- * the sole page in a single page sized ring buffer. This is the ring
- * buffer for connection/disconnection requests.
- *
- * protocol
- * Values: string (XEN_IO_PROTO_ABI_*)
- * Default Value: XEN_IO_PROTO_ABI_NATIVE
- *
- * The machine ABI rules governing the format of all ring request and
- * response structures.
- *
- */
-
-enum usb_spec_version {
- USB_VER_UNKNOWN = 0,
- USB_VER_USB11,
- USB_VER_USB20,
- USB_VER_USB30, /* not supported yet */
-};
-
-/*
- * USB pipe in usbif_request
- *
- * - port number: bits 0-4
- * (USB_MAXCHILDREN is 31)
- *
- * - operation flag: bit 5
- * (0 = submit urb,
- * 1 = unlink urb)
- *
- * - direction: bit 7
- * (0 = Host-to-Device [Out]
- * 1 = Device-to-Host [In])
- *
- * - device address: bits 8-14
- *
- * - endpoint: bits 15-18
- *
- * - pipe type: bits 30-31
- * (00 = isochronous, 01 = interrupt,
- * 10 = control, 11 = bulk)
- */
-
-#define USBIF_PIPE_PORT_MASK 0x0000001f
-#define USBIF_PIPE_UNLINK 0x00000020
-#define USBIF_PIPE_DIR 0x00000080
-#define USBIF_PIPE_DEV_MASK 0x0000007f
-#define USBIF_PIPE_DEV_SHIFT 8
-#define USBIF_PIPE_EP_MASK 0x0000000f
-#define USBIF_PIPE_EP_SHIFT 15
-#define USBIF_PIPE_TYPE_MASK 0x00000003
-#define USBIF_PIPE_TYPE_SHIFT 30
-#define USBIF_PIPE_TYPE_ISOC 0
-#define USBIF_PIPE_TYPE_INT 1
-#define USBIF_PIPE_TYPE_CTRL 2
-#define USBIF_PIPE_TYPE_BULK 3
-
-#define usbif_pipeportnum(pipe) ((pipe) & USBIF_PIPE_PORT_MASK)
-#define usbif_setportnum_pipe(pipe, portnum) ((pipe) | (portnum))
-
-#define usbif_pipeunlink(pipe) ((pipe) & USBIF_PIPE_UNLINK)
-#define usbif_pipesubmit(pipe) (!usbif_pipeunlink(pipe))
-#define usbif_setunlink_pipe(pipe) ((pipe) | USBIF_PIPE_UNLINK)
-
-#define usbif_pipein(pipe) ((pipe) & USBIF_PIPE_DIR)
-#define usbif_pipeout(pipe) (!usbif_pipein(pipe))
-
-#define usbif_pipedevice(pipe) \
- (((pipe) >> USBIF_PIPE_DEV_SHIFT) & USBIF_PIPE_DEV_MASK)
-
-#define usbif_pipeendpoint(pipe) \
- (((pipe) >> USBIF_PIPE_EP_SHIFT) & USBIF_PIPE_EP_MASK)
-
-#define usbif_pipetype(pipe) \
- (((pipe) >> USBIF_PIPE_TYPE_SHIFT) & USBIF_PIPE_TYPE_MASK)
-#define usbif_pipeisoc(pipe) (usbif_pipetype(pipe) == USBIF_PIPE_TYPE_ISOC)
-#define usbif_pipeint(pipe) (usbif_pipetype(pipe) == USBIF_PIPE_TYPE_INT)
-#define usbif_pipectrl(pipe) (usbif_pipetype(pipe) == USBIF_PIPE_TYPE_CTRL)
-#define usbif_pipebulk(pipe) (usbif_pipetype(pipe) == USBIF_PIPE_TYPE_BULK)
-
-#define USBIF_MAX_SEGMENTS_PER_REQUEST (16)
-#define USBIF_MAX_PORTNR 31
-#define USBIF_RING_SIZE 4096
-
-/*
- * RING for transferring urbs.
- */
-struct usbif_request_segment {
- grant_ref_t gref;
- uint16_t offset;
- uint16_t length;
-};
-
-struct usbif_urb_request {
- uint16_t id; /* request id */
- uint16_t nr_buffer_segs; /* number of urb->transfer_buffer segments */
-
- /* basic urb parameter */
- uint32_t pipe;
- uint16_t transfer_flags;
-#define USBIF_SHORT_NOT_OK 0x0001
- uint16_t buffer_length;
- union {
- uint8_t ctrl[8]; /* setup_packet (Ctrl) */
-
- struct {
- uint16_t interval; /* maximum (1024*8) in usb core */
- uint16_t start_frame; /* start frame */
- uint16_t number_of_packets; /* number of ISO packet */
- uint16_t nr_frame_desc_segs; /* number of iso_frame_desc segments */
- } isoc;
-
- struct {
- uint16_t interval; /* maximum (1024*8) in usb core */
- uint16_t pad[3];
- } intr;
-
- struct {
- uint16_t unlink_id; /* unlink request id */
- uint16_t pad[3];
- } unlink;
-
- } u;
-
- /* urb data segments */
- struct usbif_request_segment seg[USBIF_MAX_SEGMENTS_PER_REQUEST];
-};
-typedef struct usbif_urb_request usbif_urb_request_t;
-
-struct usbif_urb_response {
- uint16_t id; /* request id */
- uint16_t start_frame; /* start frame (ISO) */
- int32_t status; /* status (non-ISO) */
- int32_t actual_length; /* actual transfer length */
- int32_t error_count; /* number of ISO errors */
-};
-typedef struct usbif_urb_response usbif_urb_response_t;
-
-DEFINE_RING_TYPES(usbif_urb, struct usbif_urb_request, struct usbif_urb_response);
-#define USB_URB_RING_SIZE __CONST_RING_SIZE(usbif_urb, USBIF_RING_SIZE)
-
-/*
- * RING for notifying connect/disconnect events to frontend
- */
-struct usbif_conn_request {
- uint16_t id;
-};
-typedef struct usbif_conn_request usbif_conn_request_t;
-
-struct usbif_conn_response {
- uint16_t id; /* request id */
- uint8_t portnum; /* port number */
- uint8_t speed; /* usb_device_speed */
-#define USBIF_SPEED_NONE 0
-#define USBIF_SPEED_LOW 1
-#define USBIF_SPEED_FULL 2
-#define USBIF_SPEED_HIGH 3
-};
-typedef struct usbif_conn_response usbif_conn_response_t;
-
-DEFINE_RING_TYPES(usbif_conn, struct usbif_conn_request, struct usbif_conn_response);
-#define USB_CONN_RING_SIZE __CONST_RING_SIZE(usbif_conn, USBIF_RING_SIZE)
-
-#endif /* __XEN_PUBLIC_IO_USBIF_H__ */
+++ /dev/null
-/*****************************************************************************
- * xenbus.h
- *
- * Xenbus protocol details.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to
- * deal in the Software without restriction, including without limitation the
- * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
- * sell copies of the Software, and to permit persons to whom the Software is
- * furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
- * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
- * DEALINGS IN THE SOFTWARE.
- *
- * Copyright (C) 2005 XenSource Ltd.
- */
-
-#ifndef _XEN_PUBLIC_IO_XENBUS_H
-#define _XEN_PUBLIC_IO_XENBUS_H
-
-/*
- * The state of either end of the Xenbus, i.e. the current communication
- * status of initialisation across the bus. States here imply nothing about
- * the state of the connection between the driver and the kernel's device
- * layers.
- */
-enum xenbus_state {
- XenbusStateUnknown = 0,
-
- XenbusStateInitialising = 1,
-
- /*
- * InitWait: Finished early initialisation but waiting for information
- * from the peer or hotplug scripts.
- */
- XenbusStateInitWait = 2,
-
- /*
- * Initialised: Waiting for a connection from the peer.
- */
- XenbusStateInitialised = 3,
-
- XenbusStateConnected = 4,
-
- /*
- * Closing: The device is being closed due to an error or an unplug event.
- */
- XenbusStateClosing = 5,
-
- XenbusStateClosed = 6,
-
- /*
- * Reconfiguring: The device is being reconfigured.
- */
- XenbusStateReconfiguring = 7,
-
- XenbusStateReconfigured = 8
-};
-typedef enum xenbus_state XenbusState;
-
-#endif /* _XEN_PUBLIC_IO_XENBUS_H */
+++ /dev/null
-/*
- * Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to
- * deal in the Software without restriction, including without limitation the
- * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
- * sell copies of the Software, and to permit persons to whom the Software is
- * furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
- * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
- * DEALINGS IN THE SOFTWARE.
- *
- * Copyright (c) 2016, Citrix Systems, Inc.
- */
-
-#ifndef XEN_PUBLIC_ARCH_X86_HVM_START_INFO_H
-#define XEN_PUBLIC_ARCH_X86_HVM_START_INFO_H
-
-/*
- * Start of day structure passed to PVH guests and to HVM guests in %ebx.
- *
- * NOTE: nothing will be loaded at physical address 0, so a 0 value in any
- * of the address fields should be treated as not present.
- *
- * 0 +----------------+
- * | magic | Contains the magic value XEN_HVM_START_MAGIC_VALUE
- * | | ("xEn3" with the 0x80 bit of the "E" set).
- * 4 +----------------+
- * | version | Version of this structure. Current version is 1. New
- * | | versions are guaranteed to be backwards-compatible.
- * 8 +----------------+
- * | flags | SIF_xxx flags.
- * 12 +----------------+
- * | nr_modules | Number of modules passed to the kernel.
- * 16 +----------------+
- * | modlist_paddr | Physical address of an array of modules
- * | | (layout of the structure below).
- * 24 +----------------+
- * | cmdline_paddr | Physical address of the command line,
- * | | a zero-terminated ASCII string.
- * 32 +----------------+
- * | rsdp_paddr | Physical address of the RSDP ACPI data structure.
- * 40 +----------------+
- * | memmap_paddr | Physical address of the (optional) memory map. Only
- * | | present in version 1 and newer of the structure.
- * 48 +----------------+
- * | memmap_entries | Number of entries in the memory map table. Only
- * | | present in version 1 and newer of the structure.
- * | | Zero if there is no memory map being provided.
- * 52 +----------------+
- * | reserved | Version 1 and newer only.
- * 56 +----------------+
- *
- * The layout of each entry in the module structure is the following:
- *
- * 0 +----------------+
- * | paddr | Physical address of the module.
- * 8 +----------------+
- * | size | Size of the module in bytes.
- * 16 +----------------+
- * | cmdline_paddr | Physical address of the command line,
- * | | a zero-terminated ASCII string.
- * 24 +----------------+
- * | reserved |
- * 32 +----------------+
- *
- * The layout of each entry in the memory map table is as follows:
- *
- * 0 +----------------+
- * | addr | Base address
- * 8 +----------------+
- * | size | Size of mapping in bytes
- * 16 +----------------+
- * | type | Type of mapping as defined between the hypervisor
- * | | and guest it's starting. E820_TYPE_xxx, for example.
- * 20 +----------------|
- * | reserved |
- * 24 +----------------+
- *
- * The address and sizes are always a 64bit little endian unsigned integer.
- *
- * NB: Xen on x86 will always try to place all the data below the 4GiB
- * boundary.
- *
- * Version numbers of the hvm_start_info structure have evolved like this:
- *
- * Version 0:
- *
- * Version 1: Added the memmap_paddr/memmap_entries fields (plus 4 bytes of
- * padding) to the end of the hvm_start_info struct. These new
- * fields can be used to pass a memory map to the guest. The
- * memory map is optional and so guests that understand version 1
- * of the structure must check that memmap_entries is non-zero
- * before trying to read the memory map.
- */
-#define XEN_HVM_START_MAGIC_VALUE 0x336ec578
-
-/*
- * C representation of the x86/HVM start info layout.
- *
- * The canonical definition of this layout is above, this is just a way to
- * represent the layout described there using C types.
- */
-struct hvm_start_info {
- uint32_t magic; /* Contains the magic value 0x336ec578 */
- /* ("xEn3" with the 0x80 bit of the "E" set).*/
- uint32_t version; /* Version of this structure. */
- uint32_t flags; /* SIF_xxx flags. */
- uint32_t nr_modules; /* Number of modules passed to the kernel. */
- uint64_t modlist_paddr; /* Physical address of an array of */
- /* hvm_modlist_entry. */
- uint64_t cmdline_paddr; /* Physical address of the command line. */
- uint64_t rsdp_paddr; /* Physical address of the RSDP ACPI data */
- /* structure. */
- uint64_t memmap_paddr; /* Physical address of an array of */
- /* hvm_memmap_table_entry. Only present in */
- /* version 1 and newer of the structure */
- uint32_t memmap_entries; /* Number of entries in the memmap table. */
- /* Only present in version 1 and newer of */
- /* the structure. Value will be zero if */
- /* there is no memory map being provided. */
- uint32_t reserved;
-};
-
-struct hvm_modlist_entry {
- uint64_t paddr; /* Physical address of the module. */
- uint64_t size; /* Size of the module in bytes. */
- uint64_t cmdline_paddr; /* Physical address of the command line. */
- uint64_t reserved;
-};
-
-struct hvm_memmap_table_entry {
- uint64_t addr; /* Base address of the memory region */
- uint64_t size; /* Size of the memory region in bytes */
- uint32_t type; /* Mapping type */
- uint32_t reserved;
-};
-
-#endif /* XEN_PUBLIC_ARCH_X86_HVM_START_INFO_H */
+++ /dev/null
-/*
- * Copyright (c) 2018 Citrix Systems Inc.
- *
- * This work is licensed under the terms of the GNU GPL, version 2 or later.
- * See the COPYING file in the top-level directory.
- */
-
-#ifndef HW_XEN_BACKEND_H
-#define HW_XEN_BACKEND_H
-
-#include "hw/xen/xen-bus.h"
-
-typedef struct XenBackendInstance XenBackendInstance;
-
-typedef void (*XenBackendDeviceCreate)(XenBackendInstance *backend,
- QDict *opts, Error **errp);
-typedef void (*XenBackendDeviceDestroy)(XenBackendInstance *backend,
- Error **errp);
-
-typedef struct XenBackendInfo {
- const char *type;
- XenBackendDeviceCreate create;
- XenBackendDeviceDestroy destroy;
-} XenBackendInfo;
-
-XenBus *xen_backend_get_bus(XenBackendInstance *backend);
-const char *xen_backend_get_name(XenBackendInstance *backend);
-
-void xen_backend_set_device(XenBackendInstance *backend,
- XenDevice *xendevice);
-XenDevice *xen_backend_get_device(XenBackendInstance *backend);
-
-void xen_backend_register(const XenBackendInfo *info);
-const char **xen_backend_get_types(unsigned int *nr);
-
-void xen_backend_device_create(XenBus *xenbus, const char *type,
- const char *name, QDict *opts, Error **errp);
-bool xen_backend_try_device_destroy(XenDevice *xendev, Error **errp);
-
-#endif /* HW_XEN_BACKEND_H */
+++ /dev/null
-/*
- * Copyright (c) 2018 Citrix Systems Inc.
- *
- * This work is licensed under the terms of the GNU GPL, version 2 or later.
- * See the COPYING file in the top-level directory.
- */
-
-#ifndef HW_XEN_BLOCK_H
-#define HW_XEN_BLOCK_H
-
-#include "hw/xen/xen-bus.h"
-#include "hw/block/block.h"
-#include "hw/block/dataplane/xen-block.h"
-#include "sysemu/iothread.h"
-#include "qom/object.h"
-
-typedef enum XenBlockVdevType {
- XEN_BLOCK_VDEV_TYPE_INVALID,
- XEN_BLOCK_VDEV_TYPE_DP,
- XEN_BLOCK_VDEV_TYPE_XVD,
- XEN_BLOCK_VDEV_TYPE_HD,
- XEN_BLOCK_VDEV_TYPE_SD,
- XEN_BLOCK_VDEV_TYPE__MAX
-} XenBlockVdevType;
-
-typedef struct XenBlockVdev {
- XenBlockVdevType type;
- unsigned long disk;
- unsigned long partition;
- unsigned long number;
-} XenBlockVdev;
-
-
-typedef struct XenBlockProperties {
- XenBlockVdev vdev;
- BlockConf conf;
- unsigned int max_ring_page_order;
- IOThread *iothread;
-} XenBlockProperties;
-
-typedef struct XenBlockDrive {
- char *id;
- char *node_name;
-} XenBlockDrive;
-
-typedef struct XenBlockIOThread {
- char *id;
-} XenBlockIOThread;
-
-struct XenBlockDevice {
- XenDevice xendev;
- XenBlockProperties props;
- const char *device_type;
- unsigned int info;
- XenBlockDataPlane *dataplane;
- XenBlockDrive *drive;
- XenBlockIOThread *iothread;
-};
-typedef struct XenBlockDevice XenBlockDevice;
-
-typedef void (*XenBlockDeviceRealize)(XenBlockDevice *blockdev, Error **errp);
-typedef void (*XenBlockDeviceUnrealize)(XenBlockDevice *blockdev);
-
-struct XenBlockDeviceClass {
- /*< private >*/
- XenDeviceClass parent_class;
- /*< public >*/
- XenBlockDeviceRealize realize;
- XenBlockDeviceUnrealize unrealize;
-};
-
-#define TYPE_XEN_BLOCK_DEVICE "xen-block"
-OBJECT_DECLARE_TYPE(XenBlockDevice, XenBlockDeviceClass, XEN_BLOCK_DEVICE)
-
-struct XenDiskDevice {
- XenBlockDevice blockdev;
-};
-
-#define TYPE_XEN_DISK_DEVICE "xen-disk"
-OBJECT_DECLARE_SIMPLE_TYPE(XenDiskDevice, XEN_DISK_DEVICE)
-
-struct XenCDRomDevice {
- XenBlockDevice blockdev;
-};
-
-#define TYPE_XEN_CDROM_DEVICE "xen-cdrom"
-OBJECT_DECLARE_SIMPLE_TYPE(XenCDRomDevice, XEN_CDROM_DEVICE)
-
-#endif /* HW_XEN_BLOCK_H */
+++ /dev/null
-/*
- * Copyright (c) 2018 Citrix Systems Inc.
- *
- * This work is licensed under the terms of the GNU GPL, version 2 or later.
- * See the COPYING file in the top-level directory.
- */
-
-#ifndef HW_XEN_BUS_HELPER_H
-#define HW_XEN_BUS_HELPER_H
-
-#include "hw/xen/xen_common.h"
-
-const char *xs_strstate(enum xenbus_state state);
-
-void xs_node_create(struct xs_handle *xsh, xs_transaction_t tid,
- const char *node, struct xs_permissions perms[],
- unsigned int nr_perms, Error **errp);
-void xs_node_destroy(struct xs_handle *xsh, xs_transaction_t tid,
- const char *node, Error **errp);
-
-/* Write to node/key unless node is empty, in which case write to key */
-void xs_node_vprintf(struct xs_handle *xsh, xs_transaction_t tid,
- const char *node, const char *key, Error **errp,
- const char *fmt, va_list ap)
- GCC_FMT_ATTR(6, 0);
-void xs_node_printf(struct xs_handle *xsh, xs_transaction_t tid,
- const char *node, const char *key, Error **errp,
- const char *fmt, ...)
- GCC_FMT_ATTR(6, 7);
-
-/* Read from node/key unless node is empty, in which case read from key */
-int xs_node_vscanf(struct xs_handle *xsh, xs_transaction_t tid,
- const char *node, const char *key, Error **errp,
- const char *fmt, va_list ap);
-int xs_node_scanf(struct xs_handle *xsh, xs_transaction_t tid,
- const char *node, const char *key, Error **errp,
- const char *fmt, ...);
-
-/* Watch node/key unless node is empty, in which case watch key */
-void xs_node_watch(struct xs_handle *xsh, const char *node, const char *key,
- char *token, Error **errp);
-void xs_node_unwatch(struct xs_handle *xsh, const char *node, const char *key,
- const char *token, Error **errp);
-
-#endif /* HW_XEN_BUS_HELPER_H */
+++ /dev/null
-/*
- * Copyright (c) 2018 Citrix Systems Inc.
- *
- * This work is licensed under the terms of the GNU GPL, version 2 or later.
- * See the COPYING file in the top-level directory.
- */
-
-#ifndef HW_XEN_BUS_H
-#define HW_XEN_BUS_H
-
-#include "hw/xen/xen_common.h"
-#include "hw/sysbus.h"
-#include "qemu/notify.h"
-#include "qom/object.h"
-
-typedef void (*XenWatchHandler)(void *opaque);
-
-typedef struct XenWatchList XenWatchList;
-typedef struct XenWatch XenWatch;
-typedef struct XenEventChannel XenEventChannel;
-
-struct XenDevice {
- DeviceState qdev;
- domid_t frontend_id;
- char *name;
- struct xs_handle *xsh;
- XenWatchList *watch_list;
- char *backend_path, *frontend_path;
- enum xenbus_state backend_state, frontend_state;
- Notifier exit;
- XenWatch *backend_state_watch, *frontend_state_watch;
- bool backend_online;
- XenWatch *backend_online_watch;
- xengnttab_handle *xgth;
- bool feature_grant_copy;
- bool inactive;
- QLIST_HEAD(, XenEventChannel) event_channels;
- QLIST_ENTRY(XenDevice) list;
-};
-typedef struct XenDevice XenDevice;
-
-typedef char *(*XenDeviceGetName)(XenDevice *xendev, Error **errp);
-typedef void (*XenDeviceRealize)(XenDevice *xendev, Error **errp);
-typedef void (*XenDeviceFrontendChanged)(XenDevice *xendev,
- enum xenbus_state frontend_state,
- Error **errp);
-typedef void (*XenDeviceUnrealize)(XenDevice *xendev);
-
-struct XenDeviceClass {
- /*< private >*/
- DeviceClass parent_class;
- /*< public >*/
- const char *backend;
- const char *device;
- XenDeviceGetName get_name;
- XenDeviceRealize realize;
- XenDeviceFrontendChanged frontend_changed;
- XenDeviceUnrealize unrealize;
-};
-
-#define TYPE_XEN_DEVICE "xen-device"
-OBJECT_DECLARE_TYPE(XenDevice, XenDeviceClass, XEN_DEVICE)
-
-struct XenBus {
- BusState qbus;
- domid_t backend_id;
- struct xs_handle *xsh;
- XenWatchList *watch_list;
- unsigned int backend_types;
- XenWatch **backend_watch;
- QLIST_HEAD(, XenDevice) inactive_devices;
-};
-
-struct XenBusClass {
- /*< private >*/
- BusClass parent_class;
-};
-
-#define TYPE_XEN_BUS "xen-bus"
-OBJECT_DECLARE_TYPE(XenBus, XenBusClass,
- XEN_BUS)
-
-void xen_bus_init(void);
-
-void xen_device_backend_set_state(XenDevice *xendev,
- enum xenbus_state state);
-enum xenbus_state xen_device_backend_get_state(XenDevice *xendev);
-
-void xen_device_backend_printf(XenDevice *xendev, const char *key,
- const char *fmt, ...)
- GCC_FMT_ATTR(3, 4);
-void xen_device_frontend_printf(XenDevice *xendev, const char *key,
- const char *fmt, ...)
- GCC_FMT_ATTR(3, 4);
-
-int xen_device_frontend_scanf(XenDevice *xendev, const char *key,
- const char *fmt, ...);
-
-void xen_device_set_max_grant_refs(XenDevice *xendev, unsigned int nr_refs,
- Error **errp);
-void *xen_device_map_grant_refs(XenDevice *xendev, uint32_t *refs,
- unsigned int nr_refs, int prot,
- Error **errp);
-void xen_device_unmap_grant_refs(XenDevice *xendev, void *map,
- unsigned int nr_refs, Error **errp);
-
-typedef struct XenDeviceGrantCopySegment {
- union {
- void *virt;
- struct {
- uint32_t ref;
- off_t offset;
- } foreign;
- } source, dest;
- size_t len;
-} XenDeviceGrantCopySegment;
-
-void xen_device_copy_grant_refs(XenDevice *xendev, bool to_domain,
- XenDeviceGrantCopySegment segs[],
- unsigned int nr_segs, Error **errp);
-
-typedef bool (*XenEventHandler)(void *opaque);
-
-XenEventChannel *xen_device_bind_event_channel(XenDevice *xendev,
- unsigned int port,
- XenEventHandler handler,
- void *opaque, Error **errp);
-void xen_device_set_event_channel_context(XenDevice *xendev,
- XenEventChannel *channel,
- AioContext *ctx,
- Error **errp);
-void xen_device_notify_event_channel(XenDevice *xendev,
- XenEventChannel *channel,
- Error **errp);
-void xen_device_unbind_event_channel(XenDevice *xendev,
- XenEventChannel *channel,
- Error **errp);
-
-#endif /* HW_XEN_BUS_H */
+++ /dev/null
-#ifndef HW_XEN_LEGACY_BACKEND_H
-#define HW_XEN_LEGACY_BACKEND_H
-
-#include "hw/xen/xen_common.h"
-#include "hw/xen/xen_pvdev.h"
-#include "net/net.h"
-#include "qom/object.h"
-
-#define TYPE_XENSYSDEV "xen-sysdev"
-#define TYPE_XENSYSBUS "xen-sysbus"
-#define TYPE_XENBACKEND "xen-backend"
-
-typedef struct XenLegacyDevice XenLegacyDevice;
-DECLARE_INSTANCE_CHECKER(XenLegacyDevice, XENBACKEND,
- TYPE_XENBACKEND)
-
-/* variables */
-extern struct xs_handle *xenstore;
-extern const char *xen_protocol;
-extern DeviceState *xen_sysdev;
-extern BusState *xen_sysbus;
-
-int xenstore_mkdir(char *path, int p);
-int xenstore_write_be_str(struct XenLegacyDevice *xendev, const char *node,
- const char *val);
-int xenstore_write_be_int(struct XenLegacyDevice *xendev, const char *node,
- int ival);
-int xenstore_write_be_int64(struct XenLegacyDevice *xendev, const char *node,
- int64_t ival);
-char *xenstore_read_be_str(struct XenLegacyDevice *xendev, const char *node);
-int xenstore_read_be_int(struct XenLegacyDevice *xendev, const char *node,
- int *ival);
-void xenstore_update_fe(char *watch, struct XenLegacyDevice *xendev);
-void xenstore_update_be(char *watch, char *type, int dom,
- struct XenDevOps *ops);
-char *xenstore_read_fe_str(struct XenLegacyDevice *xendev, const char *node);
-int xenstore_read_fe_int(struct XenLegacyDevice *xendev, const char *node,
- int *ival);
-int xenstore_read_fe_uint64(struct XenLegacyDevice *xendev, const char *node,
- uint64_t *uval);
-
-void xen_be_check_state(struct XenLegacyDevice *xendev);
-
-/* xen backend driver bits */
-int xen_be_init(void);
-void xen_be_register_common(void);
-int xen_be_register(const char *type, struct XenDevOps *ops);
-int xen_be_set_state(struct XenLegacyDevice *xendev, enum xenbus_state state);
-int xen_be_bind_evtchn(struct XenLegacyDevice *xendev);
-void xen_be_set_max_grant_refs(struct XenLegacyDevice *xendev,
- unsigned int nr_refs);
-void *xen_be_map_grant_refs(struct XenLegacyDevice *xendev, uint32_t *refs,
- unsigned int nr_refs, int prot);
-void xen_be_unmap_grant_refs(struct XenLegacyDevice *xendev, void *ptr,
- unsigned int nr_refs);
-
-typedef struct XenGrantCopySegment {
- union {
- void *virt;
- struct {
- uint32_t ref;
- off_t offset;
- } foreign;
- } source, dest;
- size_t len;
-} XenGrantCopySegment;
-
-int xen_be_copy_grant_refs(struct XenLegacyDevice *xendev,
- bool to_domain, XenGrantCopySegment segs[],
- unsigned int nr_segs);
-
-static inline void *xen_be_map_grant_ref(struct XenLegacyDevice *xendev,
- uint32_t ref, int prot)
-{
- return xen_be_map_grant_refs(xendev, &ref, 1, prot);
-}
-
-static inline void xen_be_unmap_grant_ref(struct XenLegacyDevice *xendev,
- void *ptr)
-{
- return xen_be_unmap_grant_refs(xendev, ptr, 1);
-}
-
-/* actual backend drivers */
-extern struct XenDevOps xen_console_ops; /* xen_console.c */
-extern struct XenDevOps xen_kbdmouse_ops; /* xen_framebuffer.c */
-extern struct XenDevOps xen_framebuffer_ops; /* xen_framebuffer.c */
-extern struct XenDevOps xen_blkdev_ops; /* xen_disk.c */
-#ifdef CONFIG_VIRTFS
-extern struct XenDevOps xen_9pfs_ops; /* xen-9p-backend.c */
-#endif
-extern struct XenDevOps xen_netdev_ops; /* xen_nic.c */
-#ifdef CONFIG_USB_LIBUSB
-extern struct XenDevOps xen_usb_ops; /* xen-usb.c */
-#endif
-
-/* configuration (aka xenbus setup) */
-void xen_config_cleanup(void);
-int xen_config_dev_blk(DriveInfo *disk);
-int xen_config_dev_nic(NICInfo *nic);
-int xen_config_dev_vfb(int vdev, const char *type);
-int xen_config_dev_vkbd(int vdev);
-int xen_config_dev_console(int vdev);
-
-#endif /* HW_XEN_LEGACY_BACKEND_H */
+++ /dev/null
-/*
- * Xen X86-specific
- *
- * Copyright 2020 Red Hat, Inc.
- *
- * SPDX-License-Identifier: GPL-2.0-or-later
- */
-#ifndef QEMU_HW_XEN_X86_H
-#define QEMU_HW_XEN_X86_H
-
-#include "hw/i386/pc.h"
-
-void xen_hvm_init_pc(PCMachineState *pcms, MemoryRegion **ram_memory);
-
-#endif /* QEMU_HW_XEN_X86_H */
+++ /dev/null
-#ifndef QEMU_HW_XEN_H
-#define QEMU_HW_XEN_H
-
-/*
- * public xen header
- * stuff needed outside xen-*.c, i.e. interfaces to qemu.
- * must not depend on any xen headers being present in
- * /usr/include/xen, so it can be included unconditionally.
- */
-
-#include "exec/cpu-common.h"
-
-/* xen-machine.c */
-enum xen_mode {
- XEN_EMULATE = 0, // xen emulation, using xenner (default)
- XEN_ATTACH // attach to xen domain created by libxl
-};
-
-extern uint32_t xen_domid;
-extern enum xen_mode xen_mode;
-extern bool xen_domid_restrict;
-
-int xen_pci_slot_get_pirq(PCIDevice *pci_dev, int irq_num);
-void xen_piix3_set_irq(void *opaque, int irq_num, int level);
-void xen_piix_pci_write_config_client(uint32_t address, uint32_t val, int len);
-void xen_hvm_inject_msi(uint64_t addr, uint32_t data);
-int xen_is_pirq_msi(uint32_t msi_data);
-
-qemu_irq *xen_interrupt_controller_init(void);
-
-void xenstore_store_pv_console_info(int i, Chardev *chr);
-
-void xen_register_framebuffer(struct MemoryRegion *mr);
-
-#endif /* QEMU_HW_XEN_H */
+++ /dev/null
-#ifndef QEMU_HW_XEN_COMMON_H
-#define QEMU_HW_XEN_COMMON_H
-
-/*
- * If we have new enough libxenctrl then we do not want/need these compat
- * interfaces, despite what the user supplied cflags might say. They
- * must be undefined before including xenctrl.h
- */
-#undef XC_WANT_COMPAT_EVTCHN_API
-#undef XC_WANT_COMPAT_GNTTAB_API
-#undef XC_WANT_COMPAT_MAP_FOREIGN_API
-
-#include <xenctrl.h>
-#include <xenstore.h>
-#include "hw/xen/interface/io/xenbus.h"
-
-#include "hw/xen/xen.h"
-#include "hw/pci/pci.h"
-#include "hw/xen/trace.h"
-
-extern xc_interface *xen_xc;
-
-/*
- * We don't support Xen prior to 4.2.0.
- */
-
-/* Xen 4.2 through 4.6 */
-#if CONFIG_XEN_CTRL_INTERFACE_VERSION < 40701
-
-typedef xc_interface xenforeignmemory_handle;
-typedef xc_evtchn xenevtchn_handle;
-typedef xc_gnttab xengnttab_handle;
-typedef evtchn_port_or_error_t xenevtchn_port_or_error_t;
-
-#define xenevtchn_open(l, f) xc_evtchn_open(l, f);
-#define xenevtchn_close(h) xc_evtchn_close(h)
-#define xenevtchn_fd(h) xc_evtchn_fd(h)
-#define xenevtchn_pending(h) xc_evtchn_pending(h)
-#define xenevtchn_notify(h, p) xc_evtchn_notify(h, p)
-#define xenevtchn_bind_interdomain(h, d, p) xc_evtchn_bind_interdomain(h, d, p)
-#define xenevtchn_unmask(h, p) xc_evtchn_unmask(h, p)
-#define xenevtchn_unbind(h, p) xc_evtchn_unbind(h, p)
-
-#define xengnttab_open(l, f) xc_gnttab_open(l, f)
-#define xengnttab_close(h) xc_gnttab_close(h)
-#define xengnttab_set_max_grants(h, n) xc_gnttab_set_max_grants(h, n)
-#define xengnttab_map_grant_ref(h, d, r, p) xc_gnttab_map_grant_ref(h, d, r, p)
-#define xengnttab_unmap(h, a, n) xc_gnttab_munmap(h, a, n)
-#define xengnttab_map_grant_refs(h, c, d, r, p) \
- xc_gnttab_map_grant_refs(h, c, d, r, p)
-#define xengnttab_map_domain_grant_refs(h, c, d, r, p) \
- xc_gnttab_map_domain_grant_refs(h, c, d, r, p)
-
-#define xenforeignmemory_open(l, f) xen_xc
-#define xenforeignmemory_close(h)
-
-static inline void *xenforeignmemory_map(xc_interface *h, uint32_t dom,
- int prot, size_t pages,
- const xen_pfn_t arr[/*pages*/],
- int err[/*pages*/])
-{
- if (err)
- return xc_map_foreign_bulk(h, dom, prot, arr, err, pages);
- else
- return xc_map_foreign_pages(h, dom, prot, arr, pages);
-}
-
-#define xenforeignmemory_unmap(h, p, s) munmap(p, s * XC_PAGE_SIZE)
-
-#else /* CONFIG_XEN_CTRL_INTERFACE_VERSION >= 40701 */
-
-#include <xenevtchn.h>
-#include <xengnttab.h>
-#include <xenforeignmemory.h>
-
-#endif
-
-extern xenforeignmemory_handle *xen_fmem;
-
-#if CONFIG_XEN_CTRL_INTERFACE_VERSION < 40900
-
-typedef xc_interface xendevicemodel_handle;
-
-#else /* CONFIG_XEN_CTRL_INTERFACE_VERSION >= 40900 */
-
-#undef XC_WANT_COMPAT_DEVICEMODEL_API
-#include <xendevicemodel.h>
-
-#endif
-
-#if CONFIG_XEN_CTRL_INTERFACE_VERSION < 41100
-
-static inline int xendevicemodel_relocate_memory(
- xendevicemodel_handle *dmod, domid_t domid, uint32_t size, uint64_t src_gfn,
- uint64_t dst_gfn)
-{
- uint32_t i;
- int rc;
-
- for (i = 0; i < size; i++) {
- unsigned long idx = src_gfn + i;
- xen_pfn_t gpfn = dst_gfn + i;
-
- rc = xc_domain_add_to_physmap(xen_xc, domid, XENMAPSPACE_gmfn, idx,
- gpfn);
- if (rc) {
- return rc;
- }
- }
-
- return 0;
-}
-
-static inline int xendevicemodel_pin_memory_cacheattr(
- xendevicemodel_handle *dmod, domid_t domid, uint64_t start, uint64_t end,
- uint32_t type)
-{
- return xc_domain_pin_memory_cacheattr(xen_xc, domid, start, end, type);
-}
-
-typedef void xenforeignmemory_resource_handle;
-
-#define XENMEM_resource_ioreq_server 0
-
-#define XENMEM_resource_ioreq_server_frame_bufioreq 0
-#define XENMEM_resource_ioreq_server_frame_ioreq(n) (1 + (n))
-
-static inline xenforeignmemory_resource_handle *xenforeignmemory_map_resource(
- xenforeignmemory_handle *fmem, domid_t domid, unsigned int type,
- unsigned int id, unsigned long frame, unsigned long nr_frames,
- void **paddr, int prot, int flags)
-{
- errno = EOPNOTSUPP;
- return NULL;
-}
-
-#endif /* CONFIG_XEN_CTRL_INTERFACE_VERSION < 41100 */
-
-#if CONFIG_XEN_CTRL_INTERFACE_VERSION < 41000
-
-#define XEN_COMPAT_PHYSMAP
-static inline void *xenforeignmemory_map2(xenforeignmemory_handle *h,
- uint32_t dom, void *addr,
- int prot, int flags, size_t pages,
- const xen_pfn_t arr[/*pages*/],
- int err[/*pages*/])
-{
- assert(addr == NULL && flags == 0);
- return xenforeignmemory_map(h, dom, prot, pages, arr, err);
-}
-
-static inline int xentoolcore_restrict_all(domid_t domid)
-{
- errno = ENOTTY;
- return -1;
-}
-
-static inline int xendevicemodel_shutdown(xendevicemodel_handle *dmod,
- domid_t domid, unsigned int reason)
-{
- errno = ENOTTY;
- return -1;
-}
-
-#else /* CONFIG_XEN_CTRL_INTERFACE_VERSION >= 41000 */
-
-#include <xentoolcore.h>
-
-#endif
-
-#if CONFIG_XEN_CTRL_INTERFACE_VERSION < 40900
-
-static inline xendevicemodel_handle *xendevicemodel_open(
- struct xentoollog_logger *logger, unsigned int open_flags)
-{
- return xen_xc;
-}
-
-#if CONFIG_XEN_CTRL_INTERFACE_VERSION >= 40500
-
-static inline int xendevicemodel_create_ioreq_server(
- xendevicemodel_handle *dmod, domid_t domid, int handle_bufioreq,
- ioservid_t *id)
-{
- return xc_hvm_create_ioreq_server(dmod, domid, handle_bufioreq,
- id);
-}
-
-static inline int xendevicemodel_get_ioreq_server_info(
- xendevicemodel_handle *dmod, domid_t domid, ioservid_t id,
- xen_pfn_t *ioreq_pfn, xen_pfn_t *bufioreq_pfn,
- evtchn_port_t *bufioreq_port)
-{
- return xc_hvm_get_ioreq_server_info(dmod, domid, id, ioreq_pfn,
- bufioreq_pfn, bufioreq_port);
-}
-
-static inline int xendevicemodel_map_io_range_to_ioreq_server(
- xendevicemodel_handle *dmod, domid_t domid, ioservid_t id, int is_mmio,
- uint64_t start, uint64_t end)
-{
- return xc_hvm_map_io_range_to_ioreq_server(dmod, domid, id, is_mmio,
- start, end);
-}
-
-static inline int xendevicemodel_unmap_io_range_from_ioreq_server(
- xendevicemodel_handle *dmod, domid_t domid, ioservid_t id, int is_mmio,
- uint64_t start, uint64_t end)
-{
- return xc_hvm_unmap_io_range_from_ioreq_server(dmod, domid, id, is_mmio,
- start, end);
-}
-
-static inline int xendevicemodel_map_pcidev_to_ioreq_server(
- xendevicemodel_handle *dmod, domid_t domid, ioservid_t id,
- uint16_t segment, uint8_t bus, uint8_t device, uint8_t function)
-{
- return xc_hvm_map_pcidev_to_ioreq_server(dmod, domid, id, segment,
- bus, device, function);
-}
-
-static inline int xendevicemodel_unmap_pcidev_from_ioreq_server(
- xendevicemodel_handle *dmod, domid_t domid, ioservid_t id,
- uint16_t segment, uint8_t bus, uint8_t device, uint8_t function)
-{
- return xc_hvm_unmap_pcidev_from_ioreq_server(dmod, domid, id, segment,
- bus, device, function);
-}
-
-static inline int xendevicemodel_destroy_ioreq_server(
- xendevicemodel_handle *dmod, domid_t domid, ioservid_t id)
-{
- return xc_hvm_destroy_ioreq_server(dmod, domid, id);
-}
-
-static inline int xendevicemodel_set_ioreq_server_state(
- xendevicemodel_handle *dmod, domid_t domid, ioservid_t id, int enabled)
-{
- return xc_hvm_set_ioreq_server_state(dmod, domid, id, enabled);
-}
-
-#endif /* CONFIG_XEN_CTRL_INTERFACE_VERSION >= 40500 */
-
-static inline int xendevicemodel_set_pci_intx_level(
- xendevicemodel_handle *dmod, domid_t domid, uint16_t segment,
- uint8_t bus, uint8_t device, uint8_t intx, unsigned int level)
-{
- return xc_hvm_set_pci_intx_level(dmod, domid, segment, bus, device,
- intx, level);
-}
-
-static inline int xendevicemodel_set_isa_irq_level(
- xendevicemodel_handle *dmod, domid_t domid, uint8_t irq,
- unsigned int level)
-{
- return xc_hvm_set_isa_irq_level(dmod, domid, irq, level);
-}
-
-static inline int xendevicemodel_set_pci_link_route(
- xendevicemodel_handle *dmod, domid_t domid, uint8_t link, uint8_t irq)
-{
- return xc_hvm_set_pci_link_route(dmod, domid, link, irq);
-}
-
-static inline int xendevicemodel_inject_msi(
- xendevicemodel_handle *dmod, domid_t domid, uint64_t msi_addr,
- uint32_t msi_data)
-{
- return xc_hvm_inject_msi(dmod, domid, msi_addr, msi_data);
-}
-
-static inline int xendevicemodel_track_dirty_vram(
- xendevicemodel_handle *dmod, domid_t domid, uint64_t first_pfn,
- uint32_t nr, unsigned long *dirty_bitmap)
-{
- return xc_hvm_track_dirty_vram(dmod, domid, first_pfn, nr,
- dirty_bitmap);
-}
-
-static inline int xendevicemodel_modified_memory(
- xendevicemodel_handle *dmod, domid_t domid, uint64_t first_pfn,
- uint32_t nr)
-{
- return xc_hvm_modified_memory(dmod, domid, first_pfn, nr);
-}
-
-static inline int xendevicemodel_set_mem_type(
- xendevicemodel_handle *dmod, domid_t domid, hvmmem_type_t mem_type,
- uint64_t first_pfn, uint32_t nr)
-{
- return xc_hvm_set_mem_type(dmod, domid, mem_type, first_pfn, nr);
-}
-
-#endif
-
-extern xendevicemodel_handle *xen_dmod;
-
-static inline int xen_set_mem_type(domid_t domid, hvmmem_type_t type,
- uint64_t first_pfn, uint32_t nr)
-{
- return xendevicemodel_set_mem_type(xen_dmod, domid, type, first_pfn,
- nr);
-}
-
-static inline int xen_set_pci_intx_level(domid_t domid, uint16_t segment,
- uint8_t bus, uint8_t device,
- uint8_t intx, unsigned int level)
-{
- return xendevicemodel_set_pci_intx_level(xen_dmod, domid, segment, bus,
- device, intx, level);
-}
-
-static inline int xen_set_pci_link_route(domid_t domid, uint8_t link,
- uint8_t irq)
-{
- return xendevicemodel_set_pci_link_route(xen_dmod, domid, link, irq);
-}
-
-static inline int xen_inject_msi(domid_t domid, uint64_t msi_addr,
- uint32_t msi_data)
-{
- return xendevicemodel_inject_msi(xen_dmod, domid, msi_addr, msi_data);
-}
-
-static inline int xen_set_isa_irq_level(domid_t domid, uint8_t irq,
- unsigned int level)
-{
- return xendevicemodel_set_isa_irq_level(xen_dmod, domid, irq, level);
-}
-
-static inline int xen_track_dirty_vram(domid_t domid, uint64_t first_pfn,
- uint32_t nr, unsigned long *bitmap)
-{
- return xendevicemodel_track_dirty_vram(xen_dmod, domid, first_pfn, nr,
- bitmap);
-}
-
-static inline int xen_modified_memory(domid_t domid, uint64_t first_pfn,
- uint32_t nr)
-{
- return xendevicemodel_modified_memory(xen_dmod, domid, first_pfn, nr);
-}
-
-static inline int xen_restrict(domid_t domid)
-{
- int rc;
- rc = xentoolcore_restrict_all(domid);
- trace_xen_domid_restrict(rc ? errno : 0);
- return rc;
-}
-
-void destroy_hvm_domain(bool reboot);
-
-/* shutdown/destroy current domain because of an error */
-void xen_shutdown_fatal_error(const char *fmt, ...) GCC_FMT_ATTR(1, 2);
-
-#ifdef HVM_PARAM_VMPORT_REGS_PFN
-static inline int xen_get_vmport_regs_pfn(xc_interface *xc, domid_t dom,
- xen_pfn_t *vmport_regs_pfn)
-{
- int rc;
- uint64_t value;
- rc = xc_hvm_param_get(xc, dom, HVM_PARAM_VMPORT_REGS_PFN, &value);
- if (rc >= 0) {
- *vmport_regs_pfn = (xen_pfn_t) value;
- }
- return rc;
-}
-#else
-static inline int xen_get_vmport_regs_pfn(xc_interface *xc, domid_t dom,
- xen_pfn_t *vmport_regs_pfn)
-{
- return -ENOSYS;
-}
-#endif
-
-/* Xen before 4.6 */
-#if CONFIG_XEN_CTRL_INTERFACE_VERSION < 40600
-
-#ifndef HVM_IOREQSRV_BUFIOREQ_ATOMIC
-#define HVM_IOREQSRV_BUFIOREQ_ATOMIC 2
-#endif
-
-#endif
-
-static inline int xen_get_default_ioreq_server_info(domid_t dom,
- xen_pfn_t *ioreq_pfn,
- xen_pfn_t *bufioreq_pfn,
- evtchn_port_t
- *bufioreq_evtchn)
-{
- unsigned long param;
- int rc;
-
- rc = xc_get_hvm_param(xen_xc, dom, HVM_PARAM_IOREQ_PFN, ¶m);
- if (rc < 0) {
- fprintf(stderr, "failed to get HVM_PARAM_IOREQ_PFN\n");
- return -1;
- }
-
- *ioreq_pfn = param;
-
- rc = xc_get_hvm_param(xen_xc, dom, HVM_PARAM_BUFIOREQ_PFN, ¶m);
- if (rc < 0) {
- fprintf(stderr, "failed to get HVM_PARAM_BUFIOREQ_PFN\n");
- return -1;
- }
-
- *bufioreq_pfn = param;
-
- rc = xc_get_hvm_param(xen_xc, dom, HVM_PARAM_BUFIOREQ_EVTCHN,
- ¶m);
- if (rc < 0) {
- fprintf(stderr, "failed to get HVM_PARAM_BUFIOREQ_EVTCHN\n");
- return -1;
- }
-
- *bufioreq_evtchn = param;
-
- return 0;
-}
-
-/* Xen before 4.5 */
-#if CONFIG_XEN_CTRL_INTERFACE_VERSION < 40500
-
-#ifndef HVM_PARAM_BUFIOREQ_EVTCHN
-#define HVM_PARAM_BUFIOREQ_EVTCHN 26
-#endif
-
-#define IOREQ_TYPE_PCI_CONFIG 2
-
-typedef uint16_t ioservid_t;
-
-static inline void xen_map_memory_section(domid_t dom,
- ioservid_t ioservid,
- MemoryRegionSection *section)
-{
-}
-
-static inline void xen_unmap_memory_section(domid_t dom,
- ioservid_t ioservid,
- MemoryRegionSection *section)
-{
-}
-
-static inline void xen_map_io_section(domid_t dom,
- ioservid_t ioservid,
- MemoryRegionSection *section)
-{
-}
-
-static inline void xen_unmap_io_section(domid_t dom,
- ioservid_t ioservid,
- MemoryRegionSection *section)
-{
-}
-
-static inline void xen_map_pcidev(domid_t dom,
- ioservid_t ioservid,
- PCIDevice *pci_dev)
-{
-}
-
-static inline void xen_unmap_pcidev(domid_t dom,
- ioservid_t ioservid,
- PCIDevice *pci_dev)
-{
-}
-
-static inline void xen_create_ioreq_server(domid_t dom,
- ioservid_t *ioservid)
-{
-}
-
-static inline void xen_destroy_ioreq_server(domid_t dom,
- ioservid_t ioservid)
-{
-}
-
-static inline int xen_get_ioreq_server_info(domid_t dom,
- ioservid_t ioservid,
- xen_pfn_t *ioreq_pfn,
- xen_pfn_t *bufioreq_pfn,
- evtchn_port_t *bufioreq_evtchn)
-{
- return xen_get_default_ioreq_server_info(dom, ioreq_pfn,
- bufioreq_pfn,
- bufioreq_evtchn);
-}
-
-static inline int xen_set_ioreq_server_state(domid_t dom,
- ioservid_t ioservid,
- bool enable)
-{
- return 0;
-}
-
-/* Xen 4.5 */
-#else
-
-static bool use_default_ioreq_server;
-
-static inline void xen_map_memory_section(domid_t dom,
- ioservid_t ioservid,
- MemoryRegionSection *section)
-{
- hwaddr start_addr = section->offset_within_address_space;
- ram_addr_t size = int128_get64(section->size);
- hwaddr end_addr = start_addr + size - 1;
-
- if (use_default_ioreq_server) {
- return;
- }
-
- trace_xen_map_mmio_range(ioservid, start_addr, end_addr);
- xendevicemodel_map_io_range_to_ioreq_server(xen_dmod, dom, ioservid, 1,
- start_addr, end_addr);
-}
-
-static inline void xen_unmap_memory_section(domid_t dom,
- ioservid_t ioservid,
- MemoryRegionSection *section)
-{
- hwaddr start_addr = section->offset_within_address_space;
- ram_addr_t size = int128_get64(section->size);
- hwaddr end_addr = start_addr + size - 1;
-
- if (use_default_ioreq_server) {
- return;
- }
-
- trace_xen_unmap_mmio_range(ioservid, start_addr, end_addr);
- xendevicemodel_unmap_io_range_from_ioreq_server(xen_dmod, dom, ioservid,
- 1, start_addr, end_addr);
-}
-
-static inline void xen_map_io_section(domid_t dom,
- ioservid_t ioservid,
- MemoryRegionSection *section)
-{
- hwaddr start_addr = section->offset_within_address_space;
- ram_addr_t size = int128_get64(section->size);
- hwaddr end_addr = start_addr + size - 1;
-
- if (use_default_ioreq_server) {
- return;
- }
-
- trace_xen_map_portio_range(ioservid, start_addr, end_addr);
- xendevicemodel_map_io_range_to_ioreq_server(xen_dmod, dom, ioservid, 0,
- start_addr, end_addr);
-}
-
-static inline void xen_unmap_io_section(domid_t dom,
- ioservid_t ioservid,
- MemoryRegionSection *section)
-{
- hwaddr start_addr = section->offset_within_address_space;
- ram_addr_t size = int128_get64(section->size);
- hwaddr end_addr = start_addr + size - 1;
-
- if (use_default_ioreq_server) {
- return;
- }
-
- trace_xen_unmap_portio_range(ioservid, start_addr, end_addr);
- xendevicemodel_unmap_io_range_from_ioreq_server(xen_dmod, dom, ioservid,
- 0, start_addr, end_addr);
-}
-
-static inline void xen_map_pcidev(domid_t dom,
- ioservid_t ioservid,
- PCIDevice *pci_dev)
-{
- if (use_default_ioreq_server) {
- return;
- }
-
- trace_xen_map_pcidev(ioservid, pci_dev_bus_num(pci_dev),
- PCI_SLOT(pci_dev->devfn), PCI_FUNC(pci_dev->devfn));
- xendevicemodel_map_pcidev_to_ioreq_server(xen_dmod, dom, ioservid, 0,
- pci_dev_bus_num(pci_dev),
- PCI_SLOT(pci_dev->devfn),
- PCI_FUNC(pci_dev->devfn));
-}
-
-static inline void xen_unmap_pcidev(domid_t dom,
- ioservid_t ioservid,
- PCIDevice *pci_dev)
-{
- if (use_default_ioreq_server) {
- return;
- }
-
- trace_xen_unmap_pcidev(ioservid, pci_dev_bus_num(pci_dev),
- PCI_SLOT(pci_dev->devfn), PCI_FUNC(pci_dev->devfn));
- xendevicemodel_unmap_pcidev_from_ioreq_server(xen_dmod, dom, ioservid, 0,
- pci_dev_bus_num(pci_dev),
- PCI_SLOT(pci_dev->devfn),
- PCI_FUNC(pci_dev->devfn));
-}
-
-static inline void xen_create_ioreq_server(domid_t dom,
- ioservid_t *ioservid)
-{
- int rc = xendevicemodel_create_ioreq_server(xen_dmod, dom,
- HVM_IOREQSRV_BUFIOREQ_ATOMIC,
- ioservid);
-
- if (rc == 0) {
- trace_xen_ioreq_server_create(*ioservid);
- return;
- }
-
- *ioservid = 0;
- use_default_ioreq_server = true;
- trace_xen_default_ioreq_server();
-}
-
-static inline void xen_destroy_ioreq_server(domid_t dom,
- ioservid_t ioservid)
-{
- if (use_default_ioreq_server) {
- return;
- }
-
- trace_xen_ioreq_server_destroy(ioservid);
- xendevicemodel_destroy_ioreq_server(xen_dmod, dom, ioservid);
-}
-
-static inline int xen_get_ioreq_server_info(domid_t dom,
- ioservid_t ioservid,
- xen_pfn_t *ioreq_pfn,
- xen_pfn_t *bufioreq_pfn,
- evtchn_port_t *bufioreq_evtchn)
-{
- if (use_default_ioreq_server) {
- return xen_get_default_ioreq_server_info(dom, ioreq_pfn,
- bufioreq_pfn,
- bufioreq_evtchn);
- }
-
- return xendevicemodel_get_ioreq_server_info(xen_dmod, dom, ioservid,
- ioreq_pfn, bufioreq_pfn,
- bufioreq_evtchn);
-}
-
-static inline int xen_set_ioreq_server_state(domid_t dom,
- ioservid_t ioservid,
- bool enable)
-{
- if (use_default_ioreq_server) {
- return 0;
- }
-
- trace_xen_ioreq_server_state(ioservid, enable);
- return xendevicemodel_set_ioreq_server_state(xen_dmod, dom, ioservid,
- enable);
-}
-
-#endif
-
-/* Xen before 4.8 */
-
-#if CONFIG_XEN_CTRL_INTERFACE_VERSION < 40800
-
-struct xengnttab_grant_copy_segment {
- union xengnttab_copy_ptr {
- void *virt;
- struct {
- uint32_t ref;
- uint16_t offset;
- uint16_t domid;
- } foreign;
- } source, dest;
- uint16_t len;
- uint16_t flags;
- int16_t status;
-};
-
-typedef struct xengnttab_grant_copy_segment xengnttab_grant_copy_segment_t;
-
-static inline int xengnttab_grant_copy(xengnttab_handle *xgt, uint32_t count,
- xengnttab_grant_copy_segment_t *segs)
-{
- return -ENOSYS;
-}
-#endif
-
-#endif /* QEMU_HW_XEN_COMMON_H */
+++ /dev/null
-#ifndef QEMU_HW_XEN_PVDEV_H
-#define QEMU_HW_XEN_PVDEV_H
-
-#include "hw/xen/xen_common.h"
-/* ------------------------------------------------------------- */
-
-#define XEN_BUFSIZE 1024
-
-struct XenLegacyDevice;
-
-/* driver uses grant tables -> open gntdev device (xendev->gnttabdev) */
-#define DEVOPS_FLAG_NEED_GNTDEV 1
-/* don't expect frontend doing correct state transitions (aka console quirk) */
-#define DEVOPS_FLAG_IGNORE_STATE 2
-
-struct XenDevOps {
- size_t size;
- uint32_t flags;
- void (*alloc)(struct XenLegacyDevice *xendev);
- int (*init)(struct XenLegacyDevice *xendev);
- int (*initialise)(struct XenLegacyDevice *xendev);
- void (*connected)(struct XenLegacyDevice *xendev);
- void (*event)(struct XenLegacyDevice *xendev);
- void (*disconnect)(struct XenLegacyDevice *xendev);
- int (*free)(struct XenLegacyDevice *xendev);
- void (*backend_changed)(struct XenLegacyDevice *xendev,
- const char *node);
- void (*frontend_changed)(struct XenLegacyDevice *xendev,
- const char *node);
- int (*backend_register)(void);
-};
-
-struct XenLegacyDevice {
- DeviceState qdev;
- const char *type;
- int dom;
- int dev;
- char name[64];
- int debug;
-
- enum xenbus_state be_state;
- enum xenbus_state fe_state;
- int online;
- char be[XEN_BUFSIZE];
- char *fe;
- char *protocol;
- int remote_port;
- int local_port;
-
- xenevtchn_handle *evtchndev;
- xengnttab_handle *gnttabdev;
-
- struct XenDevOps *ops;
- QTAILQ_ENTRY(XenLegacyDevice) next;
-};
-
-/* ------------------------------------------------------------- */
-
-/* xenstore helper functions */
-int xenstore_write_str(const char *base, const char *node, const char *val);
-int xenstore_write_int(const char *base, const char *node, int ival);
-int xenstore_write_int64(const char *base, const char *node, int64_t ival);
-char *xenstore_read_str(const char *base, const char *node);
-int xenstore_read_int(const char *base, const char *node, int *ival);
-int xenstore_read_uint64(const char *base, const char *node, uint64_t *uval);
-void xenstore_update(void *unused);
-
-const char *xenbus_strstate(enum xenbus_state state);
-
-void xen_pv_evtchn_event(void *opaque);
-void xen_pv_insert_xendev(struct XenLegacyDevice *xendev);
-void xen_pv_del_xendev(struct XenLegacyDevice *xendev);
-struct XenLegacyDevice *xen_pv_find_xendev(const char *type, int dom, int dev);
-
-void xen_pv_unbind_evtchn(struct XenLegacyDevice *xendev);
-int xen_pv_send_notify(struct XenLegacyDevice *xendev);
-
-void xen_pv_printf(struct XenLegacyDevice *xendev, int msg_level,
- const char *fmt, ...) GCC_FMT_ATTR(3, 4);
-
-#endif /* QEMU_HW_XEN_PVDEV_H */
+++ /dev/null
-/*
- * Copyright (c) 2013 - 2019, Max Filippov, Open Source and Linux Lab.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of the Open Source and Linux Lab nor the
- * names of its contributors may be used to endorse or promote products
- * derived from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-
-#ifndef XTENSA_MX_PIC_H
-#define XTENSA_MX_PIC_H
-
-#include "exec/memory.h"
-
-struct XtensaMxPic;
-typedef struct XtensaMxPic XtensaMxPic;
-
-XtensaMxPic *xtensa_mx_pic_init(unsigned n_extint);
-void xtensa_mx_pic_reset(void *opaque);
-MemoryRegion *xtensa_mx_pic_register_cpu(XtensaMxPic *mx,
- qemu_irq *irq,
- qemu_irq runstall);
-qemu_irq *xtensa_mx_pic_get_extints(XtensaMxPic *mx);
-
-#endif
+++ /dev/null
-/* Interface definition for configurable Xtensa ISA support.
- *
- * Copyright (c) 2001-2013 Tensilica Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining
- * a copy of this software and associated documentation files (the
- * "Software"), to deal in the Software without restriction, including
- * without limitation the rights to use, copy, modify, merge, publish,
- * distribute, sublicense, and/or sell copies of the Software, and to
- * permit persons to whom the Software is furnished to do so, subject to
- * the following conditions:
- *
- * The above copyright notice and this permission notice shall be included
- * in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
- * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
- * CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
- * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
- * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- */
-
-#ifndef HW_XTENSA_XTENSA_ISA_H
-#define HW_XTENSA_XTENSA_ISA_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/*
- * Version number: This is intended to help support code that works with
- * versions of this library from multiple Xtensa releases.
- */
-
-#define XTENSA_ISA_VERSION 7000
-
-/*
- * This file defines the interface to the Xtensa ISA library. This
- * library contains most of the ISA-specific information for a
- * particular Xtensa processor. For example, the set of valid
- * instructions, their opcode encodings and operand fields are all
- * included here.
- *
- * This interface basically defines a number of abstract data types.
- *
- * . an instruction buffer - for holding the raw instruction bits
- * . ISA info - information about the ISA as a whole
- * . instruction formats - instruction size and slot structure
- * . opcodes - information about individual instructions
- * . operands - information about register and immediate instruction operands
- * . stateOperands - information about processor state instruction operands
- * . interfaceOperands - information about interface instruction operands
- * . register files - register file information
- * . processor states - internal processor state information
- * . system registers - "special registers" and "user registers"
- * . interfaces - TIE interfaces that are external to the processor
- * . functional units - TIE shared functions
- *
- * The interface defines a set of functions to access each data type.
- * With the exception of the instruction buffer, the internal
- * representations of the data structures are hidden. All accesses must
- * be made through the functions defined here.
- */
-
-typedef struct xtensa_isa_opaque { int unused; } *xtensa_isa;
-
-
-/*
- * Most of the Xtensa ISA entities (e.g., opcodes, regfiles, etc.) are
- * represented here using sequential integers beginning with 0. The
- * specific values are only fixed for a particular instantiation of an
- * xtensa_isa structure, so these values should only be used
- * internally.
- */
-
-typedef int xtensa_opcode;
-typedef int xtensa_format;
-typedef int xtensa_regfile;
-typedef int xtensa_state;
-typedef int xtensa_sysreg;
-typedef int xtensa_interface;
-typedef int xtensa_funcUnit;
-
-
-/* Define a unique value for undefined items. */
-
-#define XTENSA_UNDEFINED -1
-
-
-/*
- * Overview of using this interface to decode/encode instructions:
- *
- * Each Xtensa instruction is associated with a particular instruction
- * format, where the format defines a fixed number of slots for
- * operations. The formats for the core Xtensa ISA have only one slot,
- * but FLIX instructions may have multiple slots. Within each slot,
- * there is a single opcode and some number of associated operands.
- *
- * The encoding and decoding functions operate on instruction buffers,
- * not on the raw bytes of the instructions. The same instruction
- * buffer data structure is used for both entire instructions and
- * individual slots in those instructions -- the contents of a slot need
- * to be extracted from or inserted into the buffer for the instruction
- * as a whole.
- *
- * Decoding an instruction involves first finding the format, which
- * identifies the number of slots, and then decoding each slot
- * separately. A slot is decoded by finding the opcode and then using
- * the opcode to determine how many operands there are. For example:
- *
- * xtensa_insnbuf_from_chars
- * xtensa_format_decode
- * for each slot {
- * xtensa_format_get_slot
- * xtensa_opcode_decode
- * for each operand {
- * xtensa_operand_get_field
- * xtensa_operand_decode
- * }
- * }
- *
- * Encoding an instruction is roughly the same procedure in reverse:
- *
- * xtensa_format_encode
- * for each slot {
- * xtensa_opcode_encode
- * for each operand {
- * xtensa_operand_encode
- * xtensa_operand_set_field
- * }
- * xtensa_format_set_slot
- * }
- * xtensa_insnbuf_to_chars
- */
-
-
-/* Error handling. */
-
-/*
- * Error codes. The code for the most recent error condition can be
- * retrieved with the "errno" function. For any result other than
- * xtensa_isa_ok, an error message containing additional information
- * about the problem can be retrieved using the "error_msg" function.
- * The error messages are stored in an internal buffer, which should
- * not be freed and may be overwritten by subsequent operations.
- */
-
-typedef enum xtensa_isa_status_enum {
- xtensa_isa_ok = 0,
- xtensa_isa_bad_format,
- xtensa_isa_bad_slot,
- xtensa_isa_bad_opcode,
- xtensa_isa_bad_operand,
- xtensa_isa_bad_field,
- xtensa_isa_bad_iclass,
- xtensa_isa_bad_regfile,
- xtensa_isa_bad_sysreg,
- xtensa_isa_bad_state,
- xtensa_isa_bad_interface,
- xtensa_isa_bad_funcUnit,
- xtensa_isa_wrong_slot,
- xtensa_isa_no_field,
- xtensa_isa_out_of_memory,
- xtensa_isa_buffer_overflow,
- xtensa_isa_internal_error,
- xtensa_isa_bad_value
-} xtensa_isa_status;
-
-xtensa_isa_status xtensa_isa_errno(xtensa_isa isa);
-
-char *xtensa_isa_error_msg(xtensa_isa isa);
-
-
-
-/* Instruction buffers. */
-
-typedef uint32_t xtensa_insnbuf_word;
-typedef xtensa_insnbuf_word *xtensa_insnbuf;
-
-
-/* Get the size in "insnbuf_words" of the xtensa_insnbuf array. */
-
-int xtensa_insnbuf_size(xtensa_isa isa);
-
-
-/* Allocate an xtensa_insnbuf of the right size. */
-
-xtensa_insnbuf xtensa_insnbuf_alloc(xtensa_isa isa);
-
-
-/* Release an xtensa_insnbuf. */
-
-void xtensa_insnbuf_free(xtensa_isa isa, xtensa_insnbuf buf);
-
-
-/*
- * Conversion between raw memory (char arrays) and our internal
- * instruction representation. This is complicated by the Xtensa ISA's
- * variable instruction lengths. When converting to chars, the buffer
- * must contain a valid instruction so we know how many bytes to copy;
- * thus, the "to_chars" function returns the number of bytes copied or
- * XTENSA_UNDEFINED on error. The "from_chars" function first reads the
- * minimal number of bytes required to decode the instruction length and
- * then proceeds to copy the entire instruction into the buffer; if the
- * memory does not contain a valid instruction, it copies the maximum
- * number of bytes required for the longest Xtensa instruction. The
- * "num_chars" argument may be used to limit the number of bytes that
- * can be read or written. Otherwise, if "num_chars" is zero, the
- * functions may read or write past the end of the code.
- */
-
-int xtensa_insnbuf_to_chars(xtensa_isa isa, const xtensa_insnbuf insn,
- unsigned char *cp, int num_chars);
-
-void xtensa_insnbuf_from_chars(xtensa_isa isa, xtensa_insnbuf insn,
- const unsigned char *cp, int num_chars);
-
-
-
-/* ISA information. */
-
-/* Initialize the ISA information. */
-
-xtensa_isa xtensa_isa_init(void *xtensa_modules, xtensa_isa_status *errno_p,
- char **error_msg_p);
-
-
-/* Deallocate an xtensa_isa structure. */
-
-void xtensa_isa_free(xtensa_isa isa);
-
-
-/* Get the maximum instruction size in bytes. */
-
-int xtensa_isa_maxlength(xtensa_isa isa);
-
-
-/*
- * Decode the length in bytes of an instruction in raw memory (not an
- * insnbuf). This function reads only the minimal number of bytes
- * required to decode the instruction length. Returns
- * XTENSA_UNDEFINED on error.
- */
-
-int xtensa_isa_length_from_chars(xtensa_isa isa, const unsigned char *cp);
-
-
-/*
- * Get the number of stages in the processor's pipeline. The pipeline
- * stage values returned by other functions in this library will range
- * from 0 to N-1, where N is the value returned by this function.
- * Note that the stage numbers used here may not correspond to the
- * actual processor hardware, e.g., the hardware may have additional
- * stages before stage 0. Returns XTENSA_UNDEFINED on error.
- */
-
-int xtensa_isa_num_pipe_stages(xtensa_isa isa);
-
-
-/* Get the number of various entities that are defined for this processor. */
-
-int xtensa_isa_num_formats(xtensa_isa isa);
-
-int xtensa_isa_num_opcodes(xtensa_isa isa);
-
-int xtensa_isa_num_regfiles(xtensa_isa isa);
-
-int xtensa_isa_num_states(xtensa_isa isa);
-
-int xtensa_isa_num_sysregs(xtensa_isa isa);
-
-int xtensa_isa_num_interfaces(xtensa_isa isa);
-
-int xtensa_isa_num_funcUnits(xtensa_isa isa);
-
-
-
-/* Instruction formats. */
-
-/* Get the name of a format. Returns null on error. */
-
-const char *xtensa_format_name(xtensa_isa isa, xtensa_format fmt);
-
-
-/*
- * Given a format name, return the format number. Returns
- * XTENSA_UNDEFINED if the name is not a valid format.
- */
-
-xtensa_format xtensa_format_lookup(xtensa_isa isa, const char *fmtname);
-
-
-/*
- * Decode the instruction format from a binary instruction buffer.
- * Returns XTENSA_UNDEFINED if the format is not recognized.
- */
-
-xtensa_format xtensa_format_decode(xtensa_isa isa, const xtensa_insnbuf insn);
-
-
-/*
- * Set the instruction format field(s) in a binary instruction buffer.
- * All the other fields are set to zero. Returns non-zero on error.
- */
-
-int xtensa_format_encode(xtensa_isa isa, xtensa_format fmt,
- xtensa_insnbuf insn);
-
-
-/*
- * Find the length (in bytes) of an instruction. Returns
- * XTENSA_UNDEFINED on error.
- */
-
-int xtensa_format_length(xtensa_isa isa, xtensa_format fmt);
-
-
-/*
- * Get the number of slots in an instruction. Returns XTENSA_UNDEFINED
- * on error.
- */
-
-int xtensa_format_num_slots(xtensa_isa isa, xtensa_format fmt);
-
-
-/*
- * Get the opcode for a no-op in a particular slot.
- * Returns XTENSA_UNDEFINED on error.
- */
-
-xtensa_opcode xtensa_format_slot_nop_opcode(xtensa_isa isa, xtensa_format fmt,
- int slot);
-
-
-/*
- * Get the bits for a specified slot out of an insnbuf for the
- * instruction as a whole and put them into an insnbuf for that one
- * slot, and do the opposite to set a slot. Return non-zero on error.
- */
-
-int xtensa_format_get_slot(xtensa_isa isa, xtensa_format fmt, int slot,
- const xtensa_insnbuf insn, xtensa_insnbuf slotbuf);
-
-int xtensa_format_set_slot(xtensa_isa isa, xtensa_format fmt, int slot,
- xtensa_insnbuf insn, const xtensa_insnbuf slotbuf);
-
-
-
-/* Opcode information. */
-
-/*
- * Translate a mnemonic name to an opcode. Returns XTENSA_UNDEFINED if
- * the name is not a valid opcode mnemonic.
- */
-
-xtensa_opcode xtensa_opcode_lookup(xtensa_isa isa, const char *opname);
-
-
-/*
- * Decode the opcode for one instruction slot from a binary instruction
- * buffer. Returns the opcode or XTENSA_UNDEFINED if the opcode is
- * illegal.
- */
-
-xtensa_opcode xtensa_opcode_decode(xtensa_isa isa, xtensa_format fmt, int slot,
- const xtensa_insnbuf slotbuf);
-
-
-/*
- * Set the opcode field(s) for an instruction slot. All other fields
- * in the slot are set to zero. Returns non-zero if the opcode cannot
- * be encoded.
- */
-
-int xtensa_opcode_encode(xtensa_isa isa, xtensa_format fmt, int slot,
- xtensa_insnbuf slotbuf, xtensa_opcode opc);
-
-
-/* Get the mnemonic name for an opcode. Returns null on error. */
-
-const char *xtensa_opcode_name(xtensa_isa isa, xtensa_opcode opc);
-
-
-/* Check various properties of opcodes. These functions return 0 if
- * the condition is false, 1 if the condition is true, and
- * XTENSA_UNDEFINED on error. The instructions are classified as
- * follows:
- *
- * branch: conditional branch; may fall through to next instruction (B*)
- * jump: unconditional branch (J, JX, RET*, RF*)
- * loop: zero-overhead loop (LOOP*)
- * call: unconditional call; control returns to next instruction (CALL*)
- *
- * For the opcodes that affect control flow in some way, the branch
- * target may be specified by an immediate operand or it may be an
- * address stored in a register. You can distinguish these by
- * checking if the instruction has a PC-relative immediate
- * operand.
- */
-
-int xtensa_opcode_is_branch(xtensa_isa isa, xtensa_opcode opc);
-
-int xtensa_opcode_is_jump(xtensa_isa isa, xtensa_opcode opc);
-
-int xtensa_opcode_is_loop(xtensa_isa isa, xtensa_opcode opc);
-
-int xtensa_opcode_is_call(xtensa_isa isa, xtensa_opcode opc);
-
-
-/*
- * Find the number of ordinary operands, state operands, and interface
- * operands for an instruction. These return XTENSA_UNDEFINED on
- * error.
- */
-
-int xtensa_opcode_num_operands(xtensa_isa isa, xtensa_opcode opc);
-
-int xtensa_opcode_num_stateOperands(xtensa_isa isa, xtensa_opcode opc);
-
-int xtensa_opcode_num_interfaceOperands(xtensa_isa isa, xtensa_opcode opc);
-
-
-/*
- * Get functional unit usage requirements for an opcode. Each "use"
- * is identified by a <functional unit, pipeline stage> pair. The
- * "num_funcUnit_uses" function returns the number of these "uses" or
- * XTENSA_UNDEFINED on error. The "funcUnit_use" function returns
- * a pointer to a "use" pair or null on error.
- */
-
-typedef struct xtensa_funcUnit_use_struct {
- xtensa_funcUnit unit;
- int stage;
-} xtensa_funcUnit_use;
-
-int xtensa_opcode_num_funcUnit_uses(xtensa_isa isa, xtensa_opcode opc);
-
-xtensa_funcUnit_use *xtensa_opcode_funcUnit_use(xtensa_isa isa,
- xtensa_opcode opc, int u);
-
-
-
-/* Operand information. */
-
-/* Get the name of an operand. Returns null on error. */
-
-const char *xtensa_operand_name(xtensa_isa isa, xtensa_opcode opc, int opnd);
-
-
-/*
- * Some operands are "invisible", i.e., not explicitly specified in
- * assembly language. When assembling an instruction, you need not set
- * the values of invisible operands, since they are either hardwired or
- * derived from other field values. The values of invisible operands
- * can be examined in the same way as other operands, but remember that
- * an invisible operand may get its value from another visible one, so
- * the entire instruction must be available before examining the
- * invisible operand values. This function returns 1 if an operand is
- * visible, 0 if it is invisible, or XTENSA_UNDEFINED on error. Note
- * that whether an operand is visible is orthogonal to whether it is
- * "implicit", i.e., whether it is encoded in a field in the
- * instruction.
- */
-
-int xtensa_operand_is_visible(xtensa_isa isa, xtensa_opcode opc, int opnd);
-
-
-/*
- * Check if an operand is an input ('i'), output ('o'), or inout ('m')
- * operand. Note: The output operand of a conditional assignment
- * (e.g., movnez) appears here as an inout ('m') even if it is declared
- * in the TIE code as an output ('o'); this allows the compiler to
- * properly handle register allocation for conditional assignments.
- * Returns 0 on error.
- */
-
-char xtensa_operand_inout(xtensa_isa isa, xtensa_opcode opc, int opnd);
-
-
-/*
- * Get and set the raw (encoded) value of the field for the specified
- * operand. The "set" function does not check if the value fits in the
- * field; that is done by the "encode" function below. Both of these
- * functions return non-zero on error, e.g., if the field is not defined
- * for the specified slot.
- */
-
-int xtensa_operand_get_field(xtensa_isa isa, xtensa_opcode opc, int opnd,
- xtensa_format fmt, int slot,
- const xtensa_insnbuf slotbuf, uint32_t *valp);
-
-int xtensa_operand_set_field(xtensa_isa isa, xtensa_opcode opc, int opnd,
- xtensa_format fmt, int slot,
- xtensa_insnbuf slotbuf, uint32_t val);
-
-
-/*
- * Encode and decode operands. The raw bits in the operand field may
- * be encoded in a variety of different ways. These functions hide
- * the details of that encoding. The result values are returned through
- * the argument pointer. The return value is non-zero on error.
- */
-
-int xtensa_operand_encode(xtensa_isa isa, xtensa_opcode opc, int opnd,
- uint32_t *valp);
-
-int xtensa_operand_decode(xtensa_isa isa, xtensa_opcode opc, int opnd,
- uint32_t *valp);
-
-
-/*
- * An operand may be either a register operand or an immediate of some
- * sort (e.g., PC-relative or not). The "is_register" function returns
- * 0 if the operand is an immediate, 1 if it is a register, and
- * XTENSA_UNDEFINED on error. The "regfile" function returns the
- * regfile for a register operand, or XTENSA_UNDEFINED on error.
- */
-
-int xtensa_operand_is_register(xtensa_isa isa, xtensa_opcode opc, int opnd);
-
-xtensa_regfile xtensa_operand_regfile(xtensa_isa isa, xtensa_opcode opc,
- int opnd);
-
-
-/*
- * Register operands may span multiple consecutive registers, e.g., a
- * 64-bit data type may occupy two 32-bit registers. Only the first
- * register is encoded in the operand field. This function specifies
- * the number of consecutive registers occupied by this operand. For
- * non-register operands, the return value is undefined. Returns
- * XTENSA_UNDEFINED on error.
- */
-
-int xtensa_operand_num_regs(xtensa_isa isa, xtensa_opcode opc, int opnd);
-
-
-/*
- * Some register operands do not completely identify the register being
- * accessed. For example, the operand value may be added to an internal
- * state value. By definition, this implies that the corresponding
- * regfile is not allocatable. Unknown registers should generally be
- * treated with worst-case assumptions. The function returns 0 if the
- * register value is unknown, 1 if known, and XTENSA_UNDEFINED on
- * error.
- */
-
-int xtensa_operand_is_known_reg(xtensa_isa isa, xtensa_opcode opc, int opnd);
-
-
-/*
- * Check if an immediate operand is PC-relative. Returns 0 for register
- * operands and non-PC-relative immediates, 1 for PC-relative
- * immediates, and XTENSA_UNDEFINED on error.
- */
-
-int xtensa_operand_is_PCrelative(xtensa_isa isa, xtensa_opcode opc, int opnd);
-
-
-/*
- * For PC-relative offset operands, the interpretation of the offset may
- * vary between opcodes, e.g., is it relative to the current PC or that
- * of the next instruction? The following functions are defined to
- * perform PC-relative relocations and to undo them (as in the
- * disassembler). The "do_reloc" function takes the desired address
- * value and the PC of the current instruction and sets the value to the
- * corresponding PC-relative offset (which can then be encoded and
- * stored into the operand field). The "undo_reloc" function takes the
- * unencoded offset value and the current PC and sets the value to the
- * appropriate address. The return values are non-zero on error. Note
- * that these functions do not replace the encode/decode functions; the
- * operands must be encoded/decoded separately and the encode functions
- * are responsible for detecting invalid operand values.
- */
-
-int xtensa_operand_do_reloc(xtensa_isa isa, xtensa_opcode opc, int opnd,
- uint32_t *valp, uint32_t pc);
-
-int xtensa_operand_undo_reloc(xtensa_isa isa, xtensa_opcode opc, int opnd,
- uint32_t *valp, uint32_t pc);
-
-
-
-/* State Operands. */
-
-/*
- * Get the state accessed by a state operand. Returns XTENSA_UNDEFINED
- * on error.
- */
-
-xtensa_state xtensa_stateOperand_state(xtensa_isa isa, xtensa_opcode opc,
- int stOp);
-
-
-/*
- * Check if a state operand is an input ('i'), output ('o'), or inout
- * ('m') operand. Returns 0 on error.
- */
-
-char xtensa_stateOperand_inout(xtensa_isa isa, xtensa_opcode opc, int stOp);
-
-
-
-/* Interface Operands. */
-
-/*
- * Get the external interface accessed by an interface operand.
- * Returns XTENSA_UNDEFINED on error.
- */
-
-xtensa_interface xtensa_interfaceOperand_interface(xtensa_isa isa,
- xtensa_opcode opc,
- int ifOp);
-
-
-
-/* Register Files. */
-
-/*
- * Regfiles include both "real" regfiles and "views", where a view
- * allows a group of adjacent registers in a real "parent" regfile to be
- * viewed as a single register. A regfile view has all the same
- * properties as its parent except for its (long) name, bit width, number
- * of entries, and default ctype. You can use the parent function to
- * distinguish these two classes.
- */
-
-/*
- * Look up a regfile by either its name or its abbreviated "short name".
- * Returns XTENSA_UNDEFINED on error. The "lookup_shortname" function
- * ignores "view" regfiles since they always have the same shortname as
- * their parents.
- */
-
-xtensa_regfile xtensa_regfile_lookup(xtensa_isa isa, const char *name);
-
-xtensa_regfile xtensa_regfile_lookup_shortname(xtensa_isa isa,
- const char *shortname);
-
-
-/*
- * Get the name or abbreviated "short name" of a regfile.
- * Returns null on error.
- */
-
-const char *xtensa_regfile_name(xtensa_isa isa, xtensa_regfile rf);
-
-const char *xtensa_regfile_shortname(xtensa_isa isa, xtensa_regfile rf);
-
-
-/*
- * Get the parent regfile of a "view" regfile. If the regfile is not a
- * view, the result is the same as the input parameter. Returns
- * XTENSA_UNDEFINED on error.
- */
-
-xtensa_regfile xtensa_regfile_view_parent(xtensa_isa isa, xtensa_regfile rf);
-
-
-/*
- * Get the bit width of a regfile or regfile view.
- * Returns XTENSA_UNDEFINED on error.
- */
-
-int xtensa_regfile_num_bits(xtensa_isa isa, xtensa_regfile rf);
-
-
-/*
- * Get the number of regfile entries. Returns XTENSA_UNDEFINED on
- * error.
- */
-
-int xtensa_regfile_num_entries(xtensa_isa isa, xtensa_regfile rf);
-
-
-
-/* Processor States. */
-
-/* Look up a state by name. Returns XTENSA_UNDEFINED on error. */
-
-xtensa_state xtensa_state_lookup(xtensa_isa isa, const char *name);
-
-
-/* Get the name for a processor state. Returns null on error. */
-
-const char *xtensa_state_name(xtensa_isa isa, xtensa_state st);
-
-
-/*
- * Get the bit width for a processor state.
- * Returns XTENSA_UNDEFINED on error.
- */
-
-int xtensa_state_num_bits(xtensa_isa isa, xtensa_state st);
-
-
-/*
- * Check if a state is exported from the processor core. Returns 0 if
- * the condition is false, 1 if the condition is true, and
- * XTENSA_UNDEFINED on error.
- */
-
-int xtensa_state_is_exported(xtensa_isa isa, xtensa_state st);
-
-
-/*
- * Check for a "shared_or" state. Returns 0 if the condition is false,
- * 1 if the condition is true, and XTENSA_UNDEFINED on error.
- */
-
-int xtensa_state_is_shared_or(xtensa_isa isa, xtensa_state st);
-
-
-
-/* Sysregs ("special registers" and "user registers"). */
-
-/*
- * Look up a register by its number and whether it is a "user register"
- * or a "special register". Returns XTENSA_UNDEFINED if the sysreg does
- * not exist.
- */
-
-xtensa_sysreg xtensa_sysreg_lookup(xtensa_isa isa, int num, int is_user);
-
-
-/*
- * Check if there exists a sysreg with a given name.
- * If not, this function returns XTENSA_UNDEFINED.
- */
-
-xtensa_sysreg xtensa_sysreg_lookup_name(xtensa_isa isa, const char *name);
-
-
-/* Get the name of a sysreg. Returns null on error. */
-
-const char *xtensa_sysreg_name(xtensa_isa isa, xtensa_sysreg sysreg);
-
-
-/* Get the register number. Returns XTENSA_UNDEFINED on error. */
-
-int xtensa_sysreg_number(xtensa_isa isa, xtensa_sysreg sysreg);
-
-
-/*
- * Check if a sysreg is a "special register" or a "user register".
- * Returns 0 for special registers, 1 for user registers and
- * XTENSA_UNDEFINED on error.
- */
-
-int xtensa_sysreg_is_user(xtensa_isa isa, xtensa_sysreg sysreg);
-
-
-
-/* Interfaces. */
-
-/*
- * Find an interface by name. The return value is XTENSA_UNDEFINED if
- * the specified interface is not found.
- */
-
-xtensa_interface xtensa_interface_lookup(xtensa_isa isa, const char *ifname);
-
-
-/* Get the name of an interface. Returns null on error. */
-
-const char *xtensa_interface_name(xtensa_isa isa, xtensa_interface intf);
-
-
-/*
- * Get the bit width for an interface.
- * Returns XTENSA_UNDEFINED on error.
- */
-
-int xtensa_interface_num_bits(xtensa_isa isa, xtensa_interface intf);
-
-
-/*
- * Check if an interface is an input ('i') or output ('o') with respect
- * to the Xtensa processor core. Returns 0 on error.
- */
-
-char xtensa_interface_inout(xtensa_isa isa, xtensa_interface intf);
-
-
-/*
- * Check if accessing an interface has potential side effects.
- * Currently "data" interfaces have side effects and "control"
- * interfaces do not. Returns 1 if there are side effects, 0 if not,
- * and XTENSA_UNDEFINED on error.
- */
-
-int xtensa_interface_has_side_effect(xtensa_isa isa, xtensa_interface intf);
-
-
-/*
- * Some interfaces may be related such that accessing one interface
- * has side effects on a set of related interfaces. The interfaces
- * are partitioned into equivalence classes of related interfaces, and
- * each class is assigned a unique identifier number. This function
- * returns the class identifier for an interface, or XTENSA_UNDEFINED
- * on error. These identifiers can be compared to determine if two
- * interfaces are related; the specific values of the identifiers have
- * no particular meaning otherwise.
- */
-
-int xtensa_interface_class_id(xtensa_isa isa, xtensa_interface intf);
-
-
-/* Functional Units. */
-
-/*
- * Find a functional unit by name. The return value is XTENSA_UNDEFINED if
- * the specified unit is not found.
- */
-
-xtensa_funcUnit xtensa_funcUnit_lookup(xtensa_isa isa, const char *fname);
-
-
-/* Get the name of a functional unit. Returns null on error. */
-
-const char *xtensa_funcUnit_name(xtensa_isa isa, xtensa_funcUnit fun);
-
-
-/*
- * Functional units may be replicated. See how many instances of a
- * particular function unit exist. Returns XTENSA_UNDEFINED on error.
- */
-
-int xtensa_funcUnit_num_copies(xtensa_isa isa, xtensa_funcUnit fun);
-
-
-#ifdef __cplusplus
-}
-#endif
-#endif /* HW_XTENSA_XTENSA_ISA_H */
+++ /dev/null
-/* Configure decNumber for either host or target.
- Copyright (C) 2008 Free Software Foundation, Inc.
-
- This file is part of GCC.
-
- GCC is free software; you can redistribute it and/or modify it under
- the terms of the GNU General Public License as published by the Free
- Software Foundation; either version 2, or (at your option) any later
- version.
-
- In addition to the permissions in the GNU General Public License,
- the Free Software Foundation gives you unlimited permission to link
- the compiled version of this file into combinations with other
- programs, and to distribute those combinations without any
- restriction coming from the use of this file. (The General Public
- License restrictions do apply in other respects; for example, they
- cover modification of the file, and distribution when not linked
- into a combine executable.)
-
- GCC is distributed in the hope that it will be useful, but WITHOUT ANY
- WARRANTY; without even the implied warranty of MERCHANTABILITY or
- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
- for more details.
-
- You should have received a copy of the GNU General Public License
- along with GCC; see the file COPYING. If not, write to the Free
- Software Foundation, 51 Franklin Street, Fifth Floor, Boston, MA
- 02110-1301, USA. */
-
-
-#if defined(HOST_WORDS_BIGENDIAN)
-#define WORDS_BIGENDIAN 1
-#else
-#define WORDS_BIGENDIAN 0
-#endif
-
-#ifndef DECDPUN
-#define DECDPUN 3
-#endif
+++ /dev/null
-/* Decimal context header module for the decNumber C Library.
- Copyright (C) 2005, 2007 Free Software Foundation, Inc.
- Contributed by IBM Corporation. Author Mike Cowlishaw.
-
- This file is part of GCC.
-
- GCC is free software; you can redistribute it and/or modify it under
- the terms of the GNU General Public License as published by the Free
- Software Foundation; either version 2, or (at your option) any later
- version.
-
- In addition to the permissions in the GNU General Public License,
- the Free Software Foundation gives you unlimited permission to link
- the compiled version of this file into combinations with other
- programs, and to distribute those combinations without any
- restriction coming from the use of this file. (The General Public
- License restrictions do apply in other respects; for example, they
- cover modification of the file, and distribution when not linked
- into a combine executable.)
-
- GCC is distributed in the hope that it will be useful, but WITHOUT ANY
- WARRANTY; without even the implied warranty of MERCHANTABILITY or
- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
- for more details.
-
- You should have received a copy of the GNU General Public License
- along with GCC; see the file COPYING. If not, write to the Free
- Software Foundation, 51 Franklin Street, Fifth Floor, Boston, MA
- 02110-1301, USA. */
-
-/* ------------------------------------------------------------------ */
-/* Decimal Context module header */
-/* ------------------------------------------------------------------ */
-/* */
-/* Context variables must always have valid values: */
-/* */
-/* status -- [any bits may be cleared, but not set, by user] */
-/* round -- must be one of the enumerated rounding modes */
-/* */
-/* The following variables are implied for fixed size formats (i.e., */
-/* they are ignored) but should still be set correctly in case used */
-/* with decNumber functions: */
-/* */
-/* clamp -- must be either 0 or 1 */
-/* digits -- must be in the range 1 through 999999999 */
-/* emax -- must be in the range 0 through 999999999 */
-/* emin -- must be in the range 0 through -999999999 */
-/* extended -- must be either 0 or 1 [present only if DECSUBSET] */
-/* traps -- only defined bits may be set */
-/* */
-/* ------------------------------------------------------------------ */
-
-#ifndef DECCONTEXT_H
-#define DECCONTEXT_H
-
- #define DECCNAME "decContext" /* Short name */
- #define DECCFULLNAME "Decimal Context Descriptor" /* Verbose name */
- #define DECCAUTHOR "Mike Cowlishaw" /* Who to blame */
-
-
- /* Extended flags setting -- set this to 0 to use only IEEE flags */
- #define DECEXTFLAG 1 /* 1=enable extended flags */
-
- /* Conditional code flag -- set this to 0 for best performance */
- #define DECSUBSET 0 /* 1=enable subset arithmetic */
-
- /* Context for operations, with associated constants */
- enum rounding {
- DEC_ROUND_CEILING, /* round towards +infinity */
- DEC_ROUND_UP, /* round away from 0 */
- DEC_ROUND_HALF_UP, /* 0.5 rounds up */
- DEC_ROUND_HALF_EVEN, /* 0.5 rounds to nearest even */
- DEC_ROUND_HALF_DOWN, /* 0.5 rounds down */
- DEC_ROUND_DOWN, /* round towards 0 (truncate) */
- DEC_ROUND_FLOOR, /* round towards -infinity */
- DEC_ROUND_05UP, /* round for reround */
- DEC_ROUND_MAX /* enum must be less than this */
- };
- #define DEC_ROUND_DEFAULT DEC_ROUND_HALF_EVEN;
-
- typedef struct {
- int32_t digits; /* working precision */
- int32_t emax; /* maximum positive exponent */
- int32_t emin; /* minimum negative exponent */
- enum rounding round; /* rounding mode */
- uint32_t traps; /* trap-enabler flags */
- uint32_t status; /* status flags */
- uint8_t clamp; /* flag: apply IEEE exponent clamp */
- #if DECSUBSET
- uint8_t extended; /* flag: special-values allowed */
- #endif
- } decContext;
-
- /* Maxima and Minima for context settings */
- #define DEC_MAX_DIGITS 999999999
- #define DEC_MIN_DIGITS 1
- #define DEC_MAX_EMAX 999999999
- #define DEC_MIN_EMAX 0
- #define DEC_MAX_EMIN 0
- #define DEC_MIN_EMIN -999999999
- #define DEC_MAX_MATH 999999 /* max emax, etc., for math funcs. */
-
- /* Classifications for decimal numbers, aligned with 754r (note */
- /* that 'normal' and 'subnormal' are meaningful only with a */
- /* decContext or a fixed size format). */
- enum decClass {
- DEC_CLASS_SNAN,
- DEC_CLASS_QNAN,
- DEC_CLASS_NEG_INF,
- DEC_CLASS_NEG_NORMAL,
- DEC_CLASS_NEG_SUBNORMAL,
- DEC_CLASS_NEG_ZERO,
- DEC_CLASS_POS_ZERO,
- DEC_CLASS_POS_SUBNORMAL,
- DEC_CLASS_POS_NORMAL,
- DEC_CLASS_POS_INF
- };
- /* Strings for the decClasses */
- #define DEC_ClassString_SN "sNaN"
- #define DEC_ClassString_QN "NaN"
- #define DEC_ClassString_NI "-Infinity"
- #define DEC_ClassString_NN "-Normal"
- #define DEC_ClassString_NS "-Subnormal"
- #define DEC_ClassString_NZ "-Zero"
- #define DEC_ClassString_PZ "+Zero"
- #define DEC_ClassString_PS "+Subnormal"
- #define DEC_ClassString_PN "+Normal"
- #define DEC_ClassString_PI "+Infinity"
- #define DEC_ClassString_UN "Invalid"
-
- /* Trap-enabler and Status flags (exceptional conditions), and */
- /* their names. The top byte is reserved for internal use */
- #if DECEXTFLAG
- /* Extended flags */
- #define DEC_Conversion_syntax 0x00000001
- #define DEC_Division_by_zero 0x00000002
- #define DEC_Division_impossible 0x00000004
- #define DEC_Division_undefined 0x00000008
- #define DEC_Insufficient_storage 0x00000010 /* [when malloc fails] */
- #define DEC_Inexact 0x00000020
- #define DEC_Invalid_context 0x00000040
- #define DEC_Invalid_operation 0x00000080
- #if DECSUBSET
- #define DEC_Lost_digits 0x00000100
- #endif
- #define DEC_Overflow 0x00000200
- #define DEC_Clamped 0x00000400
- #define DEC_Rounded 0x00000800
- #define DEC_Subnormal 0x00001000
- #define DEC_Underflow 0x00002000
- #else
- /* IEEE flags only */
- #define DEC_Conversion_syntax 0x00000010
- #define DEC_Division_by_zero 0x00000002
- #define DEC_Division_impossible 0x00000010
- #define DEC_Division_undefined 0x00000010
- #define DEC_Insufficient_storage 0x00000010 /* [when malloc fails] */
- #define DEC_Inexact 0x00000001
- #define DEC_Invalid_context 0x00000010
- #define DEC_Invalid_operation 0x00000010
- #if DECSUBSET
- #define DEC_Lost_digits 0x00000000
- #endif
- #define DEC_Overflow 0x00000008
- #define DEC_Clamped 0x00000000
- #define DEC_Rounded 0x00000000
- #define DEC_Subnormal 0x00000000
- #define DEC_Underflow 0x00000004
- #endif
-
- /* IEEE 854 groupings for the flags */
- /* [DEC_Clamped, DEC_Lost_digits, DEC_Rounded, and DEC_Subnormal */
- /* are not in IEEE 854] */
- #define DEC_IEEE_854_Division_by_zero (DEC_Division_by_zero)
- #if DECSUBSET
- #define DEC_IEEE_854_Inexact (DEC_Inexact | DEC_Lost_digits)
- #else
- #define DEC_IEEE_854_Inexact (DEC_Inexact)
- #endif
- #define DEC_IEEE_854_Invalid_operation (DEC_Conversion_syntax | \
- DEC_Division_impossible | \
- DEC_Division_undefined | \
- DEC_Insufficient_storage | \
- DEC_Invalid_context | \
- DEC_Invalid_operation)
- #define DEC_IEEE_854_Overflow (DEC_Overflow)
- #define DEC_IEEE_854_Underflow (DEC_Underflow)
-
- /* flags which are normally errors (result is qNaN, infinite, or 0) */
- #define DEC_Errors (DEC_IEEE_854_Division_by_zero | \
- DEC_IEEE_854_Invalid_operation | \
- DEC_IEEE_854_Overflow | DEC_IEEE_854_Underflow)
- /* flags which cause a result to become qNaN */
- #define DEC_NaNs DEC_IEEE_854_Invalid_operation
-
- /* flags which are normally for information only (finite results) */
- #if DECSUBSET
- #define DEC_Information (DEC_Clamped | DEC_Rounded | DEC_Inexact \
- | DEC_Lost_digits)
- #else
- #define DEC_Information (DEC_Clamped | DEC_Rounded | DEC_Inexact)
- #endif
-
- /* Name strings for the exceptional conditions */
- #define DEC_Condition_CS "Conversion syntax"
- #define DEC_Condition_DZ "Division by zero"
- #define DEC_Condition_DI "Division impossible"
- #define DEC_Condition_DU "Division undefined"
- #define DEC_Condition_IE "Inexact"
- #define DEC_Condition_IS "Insufficient storage"
- #define DEC_Condition_IC "Invalid context"
- #define DEC_Condition_IO "Invalid operation"
- #if DECSUBSET
- #define DEC_Condition_LD "Lost digits"
- #endif
- #define DEC_Condition_OV "Overflow"
- #define DEC_Condition_PA "Clamped"
- #define DEC_Condition_RO "Rounded"
- #define DEC_Condition_SU "Subnormal"
- #define DEC_Condition_UN "Underflow"
- #define DEC_Condition_ZE "No status"
- #define DEC_Condition_MU "Multiple status"
- #define DEC_Condition_Length 21 /* length of the longest string, */
- /* including terminator */
-
- /* Initialization descriptors, used by decContextDefault */
- #define DEC_INIT_BASE 0
- #define DEC_INIT_DECIMAL32 32
- #define DEC_INIT_DECIMAL64 64
- #define DEC_INIT_DECIMAL128 128
- /* Synonyms */
- #define DEC_INIT_DECSINGLE DEC_INIT_DECIMAL32
- #define DEC_INIT_DECDOUBLE DEC_INIT_DECIMAL64
- #define DEC_INIT_DECQUAD DEC_INIT_DECIMAL128
-
- /* decContext routines */
-
-
- extern decContext * decContextClearStatus(decContext *, uint32_t);
- extern decContext * decContextDefault(decContext *, int32_t);
- extern enum rounding decContextGetRounding(decContext *);
- extern uint32_t decContextGetStatus(decContext *);
- extern decContext * decContextRestoreStatus(decContext *, uint32_t, uint32_t);
- extern uint32_t decContextSaveStatus(decContext *, uint32_t);
- extern decContext * decContextSetRounding(decContext *, enum rounding);
- extern decContext * decContextSetStatus(decContext *, uint32_t);
- extern decContext * decContextSetStatusFromString(decContext *, const char *);
- extern decContext * decContextSetStatusFromStringQuiet(decContext *, const char *);
- extern decContext * decContextSetStatusQuiet(decContext *, uint32_t);
- extern const char * decContextStatusToString(const decContext *);
- extern uint32_t decContextTestSavedStatus(uint32_t, uint32_t);
- extern uint32_t decContextTestStatus(decContext *, uint32_t);
- extern decContext * decContextZeroStatus(decContext *);
-
-#endif
+++ /dev/null
-/* Conversion lookup tables for the decNumber C Library.
- Copyright (C) 2007 Free Software Foundation, Inc.
- Contributed by IBM Corporation. Author Mike Cowlishaw.
-
- This file is part of GCC.
-
- GCC is free software; you can redistribute it and/or modify it under
- the terms of the GNU General Public License as published by the Free
- Software Foundation; either version 2, or (at your option) any later
- version.
-
- In addition to the permissions in the GNU General Public License,
- the Free Software Foundation gives you unlimited permission to link
- the compiled version of this file into combinations with other
- programs, and to distribute those combinations without any
- restriction coming from the use of this file. (The General Public
- License restrictions do apply in other respects; for example, they
- cover modification of the file, and distribution when not linked
- into a combine executable.)
-
- GCC is distributed in the hope that it will be useful, but WITHOUT ANY
- WARRANTY; without even the implied warranty of MERCHANTABILITY or
- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
- for more details.
-
- You should have received a copy of the GNU General Public License
- along with GCC; see the file COPYING. If not, write to the Free
- Software Foundation, 51 Franklin Street, Fifth Floor, Boston, MA
- 02110-1301, USA. */
-
-/* ------------------------------------------------------------------------ */
-/* Binary Coded Decimal and Densely Packed Decimal conversion lookup tables */
-/* [Automatically generated -- do not edit. 2007.05.05] */
-/* ------------------------------------------------------------------------ */
-/* ------------------------------------------------------------------------ */
-/* For details, see: http://www2.hursley.ibm.com/decimal/DPDecimal.html */
-
-
-/* This include file defines several DPD and BCD conversion tables: */
-/* */
-/* uint16_t BCD2DPD[2458]; -- BCD -> DPD (0x999 => 2457) */
-/* uint16_t BIN2DPD[1000]; -- Bin -> DPD (999 => 2457) */
-/* uint8_t BIN2CHAR[4001]; -- Bin -> CHAR (999 => '\3' '9' '9' '9') */
-/* uint8_t BIN2BCD8[4000]; -- Bin -> bytes (999 => 9 9 9 3) */
-/* uint16_t DPD2BCD[1024]; -- DPD -> BCD (0x3FF => 0x999) */
-/* uint16_t DPD2BIN[1024]; -- DPD -> BIN (0x3FF => 999) */
-/* uint32_t DPD2BINK[1024]; -- DPD -> BIN * 1000 (0x3FF => 999000) */
-/* uint32_t DPD2BINM[1024]; -- DPD -> BIN * 1E+6 (0x3FF => 999000000) */
-/* uint8_t DPD2BCD8[4096]; -- DPD -> bytes (x3FF => 9 9 9 3) */
-/* */
-/* In all cases the result (10 bits or 12 bits, or binary) is right-aligned */
-/* in the table entry. BIN2CHAR entries are a single byte length (0 for */
-/* value 0) followed by three digit characters; a trailing terminator is */
-/* included to allow 4-char moves always. BIN2BCD8 and DPD2BCD8 entries */
-/* are similar with the three BCD8 digits followed by a one-byte length */
-/* (again, length=0 for value 0). */
-/* */
-/* To use a table, its name, prefixed with DEC_, must be defined with a */
-/* value of 1 before this header file is included. For example: */
-/* #define DEC_BCD2DPD 1 */
-/* This mechanism allows software to only include tables that are needed. */
-/* ------------------------------------------------------------------------ */
-
-#if defined(DEC_BCD2DPD) && DEC_BCD2DPD==1 && !defined(DECBCD2DPD)
-#define DECBCD2DPD
-
-const uint16_t BCD2DPD[2458]={ 0, 1, 2, 3, 4, 5, 6, 7,
- 8, 9, 0, 0, 0, 0, 0, 0, 16, 17, 18, 19, 20,
- 21, 22, 23, 24, 25, 0, 0, 0, 0, 0, 0, 32, 33,
- 34, 35, 36, 37, 38, 39, 40, 41, 0, 0, 0, 0, 0,
- 0, 48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 0, 0,
- 0, 0, 0, 0, 64, 65, 66, 67, 68, 69, 70, 71, 72,
- 73, 0, 0, 0, 0, 0, 0, 80, 81, 82, 83, 84, 85,
- 86, 87, 88, 89, 0, 0, 0, 0, 0, 0, 96, 97, 98,
- 99, 100, 101, 102, 103, 104, 105, 0, 0, 0, 0, 0, 0,
- 112, 113, 114, 115, 116, 117, 118, 119, 120, 121, 0, 0, 0,
- 0, 0, 0, 10, 11, 42, 43, 74, 75, 106, 107, 78, 79,
- 0, 0, 0, 0, 0, 0, 26, 27, 58, 59, 90, 91, 122,
- 123, 94, 95, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 128, 129, 130, 131, 132, 133, 134, 135, 136, 137, 0, 0,
- 0, 0, 0, 0, 144, 145, 146, 147, 148, 149, 150, 151, 152,
- 153, 0, 0, 0, 0, 0, 0, 160, 161, 162, 163, 164, 165,
- 166, 167, 168, 169, 0, 0, 0, 0, 0, 0, 176, 177, 178,
- 179, 180, 181, 182, 183, 184, 185, 0, 0, 0, 0, 0, 0,
- 192, 193, 194, 195, 196, 197, 198, 199, 200, 201, 0, 0, 0,
- 0, 0, 0, 208, 209, 210, 211, 212, 213, 214, 215, 216, 217,
- 0, 0, 0, 0, 0, 0, 224, 225, 226, 227, 228, 229, 230,
- 231, 232, 233, 0, 0, 0, 0, 0, 0, 240, 241, 242, 243,
- 244, 245, 246, 247, 248, 249, 0, 0, 0, 0, 0, 0, 138,
- 139, 170, 171, 202, 203, 234, 235, 206, 207, 0, 0, 0, 0,
- 0, 0, 154, 155, 186, 187, 218, 219, 250, 251, 222, 223, 0,
- 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 256, 257, 258,
- 259, 260, 261, 262, 263, 264, 265, 0, 0, 0, 0, 0, 0,
- 272, 273, 274, 275, 276, 277, 278, 279, 280, 281, 0, 0, 0,
- 0, 0, 0, 288, 289, 290, 291, 292, 293, 294, 295, 296, 297,
- 0, 0, 0, 0, 0, 0, 304, 305, 306, 307, 308, 309, 310,
- 311, 312, 313, 0, 0, 0, 0, 0, 0, 320, 321, 322, 323,
- 324, 325, 326, 327, 328, 329, 0, 0, 0, 0, 0, 0, 336,
- 337, 338, 339, 340, 341, 342, 343, 344, 345, 0, 0, 0, 0,
- 0, 0, 352, 353, 354, 355, 356, 357, 358, 359, 360, 361, 0,
- 0, 0, 0, 0, 0, 368, 369, 370, 371, 372, 373, 374, 375,
- 376, 377, 0, 0, 0, 0, 0, 0, 266, 267, 298, 299, 330,
- 331, 362, 363, 334, 335, 0, 0, 0, 0, 0, 0, 282, 283,
- 314, 315, 346, 347, 378, 379, 350, 351, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 384, 385, 386, 387, 388, 389, 390,
- 391, 392, 393, 0, 0, 0, 0, 0, 0, 400, 401, 402, 403,
- 404, 405, 406, 407, 408, 409, 0, 0, 0, 0, 0, 0, 416,
- 417, 418, 419, 420, 421, 422, 423, 424, 425, 0, 0, 0, 0,
- 0, 0, 432, 433, 434, 435, 436, 437, 438, 439, 440, 441, 0,
- 0, 0, 0, 0, 0, 448, 449, 450, 451, 452, 453, 454, 455,
- 456, 457, 0, 0, 0, 0, 0, 0, 464, 465, 466, 467, 468,
- 469, 470, 471, 472, 473, 0, 0, 0, 0, 0, 0, 480, 481,
- 482, 483, 484, 485, 486, 487, 488, 489, 0, 0, 0, 0, 0,
- 0, 496, 497, 498, 499, 500, 501, 502, 503, 504, 505, 0, 0,
- 0, 0, 0, 0, 394, 395, 426, 427, 458, 459, 490, 491, 462,
- 463, 0, 0, 0, 0, 0, 0, 410, 411, 442, 443, 474, 475,
- 506, 507, 478, 479, 0, 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 512, 513, 514, 515, 516, 517, 518, 519, 520, 521, 0,
- 0, 0, 0, 0, 0, 528, 529, 530, 531, 532, 533, 534, 535,
- 536, 537, 0, 0, 0, 0, 0, 0, 544, 545, 546, 547, 548,
- 549, 550, 551, 552, 553, 0, 0, 0, 0, 0, 0, 560, 561,
- 562, 563, 564, 565, 566, 567, 568, 569, 0, 0, 0, 0, 0,
- 0, 576, 577, 578, 579, 580, 581, 582, 583, 584, 585, 0, 0,
- 0, 0, 0, 0, 592, 593, 594, 595, 596, 597, 598, 599, 600,
- 601, 0, 0, 0, 0, 0, 0, 608, 609, 610, 611, 612, 613,
- 614, 615, 616, 617, 0, 0, 0, 0, 0, 0, 624, 625, 626,
- 627, 628, 629, 630, 631, 632, 633, 0, 0, 0, 0, 0, 0,
- 522, 523, 554, 555, 586, 587, 618, 619, 590, 591, 0, 0, 0,
- 0, 0, 0, 538, 539, 570, 571, 602, 603, 634, 635, 606, 607,
- 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 640, 641,
- 642, 643, 644, 645, 646, 647, 648, 649, 0, 0, 0, 0, 0,
- 0, 656, 657, 658, 659, 660, 661, 662, 663, 664, 665, 0, 0,
- 0, 0, 0, 0, 672, 673, 674, 675, 676, 677, 678, 679, 680,
- 681, 0, 0, 0, 0, 0, 0, 688, 689, 690, 691, 692, 693,
- 694, 695, 696, 697, 0, 0, 0, 0, 0, 0, 704, 705, 706,
- 707, 708, 709, 710, 711, 712, 713, 0, 0, 0, 0, 0, 0,
- 720, 721, 722, 723, 724, 725, 726, 727, 728, 729, 0, 0, 0,
- 0, 0, 0, 736, 737, 738, 739, 740, 741, 742, 743, 744, 745,
- 0, 0, 0, 0, 0, 0, 752, 753, 754, 755, 756, 757, 758,
- 759, 760, 761, 0, 0, 0, 0, 0, 0, 650, 651, 682, 683,
- 714, 715, 746, 747, 718, 719, 0, 0, 0, 0, 0, 0, 666,
- 667, 698, 699, 730, 731, 762, 763, 734, 735, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 768, 769, 770, 771, 772, 773,
- 774, 775, 776, 777, 0, 0, 0, 0, 0, 0, 784, 785, 786,
- 787, 788, 789, 790, 791, 792, 793, 0, 0, 0, 0, 0, 0,
- 800, 801, 802, 803, 804, 805, 806, 807, 808, 809, 0, 0, 0,
- 0, 0, 0, 816, 817, 818, 819, 820, 821, 822, 823, 824, 825,
- 0, 0, 0, 0, 0, 0, 832, 833, 834, 835, 836, 837, 838,
- 839, 840, 841, 0, 0, 0, 0, 0, 0, 848, 849, 850, 851,
- 852, 853, 854, 855, 856, 857, 0, 0, 0, 0, 0, 0, 864,
- 865, 866, 867, 868, 869, 870, 871, 872, 873, 0, 0, 0, 0,
- 0, 0, 880, 881, 882, 883, 884, 885, 886, 887, 888, 889, 0,
- 0, 0, 0, 0, 0, 778, 779, 810, 811, 842, 843, 874, 875,
- 846, 847, 0, 0, 0, 0, 0, 0, 794, 795, 826, 827, 858,
- 859, 890, 891, 862, 863, 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 896, 897, 898, 899, 900, 901, 902, 903, 904, 905,
- 0, 0, 0, 0, 0, 0, 912, 913, 914, 915, 916, 917, 918,
- 919, 920, 921, 0, 0, 0, 0, 0, 0, 928, 929, 930, 931,
- 932, 933, 934, 935, 936, 937, 0, 0, 0, 0, 0, 0, 944,
- 945, 946, 947, 948, 949, 950, 951, 952, 953, 0, 0, 0, 0,
- 0, 0, 960, 961, 962, 963, 964, 965, 966, 967, 968, 969, 0,
- 0, 0, 0, 0, 0, 976, 977, 978, 979, 980, 981, 982, 983,
- 984, 985, 0, 0, 0, 0, 0, 0, 992, 993, 994, 995, 996,
- 997, 998, 999, 1000, 1001, 0, 0, 0, 0, 0, 0, 1008, 1009,
- 1010, 1011, 1012, 1013, 1014, 1015, 1016, 1017, 0, 0, 0, 0, 0,
- 0, 906, 907, 938, 939, 970, 971, 1002, 1003, 974, 975, 0, 0,
- 0, 0, 0, 0, 922, 923, 954, 955, 986, 987, 1018, 1019, 990,
- 991, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 12,
- 13, 268, 269, 524, 525, 780, 781, 46, 47, 0, 0, 0, 0,
- 0, 0, 28, 29, 284, 285, 540, 541, 796, 797, 62, 63, 0,
- 0, 0, 0, 0, 0, 44, 45, 300, 301, 556, 557, 812, 813,
- 302, 303, 0, 0, 0, 0, 0, 0, 60, 61, 316, 317, 572,
- 573, 828, 829, 318, 319, 0, 0, 0, 0, 0, 0, 76, 77,
- 332, 333, 588, 589, 844, 845, 558, 559, 0, 0, 0, 0, 0,
- 0, 92, 93, 348, 349, 604, 605, 860, 861, 574, 575, 0, 0,
- 0, 0, 0, 0, 108, 109, 364, 365, 620, 621, 876, 877, 814,
- 815, 0, 0, 0, 0, 0, 0, 124, 125, 380, 381, 636, 637,
- 892, 893, 830, 831, 0, 0, 0, 0, 0, 0, 14, 15, 270,
- 271, 526, 527, 782, 783, 110, 111, 0, 0, 0, 0, 0, 0,
- 30, 31, 286, 287, 542, 543, 798, 799, 126, 127, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0, 140, 141, 396, 397, 652,
- 653, 908, 909, 174, 175, 0, 0, 0, 0, 0, 0, 156, 157,
- 412, 413, 668, 669, 924, 925, 190, 191, 0, 0, 0, 0, 0,
- 0, 172, 173, 428, 429, 684, 685, 940, 941, 430, 431, 0, 0,
- 0, 0, 0, 0, 188, 189, 444, 445, 700, 701, 956, 957, 446,
- 447, 0, 0, 0, 0, 0, 0, 204, 205, 460, 461, 716, 717,
- 972, 973, 686, 687, 0, 0, 0, 0, 0, 0, 220, 221, 476,
- 477, 732, 733, 988, 989, 702, 703, 0, 0, 0, 0, 0, 0,
- 236, 237, 492, 493, 748, 749, 1004, 1005, 942, 943, 0, 0, 0,
- 0, 0, 0, 252, 253, 508, 509, 764, 765, 1020, 1021, 958, 959,
- 0, 0, 0, 0, 0, 0, 142, 143, 398, 399, 654, 655, 910,
- 911, 238, 239, 0, 0, 0, 0, 0, 0, 158, 159, 414, 415,
- 670, 671, 926, 927, 254, 255};
-#endif
-
-#if defined(DEC_DPD2BCD) && DEC_DPD2BCD==1 && !defined(DECDPD2BCD)
-#define DECDPD2BCD
-
-const uint16_t DPD2BCD[1024]={ 0, 1, 2, 3, 4, 5, 6, 7,
- 8, 9, 128, 129, 2048, 2049, 2176, 2177, 16, 17, 18, 19, 20,
- 21, 22, 23, 24, 25, 144, 145, 2064, 2065, 2192, 2193, 32, 33,
- 34, 35, 36, 37, 38, 39, 40, 41, 130, 131, 2080, 2081, 2056,
- 2057, 48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 146, 147,
- 2096, 2097, 2072, 2073, 64, 65, 66, 67, 68, 69, 70, 71, 72,
- 73, 132, 133, 2112, 2113, 136, 137, 80, 81, 82, 83, 84, 85,
- 86, 87, 88, 89, 148, 149, 2128, 2129, 152, 153, 96, 97, 98,
- 99, 100, 101, 102, 103, 104, 105, 134, 135, 2144, 2145, 2184, 2185,
- 112, 113, 114, 115, 116, 117, 118, 119, 120, 121, 150, 151, 2160,
- 2161, 2200, 2201, 256, 257, 258, 259, 260, 261, 262, 263, 264, 265,
- 384, 385, 2304, 2305, 2432, 2433, 272, 273, 274, 275, 276, 277, 278,
- 279, 280, 281, 400, 401, 2320, 2321, 2448, 2449, 288, 289, 290, 291,
- 292, 293, 294, 295, 296, 297, 386, 387, 2336, 2337, 2312, 2313, 304,
- 305, 306, 307, 308, 309, 310, 311, 312, 313, 402, 403, 2352, 2353,
- 2328, 2329, 320, 321, 322, 323, 324, 325, 326, 327, 328, 329, 388,
- 389, 2368, 2369, 392, 393, 336, 337, 338, 339, 340, 341, 342, 343,
- 344, 345, 404, 405, 2384, 2385, 408, 409, 352, 353, 354, 355, 356,
- 357, 358, 359, 360, 361, 390, 391, 2400, 2401, 2440, 2441, 368, 369,
- 370, 371, 372, 373, 374, 375, 376, 377, 406, 407, 2416, 2417, 2456,
- 2457, 512, 513, 514, 515, 516, 517, 518, 519, 520, 521, 640, 641,
- 2050, 2051, 2178, 2179, 528, 529, 530, 531, 532, 533, 534, 535, 536,
- 537, 656, 657, 2066, 2067, 2194, 2195, 544, 545, 546, 547, 548, 549,
- 550, 551, 552, 553, 642, 643, 2082, 2083, 2088, 2089, 560, 561, 562,
- 563, 564, 565, 566, 567, 568, 569, 658, 659, 2098, 2099, 2104, 2105,
- 576, 577, 578, 579, 580, 581, 582, 583, 584, 585, 644, 645, 2114,
- 2115, 648, 649, 592, 593, 594, 595, 596, 597, 598, 599, 600, 601,
- 660, 661, 2130, 2131, 664, 665, 608, 609, 610, 611, 612, 613, 614,
- 615, 616, 617, 646, 647, 2146, 2147, 2184, 2185, 624, 625, 626, 627,
- 628, 629, 630, 631, 632, 633, 662, 663, 2162, 2163, 2200, 2201, 768,
- 769, 770, 771, 772, 773, 774, 775, 776, 777, 896, 897, 2306, 2307,
- 2434, 2435, 784, 785, 786, 787, 788, 789, 790, 791, 792, 793, 912,
- 913, 2322, 2323, 2450, 2451, 800, 801, 802, 803, 804, 805, 806, 807,
- 808, 809, 898, 899, 2338, 2339, 2344, 2345, 816, 817, 818, 819, 820,
- 821, 822, 823, 824, 825, 914, 915, 2354, 2355, 2360, 2361, 832, 833,
- 834, 835, 836, 837, 838, 839, 840, 841, 900, 901, 2370, 2371, 904,
- 905, 848, 849, 850, 851, 852, 853, 854, 855, 856, 857, 916, 917,
- 2386, 2387, 920, 921, 864, 865, 866, 867, 868, 869, 870, 871, 872,
- 873, 902, 903, 2402, 2403, 2440, 2441, 880, 881, 882, 883, 884, 885,
- 886, 887, 888, 889, 918, 919, 2418, 2419, 2456, 2457, 1024, 1025, 1026,
- 1027, 1028, 1029, 1030, 1031, 1032, 1033, 1152, 1153, 2052, 2053, 2180, 2181,
- 1040, 1041, 1042, 1043, 1044, 1045, 1046, 1047, 1048, 1049, 1168, 1169, 2068,
- 2069, 2196, 2197, 1056, 1057, 1058, 1059, 1060, 1061, 1062, 1063, 1064, 1065,
- 1154, 1155, 2084, 2085, 2120, 2121, 1072, 1073, 1074, 1075, 1076, 1077, 1078,
- 1079, 1080, 1081, 1170, 1171, 2100, 2101, 2136, 2137, 1088, 1089, 1090, 1091,
- 1092, 1093, 1094, 1095, 1096, 1097, 1156, 1157, 2116, 2117, 1160, 1161, 1104,
- 1105, 1106, 1107, 1108, 1109, 1110, 1111, 1112, 1113, 1172, 1173, 2132, 2133,
- 1176, 1177, 1120, 1121, 1122, 1123, 1124, 1125, 1126, 1127, 1128, 1129, 1158,
- 1159, 2148, 2149, 2184, 2185, 1136, 1137, 1138, 1139, 1140, 1141, 1142, 1143,
- 1144, 1145, 1174, 1175, 2164, 2165, 2200, 2201, 1280, 1281, 1282, 1283, 1284,
- 1285, 1286, 1287, 1288, 1289, 1408, 1409, 2308, 2309, 2436, 2437, 1296, 1297,
- 1298, 1299, 1300, 1301, 1302, 1303, 1304, 1305, 1424, 1425, 2324, 2325, 2452,
- 2453, 1312, 1313, 1314, 1315, 1316, 1317, 1318, 1319, 1320, 1321, 1410, 1411,
- 2340, 2341, 2376, 2377, 1328, 1329, 1330, 1331, 1332, 1333, 1334, 1335, 1336,
- 1337, 1426, 1427, 2356, 2357, 2392, 2393, 1344, 1345, 1346, 1347, 1348, 1349,
- 1350, 1351, 1352, 1353, 1412, 1413, 2372, 2373, 1416, 1417, 1360, 1361, 1362,
- 1363, 1364, 1365, 1366, 1367, 1368, 1369, 1428, 1429, 2388, 2389, 1432, 1433,
- 1376, 1377, 1378, 1379, 1380, 1381, 1382, 1383, 1384, 1385, 1414, 1415, 2404,
- 2405, 2440, 2441, 1392, 1393, 1394, 1395, 1396, 1397, 1398, 1399, 1400, 1401,
- 1430, 1431, 2420, 2421, 2456, 2457, 1536, 1537, 1538, 1539, 1540, 1541, 1542,
- 1543, 1544, 1545, 1664, 1665, 2054, 2055, 2182, 2183, 1552, 1553, 1554, 1555,
- 1556, 1557, 1558, 1559, 1560, 1561, 1680, 1681, 2070, 2071, 2198, 2199, 1568,
- 1569, 1570, 1571, 1572, 1573, 1574, 1575, 1576, 1577, 1666, 1667, 2086, 2087,
- 2152, 2153, 1584, 1585, 1586, 1587, 1588, 1589, 1590, 1591, 1592, 1593, 1682,
- 1683, 2102, 2103, 2168, 2169, 1600, 1601, 1602, 1603, 1604, 1605, 1606, 1607,
- 1608, 1609, 1668, 1669, 2118, 2119, 1672, 1673, 1616, 1617, 1618, 1619, 1620,
- 1621, 1622, 1623, 1624, 1625, 1684, 1685, 2134, 2135, 1688, 1689, 1632, 1633,
- 1634, 1635, 1636, 1637, 1638, 1639, 1640, 1641, 1670, 1671, 2150, 2151, 2184,
- 2185, 1648, 1649, 1650, 1651, 1652, 1653, 1654, 1655, 1656, 1657, 1686, 1687,
- 2166, 2167, 2200, 2201, 1792, 1793, 1794, 1795, 1796, 1797, 1798, 1799, 1800,
- 1801, 1920, 1921, 2310, 2311, 2438, 2439, 1808, 1809, 1810, 1811, 1812, 1813,
- 1814, 1815, 1816, 1817, 1936, 1937, 2326, 2327, 2454, 2455, 1824, 1825, 1826,
- 1827, 1828, 1829, 1830, 1831, 1832, 1833, 1922, 1923, 2342, 2343, 2408, 2409,
- 1840, 1841, 1842, 1843, 1844, 1845, 1846, 1847, 1848, 1849, 1938, 1939, 2358,
- 2359, 2424, 2425, 1856, 1857, 1858, 1859, 1860, 1861, 1862, 1863, 1864, 1865,
- 1924, 1925, 2374, 2375, 1928, 1929, 1872, 1873, 1874, 1875, 1876, 1877, 1878,
- 1879, 1880, 1881, 1940, 1941, 2390, 2391, 1944, 1945, 1888, 1889, 1890, 1891,
- 1892, 1893, 1894, 1895, 1896, 1897, 1926, 1927, 2406, 2407, 2440, 2441, 1904,
- 1905, 1906, 1907, 1908, 1909, 1910, 1911, 1912, 1913, 1942, 1943, 2422, 2423,
- 2456, 2457};
-#endif
-
-#if defined(DEC_BIN2DPD) && DEC_BIN2DPD==1 && !defined(DECBIN2DPD)
-#define DECBIN2DPD
-
-const uint16_t BIN2DPD[1000]={ 0, 1, 2, 3, 4, 5, 6, 7,
- 8, 9, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 32,
- 33, 34, 35, 36, 37, 38, 39, 40, 41, 48, 49, 50, 51,
- 52, 53, 54, 55, 56, 57, 64, 65, 66, 67, 68, 69, 70,
- 71, 72, 73, 80, 81, 82, 83, 84, 85, 86, 87, 88, 89,
- 96, 97, 98, 99, 100, 101, 102, 103, 104, 105, 112, 113, 114,
- 115, 116, 117, 118, 119, 120, 121, 10, 11, 42, 43, 74, 75,
- 106, 107, 78, 79, 26, 27, 58, 59, 90, 91, 122, 123, 94,
- 95, 128, 129, 130, 131, 132, 133, 134, 135, 136, 137, 144, 145,
- 146, 147, 148, 149, 150, 151, 152, 153, 160, 161, 162, 163, 164,
- 165, 166, 167, 168, 169, 176, 177, 178, 179, 180, 181, 182, 183,
- 184, 185, 192, 193, 194, 195, 196, 197, 198, 199, 200, 201, 208,
- 209, 210, 211, 212, 213, 214, 215, 216, 217, 224, 225, 226, 227,
- 228, 229, 230, 231, 232, 233, 240, 241, 242, 243, 244, 245, 246,
- 247, 248, 249, 138, 139, 170, 171, 202, 203, 234, 235, 206, 207,
- 154, 155, 186, 187, 218, 219, 250, 251, 222, 223, 256, 257, 258,
- 259, 260, 261, 262, 263, 264, 265, 272, 273, 274, 275, 276, 277,
- 278, 279, 280, 281, 288, 289, 290, 291, 292, 293, 294, 295, 296,
- 297, 304, 305, 306, 307, 308, 309, 310, 311, 312, 313, 320, 321,
- 322, 323, 324, 325, 326, 327, 328, 329, 336, 337, 338, 339, 340,
- 341, 342, 343, 344, 345, 352, 353, 354, 355, 356, 357, 358, 359,
- 360, 361, 368, 369, 370, 371, 372, 373, 374, 375, 376, 377, 266,
- 267, 298, 299, 330, 331, 362, 363, 334, 335, 282, 283, 314, 315,
- 346, 347, 378, 379, 350, 351, 384, 385, 386, 387, 388, 389, 390,
- 391, 392, 393, 400, 401, 402, 403, 404, 405, 406, 407, 408, 409,
- 416, 417, 418, 419, 420, 421, 422, 423, 424, 425, 432, 433, 434,
- 435, 436, 437, 438, 439, 440, 441, 448, 449, 450, 451, 452, 453,
- 454, 455, 456, 457, 464, 465, 466, 467, 468, 469, 470, 471, 472,
- 473, 480, 481, 482, 483, 484, 485, 486, 487, 488, 489, 496, 497,
- 498, 499, 500, 501, 502, 503, 504, 505, 394, 395, 426, 427, 458,
- 459, 490, 491, 462, 463, 410, 411, 442, 443, 474, 475, 506, 507,
- 478, 479, 512, 513, 514, 515, 516, 517, 518, 519, 520, 521, 528,
- 529, 530, 531, 532, 533, 534, 535, 536, 537, 544, 545, 546, 547,
- 548, 549, 550, 551, 552, 553, 560, 561, 562, 563, 564, 565, 566,
- 567, 568, 569, 576, 577, 578, 579, 580, 581, 582, 583, 584, 585,
- 592, 593, 594, 595, 596, 597, 598, 599, 600, 601, 608, 609, 610,
- 611, 612, 613, 614, 615, 616, 617, 624, 625, 626, 627, 628, 629,
- 630, 631, 632, 633, 522, 523, 554, 555, 586, 587, 618, 619, 590,
- 591, 538, 539, 570, 571, 602, 603, 634, 635, 606, 607, 640, 641,
- 642, 643, 644, 645, 646, 647, 648, 649, 656, 657, 658, 659, 660,
- 661, 662, 663, 664, 665, 672, 673, 674, 675, 676, 677, 678, 679,
- 680, 681, 688, 689, 690, 691, 692, 693, 694, 695, 696, 697, 704,
- 705, 706, 707, 708, 709, 710, 711, 712, 713, 720, 721, 722, 723,
- 724, 725, 726, 727, 728, 729, 736, 737, 738, 739, 740, 741, 742,
- 743, 744, 745, 752, 753, 754, 755, 756, 757, 758, 759, 760, 761,
- 650, 651, 682, 683, 714, 715, 746, 747, 718, 719, 666, 667, 698,
- 699, 730, 731, 762, 763, 734, 735, 768, 769, 770, 771, 772, 773,
- 774, 775, 776, 777, 784, 785, 786, 787, 788, 789, 790, 791, 792,
- 793, 800, 801, 802, 803, 804, 805, 806, 807, 808, 809, 816, 817,
- 818, 819, 820, 821, 822, 823, 824, 825, 832, 833, 834, 835, 836,
- 837, 838, 839, 840, 841, 848, 849, 850, 851, 852, 853, 854, 855,
- 856, 857, 864, 865, 866, 867, 868, 869, 870, 871, 872, 873, 880,
- 881, 882, 883, 884, 885, 886, 887, 888, 889, 778, 779, 810, 811,
- 842, 843, 874, 875, 846, 847, 794, 795, 826, 827, 858, 859, 890,
- 891, 862, 863, 896, 897, 898, 899, 900, 901, 902, 903, 904, 905,
- 912, 913, 914, 915, 916, 917, 918, 919, 920, 921, 928, 929, 930,
- 931, 932, 933, 934, 935, 936, 937, 944, 945, 946, 947, 948, 949,
- 950, 951, 952, 953, 960, 961, 962, 963, 964, 965, 966, 967, 968,
- 969, 976, 977, 978, 979, 980, 981, 982, 983, 984, 985, 992, 993,
- 994, 995, 996, 997, 998, 999, 1000, 1001, 1008, 1009, 1010, 1011, 1012,
- 1013, 1014, 1015, 1016, 1017, 906, 907, 938, 939, 970, 971, 1002, 1003,
- 974, 975, 922, 923, 954, 955, 986, 987, 1018, 1019, 990, 991, 12,
- 13, 268, 269, 524, 525, 780, 781, 46, 47, 28, 29, 284, 285,
- 540, 541, 796, 797, 62, 63, 44, 45, 300, 301, 556, 557, 812,
- 813, 302, 303, 60, 61, 316, 317, 572, 573, 828, 829, 318, 319,
- 76, 77, 332, 333, 588, 589, 844, 845, 558, 559, 92, 93, 348,
- 349, 604, 605, 860, 861, 574, 575, 108, 109, 364, 365, 620, 621,
- 876, 877, 814, 815, 124, 125, 380, 381, 636, 637, 892, 893, 830,
- 831, 14, 15, 270, 271, 526, 527, 782, 783, 110, 111, 30, 31,
- 286, 287, 542, 543, 798, 799, 126, 127, 140, 141, 396, 397, 652,
- 653, 908, 909, 174, 175, 156, 157, 412, 413, 668, 669, 924, 925,
- 190, 191, 172, 173, 428, 429, 684, 685, 940, 941, 430, 431, 188,
- 189, 444, 445, 700, 701, 956, 957, 446, 447, 204, 205, 460, 461,
- 716, 717, 972, 973, 686, 687, 220, 221, 476, 477, 732, 733, 988,
- 989, 702, 703, 236, 237, 492, 493, 748, 749, 1004, 1005, 942, 943,
- 252, 253, 508, 509, 764, 765, 1020, 1021, 958, 959, 142, 143, 398,
- 399, 654, 655, 910, 911, 238, 239, 158, 159, 414, 415, 670, 671,
- 926, 927, 254, 255};
-#endif
-
-#if defined(DEC_DPD2BIN) && DEC_DPD2BIN==1 && !defined(DECDPD2BIN)
-#define DECDPD2BIN
-
-const uint16_t DPD2BIN[1024]={ 0, 1, 2, 3, 4, 5, 6, 7,
- 8, 9, 80, 81, 800, 801, 880, 881, 10, 11, 12, 13, 14,
- 15, 16, 17, 18, 19, 90, 91, 810, 811, 890, 891, 20, 21,
- 22, 23, 24, 25, 26, 27, 28, 29, 82, 83, 820, 821, 808,
- 809, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39, 92, 93,
- 830, 831, 818, 819, 40, 41, 42, 43, 44, 45, 46, 47, 48,
- 49, 84, 85, 840, 841, 88, 89, 50, 51, 52, 53, 54, 55,
- 56, 57, 58, 59, 94, 95, 850, 851, 98, 99, 60, 61, 62,
- 63, 64, 65, 66, 67, 68, 69, 86, 87, 860, 861, 888, 889,
- 70, 71, 72, 73, 74, 75, 76, 77, 78, 79, 96, 97, 870,
- 871, 898, 899, 100, 101, 102, 103, 104, 105, 106, 107, 108, 109,
- 180, 181, 900, 901, 980, 981, 110, 111, 112, 113, 114, 115, 116,
- 117, 118, 119, 190, 191, 910, 911, 990, 991, 120, 121, 122, 123,
- 124, 125, 126, 127, 128, 129, 182, 183, 920, 921, 908, 909, 130,
- 131, 132, 133, 134, 135, 136, 137, 138, 139, 192, 193, 930, 931,
- 918, 919, 140, 141, 142, 143, 144, 145, 146, 147, 148, 149, 184,
- 185, 940, 941, 188, 189, 150, 151, 152, 153, 154, 155, 156, 157,
- 158, 159, 194, 195, 950, 951, 198, 199, 160, 161, 162, 163, 164,
- 165, 166, 167, 168, 169, 186, 187, 960, 961, 988, 989, 170, 171,
- 172, 173, 174, 175, 176, 177, 178, 179, 196, 197, 970, 971, 998,
- 999, 200, 201, 202, 203, 204, 205, 206, 207, 208, 209, 280, 281,
- 802, 803, 882, 883, 210, 211, 212, 213, 214, 215, 216, 217, 218,
- 219, 290, 291, 812, 813, 892, 893, 220, 221, 222, 223, 224, 225,
- 226, 227, 228, 229, 282, 283, 822, 823, 828, 829, 230, 231, 232,
- 233, 234, 235, 236, 237, 238, 239, 292, 293, 832, 833, 838, 839,
- 240, 241, 242, 243, 244, 245, 246, 247, 248, 249, 284, 285, 842,
- 843, 288, 289, 250, 251, 252, 253, 254, 255, 256, 257, 258, 259,
- 294, 295, 852, 853, 298, 299, 260, 261, 262, 263, 264, 265, 266,
- 267, 268, 269, 286, 287, 862, 863, 888, 889, 270, 271, 272, 273,
- 274, 275, 276, 277, 278, 279, 296, 297, 872, 873, 898, 899, 300,
- 301, 302, 303, 304, 305, 306, 307, 308, 309, 380, 381, 902, 903,
- 982, 983, 310, 311, 312, 313, 314, 315, 316, 317, 318, 319, 390,
- 391, 912, 913, 992, 993, 320, 321, 322, 323, 324, 325, 326, 327,
- 328, 329, 382, 383, 922, 923, 928, 929, 330, 331, 332, 333, 334,
- 335, 336, 337, 338, 339, 392, 393, 932, 933, 938, 939, 340, 341,
- 342, 343, 344, 345, 346, 347, 348, 349, 384, 385, 942, 943, 388,
- 389, 350, 351, 352, 353, 354, 355, 356, 357, 358, 359, 394, 395,
- 952, 953, 398, 399, 360, 361, 362, 363, 364, 365, 366, 367, 368,
- 369, 386, 387, 962, 963, 988, 989, 370, 371, 372, 373, 374, 375,
- 376, 377, 378, 379, 396, 397, 972, 973, 998, 999, 400, 401, 402,
- 403, 404, 405, 406, 407, 408, 409, 480, 481, 804, 805, 884, 885,
- 410, 411, 412, 413, 414, 415, 416, 417, 418, 419, 490, 491, 814,
- 815, 894, 895, 420, 421, 422, 423, 424, 425, 426, 427, 428, 429,
- 482, 483, 824, 825, 848, 849, 430, 431, 432, 433, 434, 435, 436,
- 437, 438, 439, 492, 493, 834, 835, 858, 859, 440, 441, 442, 443,
- 444, 445, 446, 447, 448, 449, 484, 485, 844, 845, 488, 489, 450,
- 451, 452, 453, 454, 455, 456, 457, 458, 459, 494, 495, 854, 855,
- 498, 499, 460, 461, 462, 463, 464, 465, 466, 467, 468, 469, 486,
- 487, 864, 865, 888, 889, 470, 471, 472, 473, 474, 475, 476, 477,
- 478, 479, 496, 497, 874, 875, 898, 899, 500, 501, 502, 503, 504,
- 505, 506, 507, 508, 509, 580, 581, 904, 905, 984, 985, 510, 511,
- 512, 513, 514, 515, 516, 517, 518, 519, 590, 591, 914, 915, 994,
- 995, 520, 521, 522, 523, 524, 525, 526, 527, 528, 529, 582, 583,
- 924, 925, 948, 949, 530, 531, 532, 533, 534, 535, 536, 537, 538,
- 539, 592, 593, 934, 935, 958, 959, 540, 541, 542, 543, 544, 545,
- 546, 547, 548, 549, 584, 585, 944, 945, 588, 589, 550, 551, 552,
- 553, 554, 555, 556, 557, 558, 559, 594, 595, 954, 955, 598, 599,
- 560, 561, 562, 563, 564, 565, 566, 567, 568, 569, 586, 587, 964,
- 965, 988, 989, 570, 571, 572, 573, 574, 575, 576, 577, 578, 579,
- 596, 597, 974, 975, 998, 999, 600, 601, 602, 603, 604, 605, 606,
- 607, 608, 609, 680, 681, 806, 807, 886, 887, 610, 611, 612, 613,
- 614, 615, 616, 617, 618, 619, 690, 691, 816, 817, 896, 897, 620,
- 621, 622, 623, 624, 625, 626, 627, 628, 629, 682, 683, 826, 827,
- 868, 869, 630, 631, 632, 633, 634, 635, 636, 637, 638, 639, 692,
- 693, 836, 837, 878, 879, 640, 641, 642, 643, 644, 645, 646, 647,
- 648, 649, 684, 685, 846, 847, 688, 689, 650, 651, 652, 653, 654,
- 655, 656, 657, 658, 659, 694, 695, 856, 857, 698, 699, 660, 661,
- 662, 663, 664, 665, 666, 667, 668, 669, 686, 687, 866, 867, 888,
- 889, 670, 671, 672, 673, 674, 675, 676, 677, 678, 679, 696, 697,
- 876, 877, 898, 899, 700, 701, 702, 703, 704, 705, 706, 707, 708,
- 709, 780, 781, 906, 907, 986, 987, 710, 711, 712, 713, 714, 715,
- 716, 717, 718, 719, 790, 791, 916, 917, 996, 997, 720, 721, 722,
- 723, 724, 725, 726, 727, 728, 729, 782, 783, 926, 927, 968, 969,
- 730, 731, 732, 733, 734, 735, 736, 737, 738, 739, 792, 793, 936,
- 937, 978, 979, 740, 741, 742, 743, 744, 745, 746, 747, 748, 749,
- 784, 785, 946, 947, 788, 789, 750, 751, 752, 753, 754, 755, 756,
- 757, 758, 759, 794, 795, 956, 957, 798, 799, 760, 761, 762, 763,
- 764, 765, 766, 767, 768, 769, 786, 787, 966, 967, 988, 989, 770,
- 771, 772, 773, 774, 775, 776, 777, 778, 779, 796, 797, 976, 977,
- 998, 999};
-#endif
-
-#if defined(DEC_DPD2BINK) && DEC_DPD2BINK==1 && !defined(DECDPD2BINK)
-#define DECDPD2BINK
-
-const uint32_t DPD2BINK[1024]={ 0, 1000, 2000, 3000, 4000, 5000,
- 6000, 7000, 8000, 9000, 80000, 81000, 800000, 801000, 880000, 881000,
- 10000, 11000, 12000, 13000, 14000, 15000, 16000, 17000, 18000, 19000,
- 90000, 91000, 810000, 811000, 890000, 891000, 20000, 21000, 22000, 23000,
- 24000, 25000, 26000, 27000, 28000, 29000, 82000, 83000, 820000, 821000,
- 808000, 809000, 30000, 31000, 32000, 33000, 34000, 35000, 36000, 37000,
- 38000, 39000, 92000, 93000, 830000, 831000, 818000, 819000, 40000, 41000,
- 42000, 43000, 44000, 45000, 46000, 47000, 48000, 49000, 84000, 85000,
- 840000, 841000, 88000, 89000, 50000, 51000, 52000, 53000, 54000, 55000,
- 56000, 57000, 58000, 59000, 94000, 95000, 850000, 851000, 98000, 99000,
- 60000, 61000, 62000, 63000, 64000, 65000, 66000, 67000, 68000, 69000,
- 86000, 87000, 860000, 861000, 888000, 889000, 70000, 71000, 72000, 73000,
- 74000, 75000, 76000, 77000, 78000, 79000, 96000, 97000, 870000, 871000,
- 898000, 899000, 100000, 101000, 102000, 103000, 104000, 105000, 106000, 107000,
- 108000, 109000, 180000, 181000, 900000, 901000, 980000, 981000, 110000, 111000,
- 112000, 113000, 114000, 115000, 116000, 117000, 118000, 119000, 190000, 191000,
- 910000, 911000, 990000, 991000, 120000, 121000, 122000, 123000, 124000, 125000,
- 126000, 127000, 128000, 129000, 182000, 183000, 920000, 921000, 908000, 909000,
- 130000, 131000, 132000, 133000, 134000, 135000, 136000, 137000, 138000, 139000,
- 192000, 193000, 930000, 931000, 918000, 919000, 140000, 141000, 142000, 143000,
- 144000, 145000, 146000, 147000, 148000, 149000, 184000, 185000, 940000, 941000,
- 188000, 189000, 150000, 151000, 152000, 153000, 154000, 155000, 156000, 157000,
- 158000, 159000, 194000, 195000, 950000, 951000, 198000, 199000, 160000, 161000,
- 162000, 163000, 164000, 165000, 166000, 167000, 168000, 169000, 186000, 187000,
- 960000, 961000, 988000, 989000, 170000, 171000, 172000, 173000, 174000, 175000,
- 176000, 177000, 178000, 179000, 196000, 197000, 970000, 971000, 998000, 999000,
- 200000, 201000, 202000, 203000, 204000, 205000, 206000, 207000, 208000, 209000,
- 280000, 281000, 802000, 803000, 882000, 883000, 210000, 211000, 212000, 213000,
- 214000, 215000, 216000, 217000, 218000, 219000, 290000, 291000, 812000, 813000,
- 892000, 893000, 220000, 221000, 222000, 223000, 224000, 225000, 226000, 227000,
- 228000, 229000, 282000, 283000, 822000, 823000, 828000, 829000, 230000, 231000,
- 232000, 233000, 234000, 235000, 236000, 237000, 238000, 239000, 292000, 293000,
- 832000, 833000, 838000, 839000, 240000, 241000, 242000, 243000, 244000, 245000,
- 246000, 247000, 248000, 249000, 284000, 285000, 842000, 843000, 288000, 289000,
- 250000, 251000, 252000, 253000, 254000, 255000, 256000, 257000, 258000, 259000,
- 294000, 295000, 852000, 853000, 298000, 299000, 260000, 261000, 262000, 263000,
- 264000, 265000, 266000, 267000, 268000, 269000, 286000, 287000, 862000, 863000,
- 888000, 889000, 270000, 271000, 272000, 273000, 274000, 275000, 276000, 277000,
- 278000, 279000, 296000, 297000, 872000, 873000, 898000, 899000, 300000, 301000,
- 302000, 303000, 304000, 305000, 306000, 307000, 308000, 309000, 380000, 381000,
- 902000, 903000, 982000, 983000, 310000, 311000, 312000, 313000, 314000, 315000,
- 316000, 317000, 318000, 319000, 390000, 391000, 912000, 913000, 992000, 993000,
- 320000, 321000, 322000, 323000, 324000, 325000, 326000, 327000, 328000, 329000,
- 382000, 383000, 922000, 923000, 928000, 929000, 330000, 331000, 332000, 333000,
- 334000, 335000, 336000, 337000, 338000, 339000, 392000, 393000, 932000, 933000,
- 938000, 939000, 340000, 341000, 342000, 343000, 344000, 345000, 346000, 347000,
- 348000, 349000, 384000, 385000, 942000, 943000, 388000, 389000, 350000, 351000,
- 352000, 353000, 354000, 355000, 356000, 357000, 358000, 359000, 394000, 395000,
- 952000, 953000, 398000, 399000, 360000, 361000, 362000, 363000, 364000, 365000,
- 366000, 367000, 368000, 369000, 386000, 387000, 962000, 963000, 988000, 989000,
- 370000, 371000, 372000, 373000, 374000, 375000, 376000, 377000, 378000, 379000,
- 396000, 397000, 972000, 973000, 998000, 999000, 400000, 401000, 402000, 403000,
- 404000, 405000, 406000, 407000, 408000, 409000, 480000, 481000, 804000, 805000,
- 884000, 885000, 410000, 411000, 412000, 413000, 414000, 415000, 416000, 417000,
- 418000, 419000, 490000, 491000, 814000, 815000, 894000, 895000, 420000, 421000,
- 422000, 423000, 424000, 425000, 426000, 427000, 428000, 429000, 482000, 483000,
- 824000, 825000, 848000, 849000, 430000, 431000, 432000, 433000, 434000, 435000,
- 436000, 437000, 438000, 439000, 492000, 493000, 834000, 835000, 858000, 859000,
- 440000, 441000, 442000, 443000, 444000, 445000, 446000, 447000, 448000, 449000,
- 484000, 485000, 844000, 845000, 488000, 489000, 450000, 451000, 452000, 453000,
- 454000, 455000, 456000, 457000, 458000, 459000, 494000, 495000, 854000, 855000,
- 498000, 499000, 460000, 461000, 462000, 463000, 464000, 465000, 466000, 467000,
- 468000, 469000, 486000, 487000, 864000, 865000, 888000, 889000, 470000, 471000,
- 472000, 473000, 474000, 475000, 476000, 477000, 478000, 479000, 496000, 497000,
- 874000, 875000, 898000, 899000, 500000, 501000, 502000, 503000, 504000, 505000,
- 506000, 507000, 508000, 509000, 580000, 581000, 904000, 905000, 984000, 985000,
- 510000, 511000, 512000, 513000, 514000, 515000, 516000, 517000, 518000, 519000,
- 590000, 591000, 914000, 915000, 994000, 995000, 520000, 521000, 522000, 523000,
- 524000, 525000, 526000, 527000, 528000, 529000, 582000, 583000, 924000, 925000,
- 948000, 949000, 530000, 531000, 532000, 533000, 534000, 535000, 536000, 537000,
- 538000, 539000, 592000, 593000, 934000, 935000, 958000, 959000, 540000, 541000,
- 542000, 543000, 544000, 545000, 546000, 547000, 548000, 549000, 584000, 585000,
- 944000, 945000, 588000, 589000, 550000, 551000, 552000, 553000, 554000, 555000,
- 556000, 557000, 558000, 559000, 594000, 595000, 954000, 955000, 598000, 599000,
- 560000, 561000, 562000, 563000, 564000, 565000, 566000, 567000, 568000, 569000,
- 586000, 587000, 964000, 965000, 988000, 989000, 570000, 571000, 572000, 573000,
- 574000, 575000, 576000, 577000, 578000, 579000, 596000, 597000, 974000, 975000,
- 998000, 999000, 600000, 601000, 602000, 603000, 604000, 605000, 606000, 607000,
- 608000, 609000, 680000, 681000, 806000, 807000, 886000, 887000, 610000, 611000,
- 612000, 613000, 614000, 615000, 616000, 617000, 618000, 619000, 690000, 691000,
- 816000, 817000, 896000, 897000, 620000, 621000, 622000, 623000, 624000, 625000,
- 626000, 627000, 628000, 629000, 682000, 683000, 826000, 827000, 868000, 869000,
- 630000, 631000, 632000, 633000, 634000, 635000, 636000, 637000, 638000, 639000,
- 692000, 693000, 836000, 837000, 878000, 879000, 640000, 641000, 642000, 643000,
- 644000, 645000, 646000, 647000, 648000, 649000, 684000, 685000, 846000, 847000,
- 688000, 689000, 650000, 651000, 652000, 653000, 654000, 655000, 656000, 657000,
- 658000, 659000, 694000, 695000, 856000, 857000, 698000, 699000, 660000, 661000,
- 662000, 663000, 664000, 665000, 666000, 667000, 668000, 669000, 686000, 687000,
- 866000, 867000, 888000, 889000, 670000, 671000, 672000, 673000, 674000, 675000,
- 676000, 677000, 678000, 679000, 696000, 697000, 876000, 877000, 898000, 899000,
- 700000, 701000, 702000, 703000, 704000, 705000, 706000, 707000, 708000, 709000,
- 780000, 781000, 906000, 907000, 986000, 987000, 710000, 711000, 712000, 713000,
- 714000, 715000, 716000, 717000, 718000, 719000, 790000, 791000, 916000, 917000,
- 996000, 997000, 720000, 721000, 722000, 723000, 724000, 725000, 726000, 727000,
- 728000, 729000, 782000, 783000, 926000, 927000, 968000, 969000, 730000, 731000,
- 732000, 733000, 734000, 735000, 736000, 737000, 738000, 739000, 792000, 793000,
- 936000, 937000, 978000, 979000, 740000, 741000, 742000, 743000, 744000, 745000,
- 746000, 747000, 748000, 749000, 784000, 785000, 946000, 947000, 788000, 789000,
- 750000, 751000, 752000, 753000, 754000, 755000, 756000, 757000, 758000, 759000,
- 794000, 795000, 956000, 957000, 798000, 799000, 760000, 761000, 762000, 763000,
- 764000, 765000, 766000, 767000, 768000, 769000, 786000, 787000, 966000, 967000,
- 988000, 989000, 770000, 771000, 772000, 773000, 774000, 775000, 776000, 777000,
- 778000, 779000, 796000, 797000, 976000, 977000, 998000, 999000};
-#endif
-
-#if defined(DEC_DPD2BINM) && DEC_DPD2BINM==1 && !defined(DECDPD2BINM)
-#define DECDPD2BINM
-
-const uint32_t DPD2BINM[1024]={0, 1000000, 2000000, 3000000, 4000000,
- 5000000, 6000000, 7000000, 8000000, 9000000, 80000000, 81000000,
- 800000000, 801000000, 880000000, 881000000, 10000000, 11000000, 12000000,
- 13000000, 14000000, 15000000, 16000000, 17000000, 18000000, 19000000,
- 90000000, 91000000, 810000000, 811000000, 890000000, 891000000, 20000000,
- 21000000, 22000000, 23000000, 24000000, 25000000, 26000000, 27000000,
- 28000000, 29000000, 82000000, 83000000, 820000000, 821000000, 808000000,
- 809000000, 30000000, 31000000, 32000000, 33000000, 34000000, 35000000,
- 36000000, 37000000, 38000000, 39000000, 92000000, 93000000, 830000000,
- 831000000, 818000000, 819000000, 40000000, 41000000, 42000000, 43000000,
- 44000000, 45000000, 46000000, 47000000, 48000000, 49000000, 84000000,
- 85000000, 840000000, 841000000, 88000000, 89000000, 50000000, 51000000,
- 52000000, 53000000, 54000000, 55000000, 56000000, 57000000, 58000000,
- 59000000, 94000000, 95000000, 850000000, 851000000, 98000000, 99000000,
- 60000000, 61000000, 62000000, 63000000, 64000000, 65000000, 66000000,
- 67000000, 68000000, 69000000, 86000000, 87000000, 860000000, 861000000,
- 888000000, 889000000, 70000000, 71000000, 72000000, 73000000, 74000000,
- 75000000, 76000000, 77000000, 78000000, 79000000, 96000000, 97000000,
- 870000000, 871000000, 898000000, 899000000, 100000000, 101000000, 102000000,
- 103000000, 104000000, 105000000, 106000000, 107000000, 108000000, 109000000,
- 180000000, 181000000, 900000000, 901000000, 980000000, 981000000, 110000000,
- 111000000, 112000000, 113000000, 114000000, 115000000, 116000000, 117000000,
- 118000000, 119000000, 190000000, 191000000, 910000000, 911000000, 990000000,
- 991000000, 120000000, 121000000, 122000000, 123000000, 124000000, 125000000,
- 126000000, 127000000, 128000000, 129000000, 182000000, 183000000, 920000000,
- 921000000, 908000000, 909000000, 130000000, 131000000, 132000000, 133000000,
- 134000000, 135000000, 136000000, 137000000, 138000000, 139000000, 192000000,
- 193000000, 930000000, 931000000, 918000000, 919000000, 140000000, 141000000,
- 142000000, 143000000, 144000000, 145000000, 146000000, 147000000, 148000000,
- 149000000, 184000000, 185000000, 940000000, 941000000, 188000000, 189000000,
- 150000000, 151000000, 152000000, 153000000, 154000000, 155000000, 156000000,
- 157000000, 158000000, 159000000, 194000000, 195000000, 950000000, 951000000,
- 198000000, 199000000, 160000000, 161000000, 162000000, 163000000, 164000000,
- 165000000, 166000000, 167000000, 168000000, 169000000, 186000000, 187000000,
- 960000000, 961000000, 988000000, 989000000, 170000000, 171000000, 172000000,
- 173000000, 174000000, 175000000, 176000000, 177000000, 178000000, 179000000,
- 196000000, 197000000, 970000000, 971000000, 998000000, 999000000, 200000000,
- 201000000, 202000000, 203000000, 204000000, 205000000, 206000000, 207000000,
- 208000000, 209000000, 280000000, 281000000, 802000000, 803000000, 882000000,
- 883000000, 210000000, 211000000, 212000000, 213000000, 214000000, 215000000,
- 216000000, 217000000, 218000000, 219000000, 290000000, 291000000, 812000000,
- 813000000, 892000000, 893000000, 220000000, 221000000, 222000000, 223000000,
- 224000000, 225000000, 226000000, 227000000, 228000000, 229000000, 282000000,
- 283000000, 822000000, 823000000, 828000000, 829000000, 230000000, 231000000,
- 232000000, 233000000, 234000000, 235000000, 236000000, 237000000, 238000000,
- 239000000, 292000000, 293000000, 832000000, 833000000, 838000000, 839000000,
- 240000000, 241000000, 242000000, 243000000, 244000000, 245000000, 246000000,
- 247000000, 248000000, 249000000, 284000000, 285000000, 842000000, 843000000,
- 288000000, 289000000, 250000000, 251000000, 252000000, 253000000, 254000000,
- 255000000, 256000000, 257000000, 258000000, 259000000, 294000000, 295000000,
- 852000000, 853000000, 298000000, 299000000, 260000000, 261000000, 262000000,
- 263000000, 264000000, 265000000, 266000000, 267000000, 268000000, 269000000,
- 286000000, 287000000, 862000000, 863000000, 888000000, 889000000, 270000000,
- 271000000, 272000000, 273000000, 274000000, 275000000, 276000000, 277000000,
- 278000000, 279000000, 296000000, 297000000, 872000000, 873000000, 898000000,
- 899000000, 300000000, 301000000, 302000000, 303000000, 304000000, 305000000,
- 306000000, 307000000, 308000000, 309000000, 380000000, 381000000, 902000000,
- 903000000, 982000000, 983000000, 310000000, 311000000, 312000000, 313000000,
- 314000000, 315000000, 316000000, 317000000, 318000000, 319000000, 390000000,
- 391000000, 912000000, 913000000, 992000000, 993000000, 320000000, 321000000,
- 322000000, 323000000, 324000000, 325000000, 326000000, 327000000, 328000000,
- 329000000, 382000000, 383000000, 922000000, 923000000, 928000000, 929000000,
- 330000000, 331000000, 332000000, 333000000, 334000000, 335000000, 336000000,
- 337000000, 338000000, 339000000, 392000000, 393000000, 932000000, 933000000,
- 938000000, 939000000, 340000000, 341000000, 342000000, 343000000, 344000000,
- 345000000, 346000000, 347000000, 348000000, 349000000, 384000000, 385000000,
- 942000000, 943000000, 388000000, 389000000, 350000000, 351000000, 352000000,
- 353000000, 354000000, 355000000, 356000000, 357000000, 358000000, 359000000,
- 394000000, 395000000, 952000000, 953000000, 398000000, 399000000, 360000000,
- 361000000, 362000000, 363000000, 364000000, 365000000, 366000000, 367000000,
- 368000000, 369000000, 386000000, 387000000, 962000000, 963000000, 988000000,
- 989000000, 370000000, 371000000, 372000000, 373000000, 374000000, 375000000,
- 376000000, 377000000, 378000000, 379000000, 396000000, 397000000, 972000000,
- 973000000, 998000000, 999000000, 400000000, 401000000, 402000000, 403000000,
- 404000000, 405000000, 406000000, 407000000, 408000000, 409000000, 480000000,
- 481000000, 804000000, 805000000, 884000000, 885000000, 410000000, 411000000,
- 412000000, 413000000, 414000000, 415000000, 416000000, 417000000, 418000000,
- 419000000, 490000000, 491000000, 814000000, 815000000, 894000000, 895000000,
- 420000000, 421000000, 422000000, 423000000, 424000000, 425000000, 426000000,
- 427000000, 428000000, 429000000, 482000000, 483000000, 824000000, 825000000,
- 848000000, 849000000, 430000000, 431000000, 432000000, 433000000, 434000000,
- 435000000, 436000000, 437000000, 438000000, 439000000, 492000000, 493000000,
- 834000000, 835000000, 858000000, 859000000, 440000000, 441000000, 442000000,
- 443000000, 444000000, 445000000, 446000000, 447000000, 448000000, 449000000,
- 484000000, 485000000, 844000000, 845000000, 488000000, 489000000, 450000000,
- 451000000, 452000000, 453000000, 454000000, 455000000, 456000000, 457000000,
- 458000000, 459000000, 494000000, 495000000, 854000000, 855000000, 498000000,
- 499000000, 460000000, 461000000, 462000000, 463000000, 464000000, 465000000,
- 466000000, 467000000, 468000000, 469000000, 486000000, 487000000, 864000000,
- 865000000, 888000000, 889000000, 470000000, 471000000, 472000000, 473000000,
- 474000000, 475000000, 476000000, 477000000, 478000000, 479000000, 496000000,
- 497000000, 874000000, 875000000, 898000000, 899000000, 500000000, 501000000,
- 502000000, 503000000, 504000000, 505000000, 506000000, 507000000, 508000000,
- 509000000, 580000000, 581000000, 904000000, 905000000, 984000000, 985000000,
- 510000000, 511000000, 512000000, 513000000, 514000000, 515000000, 516000000,
- 517000000, 518000000, 519000000, 590000000, 591000000, 914000000, 915000000,
- 994000000, 995000000, 520000000, 521000000, 522000000, 523000000, 524000000,
- 525000000, 526000000, 527000000, 528000000, 529000000, 582000000, 583000000,
- 924000000, 925000000, 948000000, 949000000, 530000000, 531000000, 532000000,
- 533000000, 534000000, 535000000, 536000000, 537000000, 538000000, 539000000,
- 592000000, 593000000, 934000000, 935000000, 958000000, 959000000, 540000000,
- 541000000, 542000000, 543000000, 544000000, 545000000, 546000000, 547000000,
- 548000000, 549000000, 584000000, 585000000, 944000000, 945000000, 588000000,
- 589000000, 550000000, 551000000, 552000000, 553000000, 554000000, 555000000,
- 556000000, 557000000, 558000000, 559000000, 594000000, 595000000, 954000000,
- 955000000, 598000000, 599000000, 560000000, 561000000, 562000000, 563000000,
- 564000000, 565000000, 566000000, 567000000, 568000000, 569000000, 586000000,
- 587000000, 964000000, 965000000, 988000000, 989000000, 570000000, 571000000,
- 572000000, 573000000, 574000000, 575000000, 576000000, 577000000, 578000000,
- 579000000, 596000000, 597000000, 974000000, 975000000, 998000000, 999000000,
- 600000000, 601000000, 602000000, 603000000, 604000000, 605000000, 606000000,
- 607000000, 608000000, 609000000, 680000000, 681000000, 806000000, 807000000,
- 886000000, 887000000, 610000000, 611000000, 612000000, 613000000, 614000000,
- 615000000, 616000000, 617000000, 618000000, 619000000, 690000000, 691000000,
- 816000000, 817000000, 896000000, 897000000, 620000000, 621000000, 622000000,
- 623000000, 624000000, 625000000, 626000000, 627000000, 628000000, 629000000,
- 682000000, 683000000, 826000000, 827000000, 868000000, 869000000, 630000000,
- 631000000, 632000000, 633000000, 634000000, 635000000, 636000000, 637000000,
- 638000000, 639000000, 692000000, 693000000, 836000000, 837000000, 878000000,
- 879000000, 640000000, 641000000, 642000000, 643000000, 644000000, 645000000,
- 646000000, 647000000, 648000000, 649000000, 684000000, 685000000, 846000000,
- 847000000, 688000000, 689000000, 650000000, 651000000, 652000000, 653000000,
- 654000000, 655000000, 656000000, 657000000, 658000000, 659000000, 694000000,
- 695000000, 856000000, 857000000, 698000000, 699000000, 660000000, 661000000,
- 662000000, 663000000, 664000000, 665000000, 666000000, 667000000, 668000000,
- 669000000, 686000000, 687000000, 866000000, 867000000, 888000000, 889000000,
- 670000000, 671000000, 672000000, 673000000, 674000000, 675000000, 676000000,
- 677000000, 678000000, 679000000, 696000000, 697000000, 876000000, 877000000,
- 898000000, 899000000, 700000000, 701000000, 702000000, 703000000, 704000000,
- 705000000, 706000000, 707000000, 708000000, 709000000, 780000000, 781000000,
- 906000000, 907000000, 986000000, 987000000, 710000000, 711000000, 712000000,
- 713000000, 714000000, 715000000, 716000000, 717000000, 718000000, 719000000,
- 790000000, 791000000, 916000000, 917000000, 996000000, 997000000, 720000000,
- 721000000, 722000000, 723000000, 724000000, 725000000, 726000000, 727000000,
- 728000000, 729000000, 782000000, 783000000, 926000000, 927000000, 968000000,
- 969000000, 730000000, 731000000, 732000000, 733000000, 734000000, 735000000,
- 736000000, 737000000, 738000000, 739000000, 792000000, 793000000, 936000000,
- 937000000, 978000000, 979000000, 740000000, 741000000, 742000000, 743000000,
- 744000000, 745000000, 746000000, 747000000, 748000000, 749000000, 784000000,
- 785000000, 946000000, 947000000, 788000000, 789000000, 750000000, 751000000,
- 752000000, 753000000, 754000000, 755000000, 756000000, 757000000, 758000000,
- 759000000, 794000000, 795000000, 956000000, 957000000, 798000000, 799000000,
- 760000000, 761000000, 762000000, 763000000, 764000000, 765000000, 766000000,
- 767000000, 768000000, 769000000, 786000000, 787000000, 966000000, 967000000,
- 988000000, 989000000, 770000000, 771000000, 772000000, 773000000, 774000000,
- 775000000, 776000000, 777000000, 778000000, 779000000, 796000000, 797000000,
- 976000000, 977000000, 998000000, 999000000};
-#endif
-
-#if defined(DEC_BIN2CHAR) && DEC_BIN2CHAR==1 && !defined(DECBIN2CHAR)
-#define DECBIN2CHAR
-
-const uint8_t BIN2CHAR[4001]={
- '\0','0','0','0', '\1','0','0','1', '\1','0','0','2', '\1','0','0','3', '\1','0','0','4',
- '\1','0','0','5', '\1','0','0','6', '\1','0','0','7', '\1','0','0','8', '\1','0','0','9',
- '\2','0','1','0', '\2','0','1','1', '\2','0','1','2', '\2','0','1','3', '\2','0','1','4',
- '\2','0','1','5', '\2','0','1','6', '\2','0','1','7', '\2','0','1','8', '\2','0','1','9',
- '\2','0','2','0', '\2','0','2','1', '\2','0','2','2', '\2','0','2','3', '\2','0','2','4',
- '\2','0','2','5', '\2','0','2','6', '\2','0','2','7', '\2','0','2','8', '\2','0','2','9',
- '\2','0','3','0', '\2','0','3','1', '\2','0','3','2', '\2','0','3','3', '\2','0','3','4',
- '\2','0','3','5', '\2','0','3','6', '\2','0','3','7', '\2','0','3','8', '\2','0','3','9',
- '\2','0','4','0', '\2','0','4','1', '\2','0','4','2', '\2','0','4','3', '\2','0','4','4',
- '\2','0','4','5', '\2','0','4','6', '\2','0','4','7', '\2','0','4','8', '\2','0','4','9',
- '\2','0','5','0', '\2','0','5','1', '\2','0','5','2', '\2','0','5','3', '\2','0','5','4',
- '\2','0','5','5', '\2','0','5','6', '\2','0','5','7', '\2','0','5','8', '\2','0','5','9',
- '\2','0','6','0', '\2','0','6','1', '\2','0','6','2', '\2','0','6','3', '\2','0','6','4',
- '\2','0','6','5', '\2','0','6','6', '\2','0','6','7', '\2','0','6','8', '\2','0','6','9',
- '\2','0','7','0', '\2','0','7','1', '\2','0','7','2', '\2','0','7','3', '\2','0','7','4',
- '\2','0','7','5', '\2','0','7','6', '\2','0','7','7', '\2','0','7','8', '\2','0','7','9',
- '\2','0','8','0', '\2','0','8','1', '\2','0','8','2', '\2','0','8','3', '\2','0','8','4',
- '\2','0','8','5', '\2','0','8','6', '\2','0','8','7', '\2','0','8','8', '\2','0','8','9',
- '\2','0','9','0', '\2','0','9','1', '\2','0','9','2', '\2','0','9','3', '\2','0','9','4',
- '\2','0','9','5', '\2','0','9','6', '\2','0','9','7', '\2','0','9','8', '\2','0','9','9',
- '\3','1','0','0', '\3','1','0','1', '\3','1','0','2', '\3','1','0','3', '\3','1','0','4',
- '\3','1','0','5', '\3','1','0','6', '\3','1','0','7', '\3','1','0','8', '\3','1','0','9',
- '\3','1','1','0', '\3','1','1','1', '\3','1','1','2', '\3','1','1','3', '\3','1','1','4',
- '\3','1','1','5', '\3','1','1','6', '\3','1','1','7', '\3','1','1','8', '\3','1','1','9',
- '\3','1','2','0', '\3','1','2','1', '\3','1','2','2', '\3','1','2','3', '\3','1','2','4',
- '\3','1','2','5', '\3','1','2','6', '\3','1','2','7', '\3','1','2','8', '\3','1','2','9',
- '\3','1','3','0', '\3','1','3','1', '\3','1','3','2', '\3','1','3','3', '\3','1','3','4',
- '\3','1','3','5', '\3','1','3','6', '\3','1','3','7', '\3','1','3','8', '\3','1','3','9',
- '\3','1','4','0', '\3','1','4','1', '\3','1','4','2', '\3','1','4','3', '\3','1','4','4',
- '\3','1','4','5', '\3','1','4','6', '\3','1','4','7', '\3','1','4','8', '\3','1','4','9',
- '\3','1','5','0', '\3','1','5','1', '\3','1','5','2', '\3','1','5','3', '\3','1','5','4',
- '\3','1','5','5', '\3','1','5','6', '\3','1','5','7', '\3','1','5','8', '\3','1','5','9',
- '\3','1','6','0', '\3','1','6','1', '\3','1','6','2', '\3','1','6','3', '\3','1','6','4',
- '\3','1','6','5', '\3','1','6','6', '\3','1','6','7', '\3','1','6','8', '\3','1','6','9',
- '\3','1','7','0', '\3','1','7','1', '\3','1','7','2', '\3','1','7','3', '\3','1','7','4',
- '\3','1','7','5', '\3','1','7','6', '\3','1','7','7', '\3','1','7','8', '\3','1','7','9',
- '\3','1','8','0', '\3','1','8','1', '\3','1','8','2', '\3','1','8','3', '\3','1','8','4',
- '\3','1','8','5', '\3','1','8','6', '\3','1','8','7', '\3','1','8','8', '\3','1','8','9',
- '\3','1','9','0', '\3','1','9','1', '\3','1','9','2', '\3','1','9','3', '\3','1','9','4',
- '\3','1','9','5', '\3','1','9','6', '\3','1','9','7', '\3','1','9','8', '\3','1','9','9',
- '\3','2','0','0', '\3','2','0','1', '\3','2','0','2', '\3','2','0','3', '\3','2','0','4',
- '\3','2','0','5', '\3','2','0','6', '\3','2','0','7', '\3','2','0','8', '\3','2','0','9',
- '\3','2','1','0', '\3','2','1','1', '\3','2','1','2', '\3','2','1','3', '\3','2','1','4',
- '\3','2','1','5', '\3','2','1','6', '\3','2','1','7', '\3','2','1','8', '\3','2','1','9',
- '\3','2','2','0', '\3','2','2','1', '\3','2','2','2', '\3','2','2','3', '\3','2','2','4',
- '\3','2','2','5', '\3','2','2','6', '\3','2','2','7', '\3','2','2','8', '\3','2','2','9',
- '\3','2','3','0', '\3','2','3','1', '\3','2','3','2', '\3','2','3','3', '\3','2','3','4',
- '\3','2','3','5', '\3','2','3','6', '\3','2','3','7', '\3','2','3','8', '\3','2','3','9',
- '\3','2','4','0', '\3','2','4','1', '\3','2','4','2', '\3','2','4','3', '\3','2','4','4',
- '\3','2','4','5', '\3','2','4','6', '\3','2','4','7', '\3','2','4','8', '\3','2','4','9',
- '\3','2','5','0', '\3','2','5','1', '\3','2','5','2', '\3','2','5','3', '\3','2','5','4',
- '\3','2','5','5', '\3','2','5','6', '\3','2','5','7', '\3','2','5','8', '\3','2','5','9',
- '\3','2','6','0', '\3','2','6','1', '\3','2','6','2', '\3','2','6','3', '\3','2','6','4',
- '\3','2','6','5', '\3','2','6','6', '\3','2','6','7', '\3','2','6','8', '\3','2','6','9',
- '\3','2','7','0', '\3','2','7','1', '\3','2','7','2', '\3','2','7','3', '\3','2','7','4',
- '\3','2','7','5', '\3','2','7','6', '\3','2','7','7', '\3','2','7','8', '\3','2','7','9',
- '\3','2','8','0', '\3','2','8','1', '\3','2','8','2', '\3','2','8','3', '\3','2','8','4',
- '\3','2','8','5', '\3','2','8','6', '\3','2','8','7', '\3','2','8','8', '\3','2','8','9',
- '\3','2','9','0', '\3','2','9','1', '\3','2','9','2', '\3','2','9','3', '\3','2','9','4',
- '\3','2','9','5', '\3','2','9','6', '\3','2','9','7', '\3','2','9','8', '\3','2','9','9',
- '\3','3','0','0', '\3','3','0','1', '\3','3','0','2', '\3','3','0','3', '\3','3','0','4',
- '\3','3','0','5', '\3','3','0','6', '\3','3','0','7', '\3','3','0','8', '\3','3','0','9',
- '\3','3','1','0', '\3','3','1','1', '\3','3','1','2', '\3','3','1','3', '\3','3','1','4',
- '\3','3','1','5', '\3','3','1','6', '\3','3','1','7', '\3','3','1','8', '\3','3','1','9',
- '\3','3','2','0', '\3','3','2','1', '\3','3','2','2', '\3','3','2','3', '\3','3','2','4',
- '\3','3','2','5', '\3','3','2','6', '\3','3','2','7', '\3','3','2','8', '\3','3','2','9',
- '\3','3','3','0', '\3','3','3','1', '\3','3','3','2', '\3','3','3','3', '\3','3','3','4',
- '\3','3','3','5', '\3','3','3','6', '\3','3','3','7', '\3','3','3','8', '\3','3','3','9',
- '\3','3','4','0', '\3','3','4','1', '\3','3','4','2', '\3','3','4','3', '\3','3','4','4',
- '\3','3','4','5', '\3','3','4','6', '\3','3','4','7', '\3','3','4','8', '\3','3','4','9',
- '\3','3','5','0', '\3','3','5','1', '\3','3','5','2', '\3','3','5','3', '\3','3','5','4',
- '\3','3','5','5', '\3','3','5','6', '\3','3','5','7', '\3','3','5','8', '\3','3','5','9',
- '\3','3','6','0', '\3','3','6','1', '\3','3','6','2', '\3','3','6','3', '\3','3','6','4',
- '\3','3','6','5', '\3','3','6','6', '\3','3','6','7', '\3','3','6','8', '\3','3','6','9',
- '\3','3','7','0', '\3','3','7','1', '\3','3','7','2', '\3','3','7','3', '\3','3','7','4',
- '\3','3','7','5', '\3','3','7','6', '\3','3','7','7', '\3','3','7','8', '\3','3','7','9',
- '\3','3','8','0', '\3','3','8','1', '\3','3','8','2', '\3','3','8','3', '\3','3','8','4',
- '\3','3','8','5', '\3','3','8','6', '\3','3','8','7', '\3','3','8','8', '\3','3','8','9',
- '\3','3','9','0', '\3','3','9','1', '\3','3','9','2', '\3','3','9','3', '\3','3','9','4',
- '\3','3','9','5', '\3','3','9','6', '\3','3','9','7', '\3','3','9','8', '\3','3','9','9',
- '\3','4','0','0', '\3','4','0','1', '\3','4','0','2', '\3','4','0','3', '\3','4','0','4',
- '\3','4','0','5', '\3','4','0','6', '\3','4','0','7', '\3','4','0','8', '\3','4','0','9',
- '\3','4','1','0', '\3','4','1','1', '\3','4','1','2', '\3','4','1','3', '\3','4','1','4',
- '\3','4','1','5', '\3','4','1','6', '\3','4','1','7', '\3','4','1','8', '\3','4','1','9',
- '\3','4','2','0', '\3','4','2','1', '\3','4','2','2', '\3','4','2','3', '\3','4','2','4',
- '\3','4','2','5', '\3','4','2','6', '\3','4','2','7', '\3','4','2','8', '\3','4','2','9',
- '\3','4','3','0', '\3','4','3','1', '\3','4','3','2', '\3','4','3','3', '\3','4','3','4',
- '\3','4','3','5', '\3','4','3','6', '\3','4','3','7', '\3','4','3','8', '\3','4','3','9',
- '\3','4','4','0', '\3','4','4','1', '\3','4','4','2', '\3','4','4','3', '\3','4','4','4',
- '\3','4','4','5', '\3','4','4','6', '\3','4','4','7', '\3','4','4','8', '\3','4','4','9',
- '\3','4','5','0', '\3','4','5','1', '\3','4','5','2', '\3','4','5','3', '\3','4','5','4',
- '\3','4','5','5', '\3','4','5','6', '\3','4','5','7', '\3','4','5','8', '\3','4','5','9',
- '\3','4','6','0', '\3','4','6','1', '\3','4','6','2', '\3','4','6','3', '\3','4','6','4',
- '\3','4','6','5', '\3','4','6','6', '\3','4','6','7', '\3','4','6','8', '\3','4','6','9',
- '\3','4','7','0', '\3','4','7','1', '\3','4','7','2', '\3','4','7','3', '\3','4','7','4',
- '\3','4','7','5', '\3','4','7','6', '\3','4','7','7', '\3','4','7','8', '\3','4','7','9',
- '\3','4','8','0', '\3','4','8','1', '\3','4','8','2', '\3','4','8','3', '\3','4','8','4',
- '\3','4','8','5', '\3','4','8','6', '\3','4','8','7', '\3','4','8','8', '\3','4','8','9',
- '\3','4','9','0', '\3','4','9','1', '\3','4','9','2', '\3','4','9','3', '\3','4','9','4',
- '\3','4','9','5', '\3','4','9','6', '\3','4','9','7', '\3','4','9','8', '\3','4','9','9',
- '\3','5','0','0', '\3','5','0','1', '\3','5','0','2', '\3','5','0','3', '\3','5','0','4',
- '\3','5','0','5', '\3','5','0','6', '\3','5','0','7', '\3','5','0','8', '\3','5','0','9',
- '\3','5','1','0', '\3','5','1','1', '\3','5','1','2', '\3','5','1','3', '\3','5','1','4',
- '\3','5','1','5', '\3','5','1','6', '\3','5','1','7', '\3','5','1','8', '\3','5','1','9',
- '\3','5','2','0', '\3','5','2','1', '\3','5','2','2', '\3','5','2','3', '\3','5','2','4',
- '\3','5','2','5', '\3','5','2','6', '\3','5','2','7', '\3','5','2','8', '\3','5','2','9',
- '\3','5','3','0', '\3','5','3','1', '\3','5','3','2', '\3','5','3','3', '\3','5','3','4',
- '\3','5','3','5', '\3','5','3','6', '\3','5','3','7', '\3','5','3','8', '\3','5','3','9',
- '\3','5','4','0', '\3','5','4','1', '\3','5','4','2', '\3','5','4','3', '\3','5','4','4',
- '\3','5','4','5', '\3','5','4','6', '\3','5','4','7', '\3','5','4','8', '\3','5','4','9',
- '\3','5','5','0', '\3','5','5','1', '\3','5','5','2', '\3','5','5','3', '\3','5','5','4',
- '\3','5','5','5', '\3','5','5','6', '\3','5','5','7', '\3','5','5','8', '\3','5','5','9',
- '\3','5','6','0', '\3','5','6','1', '\3','5','6','2', '\3','5','6','3', '\3','5','6','4',
- '\3','5','6','5', '\3','5','6','6', '\3','5','6','7', '\3','5','6','8', '\3','5','6','9',
- '\3','5','7','0', '\3','5','7','1', '\3','5','7','2', '\3','5','7','3', '\3','5','7','4',
- '\3','5','7','5', '\3','5','7','6', '\3','5','7','7', '\3','5','7','8', '\3','5','7','9',
- '\3','5','8','0', '\3','5','8','1', '\3','5','8','2', '\3','5','8','3', '\3','5','8','4',
- '\3','5','8','5', '\3','5','8','6', '\3','5','8','7', '\3','5','8','8', '\3','5','8','9',
- '\3','5','9','0', '\3','5','9','1', '\3','5','9','2', '\3','5','9','3', '\3','5','9','4',
- '\3','5','9','5', '\3','5','9','6', '\3','5','9','7', '\3','5','9','8', '\3','5','9','9',
- '\3','6','0','0', '\3','6','0','1', '\3','6','0','2', '\3','6','0','3', '\3','6','0','4',
- '\3','6','0','5', '\3','6','0','6', '\3','6','0','7', '\3','6','0','8', '\3','6','0','9',
- '\3','6','1','0', '\3','6','1','1', '\3','6','1','2', '\3','6','1','3', '\3','6','1','4',
- '\3','6','1','5', '\3','6','1','6', '\3','6','1','7', '\3','6','1','8', '\3','6','1','9',
- '\3','6','2','0', '\3','6','2','1', '\3','6','2','2', '\3','6','2','3', '\3','6','2','4',
- '\3','6','2','5', '\3','6','2','6', '\3','6','2','7', '\3','6','2','8', '\3','6','2','9',
- '\3','6','3','0', '\3','6','3','1', '\3','6','3','2', '\3','6','3','3', '\3','6','3','4',
- '\3','6','3','5', '\3','6','3','6', '\3','6','3','7', '\3','6','3','8', '\3','6','3','9',
- '\3','6','4','0', '\3','6','4','1', '\3','6','4','2', '\3','6','4','3', '\3','6','4','4',
- '\3','6','4','5', '\3','6','4','6', '\3','6','4','7', '\3','6','4','8', '\3','6','4','9',
- '\3','6','5','0', '\3','6','5','1', '\3','6','5','2', '\3','6','5','3', '\3','6','5','4',
- '\3','6','5','5', '\3','6','5','6', '\3','6','5','7', '\3','6','5','8', '\3','6','5','9',
- '\3','6','6','0', '\3','6','6','1', '\3','6','6','2', '\3','6','6','3', '\3','6','6','4',
- '\3','6','6','5', '\3','6','6','6', '\3','6','6','7', '\3','6','6','8', '\3','6','6','9',
- '\3','6','7','0', '\3','6','7','1', '\3','6','7','2', '\3','6','7','3', '\3','6','7','4',
- '\3','6','7','5', '\3','6','7','6', '\3','6','7','7', '\3','6','7','8', '\3','6','7','9',
- '\3','6','8','0', '\3','6','8','1', '\3','6','8','2', '\3','6','8','3', '\3','6','8','4',
- '\3','6','8','5', '\3','6','8','6', '\3','6','8','7', '\3','6','8','8', '\3','6','8','9',
- '\3','6','9','0', '\3','6','9','1', '\3','6','9','2', '\3','6','9','3', '\3','6','9','4',
- '\3','6','9','5', '\3','6','9','6', '\3','6','9','7', '\3','6','9','8', '\3','6','9','9',
- '\3','7','0','0', '\3','7','0','1', '\3','7','0','2', '\3','7','0','3', '\3','7','0','4',
- '\3','7','0','5', '\3','7','0','6', '\3','7','0','7', '\3','7','0','8', '\3','7','0','9',
- '\3','7','1','0', '\3','7','1','1', '\3','7','1','2', '\3','7','1','3', '\3','7','1','4',
- '\3','7','1','5', '\3','7','1','6', '\3','7','1','7', '\3','7','1','8', '\3','7','1','9',
- '\3','7','2','0', '\3','7','2','1', '\3','7','2','2', '\3','7','2','3', '\3','7','2','4',
- '\3','7','2','5', '\3','7','2','6', '\3','7','2','7', '\3','7','2','8', '\3','7','2','9',
- '\3','7','3','0', '\3','7','3','1', '\3','7','3','2', '\3','7','3','3', '\3','7','3','4',
- '\3','7','3','5', '\3','7','3','6', '\3','7','3','7', '\3','7','3','8', '\3','7','3','9',
- '\3','7','4','0', '\3','7','4','1', '\3','7','4','2', '\3','7','4','3', '\3','7','4','4',
- '\3','7','4','5', '\3','7','4','6', '\3','7','4','7', '\3','7','4','8', '\3','7','4','9',
- '\3','7','5','0', '\3','7','5','1', '\3','7','5','2', '\3','7','5','3', '\3','7','5','4',
- '\3','7','5','5', '\3','7','5','6', '\3','7','5','7', '\3','7','5','8', '\3','7','5','9',
- '\3','7','6','0', '\3','7','6','1', '\3','7','6','2', '\3','7','6','3', '\3','7','6','4',
- '\3','7','6','5', '\3','7','6','6', '\3','7','6','7', '\3','7','6','8', '\3','7','6','9',
- '\3','7','7','0', '\3','7','7','1', '\3','7','7','2', '\3','7','7','3', '\3','7','7','4',
- '\3','7','7','5', '\3','7','7','6', '\3','7','7','7', '\3','7','7','8', '\3','7','7','9',
- '\3','7','8','0', '\3','7','8','1', '\3','7','8','2', '\3','7','8','3', '\3','7','8','4',
- '\3','7','8','5', '\3','7','8','6', '\3','7','8','7', '\3','7','8','8', '\3','7','8','9',
- '\3','7','9','0', '\3','7','9','1', '\3','7','9','2', '\3','7','9','3', '\3','7','9','4',
- '\3','7','9','5', '\3','7','9','6', '\3','7','9','7', '\3','7','9','8', '\3','7','9','9',
- '\3','8','0','0', '\3','8','0','1', '\3','8','0','2', '\3','8','0','3', '\3','8','0','4',
- '\3','8','0','5', '\3','8','0','6', '\3','8','0','7', '\3','8','0','8', '\3','8','0','9',
- '\3','8','1','0', '\3','8','1','1', '\3','8','1','2', '\3','8','1','3', '\3','8','1','4',
- '\3','8','1','5', '\3','8','1','6', '\3','8','1','7', '\3','8','1','8', '\3','8','1','9',
- '\3','8','2','0', '\3','8','2','1', '\3','8','2','2', '\3','8','2','3', '\3','8','2','4',
- '\3','8','2','5', '\3','8','2','6', '\3','8','2','7', '\3','8','2','8', '\3','8','2','9',
- '\3','8','3','0', '\3','8','3','1', '\3','8','3','2', '\3','8','3','3', '\3','8','3','4',
- '\3','8','3','5', '\3','8','3','6', '\3','8','3','7', '\3','8','3','8', '\3','8','3','9',
- '\3','8','4','0', '\3','8','4','1', '\3','8','4','2', '\3','8','4','3', '\3','8','4','4',
- '\3','8','4','5', '\3','8','4','6', '\3','8','4','7', '\3','8','4','8', '\3','8','4','9',
- '\3','8','5','0', '\3','8','5','1', '\3','8','5','2', '\3','8','5','3', '\3','8','5','4',
- '\3','8','5','5', '\3','8','5','6', '\3','8','5','7', '\3','8','5','8', '\3','8','5','9',
- '\3','8','6','0', '\3','8','6','1', '\3','8','6','2', '\3','8','6','3', '\3','8','6','4',
- '\3','8','6','5', '\3','8','6','6', '\3','8','6','7', '\3','8','6','8', '\3','8','6','9',
- '\3','8','7','0', '\3','8','7','1', '\3','8','7','2', '\3','8','7','3', '\3','8','7','4',
- '\3','8','7','5', '\3','8','7','6', '\3','8','7','7', '\3','8','7','8', '\3','8','7','9',
- '\3','8','8','0', '\3','8','8','1', '\3','8','8','2', '\3','8','8','3', '\3','8','8','4',
- '\3','8','8','5', '\3','8','8','6', '\3','8','8','7', '\3','8','8','8', '\3','8','8','9',
- '\3','8','9','0', '\3','8','9','1', '\3','8','9','2', '\3','8','9','3', '\3','8','9','4',
- '\3','8','9','5', '\3','8','9','6', '\3','8','9','7', '\3','8','9','8', '\3','8','9','9',
- '\3','9','0','0', '\3','9','0','1', '\3','9','0','2', '\3','9','0','3', '\3','9','0','4',
- '\3','9','0','5', '\3','9','0','6', '\3','9','0','7', '\3','9','0','8', '\3','9','0','9',
- '\3','9','1','0', '\3','9','1','1', '\3','9','1','2', '\3','9','1','3', '\3','9','1','4',
- '\3','9','1','5', '\3','9','1','6', '\3','9','1','7', '\3','9','1','8', '\3','9','1','9',
- '\3','9','2','0', '\3','9','2','1', '\3','9','2','2', '\3','9','2','3', '\3','9','2','4',
- '\3','9','2','5', '\3','9','2','6', '\3','9','2','7', '\3','9','2','8', '\3','9','2','9',
- '\3','9','3','0', '\3','9','3','1', '\3','9','3','2', '\3','9','3','3', '\3','9','3','4',
- '\3','9','3','5', '\3','9','3','6', '\3','9','3','7', '\3','9','3','8', '\3','9','3','9',
- '\3','9','4','0', '\3','9','4','1', '\3','9','4','2', '\3','9','4','3', '\3','9','4','4',
- '\3','9','4','5', '\3','9','4','6', '\3','9','4','7', '\3','9','4','8', '\3','9','4','9',
- '\3','9','5','0', '\3','9','5','1', '\3','9','5','2', '\3','9','5','3', '\3','9','5','4',
- '\3','9','5','5', '\3','9','5','6', '\3','9','5','7', '\3','9','5','8', '\3','9','5','9',
- '\3','9','6','0', '\3','9','6','1', '\3','9','6','2', '\3','9','6','3', '\3','9','6','4',
- '\3','9','6','5', '\3','9','6','6', '\3','9','6','7', '\3','9','6','8', '\3','9','6','9',
- '\3','9','7','0', '\3','9','7','1', '\3','9','7','2', '\3','9','7','3', '\3','9','7','4',
- '\3','9','7','5', '\3','9','7','6', '\3','9','7','7', '\3','9','7','8', '\3','9','7','9',
- '\3','9','8','0', '\3','9','8','1', '\3','9','8','2', '\3','9','8','3', '\3','9','8','4',
- '\3','9','8','5', '\3','9','8','6', '\3','9','8','7', '\3','9','8','8', '\3','9','8','9',
- '\3','9','9','0', '\3','9','9','1', '\3','9','9','2', '\3','9','9','3', '\3','9','9','4',
- '\3','9','9','5', '\3','9','9','6', '\3','9','9','7', '\3','9','9','8', '\3','9','9','9', '\0'};
-#endif
-
-#if defined(DEC_DPD2BCD8) && DEC_DPD2BCD8==1 && !defined(DECDPD2BCD8)
-#define DECDPD2BCD8
-
-const uint8_t DPD2BCD8[4096]={
- 0,0,0,0, 0,0,1,1, 0,0,2,1, 0,0,3,1, 0,0,4,1, 0,0,5,1, 0,0,6,1, 0,0,7,1, 0,0,8,1,
- 0,0,9,1, 0,8,0,2, 0,8,1,2, 8,0,0,3, 8,0,1,3, 8,8,0,3, 8,8,1,3, 0,1,0,2, 0,1,1,2,
- 0,1,2,2, 0,1,3,2, 0,1,4,2, 0,1,5,2, 0,1,6,2, 0,1,7,2, 0,1,8,2, 0,1,9,2, 0,9,0,2,
- 0,9,1,2, 8,1,0,3, 8,1,1,3, 8,9,0,3, 8,9,1,3, 0,2,0,2, 0,2,1,2, 0,2,2,2, 0,2,3,2,
- 0,2,4,2, 0,2,5,2, 0,2,6,2, 0,2,7,2, 0,2,8,2, 0,2,9,2, 0,8,2,2, 0,8,3,2, 8,2,0,3,
- 8,2,1,3, 8,0,8,3, 8,0,9,3, 0,3,0,2, 0,3,1,2, 0,3,2,2, 0,3,3,2, 0,3,4,2, 0,3,5,2,
- 0,3,6,2, 0,3,7,2, 0,3,8,2, 0,3,9,2, 0,9,2,2, 0,9,3,2, 8,3,0,3, 8,3,1,3, 8,1,8,3,
- 8,1,9,3, 0,4,0,2, 0,4,1,2, 0,4,2,2, 0,4,3,2, 0,4,4,2, 0,4,5,2, 0,4,6,2, 0,4,7,2,
- 0,4,8,2, 0,4,9,2, 0,8,4,2, 0,8,5,2, 8,4,0,3, 8,4,1,3, 0,8,8,2, 0,8,9,2, 0,5,0,2,
- 0,5,1,2, 0,5,2,2, 0,5,3,2, 0,5,4,2, 0,5,5,2, 0,5,6,2, 0,5,7,2, 0,5,8,2, 0,5,9,2,
- 0,9,4,2, 0,9,5,2, 8,5,0,3, 8,5,1,3, 0,9,8,2, 0,9,9,2, 0,6,0,2, 0,6,1,2, 0,6,2,2,
- 0,6,3,2, 0,6,4,2, 0,6,5,2, 0,6,6,2, 0,6,7,2, 0,6,8,2, 0,6,9,2, 0,8,6,2, 0,8,7,2,
- 8,6,0,3, 8,6,1,3, 8,8,8,3, 8,8,9,3, 0,7,0,2, 0,7,1,2, 0,7,2,2, 0,7,3,2, 0,7,4,2,
- 0,7,5,2, 0,7,6,2, 0,7,7,2, 0,7,8,2, 0,7,9,2, 0,9,6,2, 0,9,7,2, 8,7,0,3, 8,7,1,3,
- 8,9,8,3, 8,9,9,3, 1,0,0,3, 1,0,1,3, 1,0,2,3, 1,0,3,3, 1,0,4,3, 1,0,5,3, 1,0,6,3,
- 1,0,7,3, 1,0,8,3, 1,0,9,3, 1,8,0,3, 1,8,1,3, 9,0,0,3, 9,0,1,3, 9,8,0,3, 9,8,1,3,
- 1,1,0,3, 1,1,1,3, 1,1,2,3, 1,1,3,3, 1,1,4,3, 1,1,5,3, 1,1,6,3, 1,1,7,3, 1,1,8,3,
- 1,1,9,3, 1,9,0,3, 1,9,1,3, 9,1,0,3, 9,1,1,3, 9,9,0,3, 9,9,1,3, 1,2,0,3, 1,2,1,3,
- 1,2,2,3, 1,2,3,3, 1,2,4,3, 1,2,5,3, 1,2,6,3, 1,2,7,3, 1,2,8,3, 1,2,9,3, 1,8,2,3,
- 1,8,3,3, 9,2,0,3, 9,2,1,3, 9,0,8,3, 9,0,9,3, 1,3,0,3, 1,3,1,3, 1,3,2,3, 1,3,3,3,
- 1,3,4,3, 1,3,5,3, 1,3,6,3, 1,3,7,3, 1,3,8,3, 1,3,9,3, 1,9,2,3, 1,9,3,3, 9,3,0,3,
- 9,3,1,3, 9,1,8,3, 9,1,9,3, 1,4,0,3, 1,4,1,3, 1,4,2,3, 1,4,3,3, 1,4,4,3, 1,4,5,3,
- 1,4,6,3, 1,4,7,3, 1,4,8,3, 1,4,9,3, 1,8,4,3, 1,8,5,3, 9,4,0,3, 9,4,1,3, 1,8,8,3,
- 1,8,9,3, 1,5,0,3, 1,5,1,3, 1,5,2,3, 1,5,3,3, 1,5,4,3, 1,5,5,3, 1,5,6,3, 1,5,7,3,
- 1,5,8,3, 1,5,9,3, 1,9,4,3, 1,9,5,3, 9,5,0,3, 9,5,1,3, 1,9,8,3, 1,9,9,3, 1,6,0,3,
- 1,6,1,3, 1,6,2,3, 1,6,3,3, 1,6,4,3, 1,6,5,3, 1,6,6,3, 1,6,7,3, 1,6,8,3, 1,6,9,3,
- 1,8,6,3, 1,8,7,3, 9,6,0,3, 9,6,1,3, 9,8,8,3, 9,8,9,3, 1,7,0,3, 1,7,1,3, 1,7,2,3,
- 1,7,3,3, 1,7,4,3, 1,7,5,3, 1,7,6,3, 1,7,7,3, 1,7,8,3, 1,7,9,3, 1,9,6,3, 1,9,7,3,
- 9,7,0,3, 9,7,1,3, 9,9,8,3, 9,9,9,3, 2,0,0,3, 2,0,1,3, 2,0,2,3, 2,0,3,3, 2,0,4,3,
- 2,0,5,3, 2,0,6,3, 2,0,7,3, 2,0,8,3, 2,0,9,3, 2,8,0,3, 2,8,1,3, 8,0,2,3, 8,0,3,3,
- 8,8,2,3, 8,8,3,3, 2,1,0,3, 2,1,1,3, 2,1,2,3, 2,1,3,3, 2,1,4,3, 2,1,5,3, 2,1,6,3,
- 2,1,7,3, 2,1,8,3, 2,1,9,3, 2,9,0,3, 2,9,1,3, 8,1,2,3, 8,1,3,3, 8,9,2,3, 8,9,3,3,
- 2,2,0,3, 2,2,1,3, 2,2,2,3, 2,2,3,3, 2,2,4,3, 2,2,5,3, 2,2,6,3, 2,2,7,3, 2,2,8,3,
- 2,2,9,3, 2,8,2,3, 2,8,3,3, 8,2,2,3, 8,2,3,3, 8,2,8,3, 8,2,9,3, 2,3,0,3, 2,3,1,3,
- 2,3,2,3, 2,3,3,3, 2,3,4,3, 2,3,5,3, 2,3,6,3, 2,3,7,3, 2,3,8,3, 2,3,9,3, 2,9,2,3,
- 2,9,3,3, 8,3,2,3, 8,3,3,3, 8,3,8,3, 8,3,9,3, 2,4,0,3, 2,4,1,3, 2,4,2,3, 2,4,3,3,
- 2,4,4,3, 2,4,5,3, 2,4,6,3, 2,4,7,3, 2,4,8,3, 2,4,9,3, 2,8,4,3, 2,8,5,3, 8,4,2,3,
- 8,4,3,3, 2,8,8,3, 2,8,9,3, 2,5,0,3, 2,5,1,3, 2,5,2,3, 2,5,3,3, 2,5,4,3, 2,5,5,3,
- 2,5,6,3, 2,5,7,3, 2,5,8,3, 2,5,9,3, 2,9,4,3, 2,9,5,3, 8,5,2,3, 8,5,3,3, 2,9,8,3,
- 2,9,9,3, 2,6,0,3, 2,6,1,3, 2,6,2,3, 2,6,3,3, 2,6,4,3, 2,6,5,3, 2,6,6,3, 2,6,7,3,
- 2,6,8,3, 2,6,9,3, 2,8,6,3, 2,8,7,3, 8,6,2,3, 8,6,3,3, 8,8,8,3, 8,8,9,3, 2,7,0,3,
- 2,7,1,3, 2,7,2,3, 2,7,3,3, 2,7,4,3, 2,7,5,3, 2,7,6,3, 2,7,7,3, 2,7,8,3, 2,7,9,3,
- 2,9,6,3, 2,9,7,3, 8,7,2,3, 8,7,3,3, 8,9,8,3, 8,9,9,3, 3,0,0,3, 3,0,1,3, 3,0,2,3,
- 3,0,3,3, 3,0,4,3, 3,0,5,3, 3,0,6,3, 3,0,7,3, 3,0,8,3, 3,0,9,3, 3,8,0,3, 3,8,1,3,
- 9,0,2,3, 9,0,3,3, 9,8,2,3, 9,8,3,3, 3,1,0,3, 3,1,1,3, 3,1,2,3, 3,1,3,3, 3,1,4,3,
- 3,1,5,3, 3,1,6,3, 3,1,7,3, 3,1,8,3, 3,1,9,3, 3,9,0,3, 3,9,1,3, 9,1,2,3, 9,1,3,3,
- 9,9,2,3, 9,9,3,3, 3,2,0,3, 3,2,1,3, 3,2,2,3, 3,2,3,3, 3,2,4,3, 3,2,5,3, 3,2,6,3,
- 3,2,7,3, 3,2,8,3, 3,2,9,3, 3,8,2,3, 3,8,3,3, 9,2,2,3, 9,2,3,3, 9,2,8,3, 9,2,9,3,
- 3,3,0,3, 3,3,1,3, 3,3,2,3, 3,3,3,3, 3,3,4,3, 3,3,5,3, 3,3,6,3, 3,3,7,3, 3,3,8,3,
- 3,3,9,3, 3,9,2,3, 3,9,3,3, 9,3,2,3, 9,3,3,3, 9,3,8,3, 9,3,9,3, 3,4,0,3, 3,4,1,3,
- 3,4,2,3, 3,4,3,3, 3,4,4,3, 3,4,5,3, 3,4,6,3, 3,4,7,3, 3,4,8,3, 3,4,9,3, 3,8,4,3,
- 3,8,5,3, 9,4,2,3, 9,4,3,3, 3,8,8,3, 3,8,9,3, 3,5,0,3, 3,5,1,3, 3,5,2,3, 3,5,3,3,
- 3,5,4,3, 3,5,5,3, 3,5,6,3, 3,5,7,3, 3,5,8,3, 3,5,9,3, 3,9,4,3, 3,9,5,3, 9,5,2,3,
- 9,5,3,3, 3,9,8,3, 3,9,9,3, 3,6,0,3, 3,6,1,3, 3,6,2,3, 3,6,3,3, 3,6,4,3, 3,6,5,3,
- 3,6,6,3, 3,6,7,3, 3,6,8,3, 3,6,9,3, 3,8,6,3, 3,8,7,3, 9,6,2,3, 9,6,3,3, 9,8,8,3,
- 9,8,9,3, 3,7,0,3, 3,7,1,3, 3,7,2,3, 3,7,3,3, 3,7,4,3, 3,7,5,3, 3,7,6,3, 3,7,7,3,
- 3,7,8,3, 3,7,9,3, 3,9,6,3, 3,9,7,3, 9,7,2,3, 9,7,3,3, 9,9,8,3, 9,9,9,3, 4,0,0,3,
- 4,0,1,3, 4,0,2,3, 4,0,3,3, 4,0,4,3, 4,0,5,3, 4,0,6,3, 4,0,7,3, 4,0,8,3, 4,0,9,3,
- 4,8,0,3, 4,8,1,3, 8,0,4,3, 8,0,5,3, 8,8,4,3, 8,8,5,3, 4,1,0,3, 4,1,1,3, 4,1,2,3,
- 4,1,3,3, 4,1,4,3, 4,1,5,3, 4,1,6,3, 4,1,7,3, 4,1,8,3, 4,1,9,3, 4,9,0,3, 4,9,1,3,
- 8,1,4,3, 8,1,5,3, 8,9,4,3, 8,9,5,3, 4,2,0,3, 4,2,1,3, 4,2,2,3, 4,2,3,3, 4,2,4,3,
- 4,2,5,3, 4,2,6,3, 4,2,7,3, 4,2,8,3, 4,2,9,3, 4,8,2,3, 4,8,3,3, 8,2,4,3, 8,2,5,3,
- 8,4,8,3, 8,4,9,3, 4,3,0,3, 4,3,1,3, 4,3,2,3, 4,3,3,3, 4,3,4,3, 4,3,5,3, 4,3,6,3,
- 4,3,7,3, 4,3,8,3, 4,3,9,3, 4,9,2,3, 4,9,3,3, 8,3,4,3, 8,3,5,3, 8,5,8,3, 8,5,9,3,
- 4,4,0,3, 4,4,1,3, 4,4,2,3, 4,4,3,3, 4,4,4,3, 4,4,5,3, 4,4,6,3, 4,4,7,3, 4,4,8,3,
- 4,4,9,3, 4,8,4,3, 4,8,5,3, 8,4,4,3, 8,4,5,3, 4,8,8,3, 4,8,9,3, 4,5,0,3, 4,5,1,3,
- 4,5,2,3, 4,5,3,3, 4,5,4,3, 4,5,5,3, 4,5,6,3, 4,5,7,3, 4,5,8,3, 4,5,9,3, 4,9,4,3,
- 4,9,5,3, 8,5,4,3, 8,5,5,3, 4,9,8,3, 4,9,9,3, 4,6,0,3, 4,6,1,3, 4,6,2,3, 4,6,3,3,
- 4,6,4,3, 4,6,5,3, 4,6,6,3, 4,6,7,3, 4,6,8,3, 4,6,9,3, 4,8,6,3, 4,8,7,3, 8,6,4,3,
- 8,6,5,3, 8,8,8,3, 8,8,9,3, 4,7,0,3, 4,7,1,3, 4,7,2,3, 4,7,3,3, 4,7,4,3, 4,7,5,3,
- 4,7,6,3, 4,7,7,3, 4,7,8,3, 4,7,9,3, 4,9,6,3, 4,9,7,3, 8,7,4,3, 8,7,5,3, 8,9,8,3,
- 8,9,9,3, 5,0,0,3, 5,0,1,3, 5,0,2,3, 5,0,3,3, 5,0,4,3, 5,0,5,3, 5,0,6,3, 5,0,7,3,
- 5,0,8,3, 5,0,9,3, 5,8,0,3, 5,8,1,3, 9,0,4,3, 9,0,5,3, 9,8,4,3, 9,8,5,3, 5,1,0,3,
- 5,1,1,3, 5,1,2,3, 5,1,3,3, 5,1,4,3, 5,1,5,3, 5,1,6,3, 5,1,7,3, 5,1,8,3, 5,1,9,3,
- 5,9,0,3, 5,9,1,3, 9,1,4,3, 9,1,5,3, 9,9,4,3, 9,9,5,3, 5,2,0,3, 5,2,1,3, 5,2,2,3,
- 5,2,3,3, 5,2,4,3, 5,2,5,3, 5,2,6,3, 5,2,7,3, 5,2,8,3, 5,2,9,3, 5,8,2,3, 5,8,3,3,
- 9,2,4,3, 9,2,5,3, 9,4,8,3, 9,4,9,3, 5,3,0,3, 5,3,1,3, 5,3,2,3, 5,3,3,3, 5,3,4,3,
- 5,3,5,3, 5,3,6,3, 5,3,7,3, 5,3,8,3, 5,3,9,3, 5,9,2,3, 5,9,3,3, 9,3,4,3, 9,3,5,3,
- 9,5,8,3, 9,5,9,3, 5,4,0,3, 5,4,1,3, 5,4,2,3, 5,4,3,3, 5,4,4,3, 5,4,5,3, 5,4,6,3,
- 5,4,7,3, 5,4,8,3, 5,4,9,3, 5,8,4,3, 5,8,5,3, 9,4,4,3, 9,4,5,3, 5,8,8,3, 5,8,9,3,
- 5,5,0,3, 5,5,1,3, 5,5,2,3, 5,5,3,3, 5,5,4,3, 5,5,5,3, 5,5,6,3, 5,5,7,3, 5,5,8,3,
- 5,5,9,3, 5,9,4,3, 5,9,5,3, 9,5,4,3, 9,5,5,3, 5,9,8,3, 5,9,9,3, 5,6,0,3, 5,6,1,3,
- 5,6,2,3, 5,6,3,3, 5,6,4,3, 5,6,5,3, 5,6,6,3, 5,6,7,3, 5,6,8,3, 5,6,9,3, 5,8,6,3,
- 5,8,7,3, 9,6,4,3, 9,6,5,3, 9,8,8,3, 9,8,9,3, 5,7,0,3, 5,7,1,3, 5,7,2,3, 5,7,3,3,
- 5,7,4,3, 5,7,5,3, 5,7,6,3, 5,7,7,3, 5,7,8,3, 5,7,9,3, 5,9,6,3, 5,9,7,3, 9,7,4,3,
- 9,7,5,3, 9,9,8,3, 9,9,9,3, 6,0,0,3, 6,0,1,3, 6,0,2,3, 6,0,3,3, 6,0,4,3, 6,0,5,3,
- 6,0,6,3, 6,0,7,3, 6,0,8,3, 6,0,9,3, 6,8,0,3, 6,8,1,3, 8,0,6,3, 8,0,7,3, 8,8,6,3,
- 8,8,7,3, 6,1,0,3, 6,1,1,3, 6,1,2,3, 6,1,3,3, 6,1,4,3, 6,1,5,3, 6,1,6,3, 6,1,7,3,
- 6,1,8,3, 6,1,9,3, 6,9,0,3, 6,9,1,3, 8,1,6,3, 8,1,7,3, 8,9,6,3, 8,9,7,3, 6,2,0,3,
- 6,2,1,3, 6,2,2,3, 6,2,3,3, 6,2,4,3, 6,2,5,3, 6,2,6,3, 6,2,7,3, 6,2,8,3, 6,2,9,3,
- 6,8,2,3, 6,8,3,3, 8,2,6,3, 8,2,7,3, 8,6,8,3, 8,6,9,3, 6,3,0,3, 6,3,1,3, 6,3,2,3,
- 6,3,3,3, 6,3,4,3, 6,3,5,3, 6,3,6,3, 6,3,7,3, 6,3,8,3, 6,3,9,3, 6,9,2,3, 6,9,3,3,
- 8,3,6,3, 8,3,7,3, 8,7,8,3, 8,7,9,3, 6,4,0,3, 6,4,1,3, 6,4,2,3, 6,4,3,3, 6,4,4,3,
- 6,4,5,3, 6,4,6,3, 6,4,7,3, 6,4,8,3, 6,4,9,3, 6,8,4,3, 6,8,5,3, 8,4,6,3, 8,4,7,3,
- 6,8,8,3, 6,8,9,3, 6,5,0,3, 6,5,1,3, 6,5,2,3, 6,5,3,3, 6,5,4,3, 6,5,5,3, 6,5,6,3,
- 6,5,7,3, 6,5,8,3, 6,5,9,3, 6,9,4,3, 6,9,5,3, 8,5,6,3, 8,5,7,3, 6,9,8,3, 6,9,9,3,
- 6,6,0,3, 6,6,1,3, 6,6,2,3, 6,6,3,3, 6,6,4,3, 6,6,5,3, 6,6,6,3, 6,6,7,3, 6,6,8,3,
- 6,6,9,3, 6,8,6,3, 6,8,7,3, 8,6,6,3, 8,6,7,3, 8,8,8,3, 8,8,9,3, 6,7,0,3, 6,7,1,3,
- 6,7,2,3, 6,7,3,3, 6,7,4,3, 6,7,5,3, 6,7,6,3, 6,7,7,3, 6,7,8,3, 6,7,9,3, 6,9,6,3,
- 6,9,7,3, 8,7,6,3, 8,7,7,3, 8,9,8,3, 8,9,9,3, 7,0,0,3, 7,0,1,3, 7,0,2,3, 7,0,3,3,
- 7,0,4,3, 7,0,5,3, 7,0,6,3, 7,0,7,3, 7,0,8,3, 7,0,9,3, 7,8,0,3, 7,8,1,3, 9,0,6,3,
- 9,0,7,3, 9,8,6,3, 9,8,7,3, 7,1,0,3, 7,1,1,3, 7,1,2,3, 7,1,3,3, 7,1,4,3, 7,1,5,3,
- 7,1,6,3, 7,1,7,3, 7,1,8,3, 7,1,9,3, 7,9,0,3, 7,9,1,3, 9,1,6,3, 9,1,7,3, 9,9,6,3,
- 9,9,7,3, 7,2,0,3, 7,2,1,3, 7,2,2,3, 7,2,3,3, 7,2,4,3, 7,2,5,3, 7,2,6,3, 7,2,7,3,
- 7,2,8,3, 7,2,9,3, 7,8,2,3, 7,8,3,3, 9,2,6,3, 9,2,7,3, 9,6,8,3, 9,6,9,3, 7,3,0,3,
- 7,3,1,3, 7,3,2,3, 7,3,3,3, 7,3,4,3, 7,3,5,3, 7,3,6,3, 7,3,7,3, 7,3,8,3, 7,3,9,3,
- 7,9,2,3, 7,9,3,3, 9,3,6,3, 9,3,7,3, 9,7,8,3, 9,7,9,3, 7,4,0,3, 7,4,1,3, 7,4,2,3,
- 7,4,3,3, 7,4,4,3, 7,4,5,3, 7,4,6,3, 7,4,7,3, 7,4,8,3, 7,4,9,3, 7,8,4,3, 7,8,5,3,
- 9,4,6,3, 9,4,7,3, 7,8,8,3, 7,8,9,3, 7,5,0,3, 7,5,1,3, 7,5,2,3, 7,5,3,3, 7,5,4,3,
- 7,5,5,3, 7,5,6,3, 7,5,7,3, 7,5,8,3, 7,5,9,3, 7,9,4,3, 7,9,5,3, 9,5,6,3, 9,5,7,3,
- 7,9,8,3, 7,9,9,3, 7,6,0,3, 7,6,1,3, 7,6,2,3, 7,6,3,3, 7,6,4,3, 7,6,5,3, 7,6,6,3,
- 7,6,7,3, 7,6,8,3, 7,6,9,3, 7,8,6,3, 7,8,7,3, 9,6,6,3, 9,6,7,3, 9,8,8,3, 9,8,9,3,
- 7,7,0,3, 7,7,1,3, 7,7,2,3, 7,7,3,3, 7,7,4,3, 7,7,5,3, 7,7,6,3, 7,7,7,3, 7,7,8,3,
- 7,7,9,3, 7,9,6,3, 7,9,7,3, 9,7,6,3, 9,7,7,3, 9,9,8,3, 9,9,9,3};
-#endif
-
-#if defined(DEC_BIN2BCD8) && DEC_BIN2BCD8==1 && !defined(DECBIN2BCD8)
-#define DECBIN2BCD8
-
-const uint8_t BIN2BCD8[4000]={
- 0,0,0,0, 0,0,1,1, 0,0,2,1, 0,0,3,1, 0,0,4,1, 0,0,5,1, 0,0,6,1, 0,0,7,1, 0,0,8,1,
- 0,0,9,1, 0,1,0,2, 0,1,1,2, 0,1,2,2, 0,1,3,2, 0,1,4,2, 0,1,5,2, 0,1,6,2, 0,1,7,2,
- 0,1,8,2, 0,1,9,2, 0,2,0,2, 0,2,1,2, 0,2,2,2, 0,2,3,2, 0,2,4,2, 0,2,5,2, 0,2,6,2,
- 0,2,7,2, 0,2,8,2, 0,2,9,2, 0,3,0,2, 0,3,1,2, 0,3,2,2, 0,3,3,2, 0,3,4,2, 0,3,5,2,
- 0,3,6,2, 0,3,7,2, 0,3,8,2, 0,3,9,2, 0,4,0,2, 0,4,1,2, 0,4,2,2, 0,4,3,2, 0,4,4,2,
- 0,4,5,2, 0,4,6,2, 0,4,7,2, 0,4,8,2, 0,4,9,2, 0,5,0,2, 0,5,1,2, 0,5,2,2, 0,5,3,2,
- 0,5,4,2, 0,5,5,2, 0,5,6,2, 0,5,7,2, 0,5,8,2, 0,5,9,2, 0,6,0,2, 0,6,1,2, 0,6,2,2,
- 0,6,3,2, 0,6,4,2, 0,6,5,2, 0,6,6,2, 0,6,7,2, 0,6,8,2, 0,6,9,2, 0,7,0,2, 0,7,1,2,
- 0,7,2,2, 0,7,3,2, 0,7,4,2, 0,7,5,2, 0,7,6,2, 0,7,7,2, 0,7,8,2, 0,7,9,2, 0,8,0,2,
- 0,8,1,2, 0,8,2,2, 0,8,3,2, 0,8,4,2, 0,8,5,2, 0,8,6,2, 0,8,7,2, 0,8,8,2, 0,8,9,2,
- 0,9,0,2, 0,9,1,2, 0,9,2,2, 0,9,3,2, 0,9,4,2, 0,9,5,2, 0,9,6,2, 0,9,7,2, 0,9,8,2,
- 0,9,9,2, 1,0,0,3, 1,0,1,3, 1,0,2,3, 1,0,3,3, 1,0,4,3, 1,0,5,3, 1,0,6,3, 1,0,7,3,
- 1,0,8,3, 1,0,9,3, 1,1,0,3, 1,1,1,3, 1,1,2,3, 1,1,3,3, 1,1,4,3, 1,1,5,3, 1,1,6,3,
- 1,1,7,3, 1,1,8,3, 1,1,9,3, 1,2,0,3, 1,2,1,3, 1,2,2,3, 1,2,3,3, 1,2,4,3, 1,2,5,3,
- 1,2,6,3, 1,2,7,3, 1,2,8,3, 1,2,9,3, 1,3,0,3, 1,3,1,3, 1,3,2,3, 1,3,3,3, 1,3,4,3,
- 1,3,5,3, 1,3,6,3, 1,3,7,3, 1,3,8,3, 1,3,9,3, 1,4,0,3, 1,4,1,3, 1,4,2,3, 1,4,3,3,
- 1,4,4,3, 1,4,5,3, 1,4,6,3, 1,4,7,3, 1,4,8,3, 1,4,9,3, 1,5,0,3, 1,5,1,3, 1,5,2,3,
- 1,5,3,3, 1,5,4,3, 1,5,5,3, 1,5,6,3, 1,5,7,3, 1,5,8,3, 1,5,9,3, 1,6,0,3, 1,6,1,3,
- 1,6,2,3, 1,6,3,3, 1,6,4,3, 1,6,5,3, 1,6,6,3, 1,6,7,3, 1,6,8,3, 1,6,9,3, 1,7,0,3,
- 1,7,1,3, 1,7,2,3, 1,7,3,3, 1,7,4,3, 1,7,5,3, 1,7,6,3, 1,7,7,3, 1,7,8,3, 1,7,9,3,
- 1,8,0,3, 1,8,1,3, 1,8,2,3, 1,8,3,3, 1,8,4,3, 1,8,5,3, 1,8,6,3, 1,8,7,3, 1,8,8,3,
- 1,8,9,3, 1,9,0,3, 1,9,1,3, 1,9,2,3, 1,9,3,3, 1,9,4,3, 1,9,5,3, 1,9,6,3, 1,9,7,3,
- 1,9,8,3, 1,9,9,3, 2,0,0,3, 2,0,1,3, 2,0,2,3, 2,0,3,3, 2,0,4,3, 2,0,5,3, 2,0,6,3,
- 2,0,7,3, 2,0,8,3, 2,0,9,3, 2,1,0,3, 2,1,1,3, 2,1,2,3, 2,1,3,3, 2,1,4,3, 2,1,5,3,
- 2,1,6,3, 2,1,7,3, 2,1,8,3, 2,1,9,3, 2,2,0,3, 2,2,1,3, 2,2,2,3, 2,2,3,3, 2,2,4,3,
- 2,2,5,3, 2,2,6,3, 2,2,7,3, 2,2,8,3, 2,2,9,3, 2,3,0,3, 2,3,1,3, 2,3,2,3, 2,3,3,3,
- 2,3,4,3, 2,3,5,3, 2,3,6,3, 2,3,7,3, 2,3,8,3, 2,3,9,3, 2,4,0,3, 2,4,1,3, 2,4,2,3,
- 2,4,3,3, 2,4,4,3, 2,4,5,3, 2,4,6,3, 2,4,7,3, 2,4,8,3, 2,4,9,3, 2,5,0,3, 2,5,1,3,
- 2,5,2,3, 2,5,3,3, 2,5,4,3, 2,5,5,3, 2,5,6,3, 2,5,7,3, 2,5,8,3, 2,5,9,3, 2,6,0,3,
- 2,6,1,3, 2,6,2,3, 2,6,3,3, 2,6,4,3, 2,6,5,3, 2,6,6,3, 2,6,7,3, 2,6,8,3, 2,6,9,3,
- 2,7,0,3, 2,7,1,3, 2,7,2,3, 2,7,3,3, 2,7,4,3, 2,7,5,3, 2,7,6,3, 2,7,7,3, 2,7,8,3,
- 2,7,9,3, 2,8,0,3, 2,8,1,3, 2,8,2,3, 2,8,3,3, 2,8,4,3, 2,8,5,3, 2,8,6,3, 2,8,7,3,
- 2,8,8,3, 2,8,9,3, 2,9,0,3, 2,9,1,3, 2,9,2,3, 2,9,3,3, 2,9,4,3, 2,9,5,3, 2,9,6,3,
- 2,9,7,3, 2,9,8,3, 2,9,9,3, 3,0,0,3, 3,0,1,3, 3,0,2,3, 3,0,3,3, 3,0,4,3, 3,0,5,3,
- 3,0,6,3, 3,0,7,3, 3,0,8,3, 3,0,9,3, 3,1,0,3, 3,1,1,3, 3,1,2,3, 3,1,3,3, 3,1,4,3,
- 3,1,5,3, 3,1,6,3, 3,1,7,3, 3,1,8,3, 3,1,9,3, 3,2,0,3, 3,2,1,3, 3,2,2,3, 3,2,3,3,
- 3,2,4,3, 3,2,5,3, 3,2,6,3, 3,2,7,3, 3,2,8,3, 3,2,9,3, 3,3,0,3, 3,3,1,3, 3,3,2,3,
- 3,3,3,3, 3,3,4,3, 3,3,5,3, 3,3,6,3, 3,3,7,3, 3,3,8,3, 3,3,9,3, 3,4,0,3, 3,4,1,3,
- 3,4,2,3, 3,4,3,3, 3,4,4,3, 3,4,5,3, 3,4,6,3, 3,4,7,3, 3,4,8,3, 3,4,9,3, 3,5,0,3,
- 3,5,1,3, 3,5,2,3, 3,5,3,3, 3,5,4,3, 3,5,5,3, 3,5,6,3, 3,5,7,3, 3,5,8,3, 3,5,9,3,
- 3,6,0,3, 3,6,1,3, 3,6,2,3, 3,6,3,3, 3,6,4,3, 3,6,5,3, 3,6,6,3, 3,6,7,3, 3,6,8,3,
- 3,6,9,3, 3,7,0,3, 3,7,1,3, 3,7,2,3, 3,7,3,3, 3,7,4,3, 3,7,5,3, 3,7,6,3, 3,7,7,3,
- 3,7,8,3, 3,7,9,3, 3,8,0,3, 3,8,1,3, 3,8,2,3, 3,8,3,3, 3,8,4,3, 3,8,5,3, 3,8,6,3,
- 3,8,7,3, 3,8,8,3, 3,8,9,3, 3,9,0,3, 3,9,1,3, 3,9,2,3, 3,9,3,3, 3,9,4,3, 3,9,5,3,
- 3,9,6,3, 3,9,7,3, 3,9,8,3, 3,9,9,3, 4,0,0,3, 4,0,1,3, 4,0,2,3, 4,0,3,3, 4,0,4,3,
- 4,0,5,3, 4,0,6,3, 4,0,7,3, 4,0,8,3, 4,0,9,3, 4,1,0,3, 4,1,1,3, 4,1,2,3, 4,1,3,3,
- 4,1,4,3, 4,1,5,3, 4,1,6,3, 4,1,7,3, 4,1,8,3, 4,1,9,3, 4,2,0,3, 4,2,1,3, 4,2,2,3,
- 4,2,3,3, 4,2,4,3, 4,2,5,3, 4,2,6,3, 4,2,7,3, 4,2,8,3, 4,2,9,3, 4,3,0,3, 4,3,1,3,
- 4,3,2,3, 4,3,3,3, 4,3,4,3, 4,3,5,3, 4,3,6,3, 4,3,7,3, 4,3,8,3, 4,3,9,3, 4,4,0,3,
- 4,4,1,3, 4,4,2,3, 4,4,3,3, 4,4,4,3, 4,4,5,3, 4,4,6,3, 4,4,7,3, 4,4,8,3, 4,4,9,3,
- 4,5,0,3, 4,5,1,3, 4,5,2,3, 4,5,3,3, 4,5,4,3, 4,5,5,3, 4,5,6,3, 4,5,7,3, 4,5,8,3,
- 4,5,9,3, 4,6,0,3, 4,6,1,3, 4,6,2,3, 4,6,3,3, 4,6,4,3, 4,6,5,3, 4,6,6,3, 4,6,7,3,
- 4,6,8,3, 4,6,9,3, 4,7,0,3, 4,7,1,3, 4,7,2,3, 4,7,3,3, 4,7,4,3, 4,7,5,3, 4,7,6,3,
- 4,7,7,3, 4,7,8,3, 4,7,9,3, 4,8,0,3, 4,8,1,3, 4,8,2,3, 4,8,3,3, 4,8,4,3, 4,8,5,3,
- 4,8,6,3, 4,8,7,3, 4,8,8,3, 4,8,9,3, 4,9,0,3, 4,9,1,3, 4,9,2,3, 4,9,3,3, 4,9,4,3,
- 4,9,5,3, 4,9,6,3, 4,9,7,3, 4,9,8,3, 4,9,9,3, 5,0,0,3, 5,0,1,3, 5,0,2,3, 5,0,3,3,
- 5,0,4,3, 5,0,5,3, 5,0,6,3, 5,0,7,3, 5,0,8,3, 5,0,9,3, 5,1,0,3, 5,1,1,3, 5,1,2,3,
- 5,1,3,3, 5,1,4,3, 5,1,5,3, 5,1,6,3, 5,1,7,3, 5,1,8,3, 5,1,9,3, 5,2,0,3, 5,2,1,3,
- 5,2,2,3, 5,2,3,3, 5,2,4,3, 5,2,5,3, 5,2,6,3, 5,2,7,3, 5,2,8,3, 5,2,9,3, 5,3,0,3,
- 5,3,1,3, 5,3,2,3, 5,3,3,3, 5,3,4,3, 5,3,5,3, 5,3,6,3, 5,3,7,3, 5,3,8,3, 5,3,9,3,
- 5,4,0,3, 5,4,1,3, 5,4,2,3, 5,4,3,3, 5,4,4,3, 5,4,5,3, 5,4,6,3, 5,4,7,3, 5,4,8,3,
- 5,4,9,3, 5,5,0,3, 5,5,1,3, 5,5,2,3, 5,5,3,3, 5,5,4,3, 5,5,5,3, 5,5,6,3, 5,5,7,3,
- 5,5,8,3, 5,5,9,3, 5,6,0,3, 5,6,1,3, 5,6,2,3, 5,6,3,3, 5,6,4,3, 5,6,5,3, 5,6,6,3,
- 5,6,7,3, 5,6,8,3, 5,6,9,3, 5,7,0,3, 5,7,1,3, 5,7,2,3, 5,7,3,3, 5,7,4,3, 5,7,5,3,
- 5,7,6,3, 5,7,7,3, 5,7,8,3, 5,7,9,3, 5,8,0,3, 5,8,1,3, 5,8,2,3, 5,8,3,3, 5,8,4,3,
- 5,8,5,3, 5,8,6,3, 5,8,7,3, 5,8,8,3, 5,8,9,3, 5,9,0,3, 5,9,1,3, 5,9,2,3, 5,9,3,3,
- 5,9,4,3, 5,9,5,3, 5,9,6,3, 5,9,7,3, 5,9,8,3, 5,9,9,3, 6,0,0,3, 6,0,1,3, 6,0,2,3,
- 6,0,3,3, 6,0,4,3, 6,0,5,3, 6,0,6,3, 6,0,7,3, 6,0,8,3, 6,0,9,3, 6,1,0,3, 6,1,1,3,
- 6,1,2,3, 6,1,3,3, 6,1,4,3, 6,1,5,3, 6,1,6,3, 6,1,7,3, 6,1,8,3, 6,1,9,3, 6,2,0,3,
- 6,2,1,3, 6,2,2,3, 6,2,3,3, 6,2,4,3, 6,2,5,3, 6,2,6,3, 6,2,7,3, 6,2,8,3, 6,2,9,3,
- 6,3,0,3, 6,3,1,3, 6,3,2,3, 6,3,3,3, 6,3,4,3, 6,3,5,3, 6,3,6,3, 6,3,7,3, 6,3,8,3,
- 6,3,9,3, 6,4,0,3, 6,4,1,3, 6,4,2,3, 6,4,3,3, 6,4,4,3, 6,4,5,3, 6,4,6,3, 6,4,7,3,
- 6,4,8,3, 6,4,9,3, 6,5,0,3, 6,5,1,3, 6,5,2,3, 6,5,3,3, 6,5,4,3, 6,5,5,3, 6,5,6,3,
- 6,5,7,3, 6,5,8,3, 6,5,9,3, 6,6,0,3, 6,6,1,3, 6,6,2,3, 6,6,3,3, 6,6,4,3, 6,6,5,3,
- 6,6,6,3, 6,6,7,3, 6,6,8,3, 6,6,9,3, 6,7,0,3, 6,7,1,3, 6,7,2,3, 6,7,3,3, 6,7,4,3,
- 6,7,5,3, 6,7,6,3, 6,7,7,3, 6,7,8,3, 6,7,9,3, 6,8,0,3, 6,8,1,3, 6,8,2,3, 6,8,3,3,
- 6,8,4,3, 6,8,5,3, 6,8,6,3, 6,8,7,3, 6,8,8,3, 6,8,9,3, 6,9,0,3, 6,9,1,3, 6,9,2,3,
- 6,9,3,3, 6,9,4,3, 6,9,5,3, 6,9,6,3, 6,9,7,3, 6,9,8,3, 6,9,9,3, 7,0,0,3, 7,0,1,3,
- 7,0,2,3, 7,0,3,3, 7,0,4,3, 7,0,5,3, 7,0,6,3, 7,0,7,3, 7,0,8,3, 7,0,9,3, 7,1,0,3,
- 7,1,1,3, 7,1,2,3, 7,1,3,3, 7,1,4,3, 7,1,5,3, 7,1,6,3, 7,1,7,3, 7,1,8,3, 7,1,9,3,
- 7,2,0,3, 7,2,1,3, 7,2,2,3, 7,2,3,3, 7,2,4,3, 7,2,5,3, 7,2,6,3, 7,2,7,3, 7,2,8,3,
- 7,2,9,3, 7,3,0,3, 7,3,1,3, 7,3,2,3, 7,3,3,3, 7,3,4,3, 7,3,5,3, 7,3,6,3, 7,3,7,3,
- 7,3,8,3, 7,3,9,3, 7,4,0,3, 7,4,1,3, 7,4,2,3, 7,4,3,3, 7,4,4,3, 7,4,5,3, 7,4,6,3,
- 7,4,7,3, 7,4,8,3, 7,4,9,3, 7,5,0,3, 7,5,1,3, 7,5,2,3, 7,5,3,3, 7,5,4,3, 7,5,5,3,
- 7,5,6,3, 7,5,7,3, 7,5,8,3, 7,5,9,3, 7,6,0,3, 7,6,1,3, 7,6,2,3, 7,6,3,3, 7,6,4,3,
- 7,6,5,3, 7,6,6,3, 7,6,7,3, 7,6,8,3, 7,6,9,3, 7,7,0,3, 7,7,1,3, 7,7,2,3, 7,7,3,3,
- 7,7,4,3, 7,7,5,3, 7,7,6,3, 7,7,7,3, 7,7,8,3, 7,7,9,3, 7,8,0,3, 7,8,1,3, 7,8,2,3,
- 7,8,3,3, 7,8,4,3, 7,8,5,3, 7,8,6,3, 7,8,7,3, 7,8,8,3, 7,8,9,3, 7,9,0,3, 7,9,1,3,
- 7,9,2,3, 7,9,3,3, 7,9,4,3, 7,9,5,3, 7,9,6,3, 7,9,7,3, 7,9,8,3, 7,9,9,3, 8,0,0,3,
- 8,0,1,3, 8,0,2,3, 8,0,3,3, 8,0,4,3, 8,0,5,3, 8,0,6,3, 8,0,7,3, 8,0,8,3, 8,0,9,3,
- 8,1,0,3, 8,1,1,3, 8,1,2,3, 8,1,3,3, 8,1,4,3, 8,1,5,3, 8,1,6,3, 8,1,7,3, 8,1,8,3,
- 8,1,9,3, 8,2,0,3, 8,2,1,3, 8,2,2,3, 8,2,3,3, 8,2,4,3, 8,2,5,3, 8,2,6,3, 8,2,7,3,
- 8,2,8,3, 8,2,9,3, 8,3,0,3, 8,3,1,3, 8,3,2,3, 8,3,3,3, 8,3,4,3, 8,3,5,3, 8,3,6,3,
- 8,3,7,3, 8,3,8,3, 8,3,9,3, 8,4,0,3, 8,4,1,3, 8,4,2,3, 8,4,3,3, 8,4,4,3, 8,4,5,3,
- 8,4,6,3, 8,4,7,3, 8,4,8,3, 8,4,9,3, 8,5,0,3, 8,5,1,3, 8,5,2,3, 8,5,3,3, 8,5,4,3,
- 8,5,5,3, 8,5,6,3, 8,5,7,3, 8,5,8,3, 8,5,9,3, 8,6,0,3, 8,6,1,3, 8,6,2,3, 8,6,3,3,
- 8,6,4,3, 8,6,5,3, 8,6,6,3, 8,6,7,3, 8,6,8,3, 8,6,9,3, 8,7,0,3, 8,7,1,3, 8,7,2,3,
- 8,7,3,3, 8,7,4,3, 8,7,5,3, 8,7,6,3, 8,7,7,3, 8,7,8,3, 8,7,9,3, 8,8,0,3, 8,8,1,3,
- 8,8,2,3, 8,8,3,3, 8,8,4,3, 8,8,5,3, 8,8,6,3, 8,8,7,3, 8,8,8,3, 8,8,9,3, 8,9,0,3,
- 8,9,1,3, 8,9,2,3, 8,9,3,3, 8,9,4,3, 8,9,5,3, 8,9,6,3, 8,9,7,3, 8,9,8,3, 8,9,9,3,
- 9,0,0,3, 9,0,1,3, 9,0,2,3, 9,0,3,3, 9,0,4,3, 9,0,5,3, 9,0,6,3, 9,0,7,3, 9,0,8,3,
- 9,0,9,3, 9,1,0,3, 9,1,1,3, 9,1,2,3, 9,1,3,3, 9,1,4,3, 9,1,5,3, 9,1,6,3, 9,1,7,3,
- 9,1,8,3, 9,1,9,3, 9,2,0,3, 9,2,1,3, 9,2,2,3, 9,2,3,3, 9,2,4,3, 9,2,5,3, 9,2,6,3,
- 9,2,7,3, 9,2,8,3, 9,2,9,3, 9,3,0,3, 9,3,1,3, 9,3,2,3, 9,3,3,3, 9,3,4,3, 9,3,5,3,
- 9,3,6,3, 9,3,7,3, 9,3,8,3, 9,3,9,3, 9,4,0,3, 9,4,1,3, 9,4,2,3, 9,4,3,3, 9,4,4,3,
- 9,4,5,3, 9,4,6,3, 9,4,7,3, 9,4,8,3, 9,4,9,3, 9,5,0,3, 9,5,1,3, 9,5,2,3, 9,5,3,3,
- 9,5,4,3, 9,5,5,3, 9,5,6,3, 9,5,7,3, 9,5,8,3, 9,5,9,3, 9,6,0,3, 9,6,1,3, 9,6,2,3,
- 9,6,3,3, 9,6,4,3, 9,6,5,3, 9,6,6,3, 9,6,7,3, 9,6,8,3, 9,6,9,3, 9,7,0,3, 9,7,1,3,
- 9,7,2,3, 9,7,3,3, 9,7,4,3, 9,7,5,3, 9,7,6,3, 9,7,7,3, 9,7,8,3, 9,7,9,3, 9,8,0,3,
- 9,8,1,3, 9,8,2,3, 9,8,3,3, 9,8,4,3, 9,8,5,3, 9,8,6,3, 9,8,7,3, 9,8,8,3, 9,8,9,3,
- 9,9,0,3, 9,9,1,3, 9,9,2,3, 9,9,3,3, 9,9,4,3, 9,9,5,3, 9,9,6,3, 9,9,7,3, 9,9,8,3,
- 9,9,9,3};
-#endif
+++ /dev/null
-/* Decimal number arithmetic module header for the decNumber C Library.
- Copyright (C) 2005, 2007 Free Software Foundation, Inc.
- Contributed by IBM Corporation. Author Mike Cowlishaw.
-
- This file is part of GCC.
-
- GCC is free software; you can redistribute it and/or modify it under
- the terms of the GNU General Public License as published by the Free
- Software Foundation; either version 2, or (at your option) any later
- version.
-
- In addition to the permissions in the GNU General Public License,
- the Free Software Foundation gives you unlimited permission to link
- the compiled version of this file into combinations with other
- programs, and to distribute those combinations without any
- restriction coming from the use of this file. (The General Public
- License restrictions do apply in other respects; for example, they
- cover modification of the file, and distribution when not linked
- into a combine executable.)
-
- GCC is distributed in the hope that it will be useful, but WITHOUT ANY
- WARRANTY; without even the implied warranty of MERCHANTABILITY or
- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
- for more details.
-
- You should have received a copy of the GNU General Public License
- along with GCC; see the file COPYING. If not, write to the Free
- Software Foundation, 51 Franklin Street, Fifth Floor, Boston, MA
- 02110-1301, USA. */
-
-/* ------------------------------------------------------------------ */
-/* Decimal Number arithmetic module header */
-/* ------------------------------------------------------------------ */
-
-#ifndef DECNUMBER_H
-#define DECNUMBER_H
-
- #define DECNAME "decNumber" /* Short name */
- #define DECFULLNAME "Decimal Number Module" /* Verbose name */
- #define DECAUTHOR "Mike Cowlishaw" /* Who to blame */
-
- #include "libdecnumber/decContext.h"
-
- /* Bit settings for decNumber.bits */
- #define DECNEG 0x80 /* Sign; 1=negative, 0=positive or zero */
- #define DECINF 0x40 /* 1=Infinity */
- #define DECNAN 0x20 /* 1=NaN */
- #define DECSNAN 0x10 /* 1=sNaN */
- /* The remaining bits are reserved; they must be 0 */
- #define DECSPECIAL (DECINF|DECNAN|DECSNAN) /* any special value */
-
- /* Define the decNumber data structure. The size and shape of the */
- /* units array in the structure is determined by the following */
- /* constant. This must not be changed without recompiling the */
- /* decNumber library modules. */
-
- #define DECDPUN 3 /* DECimal Digits Per UNit [must be >0 */
- /* and <10; 3 or powers of 2 are best]. */
-
- /* DECNUMDIGITS is the default number of digits that can be held in */
- /* the structure. If undefined, 1 is assumed and it is assumed */
- /* that the structure will be immediately followed by extra space, */
- /* as required. DECNUMDIGITS is always >0. */
- #if !defined(DECNUMDIGITS)
- #define DECNUMDIGITS 1
- #endif
-
- /* The size (integer data type) of each unit is determined by the */
- /* number of digits it will hold. */
- #if DECDPUN<=2
- #define decNumberUnit uint8_t
- #elif DECDPUN<=4
- #define decNumberUnit uint16_t
- #else
- #define decNumberUnit uint32_t
- #endif
- /* The number of units needed is ceil(DECNUMDIGITS/DECDPUN) */
- #define DECNUMUNITS ((DECNUMDIGITS+DECDPUN-1)/DECDPUN)
-
- /* The data structure... */
- typedef struct {
- int32_t digits; /* Count of digits in the coefficient; >0 */
- int32_t exponent; /* Unadjusted exponent, unbiased, in */
- /* range: -1999999997 through 999999999 */
- uint8_t bits; /* Indicator bits (see above) */
- /* Coefficient, from least significant unit */
- decNumberUnit lsu[DECNUMUNITS];
- } decNumber;
-
- /* Notes: */
- /* 1. If digits is > DECDPUN then there will one or more */
- /* decNumberUnits immediately following the first element of lsu.*/
- /* These contain the remaining (more significant) digits of the */
- /* number, and may be in the lsu array, or may be guaranteed by */
- /* some other mechanism (such as being contained in another */
- /* structure, or being overlaid on dynamically allocated */
- /* storage). */
- /* */
- /* Each integer of the coefficient (except potentially the last) */
- /* contains DECDPUN digits (e.g., a value in the range 0 through */
- /* 99999999 if DECDPUN is 8, or 0 through 999 if DECDPUN is 3). */
- /* */
- /* 2. A decNumber converted to a string may need up to digits+14 */
- /* characters. The worst cases (non-exponential and exponential */
- /* formats) are -0.00000{9...}# and -9.{9...}E+999999999# */
- /* (where # is '\0') */
-
-
- /* ---------------------------------------------------------------- */
- /* decNumber public functions and macros */
- /* ---------------------------------------------------------------- */
-
-
- /* Conversions */
- decNumber * decNumberFromInt32(decNumber *, int32_t);
- decNumber * decNumberFromUInt32(decNumber *, uint32_t);
- decNumber *decNumberFromInt64(decNumber *, int64_t);
- decNumber *decNumberFromUInt64(decNumber *, uint64_t);
- decNumber * decNumberFromString(decNumber *, const char *, decContext *);
- char * decNumberToString(const decNumber *, char *);
- char * decNumberToEngString(const decNumber *, char *);
- uint32_t decNumberToUInt32(const decNumber *, decContext *);
- int32_t decNumberToInt32(const decNumber *, decContext *);
- int64_t decNumberIntegralToInt64(const decNumber *dn, decContext *set);
- uint8_t * decNumberGetBCD(const decNumber *, uint8_t *);
- decNumber * decNumberSetBCD(decNumber *, const uint8_t *, uint32_t);
-
- /* Operators and elementary functions */
- decNumber * decNumberAbs(decNumber *, const decNumber *, decContext *);
- decNumber * decNumberAdd(decNumber *, const decNumber *, const decNumber *, decContext *);
- decNumber * decNumberAnd(decNumber *, const decNumber *, const decNumber *, decContext *);
- decNumber * decNumberCompare(decNumber *, const decNumber *, const decNumber *, decContext *);
- decNumber * decNumberCompareSignal(decNumber *, const decNumber *, const decNumber *, decContext *);
- decNumber * decNumberCompareTotal(decNumber *, const decNumber *, const decNumber *, decContext *);
- decNumber * decNumberCompareTotalMag(decNumber *, const decNumber *, const decNumber *, decContext *);
- decNumber * decNumberDivide(decNumber *, const decNumber *, const decNumber *, decContext *);
- decNumber * decNumberDivideInteger(decNumber *, const decNumber *, const decNumber *, decContext *);
- decNumber * decNumberExp(decNumber *, const decNumber *, decContext *);
- decNumber * decNumberFMA(decNumber *, const decNumber *, const decNumber *, const decNumber *, decContext *);
- decNumber * decNumberInvert(decNumber *, const decNumber *, decContext *);
- decNumber * decNumberLn(decNumber *, const decNumber *, decContext *);
- decNumber * decNumberLogB(decNumber *, const decNumber *, decContext *);
- decNumber * decNumberLog10(decNumber *, const decNumber *, decContext *);
- decNumber * decNumberMax(decNumber *, const decNumber *, const decNumber *, decContext *);
- decNumber * decNumberMaxMag(decNumber *, const decNumber *, const decNumber *, decContext *);
- decNumber * decNumberMin(decNumber *, const decNumber *, const decNumber *, decContext *);
- decNumber * decNumberMinMag(decNumber *, const decNumber *, const decNumber *, decContext *);
- decNumber * decNumberMinus(decNumber *, const decNumber *, decContext *);
- decNumber * decNumberMultiply(decNumber *, const decNumber *, const decNumber *, decContext *);
- decNumber * decNumberNormalize(decNumber *, const decNumber *, decContext *);
- decNumber * decNumberOr(decNumber *, const decNumber *, const decNumber *, decContext *);
- decNumber * decNumberPlus(decNumber *, const decNumber *, decContext *);
- decNumber * decNumberPower(decNumber *, const decNumber *, const decNumber *, decContext *);
- decNumber * decNumberQuantize(decNumber *, const decNumber *, const decNumber *, decContext *);
- decNumber * decNumberReduce(decNumber *, const decNumber *, decContext *);
- decNumber * decNumberRemainder(decNumber *, const decNumber *, const decNumber *, decContext *);
- decNumber * decNumberRemainderNear(decNumber *, const decNumber *, const decNumber *, decContext *);
- decNumber * decNumberRescale(decNumber *, const decNumber *, const decNumber *, decContext *);
- decNumber * decNumberRotate(decNumber *, const decNumber *, const decNumber *, decContext *);
- decNumber * decNumberSameQuantum(decNumber *, const decNumber *, const decNumber *);
- decNumber * decNumberScaleB(decNumber *, const decNumber *, const decNumber *, decContext *);
- decNumber * decNumberShift(decNumber *, const decNumber *, const decNumber *, decContext *);
- decNumber * decNumberSquareRoot(decNumber *, const decNumber *, decContext *);
- decNumber * decNumberSubtract(decNumber *, const decNumber *, const decNumber *, decContext *);
- decNumber * decNumberToIntegralExact(decNumber *, const decNumber *, decContext *);
- decNumber * decNumberToIntegralValue(decNumber *, const decNumber *, decContext *);
- decNumber * decNumberXor(decNumber *, const decNumber *, const decNumber *, decContext *);
-
- /* Utilities */
- enum decClass decNumberClass(const decNumber *, decContext *);
- const char * decNumberClassToString(enum decClass);
- decNumber * decNumberCopy(decNumber *, const decNumber *);
- decNumber * decNumberCopyAbs(decNumber *, const decNumber *);
- decNumber * decNumberCopyNegate(decNumber *, const decNumber *);
- decNumber * decNumberCopySign(decNumber *, const decNumber *, const decNumber *);
- decNumber * decNumberNextMinus(decNumber *, const decNumber *, decContext *);
- decNumber * decNumberNextPlus(decNumber *, const decNumber *, decContext *);
- decNumber * decNumberNextToward(decNumber *, const decNumber *, const decNumber *, decContext *);
- decNumber * decNumberTrim(decNumber *);
- const char * decNumberVersion(void);
- decNumber * decNumberZero(decNumber *);
-
- /* Functions for testing decNumbers (normality depends on context) */
- int32_t decNumberIsNormal(const decNumber *, decContext *);
- int32_t decNumberIsSubnormal(const decNumber *, decContext *);
-
- /* Macros for testing decNumber *dn */
- #define decNumberIsCanonical(dn) (1) /* All decNumbers are saintly */
- #define decNumberIsFinite(dn) (((dn)->bits&DECSPECIAL)==0)
- #define decNumberIsInfinite(dn) (((dn)->bits&DECINF)!=0)
- #define decNumberIsNaN(dn) (((dn)->bits&(DECNAN|DECSNAN))!=0)
- #define decNumberIsNegative(dn) (((dn)->bits&DECNEG)!=0)
- #define decNumberIsQNaN(dn) (((dn)->bits&(DECNAN))!=0)
- #define decNumberIsSNaN(dn) (((dn)->bits&(DECSNAN))!=0)
- #define decNumberIsSpecial(dn) (((dn)->bits&DECSPECIAL)!=0)
- #define decNumberIsZero(dn) (*(dn)->lsu==0 \
- && (dn)->digits==1 \
- && (((dn)->bits&DECSPECIAL)==0))
- #define decNumberRadix(dn) (10)
-
-#endif
+++ /dev/null
-/* Local definitions for the decNumber C Library.
- Copyright (C) 2007 Free Software Foundation, Inc.
- Contributed by IBM Corporation. Author Mike Cowlishaw.
-
- This file is part of GCC.
-
- GCC is free software; you can redistribute it and/or modify it under
- the terms of the GNU General Public License as published by the Free
- Software Foundation; either version 2, or (at your option) any later
- version.
-
- In addition to the permissions in the GNU General Public License,
- the Free Software Foundation gives you unlimited permission to link
- the compiled version of this file into combinations with other
- programs, and to distribute those combinations without any
- restriction coming from the use of this file. (The General Public
- License restrictions do apply in other respects; for example, they
- cover modification of the file, and distribution when not linked
- into a combine executable.)
-
- GCC is distributed in the hope that it will be useful, but WITHOUT ANY
- WARRANTY; without even the implied warranty of MERCHANTABILITY or
- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
- for more details.
-
- You should have received a copy of the GNU General Public License
- along with GCC; see the file COPYING. If not, write to the Free
- Software Foundation, 51 Franklin Street, Fifth Floor, Boston, MA
- 02110-1301, USA. */
-
-/* ------------------------------------------------------------------ */
-/* decNumber package local type, tuning, and macro definitions */
-/* ------------------------------------------------------------------ */
-/* This header file is included by all modules in the decNumber */
-/* library, and contains local type definitions, tuning parameters, */
-/* etc. It should not need to be used by application programs. */
-/* decNumber.h or one of decDouble (etc.) must be included first. */
-/* ------------------------------------------------------------------ */
-
-#ifndef DECNUMBERLOCAL_H
-#define DECNUMBERLOCAL_H
-
- #define DECVERSION "decNumber 3.53" /* Package Version [16 max.] */
- #define DECNLAUTHOR "Mike Cowlishaw" /* Who to blame */
-
- #include "libdecnumber/dconfig.h"
- #include "libdecnumber/decContext.h"
-
- /* Conditional code flag -- set this to match hardware platform */
- /* 1=little-endian, 0=big-endian */
- #if WORDS_BIGENDIAN
- #define DECLITEND 0
- #else
- #define DECLITEND 1
- #endif
-
- /* Conditional code flag -- set this to 1 for best performance */
- #define DECUSE64 1 /* 1=use int64s, 0=int32 & smaller only */
-
- /* Conditional check flags -- set these to 0 for best performance */
- #define DECCHECK 0 /* 1 to enable robust checking */
- #define DECALLOC 0 /* 1 to enable memory accounting */
- #define DECTRACE 0 /* 1 to trace certain internals, etc. */
-
- /* Tuning parameter for decNumber (arbitrary precision) module */
- #define DECBUFFER 36 /* Size basis for local buffers. This */
- /* should be a common maximum precision */
- /* rounded up to a multiple of 4; must */
- /* be zero or positive. */
-
- /* ---------------------------------------------------------------- */
- /* Definitions for all modules (general-purpose) */
- /* ---------------------------------------------------------------- */
-
- /* Local names for common types -- for safety, decNumber modules do */
- /* not use int or long directly. */
- #define Flag uint8_t
- #define Byte int8_t
- #define uByte uint8_t
- #define Short int16_t
- #define uShort uint16_t
- #define Int int32_t
- #define uInt uint32_t
- #define Unit decNumberUnit
- #if DECUSE64
- #define Long int64_t
- #define uLong uint64_t
- #endif
-
- /* Development-use definitions */
- typedef long int LI; /* for printf arguments only */
- #define DECNOINT 0 /* 1 to check no internal use of 'int' */
- #if DECNOINT
- /* if these interfere with your C includes, do not set DECNOINT */
- #define int ? /* enable to ensure that plain C 'int' */
- #define long ?? /* .. or 'long' types are not used */
- #endif
-
- /* Shared lookup tables */
- extern const uByte DECSTICKYTAB[10]; /* re-round digits if sticky */
- extern const uLong DECPOWERS[19]; /* powers of ten table */
- /* The following are included from decDPD.h */
- extern const uShort DPD2BIN[1024]; /* DPD -> 0-999 */
- extern const uShort BIN2DPD[1000]; /* 0-999 -> DPD */
- extern const uInt DPD2BINK[1024]; /* DPD -> 0-999000 */
- extern const uInt DPD2BINM[1024]; /* DPD -> 0-999000000 */
- extern const uByte DPD2BCD8[4096]; /* DPD -> ddd + len */
- extern const uByte BIN2BCD8[4000]; /* 0-999 -> ddd + len */
- extern const uShort BCD2DPD[2458]; /* 0-0x999 -> DPD (0x999=2457)*/
-
- /* LONGMUL32HI -- set w=(u*v)>>32, where w, u, and v are uInts */
- /* (that is, sets w to be the high-order word of the 64-bit result; */
- /* the low-order word is simply u*v.) */
- /* This version is derived from Knuth via Hacker's Delight; */
- /* it seems to optimize better than some others tried */
- #define LONGMUL32HI(w, u, v) { \
- uInt u0, u1, v0, v1, w0, w1, w2, t; \
- u0=u & 0xffff; u1=u>>16; \
- v0=v & 0xffff; v1=v>>16; \
- w0=u0*v0; \
- t=u1*v0 + (w0>>16); \
- w1=t & 0xffff; w2=t>>16; \
- w1=u0*v1 + w1; \
- (w)=u1*v1 + w2 + (w1>>16);}
-
- /* ROUNDUP -- round an integer up to a multiple of n */
- #define ROUNDUP(i, n) ((((i)+(n)-1)/n)*n)
-
- /* ROUNDDOWN -- round an integer down to a multiple of n */
- #define ROUNDDOWN(i, n) (((i)/n)*n)
- #define ROUNDDOWN4(i) ((i)&~3) /* special for n=4 */
-
- /* References to multi-byte sequences under different sizes */
- /* Refer to a uInt from four bytes starting at a char* or uByte*, */
- /* etc. */
- #define UINTAT(b) (*((uInt *)(b)))
- #define USHORTAT(b) (*((uShort *)(b)))
- #define UBYTEAT(b) (*((uByte *)(b)))
-
- /* X10 and X100 -- multiply integer i by 10 or 100 */
- /* [shifts are usually faster than multiply; could be conditional] */
- #define X10(i) (((i)<<1)+((i)<<3))
- #define X100(i) (((i)<<2)+((i)<<5)+((i)<<6))
-
- /* MAXI and MINI -- general max & min (not in ANSI) for integers */
- #define MAXI(x,y) ((x)<(y)?(y):(x))
- #define MINI(x,y) ((x)>(y)?(y):(x))
-
- /* Useful constants */
- #define BILLION 1000000000 /* 10**9 */
- /* CHARMASK: 0x30303030 for ASCII/UTF8; 0xF0F0F0F0 for EBCDIC */
- #define CHARMASK ((((((((uInt)'0')<<8)+'0')<<8)+'0')<<8)+'0')
-
-
- /* ---------------------------------------------------------------- */
- /* Definitions for arbitrary-precision modules (only valid after */
- /* decNumber.h has been included) */
- /* ---------------------------------------------------------------- */
-
- /* Limits and constants */
- #define DECNUMMAXP 999999999 /* maximum precision code can handle */
- #define DECNUMMAXE 999999999 /* maximum adjusted exponent ditto */
- #define DECNUMMINE -999999999 /* minimum adjusted exponent ditto */
- #if (DECNUMMAXP != DEC_MAX_DIGITS)
- #error Maximum digits mismatch
- #endif
- #if (DECNUMMAXE != DEC_MAX_EMAX)
- #error Maximum exponent mismatch
- #endif
- #if (DECNUMMINE != DEC_MIN_EMIN)
- #error Minimum exponent mismatch
- #endif
-
- /* Set DECDPUNMAX -- the maximum integer that fits in DECDPUN */
- /* digits, and D2UTABLE -- the initializer for the D2U table */
- #if DECDPUN==1
- #define DECDPUNMAX 9
- #define D2UTABLE {0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17, \
- 18,19,20,21,22,23,24,25,26,27,28,29,30,31,32, \
- 33,34,35,36,37,38,39,40,41,42,43,44,45,46,47, \
- 48,49}
- #elif DECDPUN==2
- #define DECDPUNMAX 99
- #define D2UTABLE {0,1,1,2,2,3,3,4,4,5,5,6,6,7,7,8,8,9,9,10,10, \
- 11,11,12,12,13,13,14,14,15,15,16,16,17,17,18, \
- 18,19,19,20,20,21,21,22,22,23,23,24,24,25}
- #elif DECDPUN==3
- #define DECDPUNMAX 999
- #define D2UTABLE {0,1,1,1,2,2,2,3,3,3,4,4,4,5,5,5,6,6,6,7,7,7, \
- 8,8,8,9,9,9,10,10,10,11,11,11,12,12,12,13,13, \
- 13,14,14,14,15,15,15,16,16,16,17}
- #elif DECDPUN==4
- #define DECDPUNMAX 9999
- #define D2UTABLE {0,1,1,1,1,2,2,2,2,3,3,3,3,4,4,4,4,5,5,5,5,6, \
- 6,6,6,7,7,7,7,8,8,8,8,9,9,9,9,10,10,10,10,11, \
- 11,11,11,12,12,12,12,13}
- #elif DECDPUN==5
- #define DECDPUNMAX 99999
- #define D2UTABLE {0,1,1,1,1,1,2,2,2,2,2,3,3,3,3,3,4,4,4,4,4,5, \
- 5,5,5,5,6,6,6,6,6,7,7,7,7,7,8,8,8,8,8,9,9,9, \
- 9,9,10,10,10,10}
- #elif DECDPUN==6
- #define DECDPUNMAX 999999
- #define D2UTABLE {0,1,1,1,1,1,1,2,2,2,2,2,2,3,3,3,3,3,3,4,4,4, \
- 4,4,4,5,5,5,5,5,5,6,6,6,6,6,6,7,7,7,7,7,7,8, \
- 8,8,8,8,8,9}
- #elif DECDPUN==7
- #define DECDPUNMAX 9999999
- #define D2UTABLE {0,1,1,1,1,1,1,1,2,2,2,2,2,2,2,3,3,3,3,3,3,3, \
- 4,4,4,4,4,4,4,5,5,5,5,5,5,5,6,6,6,6,6,6,6,7, \
- 7,7,7,7,7,7}
- #elif DECDPUN==8
- #define DECDPUNMAX 99999999
- #define D2UTABLE {0,1,1,1,1,1,1,1,1,2,2,2,2,2,2,2,2,3,3,3,3,3, \
- 3,3,3,4,4,4,4,4,4,4,4,5,5,5,5,5,5,5,5,6,6,6, \
- 6,6,6,6,6,7}
- #elif DECDPUN==9
- #define DECDPUNMAX 999999999
- #define D2UTABLE {0,1,1,1,1,1,1,1,1,1,2,2,2,2,2,2,2,2,2,3,3,3, \
- 3,3,3,3,3,3,4,4,4,4,4,4,4,4,4,5,5,5,5,5,5,5, \
- 5,5,6,6,6,6}
- #elif defined(DECDPUN)
- #error DECDPUN must be in the range 1-9
- #endif
-
- /* ----- Shared data (in decNumber.c) ----- */
- /* Public lookup table used by the D2U macro (see below) */
- #define DECMAXD2U 49
- extern const uByte d2utable[DECMAXD2U+1];
-
- /* ----- Macros ----- */
- /* ISZERO -- return true if decNumber dn is a zero */
- /* [performance-critical in some situations] */
- #define ISZERO(dn) decNumberIsZero(dn) /* now just a local name */
-
- /* D2U -- return the number of Units needed to hold d digits */
- /* (runtime version, with table lookaside for small d) */
- #if DECDPUN==8
- #define D2U(d) ((unsigned)((d)<=DECMAXD2U?d2utable[d]:((d)+7)>>3))
- #elif DECDPUN==4
- #define D2U(d) ((unsigned)((d)<=DECMAXD2U?d2utable[d]:((d)+3)>>2))
- #else
- #define D2U(d) ((d)<=DECMAXD2U?d2utable[d]:((d)+DECDPUN-1)/DECDPUN)
- #endif
- /* SD2U -- static D2U macro (for compile-time calculation) */
- #define SD2U(d) (((d)+DECDPUN-1)/DECDPUN)
-
- /* MSUDIGITS -- returns digits in msu, from digits, calculated */
- /* using D2U */
- #define MSUDIGITS(d) ((d)-(D2U(d)-1)*DECDPUN)
-
- /* D2N -- return the number of decNumber structs that would be */
- /* needed to contain that number of digits (and the initial */
- /* decNumber struct) safely. Note that one Unit is included in the */
- /* initial structure. Used for allocating space that is aligned on */
- /* a decNumber struct boundary. */
- #define D2N(d) \
- ((((SD2U(d)-1)*sizeof(Unit))+sizeof(decNumber)*2-1)/sizeof(decNumber))
-
- /* TODIGIT -- macro to remove the leading digit from the unsigned */
- /* integer u at column cut (counting from the right, LSD=0) and */
- /* place it as an ASCII character into the character pointed to by */
- /* c. Note that cut must be <= 9, and the maximum value for u is */
- /* 2,000,000,000 (as is needed for negative exponents of */
- /* subnormals). The unsigned integer pow is used as a temporary */
- /* variable. */
- #define TODIGIT(u, cut, c, pow) { \
- *(c)='0'; \
- pow=DECPOWERS[cut]*2; \
- if ((u)>pow) { \
- pow*=4; \
- if ((u)>=pow) {(u)-=pow; *(c)+=8;} \
- pow/=2; \
- if ((u)>=pow) {(u)-=pow; *(c)+=4;} \
- pow/=2; \
- } \
- if ((u)>=pow) {(u)-=pow; *(c)+=2;} \
- pow/=2; \
- if ((u)>=pow) {(u)-=pow; *(c)+=1;} \
- }
-
- /* ---------------------------------------------------------------- */
- /* Definitions for fixed-precision modules (only valid after */
- /* decSingle.h, decDouble.h, or decQuad.h has been included) */
- /* ---------------------------------------------------------------- */
-
- /* bcdnum -- a structure describing a format-independent finite */
- /* number, whose coefficient is a string of bcd8 uBytes */
- typedef struct {
- uByte *msd; /* -> most significant digit */
- uByte *lsd; /* -> least ditto */
- uInt sign; /* 0=positive, DECFLOAT_Sign=negative */
- Int exponent; /* Unadjusted signed exponent (q), or */
- /* DECFLOAT_NaN etc. for a special */
- } bcdnum;
-
- /* Test if exponent or bcdnum exponent must be a special, etc. */
- #define EXPISSPECIAL(exp) ((exp)>=DECFLOAT_MinSp)
- #define EXPISINF(exp) (exp==DECFLOAT_Inf)
- #define EXPISNAN(exp) (exp==DECFLOAT_qNaN || exp==DECFLOAT_sNaN)
- #define NUMISSPECIAL(num) (EXPISSPECIAL((num)->exponent))
-
- /* Refer to a 32-bit word or byte in a decFloat (df) by big-endian */
- /* (array) notation (the 0 word or byte contains the sign bit), */
- /* automatically adjusting for endianness; similarly address a word */
- /* in the next-wider format (decFloatWider, or dfw) */
- #define DECWORDS (DECBYTES/4)
- #define DECWWORDS (DECWBYTES/4)
- #if DECLITEND
- #define DFWORD(df, off) ((df)->words[DECWORDS-1-(off)])
- #define DFBYTE(df, off) ((df)->bytes[DECBYTES-1-(off)])
- #define DFWWORD(dfw, off) ((dfw)->words[DECWWORDS-1-(off)])
- #else
- #define DFWORD(df, off) ((df)->words[off])
- #define DFBYTE(df, off) ((df)->bytes[off])
- #define DFWWORD(dfw, off) ((dfw)->words[off])
- #endif
-
- /* Tests for sign or specials, directly on DECFLOATs */
- #define DFISSIGNED(df) (DFWORD(df, 0)&0x80000000)
- #define DFISSPECIAL(df) ((DFWORD(df, 0)&0x78000000)==0x78000000)
- #define DFISINF(df) ((DFWORD(df, 0)&0x7c000000)==0x78000000)
- #define DFISNAN(df) ((DFWORD(df, 0)&0x7c000000)==0x7c000000)
- #define DFISQNAN(df) ((DFWORD(df, 0)&0x7e000000)==0x7c000000)
- #define DFISSNAN(df) ((DFWORD(df, 0)&0x7e000000)==0x7e000000)
-
- /* Shared lookup tables */
- extern const uInt DECCOMBMSD[64]; /* Combination field -> MSD */
- extern const uInt DECCOMBFROM[48]; /* exp+msd -> Combination */
-
- /* Private generic (utility) routine */
- #if DECCHECK || DECTRACE
- extern void decShowNum(const bcdnum *, const char *);
- #endif
-
- /* Format-dependent macros and constants */
- #if defined(DECPMAX)
-
- /* Useful constants */
- #define DECPMAX9 (ROUNDUP(DECPMAX, 9)/9) /* 'Pmax' in 10**9s */
- /* Top words for a zero */
- #define SINGLEZERO 0x22500000
- #define DOUBLEZERO 0x22380000
- #define QUADZERO 0x22080000
- /* [ZEROWORD is defined to be one of these in the DFISZERO macro] */
-
- /* Format-dependent common tests: */
- /* DFISZERO -- test for (any) zero */
- /* DFISCCZERO -- test for coefficient continuation being zero */
- /* DFISCC01 -- test for coefficient contains only 0s and 1s */
- /* DFISINT -- test for finite and exponent q=0 */
- /* DFISUINT01 -- test for sign=0, finite, exponent q=0, and */
- /* MSD=0 or 1 */
- /* ZEROWORD is also defined here. */
- /* In DFISZERO the first test checks the least-significant word */
- /* (most likely to be non-zero); the penultimate tests MSD and */
- /* DPDs in the signword, and the final test excludes specials and */
- /* MSD>7. DFISINT similarly has to allow for the two forms of */
- /* MSD codes. DFISUINT01 only has to allow for one form of MSD */
- /* code. */
- #if DECPMAX==7
- #define ZEROWORD SINGLEZERO
- /* [test macros not needed except for Zero] */
- #define DFISZERO(df) ((DFWORD(df, 0)&0x1c0fffff)==0 \
- && (DFWORD(df, 0)&0x60000000)!=0x60000000)
- #elif DECPMAX==16
- #define ZEROWORD DOUBLEZERO
- #define DFISZERO(df) ((DFWORD(df, 1)==0 \
- && (DFWORD(df, 0)&0x1c03ffff)==0 \
- && (DFWORD(df, 0)&0x60000000)!=0x60000000))
- #define DFISINT(df) ((DFWORD(df, 0)&0x63fc0000)==0x22380000 \
- ||(DFWORD(df, 0)&0x7bfc0000)==0x6a380000)
- #define DFISUINT01(df) ((DFWORD(df, 0)&0xfbfc0000)==0x22380000)
- #define DFISCCZERO(df) (DFWORD(df, 1)==0 \
- && (DFWORD(df, 0)&0x0003ffff)==0)
- #define DFISCC01(df) ((DFWORD(df, 0)&~0xfffc9124)==0 \
- && (DFWORD(df, 1)&~0x49124491)==0)
- #elif DECPMAX==34
- #define ZEROWORD QUADZERO
- #define DFISZERO(df) ((DFWORD(df, 3)==0 \
- && DFWORD(df, 2)==0 \
- && DFWORD(df, 1)==0 \
- && (DFWORD(df, 0)&0x1c003fff)==0 \
- && (DFWORD(df, 0)&0x60000000)!=0x60000000))
- #define DFISINT(df) ((DFWORD(df, 0)&0x63ffc000)==0x22080000 \
- ||(DFWORD(df, 0)&0x7bffc000)==0x6a080000)
- #define DFISUINT01(df) ((DFWORD(df, 0)&0xfbffc000)==0x22080000)
- #define DFISCCZERO(df) (DFWORD(df, 3)==0 \
- && DFWORD(df, 2)==0 \
- && DFWORD(df, 1)==0 \
- && (DFWORD(df, 0)&0x00003fff)==0)
-
- #define DFISCC01(df) ((DFWORD(df, 0)&~0xffffc912)==0 \
- && (DFWORD(df, 1)&~0x44912449)==0 \
- && (DFWORD(df, 2)&~0x12449124)==0 \
- && (DFWORD(df, 3)&~0x49124491)==0)
- #endif
-
- /* Macros to test if a certain 10 bits of a uInt or pair of uInts */
- /* are a canonical declet [higher or lower bits are ignored]. */
- /* declet is at offset 0 (from the right) in a uInt: */
- #define CANONDPD(dpd) (((dpd)&0x300)==0 || ((dpd)&0x6e)!=0x6e)
- /* declet is at offset k (a multiple of 2) in a uInt: */
- #define CANONDPDOFF(dpd, k) (((dpd)&(0x300<<(k)))==0 \
- || ((dpd)&(((uInt)0x6e)<<(k)))!=(((uInt)0x6e)<<(k)))
- /* declet is at offset k (a multiple of 2) in a pair of uInts: */
- /* [the top 2 bits will always be in the more-significant uInt] */
- #define CANONDPDTWO(hi, lo, k) (((hi)&(0x300>>(32-(k))))==0 \
- || ((hi)&(0x6e>>(32-(k))))!=(0x6e>>(32-(k))) \
- || ((lo)&(((uInt)0x6e)<<(k)))!=(((uInt)0x6e)<<(k)))
-
- /* Macro to test whether a full-length (length DECPMAX) BCD8 */
- /* coefficient is zero */
- /* test just the LSWord first, then the remainder */
- #if DECPMAX==7
- #define ISCOEFFZERO(u) (UINTAT((u)+DECPMAX-4)==0 \
- && UINTAT((u)+DECPMAX-7)==0)
- #elif DECPMAX==16
- #define ISCOEFFZERO(u) (UINTAT((u)+DECPMAX-4)==0 \
- && (UINTAT((u)+DECPMAX-8)+UINTAT((u)+DECPMAX-12) \
- +UINTAT((u)+DECPMAX-16))==0)
- #elif DECPMAX==34
- #define ISCOEFFZERO(u) (UINTAT((u)+DECPMAX-4)==0 \
- && (UINTAT((u)+DECPMAX-8) +UINTAT((u)+DECPMAX-12) \
- +UINTAT((u)+DECPMAX-16)+UINTAT((u)+DECPMAX-20) \
- +UINTAT((u)+DECPMAX-24)+UINTAT((u)+DECPMAX-28) \
- +UINTAT((u)+DECPMAX-32)+USHORTAT((u)+DECPMAX-34))==0)
- #endif
-
- /* Macros and masks for the exponent continuation field and MSD */
- /* Get the exponent continuation from a decFloat *df as an Int */
- #define GETECON(df) ((Int)((DFWORD((df), 0)&0x03ffffff)>>(32-6-DECECONL)))
- /* Ditto, from the next-wider format */
- #define GETWECON(df) ((Int)((DFWWORD((df), 0)&0x03ffffff)>>(32-6-DECWECONL)))
- /* Get the biased exponent similarly */
- #define GETEXP(df) ((Int)(DECCOMBEXP[DFWORD((df), 0)>>26]+GETECON(df)))
- /* Get the unbiased exponent similarly */
- #define GETEXPUN(df) ((Int)GETEXP(df)-DECBIAS)
- /* Get the MSD similarly (as uInt) */
- #define GETMSD(df) (DECCOMBMSD[DFWORD((df), 0)>>26])
-
- /* Compile-time computes of the exponent continuation field masks */
- /* full exponent continuation field: */
- #define ECONMASK ((0x03ffffff>>(32-6-DECECONL))<<(32-6-DECECONL))
- /* same, not including its first digit (the qNaN/sNaN selector): */
- #define ECONNANMASK ((0x01ffffff>>(32-6-DECECONL))<<(32-6-DECECONL))
-
- /* Macros to decode the coefficient in a finite decFloat *df into */
- /* a BCD string (uByte *bcdin) of length DECPMAX uBytes */
-
- /* In-line sequence to convert 10 bits at right end of uInt dpd */
- /* to three BCD8 digits starting at uByte u. Note that an extra */
- /* byte is written to the right of the three digits because this */
- /* moves four at a time for speed; the alternative macro moves */
- /* exactly three bytes */
- #define dpd2bcd8(u, dpd) { \
- UINTAT(u)=UINTAT(&DPD2BCD8[((dpd)&0x3ff)*4]);}
-
- #define dpd2bcd83(u, dpd) { \
- *(u)=DPD2BCD8[((dpd)&0x3ff)*4]; \
- *(u+1)=DPD2BCD8[((dpd)&0x3ff)*4+1]; \
- *(u+2)=DPD2BCD8[((dpd)&0x3ff)*4+2];}
-
- /* Decode the declets. After extracting each one, it is decoded */
- /* to BCD8 using a table lookup (also used for variable-length */
- /* decode). Each DPD decode is 3 bytes BCD8 plus a one-byte */
- /* length which is not used, here). Fixed-length 4-byte moves */
- /* are fast, however, almost everywhere, and so are used except */
- /* for the final three bytes (to avoid overrun). The code below */
- /* is 36 instructions for Doubles and about 70 for Quads, even */
- /* on IA32. */
-
- /* Two macros are defined for each format: */
- /* GETCOEFF extracts the coefficient of the current format */
- /* GETWCOEFF extracts the coefficient of the next-wider format. */
- /* The latter is a copy of the next-wider GETCOEFF using DFWWORD. */
-
- #if DECPMAX==7
- #define GETCOEFF(df, bcd) { \
- uInt sourhi=DFWORD(df, 0); \
- *(bcd)=(uByte)DECCOMBMSD[sourhi>>26]; \
- dpd2bcd8(bcd+1, sourhi>>10); \
- dpd2bcd83(bcd+4, sourhi);}
- #define GETWCOEFF(df, bcd) { \
- uInt sourhi=DFWWORD(df, 0); \
- uInt sourlo=DFWWORD(df, 1); \
- *(bcd)=(uByte)DECCOMBMSD[sourhi>>26]; \
- dpd2bcd8(bcd+1, sourhi>>8); \
- dpd2bcd8(bcd+4, (sourhi<<2) | (sourlo>>30)); \
- dpd2bcd8(bcd+7, sourlo>>20); \
- dpd2bcd8(bcd+10, sourlo>>10); \
- dpd2bcd83(bcd+13, sourlo);}
-
- #elif DECPMAX==16
- #define GETCOEFF(df, bcd) { \
- uInt sourhi=DFWORD(df, 0); \
- uInt sourlo=DFWORD(df, 1); \
- *(bcd)=(uByte)DECCOMBMSD[sourhi>>26]; \
- dpd2bcd8(bcd+1, sourhi>>8); \
- dpd2bcd8(bcd+4, (sourhi<<2) | (sourlo>>30)); \
- dpd2bcd8(bcd+7, sourlo>>20); \
- dpd2bcd8(bcd+10, sourlo>>10); \
- dpd2bcd83(bcd+13, sourlo);}
- #define GETWCOEFF(df, bcd) { \
- uInt sourhi=DFWWORD(df, 0); \
- uInt sourmh=DFWWORD(df, 1); \
- uInt sourml=DFWWORD(df, 2); \
- uInt sourlo=DFWWORD(df, 3); \
- *(bcd)=(uByte)DECCOMBMSD[sourhi>>26]; \
- dpd2bcd8(bcd+1, sourhi>>4); \
- dpd2bcd8(bcd+4, ((sourhi)<<6) | (sourmh>>26)); \
- dpd2bcd8(bcd+7, sourmh>>16); \
- dpd2bcd8(bcd+10, sourmh>>6); \
- dpd2bcd8(bcd+13, ((sourmh)<<4) | (sourml>>28)); \
- dpd2bcd8(bcd+16, sourml>>18); \
- dpd2bcd8(bcd+19, sourml>>8); \
- dpd2bcd8(bcd+22, ((sourml)<<2) | (sourlo>>30)); \
- dpd2bcd8(bcd+25, sourlo>>20); \
- dpd2bcd8(bcd+28, sourlo>>10); \
- dpd2bcd83(bcd+31, sourlo);}
-
- #elif DECPMAX==34
- #define GETCOEFF(df, bcd) { \
- uInt sourhi=DFWORD(df, 0); \
- uInt sourmh=DFWORD(df, 1); \
- uInt sourml=DFWORD(df, 2); \
- uInt sourlo=DFWORD(df, 3); \
- *(bcd)=(uByte)DECCOMBMSD[sourhi>>26]; \
- dpd2bcd8(bcd+1, sourhi>>4); \
- dpd2bcd8(bcd+4, ((sourhi)<<6) | (sourmh>>26)); \
- dpd2bcd8(bcd+7, sourmh>>16); \
- dpd2bcd8(bcd+10, sourmh>>6); \
- dpd2bcd8(bcd+13, ((sourmh)<<4) | (sourml>>28)); \
- dpd2bcd8(bcd+16, sourml>>18); \
- dpd2bcd8(bcd+19, sourml>>8); \
- dpd2bcd8(bcd+22, ((sourml)<<2) | (sourlo>>30)); \
- dpd2bcd8(bcd+25, sourlo>>20); \
- dpd2bcd8(bcd+28, sourlo>>10); \
- dpd2bcd83(bcd+31, sourlo);}
-
- #define GETWCOEFF(df, bcd) {??} /* [should never be used] */
- #endif
-
- /* Macros to decode the coefficient in a finite decFloat *df into */
- /* a base-billion uInt array, with the least-significant */
- /* 0-999999999 'digit' at offset 0. */
-
- /* Decode the declets. After extracting each one, it is decoded */
- /* to binary using a table lookup. Three tables are used; one */
- /* the usual DPD to binary, the other two pre-multiplied by 1000 */
- /* and 1000000 to avoid multiplication during decode. These */
- /* tables can also be used for multiplying up the MSD as the DPD */
- /* code for 0 through 9 is the identity. */
- #define DPD2BIN0 DPD2BIN /* for prettier code */
-
- #if DECPMAX==7
- #define GETCOEFFBILL(df, buf) { \
- uInt sourhi=DFWORD(df, 0); \
- (buf)[0]=DPD2BIN0[sourhi&0x3ff] \
- +DPD2BINK[(sourhi>>10)&0x3ff] \
- +DPD2BINM[DECCOMBMSD[sourhi>>26]];}
-
- #elif DECPMAX==16
- #define GETCOEFFBILL(df, buf) { \
- uInt sourhi, sourlo; \
- sourlo=DFWORD(df, 1); \
- (buf)[0]=DPD2BIN0[sourlo&0x3ff] \
- +DPD2BINK[(sourlo>>10)&0x3ff] \
- +DPD2BINM[(sourlo>>20)&0x3ff]; \
- sourhi=DFWORD(df, 0); \
- (buf)[1]=DPD2BIN0[((sourhi<<2) | (sourlo>>30))&0x3ff] \
- +DPD2BINK[(sourhi>>8)&0x3ff] \
- +DPD2BINM[DECCOMBMSD[sourhi>>26]];}
-
- #elif DECPMAX==34
- #define GETCOEFFBILL(df, buf) { \
- uInt sourhi, sourmh, sourml, sourlo; \
- sourlo=DFWORD(df, 3); \
- (buf)[0]=DPD2BIN0[sourlo&0x3ff] \
- +DPD2BINK[(sourlo>>10)&0x3ff] \
- +DPD2BINM[(sourlo>>20)&0x3ff]; \
- sourml=DFWORD(df, 2); \
- (buf)[1]=DPD2BIN0[((sourml<<2) | (sourlo>>30))&0x3ff] \
- +DPD2BINK[(sourml>>8)&0x3ff] \
- +DPD2BINM[(sourml>>18)&0x3ff]; \
- sourmh=DFWORD(df, 1); \
- (buf)[2]=DPD2BIN0[((sourmh<<4) | (sourml>>28))&0x3ff] \
- +DPD2BINK[(sourmh>>6)&0x3ff] \
- +DPD2BINM[(sourmh>>16)&0x3ff]; \
- sourhi=DFWORD(df, 0); \
- (buf)[3]=DPD2BIN0[((sourhi<<6) | (sourmh>>26))&0x3ff] \
- +DPD2BINK[(sourhi>>4)&0x3ff] \
- +DPD2BINM[DECCOMBMSD[sourhi>>26]];}
-
- #endif
-
- /* Macros to decode the coefficient in a finite decFloat *df into */
- /* a base-thousand uInt array, with the least-significant 0-999 */
- /* 'digit' at offset 0. */
-
- /* Decode the declets. After extracting each one, it is decoded */
- /* to binary using a table lookup. */
- #if DECPMAX==7
- #define GETCOEFFTHOU(df, buf) { \
- uInt sourhi=DFWORD(df, 0); \
- (buf)[0]=DPD2BIN[sourhi&0x3ff]; \
- (buf)[1]=DPD2BIN[(sourhi>>10)&0x3ff]; \
- (buf)[2]=DECCOMBMSD[sourhi>>26];}
-
- #elif DECPMAX==16
- #define GETCOEFFTHOU(df, buf) { \
- uInt sourhi, sourlo; \
- sourlo=DFWORD(df, 1); \
- (buf)[0]=DPD2BIN[sourlo&0x3ff]; \
- (buf)[1]=DPD2BIN[(sourlo>>10)&0x3ff]; \
- (buf)[2]=DPD2BIN[(sourlo>>20)&0x3ff]; \
- sourhi=DFWORD(df, 0); \
- (buf)[3]=DPD2BIN[((sourhi<<2) | (sourlo>>30))&0x3ff]; \
- (buf)[4]=DPD2BIN[(sourhi>>8)&0x3ff]; \
- (buf)[5]=DECCOMBMSD[sourhi>>26];}
-
- #elif DECPMAX==34
- #define GETCOEFFTHOU(df, buf) { \
- uInt sourhi, sourmh, sourml, sourlo; \
- sourlo=DFWORD(df, 3); \
- (buf)[0]=DPD2BIN[sourlo&0x3ff]; \
- (buf)[1]=DPD2BIN[(sourlo>>10)&0x3ff]; \
- (buf)[2]=DPD2BIN[(sourlo>>20)&0x3ff]; \
- sourml=DFWORD(df, 2); \
- (buf)[3]=DPD2BIN[((sourml<<2) | (sourlo>>30))&0x3ff]; \
- (buf)[4]=DPD2BIN[(sourml>>8)&0x3ff]; \
- (buf)[5]=DPD2BIN[(sourml>>18)&0x3ff]; \
- sourmh=DFWORD(df, 1); \
- (buf)[6]=DPD2BIN[((sourmh<<4) | (sourml>>28))&0x3ff]; \
- (buf)[7]=DPD2BIN[(sourmh>>6)&0x3ff]; \
- (buf)[8]=DPD2BIN[(sourmh>>16)&0x3ff]; \
- sourhi=DFWORD(df, 0); \
- (buf)[9]=DPD2BIN[((sourhi<<6) | (sourmh>>26))&0x3ff]; \
- (buf)[10]=DPD2BIN[(sourhi>>4)&0x3ff]; \
- (buf)[11]=DECCOMBMSD[sourhi>>26];}
-
- #endif
-
- /* Set a decFloat to the maximum positive finite number (Nmax) */
- #if DECPMAX==7
- #define DFSETNMAX(df) \
- {DFWORD(df, 0)=0x77f3fcff;}
- #elif DECPMAX==16
- #define DFSETNMAX(df) \
- {DFWORD(df, 0)=0x77fcff3f; \
- DFWORD(df, 1)=0xcff3fcff;}
- #elif DECPMAX==34
- #define DFSETNMAX(df) \
- {DFWORD(df, 0)=0x77ffcff3; \
- DFWORD(df, 1)=0xfcff3fcf; \
- DFWORD(df, 2)=0xf3fcff3f; \
- DFWORD(df, 3)=0xcff3fcff;}
- #endif
-
- /* [end of format-dependent macros and constants] */
- #endif
-
-#endif
+++ /dev/null
-/* Decimal 128-bit format module header for the decNumber C Library.
- Copyright (C) 2005, 2007 Free Software Foundation, Inc.
- Contributed by IBM Corporation. Author Mike Cowlishaw.
-
- This file is part of GCC.
-
- GCC is free software; you can redistribute it and/or modify it under
- the terms of the GNU General Public License as published by the Free
- Software Foundation; either version 2, or (at your option) any later
- version.
-
- In addition to the permissions in the GNU General Public License,
- the Free Software Foundation gives you unlimited permission to link
- the compiled version of this file into combinations with other
- programs, and to distribute those combinations without any
- restriction coming from the use of this file. (The General Public
- License restrictions do apply in other respects; for example, they
- cover modification of the file, and distribution when not linked
- into a combine executable.)
-
- GCC is distributed in the hope that it will be useful, but WITHOUT ANY
- WARRANTY; without even the implied warranty of MERCHANTABILITY or
- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
- for more details.
-
- You should have received a copy of the GNU General Public License
- along with GCC; see the file COPYING. If not, write to the Free
- Software Foundation, 51 Franklin Street, Fifth Floor, Boston, MA
- 02110-1301, USA. */
-
-/* ------------------------------------------------------------------ */
-/* Decimal 128-bit format module header */
-/* ------------------------------------------------------------------ */
-
-#ifndef DECIMAL128_H
-#define DECIMAL128_H
-
- #define DEC128NAME "decimal128" /* Short name */
- #define DEC128FULLNAME "Decimal 128-bit Number" /* Verbose name */
- #define DEC128AUTHOR "Mike Cowlishaw" /* Who to blame */
-
- /* parameters for decimal128s */
- #define DECIMAL128_Bytes 16 /* length */
- #define DECIMAL128_Pmax 34 /* maximum precision (digits) */
- #define DECIMAL128_Emax 6144 /* maximum adjusted exponent */
- #define DECIMAL128_Emin -6143 /* minimum adjusted exponent */
- #define DECIMAL128_Bias 6176 /* bias for the exponent */
- #define DECIMAL128_String 43 /* maximum string length, +1 */
- #define DECIMAL128_EconL 12 /* exp. continuation length */
- /* highest biased exponent (Elimit-1) */
- #define DECIMAL128_Ehigh (DECIMAL128_Emax+DECIMAL128_Bias-DECIMAL128_Pmax+1)
-
- /* check enough digits, if pre-defined */
- #if defined(DECNUMDIGITS)
- #if (DECNUMDIGITS<DECIMAL128_Pmax)
- #error decimal128.h needs pre-defined DECNUMDIGITS>=34 for safe use
- #endif
- #endif
-
- #ifndef DECNUMDIGITS
- #define DECNUMDIGITS DECIMAL128_Pmax /* size if not already defined*/
- #endif
- #include "libdecnumber/decNumber.h"
-
- /* Decimal 128-bit type, accessible by bytes */
- typedef struct {
- uint8_t bytes[DECIMAL128_Bytes]; /* decimal128: 1, 5, 12, 110 bits*/
- } decimal128;
-
- /* special values [top byte excluding sign bit; last two bits are */
- /* don't-care for Infinity on input, last bit don't-care for NaN] */
- #if !defined(DECIMAL_NaN)
- #define DECIMAL_NaN 0x7c /* 0 11111 00 NaN */
- #define DECIMAL_sNaN 0x7e /* 0 11111 10 sNaN */
- #define DECIMAL_Inf 0x78 /* 0 11110 00 Infinity */
- #endif
-
- #include "decimal128Local.h"
-
- /* ---------------------------------------------------------------- */
- /* Routines */
- /* ---------------------------------------------------------------- */
-
-
- /* String conversions */
- decimal128 * decimal128FromString(decimal128 *, const char *, decContext *);
- char * decimal128ToString(const decimal128 *, char *);
- char * decimal128ToEngString(const decimal128 *, char *);
-
- /* decNumber conversions */
- decimal128 * decimal128FromNumber(decimal128 *, const decNumber *,
- decContext *);
- decNumber * decimal128ToNumber(const decimal128 *, decNumber *);
-
- /* Format-dependent utilities */
- uint32_t decimal128IsCanonical(const decimal128 *);
- decimal128 * decimal128Canonical(decimal128 *, const decimal128 *);
-
-#endif
+++ /dev/null
-/* Local definitions for use with the decNumber C Library.
- Copyright (C) 2007 Free Software Foundation, Inc.
-
- This file is part of GCC.
-
- GCC is free software; you can redistribute it and/or modify it under
- the terms of the GNU General Public License as published by the Free
- Software Foundation; either version 2, or (at your option) any later
- version.
-
- In addition to the permissions in the GNU General Public License,
- the Free Software Foundation gives you unlimited permission to link
- the compiled version of this file into combinations with other
- programs, and to distribute those combinations without any
- restriction coming from the use of this file. (The General Public
- License restrictions do apply in other respects; for example, they
- cover modification of the file, and distribution when not linked
- into a combine executable.)
-
- GCC is distributed in the hope that it will be useful, but WITHOUT ANY
- WARRANTY; without even the implied warranty of MERCHANTABILITY or
- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
- for more details.
-
- You should have received a copy of the GNU General Public License
- along with GCC; see the file COPYING. If not, write to the Free
- Software Foundation, 51 Franklin Street, Fifth Floor, Boston, MA
- 02110-1301, USA. */
-
-#if !defined(DECIMAL128LOCAL)
-
-/* The compiler needs sign manipulation functions for decimal128 which
- are not part of the decNumber package. */
-
-/* Set sign; this assumes the sign was previously zero. */
-#define decimal128SetSign(d,b) \
- { (d)->bytes[WORDS_BIGENDIAN ? 0 : 15] |= ((unsigned) (b) << 7); }
-
-/* Clear sign. */
-#define decimal128ClearSign(d) \
- { (d)->bytes[WORDS_BIGENDIAN ? 0 : 15] &= ~0x80; }
-
-/* Flip sign. */
-#define decimal128FlipSign(d) \
- { (d)->bytes[WORDS_BIGENDIAN ? 0 : 15] ^= 0x80; }
-
-#endif
+++ /dev/null
-/* Decimal 32-bit format module header for the decNumber C Library.
- Copyright (C) 2005, 2007 Free Software Foundation, Inc.
- Contributed by IBM Corporation. Author Mike Cowlishaw.
-
- This file is part of GCC.
-
- GCC is free software; you can redistribute it and/or modify it under
- the terms of the GNU General Public License as published by the Free
- Software Foundation; either version 2, or (at your option) any later
- version.
-
- In addition to the permissions in the GNU General Public License,
- the Free Software Foundation gives you unlimited permission to link
- the compiled version of this file into combinations with other
- programs, and to distribute those combinations without any
- restriction coming from the use of this file. (The General Public
- License restrictions do apply in other respects; for example, they
- cover modification of the file, and distribution when not linked
- into a combine executable.)
-
- GCC is distributed in the hope that it will be useful, but WITHOUT ANY
- WARRANTY; without even the implied warranty of MERCHANTABILITY or
- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
- for more details.
-
- You should have received a copy of the GNU General Public License
- along with GCC; see the file COPYING. If not, write to the Free
- Software Foundation, 51 Franklin Street, Fifth Floor, Boston, MA
- 02110-1301, USA. */
-
-/* ------------------------------------------------------------------ */
-/* Decimal 32-bit format module header */
-/* ------------------------------------------------------------------ */
-
-#ifndef DECIMAL32_H
-#define DECIMAL32_H
-
- #define DEC32NAME "decimal32" /* Short name */
- #define DEC32FULLNAME "Decimal 32-bit Number" /* Verbose name */
- #define DEC32AUTHOR "Mike Cowlishaw" /* Who to blame */
-
- /* parameters for decimal32s */
- #define DECIMAL32_Bytes 4 /* length */
- #define DECIMAL32_Pmax 7 /* maximum precision (digits) */
- #define DECIMAL32_Emax 96 /* maximum adjusted exponent */
- #define DECIMAL32_Emin -95 /* minimum adjusted exponent */
- #define DECIMAL32_Bias 101 /* bias for the exponent */
- #define DECIMAL32_String 15 /* maximum string length, +1 */
- #define DECIMAL32_EconL 6 /* exp. continuation length */
- /* highest biased exponent (Elimit-1) */
- #define DECIMAL32_Ehigh (DECIMAL32_Emax+DECIMAL32_Bias-DECIMAL32_Pmax+1)
-
- /* check enough digits, if pre-defined */
- #if defined(DECNUMDIGITS)
- #if (DECNUMDIGITS<DECIMAL32_Pmax)
- #error decimal32.h needs pre-defined DECNUMDIGITS>=7 for safe use
- #endif
- #endif
-
- #ifndef DECNUMDIGITS
- #define DECNUMDIGITS DECIMAL32_Pmax /* size if not already defined*/
- #endif
- #include "libdecnumber/decNumber.h"
-
- /* Decimal 32-bit type, accessible by bytes */
- typedef struct {
- uint8_t bytes[DECIMAL32_Bytes]; /* decimal32: 1, 5, 6, 20 bits*/
- } decimal32;
-
- /* special values [top byte excluding sign bit; last two bits are */
- /* don't-care for Infinity on input, last bit don't-care for NaN] */
- #if !defined(DECIMAL_NaN)
- #define DECIMAL_NaN 0x7c /* 0 11111 00 NaN */
- #define DECIMAL_sNaN 0x7e /* 0 11111 10 sNaN */
- #define DECIMAL_Inf 0x78 /* 0 11110 00 Infinity */
- #endif
-
- /* ---------------------------------------------------------------- */
- /* Routines */
- /* ---------------------------------------------------------------- */
-
-
- /* String conversions */
- decimal32 * decimal32FromString(decimal32 *, const char *, decContext *);
- char * decimal32ToString(const decimal32 *, char *);
- char * decimal32ToEngString(const decimal32 *, char *);
-
- /* decNumber conversions */
- decimal32 * decimal32FromNumber(decimal32 *, const decNumber *,
- decContext *);
- decNumber * decimal32ToNumber(const decimal32 *, decNumber *);
-
- /* Format-dependent utilities */
- uint32_t decimal32IsCanonical(const decimal32 *);
- decimal32 * decimal32Canonical(decimal32 *, const decimal32 *);
-
-#endif
+++ /dev/null
-/* Decimal 64-bit format module header for the decNumber C Library.
- Copyright (C) 2005, 2007 Free Software Foundation, Inc.
- Contributed by IBM Corporation. Author Mike Cowlishaw.
-
- This file is part of GCC.
-
- GCC is free software; you can redistribute it and/or modify it under
- the terms of the GNU General Public License as published by the Free
- Software Foundation; either version 2, or (at your option) any later
- version.
-
- In addition to the permissions in the GNU General Public License,
- the Free Software Foundation gives you unlimited permission to link
- the compiled version of this file into combinations with other
- programs, and to distribute those combinations without any
- restriction coming from the use of this file. (The General Public
- License restrictions do apply in other respects; for example, they
- cover modification of the file, and distribution when not linked
- into a combine executable.)
-
- GCC is distributed in the hope that it will be useful, but WITHOUT ANY
- WARRANTY; without even the implied warranty of MERCHANTABILITY or
- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
- for more details.
-
- You should have received a copy of the GNU General Public License
- along with GCC; see the file COPYING. If not, write to the Free
- Software Foundation, 51 Franklin Street, Fifth Floor, Boston, MA
- 02110-1301, USA. */
-
-/* ------------------------------------------------------------------ */
-/* Decimal 64-bit format module header */
-/* ------------------------------------------------------------------ */
-
-#ifndef DECIMAL64_H
-#define DECIMAL64_H
-
- #define DEC64NAME "decimal64" /* Short name */
- #define DEC64FULLNAME "Decimal 64-bit Number" /* Verbose name */
- #define DEC64AUTHOR "Mike Cowlishaw" /* Who to blame */
-
-
- /* parameters for decimal64s */
- #define DECIMAL64_Bytes 8 /* length */
- #define DECIMAL64_Pmax 16 /* maximum precision (digits) */
- #define DECIMAL64_Emax 384 /* maximum adjusted exponent */
- #define DECIMAL64_Emin -383 /* minimum adjusted exponent */
- #define DECIMAL64_Bias 398 /* bias for the exponent */
- #define DECIMAL64_String 24 /* maximum string length, +1 */
- #define DECIMAL64_EconL 8 /* exp. continuation length */
- /* highest biased exponent (Elimit-1) */
- #define DECIMAL64_Ehigh (DECIMAL64_Emax+DECIMAL64_Bias-DECIMAL64_Pmax+1)
-
- /* check enough digits, if pre-defined */
- #if defined(DECNUMDIGITS)
- #if (DECNUMDIGITS<DECIMAL64_Pmax)
- #error decimal64.h needs pre-defined DECNUMDIGITS>=16 for safe use
- #endif
- #endif
-
-
- #ifndef DECNUMDIGITS
- #define DECNUMDIGITS DECIMAL64_Pmax /* size if not already defined*/
- #endif
- #include "libdecnumber/decNumber.h"
-
- /* Decimal 64-bit type, accessible by bytes */
- typedef struct {
- uint8_t bytes[DECIMAL64_Bytes]; /* decimal64: 1, 5, 8, 50 bits*/
- } decimal64;
-
- /* special values [top byte excluding sign bit; last two bits are */
- /* don't-care for Infinity on input, last bit don't-care for NaN] */
- #if !defined(DECIMAL_NaN)
- #define DECIMAL_NaN 0x7c /* 0 11111 00 NaN */
- #define DECIMAL_sNaN 0x7e /* 0 11111 10 sNaN */
- #define DECIMAL_Inf 0x78 /* 0 11110 00 Infinity */
- #endif
-
- /* ---------------------------------------------------------------- */
- /* Routines */
- /* ---------------------------------------------------------------- */
-
-
- /* String conversions */
- decimal64 * decimal64FromString(decimal64 *, const char *, decContext *);
- char * decimal64ToString(const decimal64 *, char *);
- char * decimal64ToEngString(const decimal64 *, char *);
-
- /* decNumber conversions */
- decimal64 * decimal64FromNumber(decimal64 *, const decNumber *,
- decContext *);
- decNumber * decimal64ToNumber(const decimal64 *, decNumber *);
-
- /* Format-dependent utilities */
- uint32_t decimal64IsCanonical(const decimal64 *);
- decimal64 * decimal64Canonical(decimal64 *, const decimal64 *);
-
-#endif
+++ /dev/null
-/* SPDX-License-Identifier: ((GPL-2.0 WITH Linux-syscall-note) OR BSD-3-Clause) */
-/*
- * Definitions for virtio-ccw devices.
- *
- * Copyright IBM Corp. 2013
- *
- * Author(s): Cornelia Huck <cornelia.huck@de.ibm.com>
- */
-#ifndef __KVM_VIRTIO_CCW_H
-#define __KVM_VIRTIO_CCW_H
-
-/* Alignment of vring buffers. */
-#define KVM_VIRTIO_CCW_RING_ALIGN 4096
-
-/* Subcode for diagnose 500 (virtio hypercall). */
-#define KVM_S390_VIRTIO_CCW_NOTIFY 3
-
-#endif
+++ /dev/null
-/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
-#ifndef _ASM_X86_BOOTPARAM_H
-#define _ASM_X86_BOOTPARAM_H
-
-/* setup_data/setup_indirect types */
-#define SETUP_NONE 0
-#define SETUP_E820_EXT 1
-#define SETUP_DTB 2
-#define SETUP_PCI 3
-#define SETUP_EFI 4
-#define SETUP_APPLE_PROPERTIES 5
-#define SETUP_JAILHOUSE 6
-
-#define SETUP_INDIRECT (1<<31)
-
-/* SETUP_INDIRECT | max(SETUP_*) */
-#define SETUP_TYPE_MAX (SETUP_INDIRECT | SETUP_JAILHOUSE)
-
-/* ram_size flags */
-#define RAMDISK_IMAGE_START_MASK 0x07FF
-#define RAMDISK_PROMPT_FLAG 0x8000
-#define RAMDISK_LOAD_FLAG 0x4000
-
-/* loadflags */
-#define LOADED_HIGH (1<<0)
-#define KASLR_FLAG (1<<1)
-#define QUIET_FLAG (1<<5)
-#define KEEP_SEGMENTS (1<<6)
-#define CAN_USE_HEAP (1<<7)
-
-/* xloadflags */
-#define XLF_KERNEL_64 (1<<0)
-#define XLF_CAN_BE_LOADED_ABOVE_4G (1<<1)
-#define XLF_EFI_HANDOVER_32 (1<<2)
-#define XLF_EFI_HANDOVER_64 (1<<3)
-#define XLF_EFI_KEXEC (1<<4)
-#define XLF_5LEVEL (1<<5)
-#define XLF_5LEVEL_ENABLED (1<<6)
-
-
-#endif /* _ASM_X86_BOOTPARAM_H */
+++ /dev/null
-/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
-#ifndef _ASM_X86_KVM_PARA_H
-#define _ASM_X86_KVM_PARA_H
-
-#include "standard-headers/linux/types.h"
-
-/* This CPUID returns the signature 'KVMKVMKVM' in ebx, ecx, and edx. It
- * should be used to determine that a VM is running under KVM.
- */
-#define KVM_CPUID_SIGNATURE 0x40000000
-
-/* This CPUID returns two feature bitmaps in eax, edx. Before enabling
- * a particular paravirtualization, the appropriate feature bit should
- * be checked in eax. The performance hint feature bit should be checked
- * in edx.
- */
-#define KVM_CPUID_FEATURES 0x40000001
-#define KVM_FEATURE_CLOCKSOURCE 0
-#define KVM_FEATURE_NOP_IO_DELAY 1
-#define KVM_FEATURE_MMU_OP 2
-/* This indicates that the new set of kvmclock msrs
- * are available. The use of 0x11 and 0x12 is deprecated
- */
-#define KVM_FEATURE_CLOCKSOURCE2 3
-#define KVM_FEATURE_ASYNC_PF 4
-#define KVM_FEATURE_STEAL_TIME 5
-#define KVM_FEATURE_PV_EOI 6
-#define KVM_FEATURE_PV_UNHALT 7
-#define KVM_FEATURE_PV_TLB_FLUSH 9
-#define KVM_FEATURE_ASYNC_PF_VMEXIT 10
-#define KVM_FEATURE_PV_SEND_IPI 11
-#define KVM_FEATURE_POLL_CONTROL 12
-#define KVM_FEATURE_PV_SCHED_YIELD 13
-#define KVM_FEATURE_ASYNC_PF_INT 14
-
-#define KVM_HINTS_REALTIME 0
-
-/* The last 8 bits are used to indicate how to interpret the flags field
- * in pvclock structure. If no bits are set, all flags are ignored.
- */
-#define KVM_FEATURE_CLOCKSOURCE_STABLE_BIT 24
-
-#define MSR_KVM_WALL_CLOCK 0x11
-#define MSR_KVM_SYSTEM_TIME 0x12
-
-#define KVM_MSR_ENABLED 1
-/* Custom MSRs falls in the range 0x4b564d00-0x4b564dff */
-#define MSR_KVM_WALL_CLOCK_NEW 0x4b564d00
-#define MSR_KVM_SYSTEM_TIME_NEW 0x4b564d01
-#define MSR_KVM_ASYNC_PF_EN 0x4b564d02
-#define MSR_KVM_STEAL_TIME 0x4b564d03
-#define MSR_KVM_PV_EOI_EN 0x4b564d04
-#define MSR_KVM_POLL_CONTROL 0x4b564d05
-#define MSR_KVM_ASYNC_PF_INT 0x4b564d06
-#define MSR_KVM_ASYNC_PF_ACK 0x4b564d07
-
-struct kvm_steal_time {
- uint64_t steal;
- uint32_t version;
- uint32_t flags;
- uint8_t preempted;
- uint8_t uint8_t_pad[3];
- uint32_t pad[11];
-};
-
-#define KVM_VCPU_PREEMPTED (1 << 0)
-#define KVM_VCPU_FLUSH_TLB (1 << 1)
-
-#define KVM_CLOCK_PAIRING_WALLCLOCK 0
-struct kvm_clock_pairing {
- int64_t sec;
- int64_t nsec;
- uint64_t tsc;
- uint32_t flags;
- uint32_t pad[9];
-};
-
-#define KVM_STEAL_ALIGNMENT_BITS 5
-#define KVM_STEAL_VALID_BITS ((-1ULL << (KVM_STEAL_ALIGNMENT_BITS + 1)))
-#define KVM_STEAL_RESERVED_MASK (((1 << KVM_STEAL_ALIGNMENT_BITS) - 1 ) << 1)
-
-#define KVM_MAX_MMU_OP_BATCH 32
-
-#define KVM_ASYNC_PF_ENABLED (1 << 0)
-#define KVM_ASYNC_PF_SEND_ALWAYS (1 << 1)
-#define KVM_ASYNC_PF_DELIVERY_AS_PF_VMEXIT (1 << 2)
-#define KVM_ASYNC_PF_DELIVERY_AS_INT (1 << 3)
-
-/* MSR_KVM_ASYNC_PF_INT */
-#define KVM_ASYNC_PF_VEC_MASK GENMASK(7, 0)
-
-
-/* Operations for KVM_HC_MMU_OP */
-#define KVM_MMU_OP_WRITE_PTE 1
-#define KVM_MMU_OP_FLUSH_TLB 2
-#define KVM_MMU_OP_RELEASE_PT 3
-
-/* Payload for KVM_HC_MMU_OP */
-struct kvm_mmu_op_header {
- uint32_t op;
- uint32_t pad;
-};
-
-struct kvm_mmu_op_write_pte {
- struct kvm_mmu_op_header header;
- uint64_t pte_phys;
- uint64_t pte_val;
-};
-
-struct kvm_mmu_op_flush_tlb {
- struct kvm_mmu_op_header header;
-};
-
-struct kvm_mmu_op_release_pt {
- struct kvm_mmu_op_header header;
- uint64_t pt_phys;
-};
-
-#define KVM_PV_REASON_PAGE_NOT_PRESENT 1
-#define KVM_PV_REASON_PAGE_READY 2
-
-struct kvm_vcpu_pv_apf_data {
- /* Used for 'page not present' events delivered via #PF */
- uint32_t flags;
-
- /* Used for 'page ready' events delivered via interrupt notification */
- uint32_t token;
-
- uint8_t pad[56];
- uint32_t enabled;
-};
-
-#define KVM_PV_EOI_BIT 0
-#define KVM_PV_EOI_MASK (0x1 << KVM_PV_EOI_BIT)
-#define KVM_PV_EOI_ENABLED KVM_PV_EOI_MASK
-#define KVM_PV_EOI_DISABLED 0x0
-
-#endif /* _ASM_X86_KVM_PARA_H */
+++ /dev/null
-/*
- * Copyright (c) 2012-2016 VMware, Inc. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of EITHER the GNU General Public License
- * version 2 as published by the Free Software Foundation or the BSD
- * 2-Clause License. This program is distributed in the hope that it
- * will be useful, but WITHOUT ANY WARRANTY; WITHOUT EVEN THE IMPLIED
- * WARRANTY OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE.
- * See the GNU General Public License version 2 for more details at
- * http://www.gnu.org/licenses/old-licenses/gpl-2.0.en.html.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program available in the file COPYING in the main
- * directory of this source tree.
- *
- * The BSD 2-Clause License
- *
- * Redistribution and use in source and binary forms, with or
- * without modification, are permitted provided that the following
- * conditions are met:
- *
- * - Redistributions of source code must retain the above
- * copyright notice, this list of conditions and the following
- * disclaimer.
- *
- * - Redistributions in binary form must reproduce the above
- * copyright notice, this list of conditions and the following
- * disclaimer in the documentation and/or other materials
- * provided with the distribution.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
- * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
- * COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
- * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
- * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
- * OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-
-#ifndef __PVRDMA_DEV_API_H__
-#define __PVRDMA_DEV_API_H__
-
-#include "standard-headers/linux/types.h"
-
-#include "pvrdma_verbs.h"
-
-/*
- * PVRDMA version macros. Some new features require updates to PVRDMA_VERSION.
- * These macros allow us to check for different features if necessary.
- */
-
-#define PVRDMA_ROCEV1_VERSION 17
-#define PVRDMA_ROCEV2_VERSION 18
-#define PVRDMA_PPN64_VERSION 19
-#define PVRDMA_QPHANDLE_VERSION 20
-#define PVRDMA_VERSION PVRDMA_QPHANDLE_VERSION
-
-#define PVRDMA_BOARD_ID 1
-#define PVRDMA_REV_ID 1
-
-/*
- * Masks and accessors for page directory, which is a two-level lookup:
- * page directory -> page table -> page. Only one directory for now, but we
- * could expand that easily. 9 bits for tables, 9 bits for pages, gives one
- * gigabyte for memory regions and so forth.
- */
-
-#define PVRDMA_PDIR_SHIFT 18
-#define PVRDMA_PTABLE_SHIFT 9
-#define PVRDMA_PAGE_DIR_DIR(x) (((x) >> PVRDMA_PDIR_SHIFT) & 0x1)
-#define PVRDMA_PAGE_DIR_TABLE(x) (((x) >> PVRDMA_PTABLE_SHIFT) & 0x1ff)
-#define PVRDMA_PAGE_DIR_PAGE(x) ((x) & 0x1ff)
-#define PVRDMA_PAGE_DIR_MAX_PAGES (1 * 512 * 512)
-#define PVRDMA_MAX_FAST_REG_PAGES 128
-
-/*
- * Max MSI-X vectors.
- */
-
-#define PVRDMA_MAX_INTERRUPTS 3
-
-/* Register offsets within PCI resource on BAR1. */
-#define PVRDMA_REG_VERSION 0x00 /* R: Version of device. */
-#define PVRDMA_REG_DSRLOW 0x04 /* W: Device shared region low PA. */
-#define PVRDMA_REG_DSRHIGH 0x08 /* W: Device shared region high PA. */
-#define PVRDMA_REG_CTL 0x0c /* W: PVRDMA_DEVICE_CTL */
-#define PVRDMA_REG_REQUEST 0x10 /* W: Indicate device request. */
-#define PVRDMA_REG_ERR 0x14 /* R: Device error. */
-#define PVRDMA_REG_ICR 0x18 /* R: Interrupt cause. */
-#define PVRDMA_REG_IMR 0x1c /* R/W: Interrupt mask. */
-#define PVRDMA_REG_MACL 0x20 /* R/W: MAC address low. */
-#define PVRDMA_REG_MACH 0x24 /* R/W: MAC address high. */
-
-/* Object flags. */
-#define PVRDMA_CQ_FLAG_ARMED_SOL BIT(0) /* Armed for solicited-only. */
-#define PVRDMA_CQ_FLAG_ARMED BIT(1) /* Armed. */
-#define PVRDMA_MR_FLAG_DMA BIT(0) /* DMA region. */
-#define PVRDMA_MR_FLAG_FRMR BIT(1) /* Fast reg memory region. */
-
-/*
- * Atomic operation capability (masked versions are extended atomic
- * operations.
- */
-
-#define PVRDMA_ATOMIC_OP_COMP_SWAP BIT(0) /* Compare and swap. */
-#define PVRDMA_ATOMIC_OP_FETCH_ADD BIT(1) /* Fetch and add. */
-#define PVRDMA_ATOMIC_OP_MASK_COMP_SWAP BIT(2) /* Masked compare and swap. */
-#define PVRDMA_ATOMIC_OP_MASK_FETCH_ADD BIT(3) /* Masked fetch and add. */
-
-/*
- * Base Memory Management Extension flags to support Fast Reg Memory Regions
- * and Fast Reg Work Requests. Each flag represents a verb operation and we
- * must support all of them to qualify for the BMME device cap.
- */
-
-#define PVRDMA_BMME_FLAG_LOCAL_INV BIT(0) /* Local Invalidate. */
-#define PVRDMA_BMME_FLAG_REMOTE_INV BIT(1) /* Remote Invalidate. */
-#define PVRDMA_BMME_FLAG_FAST_REG_WR BIT(2) /* Fast Reg Work Request. */
-
-/*
- * GID types. The interpretation of the gid_types bit field in the device
- * capabilities will depend on the device mode. For now, the device only
- * supports RoCE as mode, so only the different GID types for RoCE are
- * defined.
- */
-
-#define PVRDMA_GID_TYPE_FLAG_ROCE_V1 BIT(0)
-#define PVRDMA_GID_TYPE_FLAG_ROCE_V2 BIT(1)
-
-/*
- * Version checks. This checks whether each version supports specific
- * capabilities from the device.
- */
-
-#define PVRDMA_IS_VERSION17(_dev) \
- (_dev->dsr_version == PVRDMA_ROCEV1_VERSION && \
- _dev->dsr->caps.gid_types == PVRDMA_GID_TYPE_FLAG_ROCE_V1)
-
-#define PVRDMA_IS_VERSION18(_dev) \
- (_dev->dsr_version >= PVRDMA_ROCEV2_VERSION && \
- (_dev->dsr->caps.gid_types == PVRDMA_GID_TYPE_FLAG_ROCE_V1 || \
- _dev->dsr->caps.gid_types == PVRDMA_GID_TYPE_FLAG_ROCE_V2)) \
-
-#define PVRDMA_SUPPORTED(_dev) \
- ((_dev->dsr->caps.mode == PVRDMA_DEVICE_MODE_ROCE) && \
- (PVRDMA_IS_VERSION17(_dev) || PVRDMA_IS_VERSION18(_dev)))
-
-/*
- * Get capability values based on device version.
- */
-
-#define PVRDMA_GET_CAP(_dev, _old_val, _val) \
- ((PVRDMA_IS_VERSION18(_dev)) ? _val : _old_val)
-
-enum pvrdma_pci_resource {
- PVRDMA_PCI_RESOURCE_MSIX, /* BAR0: MSI-X, MMIO. */
- PVRDMA_PCI_RESOURCE_REG, /* BAR1: Registers, MMIO. */
- PVRDMA_PCI_RESOURCE_UAR, /* BAR2: UAR pages, MMIO, 64-bit. */
- PVRDMA_PCI_RESOURCE_LAST, /* Last. */
-};
-
-enum pvrdma_device_ctl {
- PVRDMA_DEVICE_CTL_ACTIVATE, /* Activate device. */
- PVRDMA_DEVICE_CTL_UNQUIESCE, /* Unquiesce device. */
- PVRDMA_DEVICE_CTL_RESET, /* Reset device. */
-};
-
-enum pvrdma_intr_vector {
- PVRDMA_INTR_VECTOR_RESPONSE, /* Command response. */
- PVRDMA_INTR_VECTOR_ASYNC, /* Async events. */
- PVRDMA_INTR_VECTOR_CQ, /* CQ notification. */
- /* Additional CQ notification vectors. */
-};
-
-enum pvrdma_intr_cause {
- PVRDMA_INTR_CAUSE_RESPONSE = (1 << PVRDMA_INTR_VECTOR_RESPONSE),
- PVRDMA_INTR_CAUSE_ASYNC = (1 << PVRDMA_INTR_VECTOR_ASYNC),
- PVRDMA_INTR_CAUSE_CQ = (1 << PVRDMA_INTR_VECTOR_CQ),
-};
-
-enum pvrdma_gos_bits {
- PVRDMA_GOS_BITS_UNK, /* Unknown. */
- PVRDMA_GOS_BITS_32, /* 32-bit. */
- PVRDMA_GOS_BITS_64, /* 64-bit. */
-};
-
-enum pvrdma_gos_type {
- PVRDMA_GOS_TYPE_UNK, /* Unknown. */
- PVRDMA_GOS_TYPE_LINUX, /* Linux. */
-};
-
-enum pvrdma_device_mode {
- PVRDMA_DEVICE_MODE_ROCE, /* RoCE. */
- PVRDMA_DEVICE_MODE_IWARP, /* iWarp. */
- PVRDMA_DEVICE_MODE_IB, /* InfiniBand. */
-};
-
-struct pvrdma_gos_info {
- uint32_t gos_bits:2; /* W: PVRDMA_GOS_BITS_ */
- uint32_t gos_type:4; /* W: PVRDMA_GOS_TYPE_ */
- uint32_t gos_ver:16; /* W: Guest OS version. */
- uint32_t gos_misc:10; /* W: Other. */
- uint32_t pad; /* Pad to 8-byte alignment. */
-};
-
-struct pvrdma_device_caps {
- uint64_t fw_ver; /* R: Query device. */
- uint64_t node_guid;
- uint64_t sys_image_guid;
- uint64_t max_mr_size;
- uint64_t page_size_cap;
- uint64_t atomic_arg_sizes; /* EX verbs. */
- uint32_t ex_comp_mask; /* EX verbs. */
- uint32_t device_cap_flags2; /* EX verbs. */
- uint32_t max_fa_bit_boundary; /* EX verbs. */
- uint32_t log_max_atomic_inline_arg; /* EX verbs. */
- uint32_t vendor_id;
- uint32_t vendor_part_id;
- uint32_t hw_ver;
- uint32_t max_qp;
- uint32_t max_qp_wr;
- uint32_t device_cap_flags;
- uint32_t max_sge;
- uint32_t max_sge_rd;
- uint32_t max_cq;
- uint32_t max_cqe;
- uint32_t max_mr;
- uint32_t max_pd;
- uint32_t max_qp_rd_atom;
- uint32_t max_ee_rd_atom;
- uint32_t max_res_rd_atom;
- uint32_t max_qp_init_rd_atom;
- uint32_t max_ee_init_rd_atom;
- uint32_t max_ee;
- uint32_t max_rdd;
- uint32_t max_mw;
- uint32_t max_raw_ipv6_qp;
- uint32_t max_raw_ethy_qp;
- uint32_t max_mcast_grp;
- uint32_t max_mcast_qp_attach;
- uint32_t max_total_mcast_qp_attach;
- uint32_t max_ah;
- uint32_t max_fmr;
- uint32_t max_map_per_fmr;
- uint32_t max_srq;
- uint32_t max_srq_wr;
- uint32_t max_srq_sge;
- uint32_t max_uar;
- uint32_t gid_tbl_len;
- uint16_t max_pkeys;
- uint8_t local_ca_ack_delay;
- uint8_t phys_port_cnt;
- uint8_t mode; /* PVRDMA_DEVICE_MODE_ */
- uint8_t atomic_ops; /* PVRDMA_ATOMIC_OP_* bits */
- uint8_t bmme_flags; /* FRWR Mem Mgmt Extensions */
- uint8_t gid_types; /* PVRDMA_GID_TYPE_FLAG_ */
- uint32_t max_fast_reg_page_list_len;
-};
-
-struct pvrdma_ring_page_info {
- uint32_t num_pages; /* Num pages incl. header. */
- uint32_t reserved; /* Reserved. */
- uint64_t pdir_dma; /* Page directory PA. */
-};
-
-#pragma pack(push, 1)
-
-struct pvrdma_device_shared_region {
- uint32_t driver_version; /* W: Driver version. */
- uint32_t pad; /* Pad to 8-byte align. */
- struct pvrdma_gos_info gos_info; /* W: Guest OS information. */
- uint64_t cmd_slot_dma; /* W: Command slot address. */
- uint64_t resp_slot_dma; /* W: Response slot address. */
- struct pvrdma_ring_page_info async_ring_pages;
- /* W: Async ring page info. */
- struct pvrdma_ring_page_info cq_ring_pages;
- /* W: CQ ring page info. */
- union {
- uint32_t uar_pfn; /* W: UAR pageframe. */
- uint64_t uar_pfn64; /* W: 64-bit UAR page frame. */
- };
- struct pvrdma_device_caps caps; /* R: Device capabilities. */
-};
-
-#pragma pack(pop)
-
-/* Event types. Currently a 1:1 mapping with enum ib_event. */
-enum pvrdma_eqe_type {
- PVRDMA_EVENT_CQ_ERR,
- PVRDMA_EVENT_QP_FATAL,
- PVRDMA_EVENT_QP_REQ_ERR,
- PVRDMA_EVENT_QP_ACCESS_ERR,
- PVRDMA_EVENT_COMM_EST,
- PVRDMA_EVENT_SQ_DRAINED,
- PVRDMA_EVENT_PATH_MIG,
- PVRDMA_EVENT_PATH_MIG_ERR,
- PVRDMA_EVENT_DEVICE_FATAL,
- PVRDMA_EVENT_PORT_ACTIVE,
- PVRDMA_EVENT_PORT_ERR,
- PVRDMA_EVENT_LID_CHANGE,
- PVRDMA_EVENT_PKEY_CHANGE,
- PVRDMA_EVENT_SM_CHANGE,
- PVRDMA_EVENT_SRQ_ERR,
- PVRDMA_EVENT_SRQ_LIMIT_REACHED,
- PVRDMA_EVENT_QP_LAST_WQE_REACHED,
- PVRDMA_EVENT_CLIENT_REREGISTER,
- PVRDMA_EVENT_GID_CHANGE,
-};
-
-/* Event queue element. */
-struct pvrdma_eqe {
- uint32_t type; /* Event type. */
- uint32_t info; /* Handle, other. */
-};
-
-/* CQ notification queue element. */
-struct pvrdma_cqne {
- uint32_t info; /* Handle */
-};
-
-enum {
- PVRDMA_CMD_FIRST,
- PVRDMA_CMD_QUERY_PORT = PVRDMA_CMD_FIRST,
- PVRDMA_CMD_QUERY_PKEY,
- PVRDMA_CMD_CREATE_PD,
- PVRDMA_CMD_DESTROY_PD,
- PVRDMA_CMD_CREATE_MR,
- PVRDMA_CMD_DESTROY_MR,
- PVRDMA_CMD_CREATE_CQ,
- PVRDMA_CMD_RESIZE_CQ,
- PVRDMA_CMD_DESTROY_CQ,
- PVRDMA_CMD_CREATE_QP,
- PVRDMA_CMD_MODIFY_QP,
- PVRDMA_CMD_QUERY_QP,
- PVRDMA_CMD_DESTROY_QP,
- PVRDMA_CMD_CREATE_UC,
- PVRDMA_CMD_DESTROY_UC,
- PVRDMA_CMD_CREATE_BIND,
- PVRDMA_CMD_DESTROY_BIND,
- PVRDMA_CMD_CREATE_SRQ,
- PVRDMA_CMD_MODIFY_SRQ,
- PVRDMA_CMD_QUERY_SRQ,
- PVRDMA_CMD_DESTROY_SRQ,
- PVRDMA_CMD_MAX,
-};
-
-enum {
- PVRDMA_CMD_FIRST_RESP = (1 << 31),
- PVRDMA_CMD_QUERY_PORT_RESP = PVRDMA_CMD_FIRST_RESP,
- PVRDMA_CMD_QUERY_PKEY_RESP,
- PVRDMA_CMD_CREATE_PD_RESP,
- PVRDMA_CMD_DESTROY_PD_RESP_NOOP,
- PVRDMA_CMD_CREATE_MR_RESP,
- PVRDMA_CMD_DESTROY_MR_RESP_NOOP,
- PVRDMA_CMD_CREATE_CQ_RESP,
- PVRDMA_CMD_RESIZE_CQ_RESP,
- PVRDMA_CMD_DESTROY_CQ_RESP_NOOP,
- PVRDMA_CMD_CREATE_QP_RESP,
- PVRDMA_CMD_MODIFY_QP_RESP,
- PVRDMA_CMD_QUERY_QP_RESP,
- PVRDMA_CMD_DESTROY_QP_RESP,
- PVRDMA_CMD_CREATE_UC_RESP,
- PVRDMA_CMD_DESTROY_UC_RESP_NOOP,
- PVRDMA_CMD_CREATE_BIND_RESP_NOOP,
- PVRDMA_CMD_DESTROY_BIND_RESP_NOOP,
- PVRDMA_CMD_CREATE_SRQ_RESP,
- PVRDMA_CMD_MODIFY_SRQ_RESP,
- PVRDMA_CMD_QUERY_SRQ_RESP,
- PVRDMA_CMD_DESTROY_SRQ_RESP,
- PVRDMA_CMD_MAX_RESP,
-};
-
-struct pvrdma_cmd_hdr {
- uint64_t response; /* Key for response lookup. */
- uint32_t cmd; /* PVRDMA_CMD_ */
- uint32_t reserved; /* Reserved. */
-};
-
-struct pvrdma_cmd_resp_hdr {
- uint64_t response; /* From cmd hdr. */
- uint32_t ack; /* PVRDMA_CMD_XXX_RESP */
- uint8_t err; /* Error. */
- uint8_t reserved[3]; /* Reserved. */
-};
-
-struct pvrdma_cmd_query_port {
- struct pvrdma_cmd_hdr hdr;
- uint8_t port_num;
- uint8_t reserved[7];
-};
-
-struct pvrdma_cmd_query_port_resp {
- struct pvrdma_cmd_resp_hdr hdr;
- struct pvrdma_port_attr attrs;
-};
-
-struct pvrdma_cmd_query_pkey {
- struct pvrdma_cmd_hdr hdr;
- uint8_t port_num;
- uint8_t index;
- uint8_t reserved[6];
-};
-
-struct pvrdma_cmd_query_pkey_resp {
- struct pvrdma_cmd_resp_hdr hdr;
- uint16_t pkey;
- uint8_t reserved[6];
-};
-
-struct pvrdma_cmd_create_uc {
- struct pvrdma_cmd_hdr hdr;
- union {
- uint32_t pfn; /* UAR page frame number */
- uint64_t pfn64; /* 64-bit UAR page frame number */
- };
-};
-
-struct pvrdma_cmd_create_uc_resp {
- struct pvrdma_cmd_resp_hdr hdr;
- uint32_t ctx_handle;
- uint8_t reserved[4];
-};
-
-struct pvrdma_cmd_destroy_uc {
- struct pvrdma_cmd_hdr hdr;
- uint32_t ctx_handle;
- uint8_t reserved[4];
-};
-
-struct pvrdma_cmd_create_pd {
- struct pvrdma_cmd_hdr hdr;
- uint32_t ctx_handle;
- uint8_t reserved[4];
-};
-
-struct pvrdma_cmd_create_pd_resp {
- struct pvrdma_cmd_resp_hdr hdr;
- uint32_t pd_handle;
- uint8_t reserved[4];
-};
-
-struct pvrdma_cmd_destroy_pd {
- struct pvrdma_cmd_hdr hdr;
- uint32_t pd_handle;
- uint8_t reserved[4];
-};
-
-struct pvrdma_cmd_create_mr {
- struct pvrdma_cmd_hdr hdr;
- uint64_t start;
- uint64_t length;
- uint64_t pdir_dma;
- uint32_t pd_handle;
- uint32_t access_flags;
- uint32_t flags;
- uint32_t nchunks;
-};
-
-struct pvrdma_cmd_create_mr_resp {
- struct pvrdma_cmd_resp_hdr hdr;
- uint32_t mr_handle;
- uint32_t lkey;
- uint32_t rkey;
- uint8_t reserved[4];
-};
-
-struct pvrdma_cmd_destroy_mr {
- struct pvrdma_cmd_hdr hdr;
- uint32_t mr_handle;
- uint8_t reserved[4];
-};
-
-struct pvrdma_cmd_create_cq {
- struct pvrdma_cmd_hdr hdr;
- uint64_t pdir_dma;
- uint32_t ctx_handle;
- uint32_t cqe;
- uint32_t nchunks;
- uint8_t reserved[4];
-};
-
-struct pvrdma_cmd_create_cq_resp {
- struct pvrdma_cmd_resp_hdr hdr;
- uint32_t cq_handle;
- uint32_t cqe;
-};
-
-struct pvrdma_cmd_resize_cq {
- struct pvrdma_cmd_hdr hdr;
- uint32_t cq_handle;
- uint32_t cqe;
-};
-
-struct pvrdma_cmd_resize_cq_resp {
- struct pvrdma_cmd_resp_hdr hdr;
- uint32_t cqe;
- uint8_t reserved[4];
-};
-
-struct pvrdma_cmd_destroy_cq {
- struct pvrdma_cmd_hdr hdr;
- uint32_t cq_handle;
- uint8_t reserved[4];
-};
-
-struct pvrdma_cmd_create_srq {
- struct pvrdma_cmd_hdr hdr;
- uint64_t pdir_dma;
- uint32_t pd_handle;
- uint32_t nchunks;
- struct pvrdma_srq_attr attrs;
- uint8_t srq_type;
- uint8_t reserved[7];
-};
-
-struct pvrdma_cmd_create_srq_resp {
- struct pvrdma_cmd_resp_hdr hdr;
- uint32_t srqn;
- uint8_t reserved[4];
-};
-
-struct pvrdma_cmd_modify_srq {
- struct pvrdma_cmd_hdr hdr;
- uint32_t srq_handle;
- uint32_t attr_mask;
- struct pvrdma_srq_attr attrs;
-};
-
-struct pvrdma_cmd_query_srq {
- struct pvrdma_cmd_hdr hdr;
- uint32_t srq_handle;
- uint8_t reserved[4];
-};
-
-struct pvrdma_cmd_query_srq_resp {
- struct pvrdma_cmd_resp_hdr hdr;
- struct pvrdma_srq_attr attrs;
-};
-
-struct pvrdma_cmd_destroy_srq {
- struct pvrdma_cmd_hdr hdr;
- uint32_t srq_handle;
- uint8_t reserved[4];
-};
-
-struct pvrdma_cmd_create_qp {
- struct pvrdma_cmd_hdr hdr;
- uint64_t pdir_dma;
- uint32_t pd_handle;
- uint32_t send_cq_handle;
- uint32_t recv_cq_handle;
- uint32_t srq_handle;
- uint32_t max_send_wr;
- uint32_t max_recv_wr;
- uint32_t max_send_sge;
- uint32_t max_recv_sge;
- uint32_t max_inline_data;
- uint32_t lkey;
- uint32_t access_flags;
- uint16_t total_chunks;
- uint16_t send_chunks;
- uint16_t max_atomic_arg;
- uint8_t sq_sig_all;
- uint8_t qp_type;
- uint8_t is_srq;
- uint8_t reserved[3];
-};
-
-struct pvrdma_cmd_create_qp_resp {
- struct pvrdma_cmd_resp_hdr hdr;
- uint32_t qpn;
- uint32_t max_send_wr;
- uint32_t max_recv_wr;
- uint32_t max_send_sge;
- uint32_t max_recv_sge;
- uint32_t max_inline_data;
-};
-
-struct pvrdma_cmd_create_qp_resp_v2 {
- struct pvrdma_cmd_resp_hdr hdr;
- uint32_t qpn;
- uint32_t qp_handle;
- uint32_t max_send_wr;
- uint32_t max_recv_wr;
- uint32_t max_send_sge;
- uint32_t max_recv_sge;
- uint32_t max_inline_data;
-};
-
-struct pvrdma_cmd_modify_qp {
- struct pvrdma_cmd_hdr hdr;
- uint32_t qp_handle;
- uint32_t attr_mask;
- struct pvrdma_qp_attr attrs;
-};
-
-struct pvrdma_cmd_query_qp {
- struct pvrdma_cmd_hdr hdr;
- uint32_t qp_handle;
- uint32_t attr_mask;
-};
-
-struct pvrdma_cmd_query_qp_resp {
- struct pvrdma_cmd_resp_hdr hdr;
- struct pvrdma_qp_attr attrs;
-};
-
-struct pvrdma_cmd_destroy_qp {
- struct pvrdma_cmd_hdr hdr;
- uint32_t qp_handle;
- uint8_t reserved[4];
-};
-
-struct pvrdma_cmd_destroy_qp_resp {
- struct pvrdma_cmd_resp_hdr hdr;
- uint32_t events_reported;
- uint8_t reserved[4];
-};
-
-struct pvrdma_cmd_create_bind {
- struct pvrdma_cmd_hdr hdr;
- uint32_t mtu;
- uint32_t vlan;
- uint32_t index;
- uint8_t new_gid[16];
- uint8_t gid_type;
- uint8_t reserved[3];
-};
-
-struct pvrdma_cmd_destroy_bind {
- struct pvrdma_cmd_hdr hdr;
- uint32_t index;
- uint8_t dest_gid[16];
- uint8_t reserved[4];
-};
-
-union pvrdma_cmd_req {
- struct pvrdma_cmd_hdr hdr;
- struct pvrdma_cmd_query_port query_port;
- struct pvrdma_cmd_query_pkey query_pkey;
- struct pvrdma_cmd_create_uc create_uc;
- struct pvrdma_cmd_destroy_uc destroy_uc;
- struct pvrdma_cmd_create_pd create_pd;
- struct pvrdma_cmd_destroy_pd destroy_pd;
- struct pvrdma_cmd_create_mr create_mr;
- struct pvrdma_cmd_destroy_mr destroy_mr;
- struct pvrdma_cmd_create_cq create_cq;
- struct pvrdma_cmd_resize_cq resize_cq;
- struct pvrdma_cmd_destroy_cq destroy_cq;
- struct pvrdma_cmd_create_qp create_qp;
- struct pvrdma_cmd_modify_qp modify_qp;
- struct pvrdma_cmd_query_qp query_qp;
- struct pvrdma_cmd_destroy_qp destroy_qp;
- struct pvrdma_cmd_create_bind create_bind;
- struct pvrdma_cmd_destroy_bind destroy_bind;
- struct pvrdma_cmd_create_srq create_srq;
- struct pvrdma_cmd_modify_srq modify_srq;
- struct pvrdma_cmd_query_srq query_srq;
- struct pvrdma_cmd_destroy_srq destroy_srq;
-};
-
-union pvrdma_cmd_resp {
- struct pvrdma_cmd_resp_hdr hdr;
- struct pvrdma_cmd_query_port_resp query_port_resp;
- struct pvrdma_cmd_query_pkey_resp query_pkey_resp;
- struct pvrdma_cmd_create_uc_resp create_uc_resp;
- struct pvrdma_cmd_create_pd_resp create_pd_resp;
- struct pvrdma_cmd_create_mr_resp create_mr_resp;
- struct pvrdma_cmd_create_cq_resp create_cq_resp;
- struct pvrdma_cmd_resize_cq_resp resize_cq_resp;
- struct pvrdma_cmd_create_qp_resp create_qp_resp;
- struct pvrdma_cmd_create_qp_resp_v2 create_qp_resp_v2;
- struct pvrdma_cmd_query_qp_resp query_qp_resp;
- struct pvrdma_cmd_destroy_qp_resp destroy_qp_resp;
- struct pvrdma_cmd_create_srq_resp create_srq_resp;
- struct pvrdma_cmd_query_srq_resp query_srq_resp;
-};
-
-#endif /* __PVRDMA_DEV_API_H__ */
+++ /dev/null
-/*
- * Copyright (c) 2012-2016 VMware, Inc. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of EITHER the GNU General Public License
- * version 2 as published by the Free Software Foundation or the BSD
- * 2-Clause License. This program is distributed in the hope that it
- * will be useful, but WITHOUT ANY WARRANTY; WITHOUT EVEN THE IMPLIED
- * WARRANTY OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE.
- * See the GNU General Public License version 2 for more details at
- * http://www.gnu.org/licenses/old-licenses/gpl-2.0.en.html.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program available in the file COPYING in the main
- * directory of this source tree.
- *
- * The BSD 2-Clause License
- *
- * Redistribution and use in source and binary forms, with or
- * without modification, are permitted provided that the following
- * conditions are met:
- *
- * - Redistributions of source code must retain the above
- * copyright notice, this list of conditions and the following
- * disclaimer.
- *
- * - Redistributions in binary form must reproduce the above
- * copyright notice, this list of conditions and the following
- * disclaimer in the documentation and/or other materials
- * provided with the distribution.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
- * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
- * COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
- * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
- * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
- * OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-
-#ifndef __PVRDMA_RING_H__
-#define __PVRDMA_RING_H__
-
-#include "standard-headers/linux/types.h"
-
-#define PVRDMA_INVALID_IDX -1 /* Invalid index. */
-
-struct pvrdma_ring {
- int prod_tail; /* Producer tail. */
- int cons_head; /* Consumer head. */
-};
-
-struct pvrdma_ring_state {
- struct pvrdma_ring tx; /* Tx ring. */
- struct pvrdma_ring rx; /* Rx ring. */
-};
-
-static inline int pvrdma_idx_valid(uint32_t idx, uint32_t max_elems)
-{
- /* Generates fewer instructions than a less-than. */
- return (idx & ~((max_elems << 1) - 1)) == 0;
-}
-
-static inline int32_t pvrdma_idx(int *var, uint32_t max_elems)
-{
- const unsigned int idx = qatomic_read(var);
-
- if (pvrdma_idx_valid(idx, max_elems))
- return idx & (max_elems - 1);
- return PVRDMA_INVALID_IDX;
-}
-
-static inline void pvrdma_idx_ring_inc(int *var, uint32_t max_elems)
-{
- uint32_t idx = qatomic_read(var) + 1; /* Increment. */
-
- idx &= (max_elems << 1) - 1; /* Modulo size, flip gen. */
- qatomic_set(var, idx);
-}
-
-static inline int32_t pvrdma_idx_ring_has_space(const struct pvrdma_ring *r,
- uint32_t max_elems, uint32_t *out_tail)
-{
- const uint32_t tail = qatomic_read(&r->prod_tail);
- const uint32_t head = qatomic_read(&r->cons_head);
-
- if (pvrdma_idx_valid(tail, max_elems) &&
- pvrdma_idx_valid(head, max_elems)) {
- *out_tail = tail & (max_elems - 1);
- return tail != (head ^ max_elems);
- }
- return PVRDMA_INVALID_IDX;
-}
-
-static inline int32_t pvrdma_idx_ring_has_data(const struct pvrdma_ring *r,
- uint32_t max_elems, uint32_t *out_head)
-{
- const uint32_t tail = qatomic_read(&r->prod_tail);
- const uint32_t head = qatomic_read(&r->cons_head);
-
- if (pvrdma_idx_valid(tail, max_elems) &&
- pvrdma_idx_valid(head, max_elems)) {
- *out_head = head & (max_elems - 1);
- return tail != head;
- }
- return PVRDMA_INVALID_IDX;
-}
-
-#endif /* __PVRDMA_RING_H__ */
+++ /dev/null
-/*
- * Copyright (c) 2012-2016 VMware, Inc. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of EITHER the GNU General Public License
- * version 2 as published by the Free Software Foundation or the BSD
- * 2-Clause License. This program is distributed in the hope that it
- * will be useful, but WITHOUT ANY WARRANTY; WITHOUT EVEN THE IMPLIED
- * WARRANTY OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE.
- * See the GNU General Public License version 2 for more details at
- * http://www.gnu.org/licenses/old-licenses/gpl-2.0.en.html.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program available in the file COPYING in the main
- * directory of this source tree.
- *
- * The BSD 2-Clause License
- *
- * Redistribution and use in source and binary forms, with or
- * without modification, are permitted provided that the following
- * conditions are met:
- *
- * - Redistributions of source code must retain the above
- * copyright notice, this list of conditions and the following
- * disclaimer.
- *
- * - Redistributions in binary form must reproduce the above
- * copyright notice, this list of conditions and the following
- * disclaimer in the documentation and/or other materials
- * provided with the distribution.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
- * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
- * COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
- * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
- * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
- * OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-
-#ifndef __PVRDMA_VERBS_H__
-#define __PVRDMA_VERBS_H__
-
-#include "standard-headers/linux/types.h"
-
-union pvrdma_gid {
- uint8_t raw[16];
- struct {
- uint64_t subnet_prefix;
- uint64_t interface_id;
- } global;
-};
-
-enum pvrdma_link_layer {
- PVRDMA_LINK_LAYER_UNSPECIFIED,
- PVRDMA_LINK_LAYER_INFINIBAND,
- PVRDMA_LINK_LAYER_ETHERNET,
-};
-
-enum pvrdma_mtu {
- PVRDMA_MTU_256 = 1,
- PVRDMA_MTU_512 = 2,
- PVRDMA_MTU_1024 = 3,
- PVRDMA_MTU_2048 = 4,
- PVRDMA_MTU_4096 = 5,
-};
-
-static inline int pvrdma_mtu_enum_to_int(enum pvrdma_mtu mtu)
-{
- switch (mtu) {
- case PVRDMA_MTU_256: return 256;
- case PVRDMA_MTU_512: return 512;
- case PVRDMA_MTU_1024: return 1024;
- case PVRDMA_MTU_2048: return 2048;
- case PVRDMA_MTU_4096: return 4096;
- default: return -1;
- }
-}
-
-static inline enum pvrdma_mtu pvrdma_mtu_int_to_enum(int mtu)
-{
- switch (mtu) {
- case 256: return PVRDMA_MTU_256;
- case 512: return PVRDMA_MTU_512;
- case 1024: return PVRDMA_MTU_1024;
- case 2048: return PVRDMA_MTU_2048;
- case 4096:
- default: return PVRDMA_MTU_4096;
- }
-}
-
-enum pvrdma_port_state {
- PVRDMA_PORT_NOP = 0,
- PVRDMA_PORT_DOWN = 1,
- PVRDMA_PORT_INIT = 2,
- PVRDMA_PORT_ARMED = 3,
- PVRDMA_PORT_ACTIVE = 4,
- PVRDMA_PORT_ACTIVE_DEFER = 5,
-};
-
-enum pvrdma_port_cap_flags {
- PVRDMA_PORT_SM = 1 << 1,
- PVRDMA_PORT_NOTICE_SUP = 1 << 2,
- PVRDMA_PORT_TRAP_SUP = 1 << 3,
- PVRDMA_PORT_OPT_IPD_SUP = 1 << 4,
- PVRDMA_PORT_AUTO_MIGR_SUP = 1 << 5,
- PVRDMA_PORT_SL_MAP_SUP = 1 << 6,
- PVRDMA_PORT_MKEY_NVRAM = 1 << 7,
- PVRDMA_PORT_PKEY_NVRAM = 1 << 8,
- PVRDMA_PORT_LED_INFO_SUP = 1 << 9,
- PVRDMA_PORT_SM_DISABLED = 1 << 10,
- PVRDMA_PORT_SYS_IMAGE_GUID_SUP = 1 << 11,
- PVRDMA_PORT_PKEY_SW_EXT_PORT_TRAP_SUP = 1 << 12,
- PVRDMA_PORT_EXTENDED_SPEEDS_SUP = 1 << 14,
- PVRDMA_PORT_CM_SUP = 1 << 16,
- PVRDMA_PORT_SNMP_TUNNEL_SUP = 1 << 17,
- PVRDMA_PORT_REINIT_SUP = 1 << 18,
- PVRDMA_PORT_DEVICE_MGMT_SUP = 1 << 19,
- PVRDMA_PORT_VENDOR_CLASS_SUP = 1 << 20,
- PVRDMA_PORT_DR_NOTICE_SUP = 1 << 21,
- PVRDMA_PORT_CAP_MASK_NOTICE_SUP = 1 << 22,
- PVRDMA_PORT_BOOT_MGMT_SUP = 1 << 23,
- PVRDMA_PORT_LINK_LATENCY_SUP = 1 << 24,
- PVRDMA_PORT_CLIENT_REG_SUP = 1 << 25,
- PVRDMA_PORT_IP_BASED_GIDS = 1 << 26,
- PVRDMA_PORT_CAP_FLAGS_MAX = PVRDMA_PORT_IP_BASED_GIDS,
-};
-
-enum pvrdma_port_width {
- PVRDMA_WIDTH_1X = 1,
- PVRDMA_WIDTH_4X = 2,
- PVRDMA_WIDTH_8X = 4,
- PVRDMA_WIDTH_12X = 8,
-};
-
-static inline int pvrdma_width_enum_to_int(enum pvrdma_port_width width)
-{
- switch (width) {
- case PVRDMA_WIDTH_1X: return 1;
- case PVRDMA_WIDTH_4X: return 4;
- case PVRDMA_WIDTH_8X: return 8;
- case PVRDMA_WIDTH_12X: return 12;
- default: return -1;
- }
-}
-
-enum pvrdma_port_speed {
- PVRDMA_SPEED_SDR = 1,
- PVRDMA_SPEED_DDR = 2,
- PVRDMA_SPEED_QDR = 4,
- PVRDMA_SPEED_FDR10 = 8,
- PVRDMA_SPEED_FDR = 16,
- PVRDMA_SPEED_EDR = 32,
-};
-
-struct pvrdma_port_attr {
- enum pvrdma_port_state state;
- enum pvrdma_mtu max_mtu;
- enum pvrdma_mtu active_mtu;
- uint32_t gid_tbl_len;
- uint32_t port_cap_flags;
- uint32_t max_msg_sz;
- uint32_t bad_pkey_cntr;
- uint32_t qkey_viol_cntr;
- uint16_t pkey_tbl_len;
- uint16_t lid;
- uint16_t sm_lid;
- uint8_t lmc;
- uint8_t max_vl_num;
- uint8_t sm_sl;
- uint8_t subnet_timeout;
- uint8_t init_type_reply;
- uint8_t active_width;
- uint8_t active_speed;
- uint8_t phys_state;
- uint8_t reserved[2];
-};
-
-struct pvrdma_global_route {
- union pvrdma_gid dgid;
- uint32_t flow_label;
- uint8_t sgid_index;
- uint8_t hop_limit;
- uint8_t traffic_class;
- uint8_t reserved;
-};
-
-struct pvrdma_grh {
- uint32_t version_tclass_flow;
- uint16_t paylen;
- uint8_t next_hdr;
- uint8_t hop_limit;
- union pvrdma_gid sgid;
- union pvrdma_gid dgid;
-};
-
-enum pvrdma_ah_flags {
- PVRDMA_AH_GRH = 1,
-};
-
-enum pvrdma_rate {
- PVRDMA_RATE_PORT_CURRENT = 0,
- PVRDMA_RATE_2_5_GBPS = 2,
- PVRDMA_RATE_5_GBPS = 5,
- PVRDMA_RATE_10_GBPS = 3,
- PVRDMA_RATE_20_GBPS = 6,
- PVRDMA_RATE_30_GBPS = 4,
- PVRDMA_RATE_40_GBPS = 7,
- PVRDMA_RATE_60_GBPS = 8,
- PVRDMA_RATE_80_GBPS = 9,
- PVRDMA_RATE_120_GBPS = 10,
- PVRDMA_RATE_14_GBPS = 11,
- PVRDMA_RATE_56_GBPS = 12,
- PVRDMA_RATE_112_GBPS = 13,
- PVRDMA_RATE_168_GBPS = 14,
- PVRDMA_RATE_25_GBPS = 15,
- PVRDMA_RATE_100_GBPS = 16,
- PVRDMA_RATE_200_GBPS = 17,
- PVRDMA_RATE_300_GBPS = 18,
-};
-
-struct pvrdma_ah_attr {
- struct pvrdma_global_route grh;
- uint16_t dlid;
- uint16_t vlan_id;
- uint8_t sl;
- uint8_t src_path_bits;
- uint8_t static_rate;
- uint8_t ah_flags;
- uint8_t port_num;
- uint8_t dmac[6];
- uint8_t reserved;
-};
-
-enum pvrdma_cq_notify_flags {
- PVRDMA_CQ_SOLICITED = 1 << 0,
- PVRDMA_CQ_NEXT_COMP = 1 << 1,
- PVRDMA_CQ_SOLICITED_MASK = PVRDMA_CQ_SOLICITED |
- PVRDMA_CQ_NEXT_COMP,
- PVRDMA_CQ_REPORT_MISSED_EVENTS = 1 << 2,
-};
-
-struct pvrdma_qp_cap {
- uint32_t max_send_wr;
- uint32_t max_recv_wr;
- uint32_t max_send_sge;
- uint32_t max_recv_sge;
- uint32_t max_inline_data;
- uint32_t reserved;
-};
-
-enum pvrdma_sig_type {
- PVRDMA_SIGNAL_ALL_WR,
- PVRDMA_SIGNAL_REQ_WR,
-};
-
-enum pvrdma_qp_type {
- PVRDMA_QPT_SMI,
- PVRDMA_QPT_GSI,
- PVRDMA_QPT_RC,
- PVRDMA_QPT_UC,
- PVRDMA_QPT_UD,
- PVRDMA_QPT_RAW_IPV6,
- PVRDMA_QPT_RAW_ETHERTYPE,
- PVRDMA_QPT_RAW_PACKET = 8,
- PVRDMA_QPT_XRC_INI = 9,
- PVRDMA_QPT_XRC_TGT,
- PVRDMA_QPT_MAX,
-};
-
-enum pvrdma_qp_create_flags {
- PVRDMA_QP_CREATE_IPOPVRDMA_UD_LSO = 1 << 0,
- PVRDMA_QP_CREATE_BLOCK_MULTICAST_LOOPBACK = 1 << 1,
-};
-
-enum pvrdma_qp_attr_mask {
- PVRDMA_QP_STATE = 1 << 0,
- PVRDMA_QP_CUR_STATE = 1 << 1,
- PVRDMA_QP_EN_SQD_ASYNC_NOTIFY = 1 << 2,
- PVRDMA_QP_ACCESS_FLAGS = 1 << 3,
- PVRDMA_QP_PKEY_INDEX = 1 << 4,
- PVRDMA_QP_PORT = 1 << 5,
- PVRDMA_QP_QKEY = 1 << 6,
- PVRDMA_QP_AV = 1 << 7,
- PVRDMA_QP_PATH_MTU = 1 << 8,
- PVRDMA_QP_TIMEOUT = 1 << 9,
- PVRDMA_QP_RETRY_CNT = 1 << 10,
- PVRDMA_QP_RNR_RETRY = 1 << 11,
- PVRDMA_QP_RQ_PSN = 1 << 12,
- PVRDMA_QP_MAX_QP_RD_ATOMIC = 1 << 13,
- PVRDMA_QP_ALT_PATH = 1 << 14,
- PVRDMA_QP_MIN_RNR_TIMER = 1 << 15,
- PVRDMA_QP_SQ_PSN = 1 << 16,
- PVRDMA_QP_MAX_DEST_RD_ATOMIC = 1 << 17,
- PVRDMA_QP_PATH_MIG_STATE = 1 << 18,
- PVRDMA_QP_CAP = 1 << 19,
- PVRDMA_QP_DEST_QPN = 1 << 20,
- PVRDMA_QP_ATTR_MASK_MAX = PVRDMA_QP_DEST_QPN,
-};
-
-enum pvrdma_qp_state {
- PVRDMA_QPS_RESET,
- PVRDMA_QPS_INIT,
- PVRDMA_QPS_RTR,
- PVRDMA_QPS_RTS,
- PVRDMA_QPS_SQD,
- PVRDMA_QPS_SQE,
- PVRDMA_QPS_ERR,
-};
-
-enum pvrdma_mig_state {
- PVRDMA_MIG_MIGRATED,
- PVRDMA_MIG_REARM,
- PVRDMA_MIG_ARMED,
-};
-
-enum pvrdma_mw_type {
- PVRDMA_MW_TYPE_1 = 1,
- PVRDMA_MW_TYPE_2 = 2,
-};
-
-struct pvrdma_srq_attr {
- uint32_t max_wr;
- uint32_t max_sge;
- uint32_t srq_limit;
- uint32_t reserved;
-};
-
-struct pvrdma_qp_attr {
- enum pvrdma_qp_state qp_state;
- enum pvrdma_qp_state cur_qp_state;
- enum pvrdma_mtu path_mtu;
- enum pvrdma_mig_state path_mig_state;
- uint32_t qkey;
- uint32_t rq_psn;
- uint32_t sq_psn;
- uint32_t dest_qp_num;
- uint32_t qp_access_flags;
- uint16_t pkey_index;
- uint16_t alt_pkey_index;
- uint8_t en_sqd_async_notify;
- uint8_t sq_draining;
- uint8_t max_rd_atomic;
- uint8_t max_dest_rd_atomic;
- uint8_t min_rnr_timer;
- uint8_t port_num;
- uint8_t timeout;
- uint8_t retry_cnt;
- uint8_t rnr_retry;
- uint8_t alt_port_num;
- uint8_t alt_timeout;
- uint8_t reserved[5];
- struct pvrdma_qp_cap cap;
- struct pvrdma_ah_attr ah_attr;
- struct pvrdma_ah_attr alt_ah_attr;
-};
-
-enum pvrdma_send_flags {
- PVRDMA_SEND_FENCE = 1 << 0,
- PVRDMA_SEND_SIGNALED = 1 << 1,
- PVRDMA_SEND_SOLICITED = 1 << 2,
- PVRDMA_SEND_INLINE = 1 << 3,
- PVRDMA_SEND_IP_CSUM = 1 << 4,
- PVRDMA_SEND_FLAGS_MAX = PVRDMA_SEND_IP_CSUM,
-};
-
-enum pvrdma_access_flags {
- PVRDMA_ACCESS_LOCAL_WRITE = 1 << 0,
- PVRDMA_ACCESS_REMOTE_WRITE = 1 << 1,
- PVRDMA_ACCESS_REMOTE_READ = 1 << 2,
- PVRDMA_ACCESS_REMOTE_ATOMIC = 1 << 3,
- PVRDMA_ACCESS_MW_BIND = 1 << 4,
- PVRDMA_ZERO_BASED = 1 << 5,
- PVRDMA_ACCESS_ON_DEMAND = 1 << 6,
- PVRDMA_ACCESS_FLAGS_MAX = PVRDMA_ACCESS_ON_DEMAND,
-};
-
-#endif /* __PVRDMA_VERBS_H__ */
+++ /dev/null
-/*
- * Copyright 2011 Intel Corporation
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice (including the next
- * paragraph) shall be included in all copies or substantial portions of the
- * Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- */
-
-#ifndef DRM_FOURCC_H
-#define DRM_FOURCC_H
-
-
-#if defined(__cplusplus)
-extern "C" {
-#endif
-
-/**
- * DOC: overview
- *
- * In the DRM subsystem, framebuffer pixel formats are described using the
- * fourcc codes defined in `include/uapi/drm/drm_fourcc.h`. In addition to the
- * fourcc code, a Format Modifier may optionally be provided, in order to
- * further describe the buffer's format - for example tiling or compression.
- *
- * Format Modifiers
- * ----------------
- *
- * Format modifiers are used in conjunction with a fourcc code, forming a
- * unique fourcc:modifier pair. This format:modifier pair must fully define the
- * format and data layout of the buffer, and should be the only way to describe
- * that particular buffer.
- *
- * Having multiple fourcc:modifier pairs which describe the same layout should
- * be avoided, as such aliases run the risk of different drivers exposing
- * different names for the same data format, forcing userspace to understand
- * that they are aliases.
- *
- * Format modifiers may change any property of the buffer, including the number
- * of planes and/or the required allocation size. Format modifiers are
- * vendor-namespaced, and as such the relationship between a fourcc code and a
- * modifier is specific to the modifer being used. For example, some modifiers
- * may preserve meaning - such as number of planes - from the fourcc code,
- * whereas others may not.
- *
- * Modifiers must uniquely encode buffer layout. In other words, a buffer must
- * match only a single modifier. A modifier must not be a subset of layouts of
- * another modifier. For instance, it's incorrect to encode pitch alignment in
- * a modifier: a buffer may match a 64-pixel aligned modifier and a 32-pixel
- * aligned modifier. That said, modifiers can have implicit minimal
- * requirements.
- *
- * For modifiers where the combination of fourcc code and modifier can alias,
- * a canonical pair needs to be defined and used by all drivers. Preferred
- * combinations are also encouraged where all combinations might lead to
- * confusion and unnecessarily reduced interoperability. An example for the
- * latter is AFBC, where the ABGR layouts are preferred over ARGB layouts.
- *
- * There are two kinds of modifier users:
- *
- * - Kernel and user-space drivers: for drivers it's important that modifiers
- * don't alias, otherwise two drivers might support the same format but use
- * different aliases, preventing them from sharing buffers in an efficient
- * format.
- * - Higher-level programs interfacing with KMS/GBM/EGL/Vulkan/etc: these users
- * see modifiers as opaque tokens they can check for equality and intersect.
- * These users musn't need to know to reason about the modifier value
- * (i.e. they are not expected to extract information out of the modifier).
- *
- * Vendors should document their modifier usage in as much detail as
- * possible, to ensure maximum compatibility across devices, drivers and
- * applications.
- *
- * The authoritative list of format modifier codes is found in
- * `include/uapi/drm/drm_fourcc.h`
- */
-
-#define fourcc_code(a, b, c, d) ((uint32_t)(a) | ((uint32_t)(b) << 8) | \
- ((uint32_t)(c) << 16) | ((uint32_t)(d) << 24))
-
-#define DRM_FORMAT_BIG_ENDIAN (1U<<31) /* format is big endian instead of little endian */
-
-/* Reserve 0 for the invalid format specifier */
-#define DRM_FORMAT_INVALID 0
-
-/* color index */
-#define DRM_FORMAT_C8 fourcc_code('C', '8', ' ', ' ') /* [7:0] C */
-
-/* 8 bpp Red */
-#define DRM_FORMAT_R8 fourcc_code('R', '8', ' ', ' ') /* [7:0] R */
-
-/* 16 bpp Red */
-#define DRM_FORMAT_R16 fourcc_code('R', '1', '6', ' ') /* [15:0] R little endian */
-
-/* 16 bpp RG */
-#define DRM_FORMAT_RG88 fourcc_code('R', 'G', '8', '8') /* [15:0] R:G 8:8 little endian */
-#define DRM_FORMAT_GR88 fourcc_code('G', 'R', '8', '8') /* [15:0] G:R 8:8 little endian */
-
-/* 32 bpp RG */
-#define DRM_FORMAT_RG1616 fourcc_code('R', 'G', '3', '2') /* [31:0] R:G 16:16 little endian */
-#define DRM_FORMAT_GR1616 fourcc_code('G', 'R', '3', '2') /* [31:0] G:R 16:16 little endian */
-
-/* 8 bpp RGB */
-#define DRM_FORMAT_RGB332 fourcc_code('R', 'G', 'B', '8') /* [7:0] R:G:B 3:3:2 */
-#define DRM_FORMAT_BGR233 fourcc_code('B', 'G', 'R', '8') /* [7:0] B:G:R 2:3:3 */
-
-/* 16 bpp RGB */
-#define DRM_FORMAT_XRGB4444 fourcc_code('X', 'R', '1', '2') /* [15:0] x:R:G:B 4:4:4:4 little endian */
-#define DRM_FORMAT_XBGR4444 fourcc_code('X', 'B', '1', '2') /* [15:0] x:B:G:R 4:4:4:4 little endian */
-#define DRM_FORMAT_RGBX4444 fourcc_code('R', 'X', '1', '2') /* [15:0] R:G:B:x 4:4:4:4 little endian */
-#define DRM_FORMAT_BGRX4444 fourcc_code('B', 'X', '1', '2') /* [15:0] B:G:R:x 4:4:4:4 little endian */
-
-#define DRM_FORMAT_ARGB4444 fourcc_code('A', 'R', '1', '2') /* [15:0] A:R:G:B 4:4:4:4 little endian */
-#define DRM_FORMAT_ABGR4444 fourcc_code('A', 'B', '1', '2') /* [15:0] A:B:G:R 4:4:4:4 little endian */
-#define DRM_FORMAT_RGBA4444 fourcc_code('R', 'A', '1', '2') /* [15:0] R:G:B:A 4:4:4:4 little endian */
-#define DRM_FORMAT_BGRA4444 fourcc_code('B', 'A', '1', '2') /* [15:0] B:G:R:A 4:4:4:4 little endian */
-
-#define DRM_FORMAT_XRGB1555 fourcc_code('X', 'R', '1', '5') /* [15:0] x:R:G:B 1:5:5:5 little endian */
-#define DRM_FORMAT_XBGR1555 fourcc_code('X', 'B', '1', '5') /* [15:0] x:B:G:R 1:5:5:5 little endian */
-#define DRM_FORMAT_RGBX5551 fourcc_code('R', 'X', '1', '5') /* [15:0] R:G:B:x 5:5:5:1 little endian */
-#define DRM_FORMAT_BGRX5551 fourcc_code('B', 'X', '1', '5') /* [15:0] B:G:R:x 5:5:5:1 little endian */
-
-#define DRM_FORMAT_ARGB1555 fourcc_code('A', 'R', '1', '5') /* [15:0] A:R:G:B 1:5:5:5 little endian */
-#define DRM_FORMAT_ABGR1555 fourcc_code('A', 'B', '1', '5') /* [15:0] A:B:G:R 1:5:5:5 little endian */
-#define DRM_FORMAT_RGBA5551 fourcc_code('R', 'A', '1', '5') /* [15:0] R:G:B:A 5:5:5:1 little endian */
-#define DRM_FORMAT_BGRA5551 fourcc_code('B', 'A', '1', '5') /* [15:0] B:G:R:A 5:5:5:1 little endian */
-
-#define DRM_FORMAT_RGB565 fourcc_code('R', 'G', '1', '6') /* [15:0] R:G:B 5:6:5 little endian */
-#define DRM_FORMAT_BGR565 fourcc_code('B', 'G', '1', '6') /* [15:0] B:G:R 5:6:5 little endian */
-
-/* 24 bpp RGB */
-#define DRM_FORMAT_RGB888 fourcc_code('R', 'G', '2', '4') /* [23:0] R:G:B little endian */
-#define DRM_FORMAT_BGR888 fourcc_code('B', 'G', '2', '4') /* [23:0] B:G:R little endian */
-
-/* 32 bpp RGB */
-#define DRM_FORMAT_XRGB8888 fourcc_code('X', 'R', '2', '4') /* [31:0] x:R:G:B 8:8:8:8 little endian */
-#define DRM_FORMAT_XBGR8888 fourcc_code('X', 'B', '2', '4') /* [31:0] x:B:G:R 8:8:8:8 little endian */
-#define DRM_FORMAT_RGBX8888 fourcc_code('R', 'X', '2', '4') /* [31:0] R:G:B:x 8:8:8:8 little endian */
-#define DRM_FORMAT_BGRX8888 fourcc_code('B', 'X', '2', '4') /* [31:0] B:G:R:x 8:8:8:8 little endian */
-
-#define DRM_FORMAT_ARGB8888 fourcc_code('A', 'R', '2', '4') /* [31:0] A:R:G:B 8:8:8:8 little endian */
-#define DRM_FORMAT_ABGR8888 fourcc_code('A', 'B', '2', '4') /* [31:0] A:B:G:R 8:8:8:8 little endian */
-#define DRM_FORMAT_RGBA8888 fourcc_code('R', 'A', '2', '4') /* [31:0] R:G:B:A 8:8:8:8 little endian */
-#define DRM_FORMAT_BGRA8888 fourcc_code('B', 'A', '2', '4') /* [31:0] B:G:R:A 8:8:8:8 little endian */
-
-#define DRM_FORMAT_XRGB2101010 fourcc_code('X', 'R', '3', '0') /* [31:0] x:R:G:B 2:10:10:10 little endian */
-#define DRM_FORMAT_XBGR2101010 fourcc_code('X', 'B', '3', '0') /* [31:0] x:B:G:R 2:10:10:10 little endian */
-#define DRM_FORMAT_RGBX1010102 fourcc_code('R', 'X', '3', '0') /* [31:0] R:G:B:x 10:10:10:2 little endian */
-#define DRM_FORMAT_BGRX1010102 fourcc_code('B', 'X', '3', '0') /* [31:0] B:G:R:x 10:10:10:2 little endian */
-
-#define DRM_FORMAT_ARGB2101010 fourcc_code('A', 'R', '3', '0') /* [31:0] A:R:G:B 2:10:10:10 little endian */
-#define DRM_FORMAT_ABGR2101010 fourcc_code('A', 'B', '3', '0') /* [31:0] A:B:G:R 2:10:10:10 little endian */
-#define DRM_FORMAT_RGBA1010102 fourcc_code('R', 'A', '3', '0') /* [31:0] R:G:B:A 10:10:10:2 little endian */
-#define DRM_FORMAT_BGRA1010102 fourcc_code('B', 'A', '3', '0') /* [31:0] B:G:R:A 10:10:10:2 little endian */
-
-/*
- * Floating point 64bpp RGB
- * IEEE 754-2008 binary16 half-precision float
- * [15:0] sign:exponent:mantissa 1:5:10
- */
-#define DRM_FORMAT_XRGB16161616F fourcc_code('X', 'R', '4', 'H') /* [63:0] x:R:G:B 16:16:16:16 little endian */
-#define DRM_FORMAT_XBGR16161616F fourcc_code('X', 'B', '4', 'H') /* [63:0] x:B:G:R 16:16:16:16 little endian */
-
-#define DRM_FORMAT_ARGB16161616F fourcc_code('A', 'R', '4', 'H') /* [63:0] A:R:G:B 16:16:16:16 little endian */
-#define DRM_FORMAT_ABGR16161616F fourcc_code('A', 'B', '4', 'H') /* [63:0] A:B:G:R 16:16:16:16 little endian */
-
-/*
- * RGBA format with 10-bit components packed in 64-bit per pixel, with 6 bits
- * of unused padding per component:
- */
-#define DRM_FORMAT_AXBXGXRX106106106106 fourcc_code('A', 'B', '1', '0') /* [63:0] A:x:B:x:G:x:R:x 10:6:10:6:10:6:10:6 little endian */
-
-/* packed YCbCr */
-#define DRM_FORMAT_YUYV fourcc_code('Y', 'U', 'Y', 'V') /* [31:0] Cr0:Y1:Cb0:Y0 8:8:8:8 little endian */
-#define DRM_FORMAT_YVYU fourcc_code('Y', 'V', 'Y', 'U') /* [31:0] Cb0:Y1:Cr0:Y0 8:8:8:8 little endian */
-#define DRM_FORMAT_UYVY fourcc_code('U', 'Y', 'V', 'Y') /* [31:0] Y1:Cr0:Y0:Cb0 8:8:8:8 little endian */
-#define DRM_FORMAT_VYUY fourcc_code('V', 'Y', 'U', 'Y') /* [31:0] Y1:Cb0:Y0:Cr0 8:8:8:8 little endian */
-
-#define DRM_FORMAT_AYUV fourcc_code('A', 'Y', 'U', 'V') /* [31:0] A:Y:Cb:Cr 8:8:8:8 little endian */
-#define DRM_FORMAT_XYUV8888 fourcc_code('X', 'Y', 'U', 'V') /* [31:0] X:Y:Cb:Cr 8:8:8:8 little endian */
-#define DRM_FORMAT_VUY888 fourcc_code('V', 'U', '2', '4') /* [23:0] Cr:Cb:Y 8:8:8 little endian */
-#define DRM_FORMAT_VUY101010 fourcc_code('V', 'U', '3', '0') /* Y followed by U then V, 10:10:10. Non-linear modifier only */
-
-/*
- * packed Y2xx indicate for each component, xx valid data occupy msb
- * 16-xx padding occupy lsb
- */
-#define DRM_FORMAT_Y210 fourcc_code('Y', '2', '1', '0') /* [63:0] Cr0:0:Y1:0:Cb0:0:Y0:0 10:6:10:6:10:6:10:6 little endian per 2 Y pixels */
-#define DRM_FORMAT_Y212 fourcc_code('Y', '2', '1', '2') /* [63:0] Cr0:0:Y1:0:Cb0:0:Y0:0 12:4:12:4:12:4:12:4 little endian per 2 Y pixels */
-#define DRM_FORMAT_Y216 fourcc_code('Y', '2', '1', '6') /* [63:0] Cr0:Y1:Cb0:Y0 16:16:16:16 little endian per 2 Y pixels */
-
-/*
- * packed Y4xx indicate for each component, xx valid data occupy msb
- * 16-xx padding occupy lsb except Y410
- */
-#define DRM_FORMAT_Y410 fourcc_code('Y', '4', '1', '0') /* [31:0] A:Cr:Y:Cb 2:10:10:10 little endian */
-#define DRM_FORMAT_Y412 fourcc_code('Y', '4', '1', '2') /* [63:0] A:0:Cr:0:Y:0:Cb:0 12:4:12:4:12:4:12:4 little endian */
-#define DRM_FORMAT_Y416 fourcc_code('Y', '4', '1', '6') /* [63:0] A:Cr:Y:Cb 16:16:16:16 little endian */
-
-#define DRM_FORMAT_XVYU2101010 fourcc_code('X', 'V', '3', '0') /* [31:0] X:Cr:Y:Cb 2:10:10:10 little endian */
-#define DRM_FORMAT_XVYU12_16161616 fourcc_code('X', 'V', '3', '6') /* [63:0] X:0:Cr:0:Y:0:Cb:0 12:4:12:4:12:4:12:4 little endian */
-#define DRM_FORMAT_XVYU16161616 fourcc_code('X', 'V', '4', '8') /* [63:0] X:Cr:Y:Cb 16:16:16:16 little endian */
-
-/*
- * packed YCbCr420 2x2 tiled formats
- * first 64 bits will contain Y,Cb,Cr components for a 2x2 tile
- */
-/* [63:0] A3:A2:Y3:0:Cr0:0:Y2:0:A1:A0:Y1:0:Cb0:0:Y0:0 1:1:8:2:8:2:8:2:1:1:8:2:8:2:8:2 little endian */
-#define DRM_FORMAT_Y0L0 fourcc_code('Y', '0', 'L', '0')
-/* [63:0] X3:X2:Y3:0:Cr0:0:Y2:0:X1:X0:Y1:0:Cb0:0:Y0:0 1:1:8:2:8:2:8:2:1:1:8:2:8:2:8:2 little endian */
-#define DRM_FORMAT_X0L0 fourcc_code('X', '0', 'L', '0')
-
-/* [63:0] A3:A2:Y3:Cr0:Y2:A1:A0:Y1:Cb0:Y0 1:1:10:10:10:1:1:10:10:10 little endian */
-#define DRM_FORMAT_Y0L2 fourcc_code('Y', '0', 'L', '2')
-/* [63:0] X3:X2:Y3:Cr0:Y2:X1:X0:Y1:Cb0:Y0 1:1:10:10:10:1:1:10:10:10 little endian */
-#define DRM_FORMAT_X0L2 fourcc_code('X', '0', 'L', '2')
-
-/*
- * 1-plane YUV 4:2:0
- * In these formats, the component ordering is specified (Y, followed by U
- * then V), but the exact Linear layout is undefined.
- * These formats can only be used with a non-Linear modifier.
- */
-#define DRM_FORMAT_YUV420_8BIT fourcc_code('Y', 'U', '0', '8')
-#define DRM_FORMAT_YUV420_10BIT fourcc_code('Y', 'U', '1', '0')
-
-/*
- * 2 plane RGB + A
- * index 0 = RGB plane, same format as the corresponding non _A8 format has
- * index 1 = A plane, [7:0] A
- */
-#define DRM_FORMAT_XRGB8888_A8 fourcc_code('X', 'R', 'A', '8')
-#define DRM_FORMAT_XBGR8888_A8 fourcc_code('X', 'B', 'A', '8')
-#define DRM_FORMAT_RGBX8888_A8 fourcc_code('R', 'X', 'A', '8')
-#define DRM_FORMAT_BGRX8888_A8 fourcc_code('B', 'X', 'A', '8')
-#define DRM_FORMAT_RGB888_A8 fourcc_code('R', '8', 'A', '8')
-#define DRM_FORMAT_BGR888_A8 fourcc_code('B', '8', 'A', '8')
-#define DRM_FORMAT_RGB565_A8 fourcc_code('R', '5', 'A', '8')
-#define DRM_FORMAT_BGR565_A8 fourcc_code('B', '5', 'A', '8')
-
-/*
- * 2 plane YCbCr
- * index 0 = Y plane, [7:0] Y
- * index 1 = Cr:Cb plane, [15:0] Cr:Cb little endian
- * or
- * index 1 = Cb:Cr plane, [15:0] Cb:Cr little endian
- */
-#define DRM_FORMAT_NV12 fourcc_code('N', 'V', '1', '2') /* 2x2 subsampled Cr:Cb plane */
-#define DRM_FORMAT_NV21 fourcc_code('N', 'V', '2', '1') /* 2x2 subsampled Cb:Cr plane */
-#define DRM_FORMAT_NV16 fourcc_code('N', 'V', '1', '6') /* 2x1 subsampled Cr:Cb plane */
-#define DRM_FORMAT_NV61 fourcc_code('N', 'V', '6', '1') /* 2x1 subsampled Cb:Cr plane */
-#define DRM_FORMAT_NV24 fourcc_code('N', 'V', '2', '4') /* non-subsampled Cr:Cb plane */
-#define DRM_FORMAT_NV42 fourcc_code('N', 'V', '4', '2') /* non-subsampled Cb:Cr plane */
-/*
- * 2 plane YCbCr
- * index 0 = Y plane, [39:0] Y3:Y2:Y1:Y0 little endian
- * index 1 = Cr:Cb plane, [39:0] Cr1:Cb1:Cr0:Cb0 little endian
- */
-#define DRM_FORMAT_NV15 fourcc_code('N', 'V', '1', '5') /* 2x2 subsampled Cr:Cb plane */
-
-/*
- * 2 plane YCbCr MSB aligned
- * index 0 = Y plane, [15:0] Y:x [10:6] little endian
- * index 1 = Cr:Cb plane, [31:0] Cr:x:Cb:x [10:6:10:6] little endian
- */
-#define DRM_FORMAT_P210 fourcc_code('P', '2', '1', '0') /* 2x1 subsampled Cr:Cb plane, 10 bit per channel */
-
-/*
- * 2 plane YCbCr MSB aligned
- * index 0 = Y plane, [15:0] Y:x [10:6] little endian
- * index 1 = Cr:Cb plane, [31:0] Cr:x:Cb:x [10:6:10:6] little endian
- */
-#define DRM_FORMAT_P010 fourcc_code('P', '0', '1', '0') /* 2x2 subsampled Cr:Cb plane 10 bits per channel */
-
-/*
- * 2 plane YCbCr MSB aligned
- * index 0 = Y plane, [15:0] Y:x [12:4] little endian
- * index 1 = Cr:Cb plane, [31:0] Cr:x:Cb:x [12:4:12:4] little endian
- */
-#define DRM_FORMAT_P012 fourcc_code('P', '0', '1', '2') /* 2x2 subsampled Cr:Cb plane 12 bits per channel */
-
-/*
- * 2 plane YCbCr MSB aligned
- * index 0 = Y plane, [15:0] Y little endian
- * index 1 = Cr:Cb plane, [31:0] Cr:Cb [16:16] little endian
- */
-#define DRM_FORMAT_P016 fourcc_code('P', '0', '1', '6') /* 2x2 subsampled Cr:Cb plane 16 bits per channel */
-
-/* 3 plane non-subsampled (444) YCbCr
- * 16 bits per component, but only 10 bits are used and 6 bits are padded
- * index 0: Y plane, [15:0] Y:x [10:6] little endian
- * index 1: Cb plane, [15:0] Cb:x [10:6] little endian
- * index 2: Cr plane, [15:0] Cr:x [10:6] little endian
- */
-#define DRM_FORMAT_Q410 fourcc_code('Q', '4', '1', '0')
-
-/* 3 plane non-subsampled (444) YCrCb
- * 16 bits per component, but only 10 bits are used and 6 bits are padded
- * index 0: Y plane, [15:0] Y:x [10:6] little endian
- * index 1: Cr plane, [15:0] Cr:x [10:6] little endian
- * index 2: Cb plane, [15:0] Cb:x [10:6] little endian
- */
-#define DRM_FORMAT_Q401 fourcc_code('Q', '4', '0', '1')
-
-/*
- * 3 plane YCbCr
- * index 0: Y plane, [7:0] Y
- * index 1: Cb plane, [7:0] Cb
- * index 2: Cr plane, [7:0] Cr
- * or
- * index 1: Cr plane, [7:0] Cr
- * index 2: Cb plane, [7:0] Cb
- */
-#define DRM_FORMAT_YUV410 fourcc_code('Y', 'U', 'V', '9') /* 4x4 subsampled Cb (1) and Cr (2) planes */
-#define DRM_FORMAT_YVU410 fourcc_code('Y', 'V', 'U', '9') /* 4x4 subsampled Cr (1) and Cb (2) planes */
-#define DRM_FORMAT_YUV411 fourcc_code('Y', 'U', '1', '1') /* 4x1 subsampled Cb (1) and Cr (2) planes */
-#define DRM_FORMAT_YVU411 fourcc_code('Y', 'V', '1', '1') /* 4x1 subsampled Cr (1) and Cb (2) planes */
-#define DRM_FORMAT_YUV420 fourcc_code('Y', 'U', '1', '2') /* 2x2 subsampled Cb (1) and Cr (2) planes */
-#define DRM_FORMAT_YVU420 fourcc_code('Y', 'V', '1', '2') /* 2x2 subsampled Cr (1) and Cb (2) planes */
-#define DRM_FORMAT_YUV422 fourcc_code('Y', 'U', '1', '6') /* 2x1 subsampled Cb (1) and Cr (2) planes */
-#define DRM_FORMAT_YVU422 fourcc_code('Y', 'V', '1', '6') /* 2x1 subsampled Cr (1) and Cb (2) planes */
-#define DRM_FORMAT_YUV444 fourcc_code('Y', 'U', '2', '4') /* non-subsampled Cb (1) and Cr (2) planes */
-#define DRM_FORMAT_YVU444 fourcc_code('Y', 'V', '2', '4') /* non-subsampled Cr (1) and Cb (2) planes */
-
-
-/*
- * Format Modifiers:
- *
- * Format modifiers describe, typically, a re-ordering or modification
- * of the data in a plane of an FB. This can be used to express tiled/
- * swizzled formats, or compression, or a combination of the two.
- *
- * The upper 8 bits of the format modifier are a vendor-id as assigned
- * below. The lower 56 bits are assigned as vendor sees fit.
- */
-
-/* Vendor Ids: */
-#define DRM_FORMAT_MOD_VENDOR_NONE 0
-#define DRM_FORMAT_MOD_VENDOR_INTEL 0x01
-#define DRM_FORMAT_MOD_VENDOR_AMD 0x02
-#define DRM_FORMAT_MOD_VENDOR_NVIDIA 0x03
-#define DRM_FORMAT_MOD_VENDOR_SAMSUNG 0x04
-#define DRM_FORMAT_MOD_VENDOR_QCOM 0x05
-#define DRM_FORMAT_MOD_VENDOR_VIVANTE 0x06
-#define DRM_FORMAT_MOD_VENDOR_BROADCOM 0x07
-#define DRM_FORMAT_MOD_VENDOR_ARM 0x08
-#define DRM_FORMAT_MOD_VENDOR_ALLWINNER 0x09
-#define DRM_FORMAT_MOD_VENDOR_AMLOGIC 0x0a
-
-/* add more to the end as needed */
-
-#define DRM_FORMAT_RESERVED ((1ULL << 56) - 1)
-
-#define fourcc_mod_code(vendor, val) \
- ((((uint64_t)DRM_FORMAT_MOD_VENDOR_## vendor) << 56) | ((val) & 0x00ffffffffffffffULL))
-
-/*
- * Format Modifier tokens:
- *
- * When adding a new token please document the layout with a code comment,
- * similar to the fourcc codes above. drm_fourcc.h is considered the
- * authoritative source for all of these.
- *
- * Generic modifier names:
- *
- * DRM_FORMAT_MOD_GENERIC_* definitions are used to provide vendor-neutral names
- * for layouts which are common across multiple vendors. To preserve
- * compatibility, in cases where a vendor-specific definition already exists and
- * a generic name for it is desired, the common name is a purely symbolic alias
- * and must use the same numerical value as the original definition.
- *
- * Note that generic names should only be used for modifiers which describe
- * generic layouts (such as pixel re-ordering), which may have
- * independently-developed support across multiple vendors.
- *
- * In future cases where a generic layout is identified before merging with a
- * vendor-specific modifier, a new 'GENERIC' vendor or modifier using vendor
- * 'NONE' could be considered. This should only be for obvious, exceptional
- * cases to avoid polluting the 'GENERIC' namespace with modifiers which only
- * apply to a single vendor.
- *
- * Generic names should not be used for cases where multiple hardware vendors
- * have implementations of the same standardised compression scheme (such as
- * AFBC). In those cases, all implementations should use the same format
- * modifier(s), reflecting the vendor of the standard.
- */
-
-#define DRM_FORMAT_MOD_GENERIC_16_16_TILE DRM_FORMAT_MOD_SAMSUNG_16_16_TILE
-
-/*
- * Invalid Modifier
- *
- * This modifier can be used as a sentinel to terminate the format modifiers
- * list, or to initialize a variable with an invalid modifier. It might also be
- * used to report an error back to userspace for certain APIs.
- */
-#define DRM_FORMAT_MOD_INVALID fourcc_mod_code(NONE, DRM_FORMAT_RESERVED)
-
-/*
- * Linear Layout
- *
- * Just plain linear layout. Note that this is different from no specifying any
- * modifier (e.g. not setting DRM_MODE_FB_MODIFIERS in the DRM_ADDFB2 ioctl),
- * which tells the driver to also take driver-internal information into account
- * and so might actually result in a tiled framebuffer.
- */
-#define DRM_FORMAT_MOD_LINEAR fourcc_mod_code(NONE, 0)
-
-/*
- * Deprecated: use DRM_FORMAT_MOD_LINEAR instead
- *
- * The "none" format modifier doesn't actually mean that the modifier is
- * implicit, instead it means that the layout is linear. Whether modifiers are
- * used is out-of-band information carried in an API-specific way (e.g. in a
- * flag for drm_mode_fb_cmd2).
- */
-#define DRM_FORMAT_MOD_NONE 0
-
-/* Intel framebuffer modifiers */
-
-/*
- * Intel X-tiling layout
- *
- * This is a tiled layout using 4Kb tiles (except on gen2 where the tiles 2Kb)
- * in row-major layout. Within the tile bytes are laid out row-major, with
- * a platform-dependent stride. On top of that the memory can apply
- * platform-depending swizzling of some higher address bits into bit6.
- *
- * Note that this layout is only accurate on intel gen 8+ or valleyview chipsets.
- * On earlier platforms the is highly platforms specific and not useful for
- * cross-driver sharing. It exists since on a given platform it does uniquely
- * identify the layout in a simple way for i915-specific userspace, which
- * facilitated conversion of userspace to modifiers. Additionally the exact
- * format on some really old platforms is not known.
- */
-#define I915_FORMAT_MOD_X_TILED fourcc_mod_code(INTEL, 1)
-
-/*
- * Intel Y-tiling layout
- *
- * This is a tiled layout using 4Kb tiles (except on gen2 where the tiles 2Kb)
- * in row-major layout. Within the tile bytes are laid out in OWORD (16 bytes)
- * chunks column-major, with a platform-dependent height. On top of that the
- * memory can apply platform-depending swizzling of some higher address bits
- * into bit6.
- *
- * Note that this layout is only accurate on intel gen 8+ or valleyview chipsets.
- * On earlier platforms the is highly platforms specific and not useful for
- * cross-driver sharing. It exists since on a given platform it does uniquely
- * identify the layout in a simple way for i915-specific userspace, which
- * facilitated conversion of userspace to modifiers. Additionally the exact
- * format on some really old platforms is not known.
- */
-#define I915_FORMAT_MOD_Y_TILED fourcc_mod_code(INTEL, 2)
-
-/*
- * Intel Yf-tiling layout
- *
- * This is a tiled layout using 4Kb tiles in row-major layout.
- * Within the tile pixels are laid out in 16 256 byte units / sub-tiles which
- * are arranged in four groups (two wide, two high) with column-major layout.
- * Each group therefore consits out of four 256 byte units, which are also laid
- * out as 2x2 column-major.
- * 256 byte units are made out of four 64 byte blocks of pixels, producing
- * either a square block or a 2:1 unit.
- * 64 byte blocks of pixels contain four pixel rows of 16 bytes, where the width
- * in pixel depends on the pixel depth.
- */
-#define I915_FORMAT_MOD_Yf_TILED fourcc_mod_code(INTEL, 3)
-
-/*
- * Intel color control surface (CCS) for render compression
- *
- * The framebuffer format must be one of the 8:8:8:8 RGB formats.
- * The main surface will be plane index 0 and must be Y/Yf-tiled,
- * the CCS will be plane index 1.
- *
- * Each CCS tile matches a 1024x512 pixel area of the main surface.
- * To match certain aspects of the 3D hardware the CCS is
- * considered to be made up of normal 128Bx32 Y tiles, Thus
- * the CCS pitch must be specified in multiples of 128 bytes.
- *
- * In reality the CCS tile appears to be a 64Bx64 Y tile, composed
- * of QWORD (8 bytes) chunks instead of OWORD (16 bytes) chunks.
- * But that fact is not relevant unless the memory is accessed
- * directly.
- */
-#define I915_FORMAT_MOD_Y_TILED_CCS fourcc_mod_code(INTEL, 4)
-#define I915_FORMAT_MOD_Yf_TILED_CCS fourcc_mod_code(INTEL, 5)
-
-/*
- * Intel color control surfaces (CCS) for Gen-12 render compression.
- *
- * The main surface is Y-tiled and at plane index 0, the CCS is linear and
- * at index 1. A 64B CCS cache line corresponds to an area of 4x1 tiles in
- * main surface. In other words, 4 bits in CCS map to a main surface cache
- * line pair. The main surface pitch is required to be a multiple of four
- * Y-tile widths.
- */
-#define I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS fourcc_mod_code(INTEL, 6)
-
-/*
- * Intel color control surfaces (CCS) for Gen-12 media compression
- *
- * The main surface is Y-tiled and at plane index 0, the CCS is linear and
- * at index 1. A 64B CCS cache line corresponds to an area of 4x1 tiles in
- * main surface. In other words, 4 bits in CCS map to a main surface cache
- * line pair. The main surface pitch is required to be a multiple of four
- * Y-tile widths. For semi-planar formats like NV12, CCS planes follow the
- * Y and UV planes i.e., planes 0 and 1 are used for Y and UV surfaces,
- * planes 2 and 3 for the respective CCS.
- */
-#define I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS fourcc_mod_code(INTEL, 7)
-
-/*
- * Tiled, NV12MT, grouped in 64 (pixels) x 32 (lines) -sized macroblocks
- *
- * Macroblocks are laid in a Z-shape, and each pixel data is following the
- * standard NV12 style.
- * As for NV12, an image is the result of two frame buffers: one for Y,
- * one for the interleaved Cb/Cr components (1/2 the height of the Y buffer).
- * Alignment requirements are (for each buffer):
- * - multiple of 128 pixels for the width
- * - multiple of 32 pixels for the height
- *
- * For more information: see https://linuxtv.org/downloads/v4l-dvb-apis/re32.html
- */
-#define DRM_FORMAT_MOD_SAMSUNG_64_32_TILE fourcc_mod_code(SAMSUNG, 1)
-
-/*
- * Tiled, 16 (pixels) x 16 (lines) - sized macroblocks
- *
- * This is a simple tiled layout using tiles of 16x16 pixels in a row-major
- * layout. For YCbCr formats Cb/Cr components are taken in such a way that
- * they correspond to their 16x16 luma block.
- */
-#define DRM_FORMAT_MOD_SAMSUNG_16_16_TILE fourcc_mod_code(SAMSUNG, 2)
-
-/*
- * Qualcomm Compressed Format
- *
- * Refers to a compressed variant of the base format that is compressed.
- * Implementation may be platform and base-format specific.
- *
- * Each macrotile consists of m x n (mostly 4 x 4) tiles.
- * Pixel data pitch/stride is aligned with macrotile width.
- * Pixel data height is aligned with macrotile height.
- * Entire pixel data buffer is aligned with 4k(bytes).
- */
-#define DRM_FORMAT_MOD_QCOM_COMPRESSED fourcc_mod_code(QCOM, 1)
-
-/* Vivante framebuffer modifiers */
-
-/*
- * Vivante 4x4 tiling layout
- *
- * This is a simple tiled layout using tiles of 4x4 pixels in a row-major
- * layout.
- */
-#define DRM_FORMAT_MOD_VIVANTE_TILED fourcc_mod_code(VIVANTE, 1)
-
-/*
- * Vivante 64x64 super-tiling layout
- *
- * This is a tiled layout using 64x64 pixel super-tiles, where each super-tile
- * contains 8x4 groups of 2x4 tiles of 4x4 pixels (like above) each, all in row-
- * major layout.
- *
- * For more information: see
- * https://github.com/etnaviv/etna_viv/blob/master/doc/hardware.md#texture-tiling
- */
-#define DRM_FORMAT_MOD_VIVANTE_SUPER_TILED fourcc_mod_code(VIVANTE, 2)
-
-/*
- * Vivante 4x4 tiling layout for dual-pipe
- *
- * Same as the 4x4 tiling layout, except every second 4x4 pixel tile starts at a
- * different base address. Offsets from the base addresses are therefore halved
- * compared to the non-split tiled layout.
- */
-#define DRM_FORMAT_MOD_VIVANTE_SPLIT_TILED fourcc_mod_code(VIVANTE, 3)
-
-/*
- * Vivante 64x64 super-tiling layout for dual-pipe
- *
- * Same as the 64x64 super-tiling layout, except every second 4x4 pixel tile
- * starts at a different base address. Offsets from the base addresses are
- * therefore halved compared to the non-split super-tiled layout.
- */
-#define DRM_FORMAT_MOD_VIVANTE_SPLIT_SUPER_TILED fourcc_mod_code(VIVANTE, 4)
-
-/* NVIDIA frame buffer modifiers */
-
-/*
- * Tegra Tiled Layout, used by Tegra 2, 3 and 4.
- *
- * Pixels are arranged in simple tiles of 16 x 16 bytes.
- */
-#define DRM_FORMAT_MOD_NVIDIA_TEGRA_TILED fourcc_mod_code(NVIDIA, 1)
-
-/*
- * Generalized Block Linear layout, used by desktop GPUs starting with NV50/G80,
- * and Tegra GPUs starting with Tegra K1.
- *
- * Pixels are arranged in Groups of Bytes (GOBs). GOB size and layout varies
- * based on the architecture generation. GOBs themselves are then arranged in
- * 3D blocks, with the block dimensions (in terms of GOBs) always being a power
- * of two, and hence expressible as their log2 equivalent (E.g., "2" represents
- * a block depth or height of "4").
- *
- * Chapter 20 "Pixel Memory Formats" of the Tegra X1 TRM describes this format
- * in full detail.
- *
- * Macro
- * Bits Param Description
- * ---- ----- -----------------------------------------------------------------
- *
- * 3:0 h log2(height) of each block, in GOBs. Placed here for
- * compatibility with the existing
- * DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK()-based modifiers.
- *
- * 4:4 - Must be 1, to indicate block-linear layout. Necessary for
- * compatibility with the existing
- * DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK()-based modifiers.
- *
- * 8:5 - Reserved (To support 3D-surfaces with variable log2(depth) block
- * size). Must be zero.
- *
- * Note there is no log2(width) parameter. Some portions of the
- * hardware support a block width of two gobs, but it is impractical
- * to use due to lack of support elsewhere, and has no known
- * benefits.
- *
- * 11:9 - Reserved (To support 2D-array textures with variable array stride
- * in blocks, specified via log2(tile width in blocks)). Must be
- * zero.
- *
- * 19:12 k Page Kind. This value directly maps to a field in the page
- * tables of all GPUs >= NV50. It affects the exact layout of bits
- * in memory and can be derived from the tuple
- *
- * (format, GPU model, compression type, samples per pixel)
- *
- * Where compression type is defined below. If GPU model were
- * implied by the format modifier, format, or memory buffer, page
- * kind would not need to be included in the modifier itself, but
- * since the modifier should define the layout of the associated
- * memory buffer independent from any device or other context, it
- * must be included here.
- *
- * 21:20 g GOB Height and Page Kind Generation. The height of a GOB changed
- * starting with Fermi GPUs. Additionally, the mapping between page
- * kind and bit layout has changed at various points.
- *
- * 0 = Gob Height 8, Fermi - Volta, Tegra K1+ Page Kind mapping
- * 1 = Gob Height 4, G80 - GT2XX Page Kind mapping
- * 2 = Gob Height 8, Turing+ Page Kind mapping
- * 3 = Reserved for future use.
- *
- * 22:22 s Sector layout. On Tegra GPUs prior to Xavier, there is a further
- * bit remapping step that occurs at an even lower level than the
- * page kind and block linear swizzles. This causes the layout of
- * surfaces mapped in those SOC's GPUs to be incompatible with the
- * equivalent mapping on other GPUs in the same system.
- *
- * 0 = Tegra K1 - Tegra Parker/TX2 Layout.
- * 1 = Desktop GPU and Tegra Xavier+ Layout
- *
- * 25:23 c Lossless Framebuffer Compression type.
- *
- * 0 = none
- * 1 = ROP/3D, layout 1, exact compression format implied by Page
- * Kind field
- * 2 = ROP/3D, layout 2, exact compression format implied by Page
- * Kind field
- * 3 = CDE horizontal
- * 4 = CDE vertical
- * 5 = Reserved for future use
- * 6 = Reserved for future use
- * 7 = Reserved for future use
- *
- * 55:25 - Reserved for future use. Must be zero.
- */
-#define DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(c, s, g, k, h) \
- fourcc_mod_code(NVIDIA, (0x10 | \
- ((h) & 0xf) | \
- (((k) & 0xff) << 12) | \
- (((g) & 0x3) << 20) | \
- (((s) & 0x1) << 22) | \
- (((c) & 0x7) << 23)))
-
-/* To grandfather in prior block linear format modifiers to the above layout,
- * the page kind "0", which corresponds to "pitch/linear" and hence is unusable
- * with block-linear layouts, is remapped within drivers to the value 0xfe,
- * which corresponds to the "generic" kind used for simple single-sample
- * uncompressed color formats on Fermi - Volta GPUs.
- */
-static inline uint64_t
-drm_fourcc_canonicalize_nvidia_format_mod(uint64_t modifier)
-{
- if (!(modifier & 0x10) || (modifier & (0xff << 12)))
- return modifier;
- else
- return modifier | (0xfe << 12);
-}
-
-/*
- * 16Bx2 Block Linear layout, used by Tegra K1 and later
- *
- * Pixels are arranged in 64x8 Groups Of Bytes (GOBs). GOBs are then stacked
- * vertically by a power of 2 (1 to 32 GOBs) to form a block.
- *
- * Within a GOB, data is ordered as 16B x 2 lines sectors laid in Z-shape.
- *
- * Parameter 'v' is the log2 encoding of the number of GOBs stacked vertically.
- * Valid values are:
- *
- * 0 == ONE_GOB
- * 1 == TWO_GOBS
- * 2 == FOUR_GOBS
- * 3 == EIGHT_GOBS
- * 4 == SIXTEEN_GOBS
- * 5 == THIRTYTWO_GOBS
- *
- * Chapter 20 "Pixel Memory Formats" of the Tegra X1 TRM describes this format
- * in full detail.
- */
-#define DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(v) \
- DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 0, 0, 0, (v))
-
-#define DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK_ONE_GOB \
- DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(0)
-#define DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK_TWO_GOB \
- DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(1)
-#define DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK_FOUR_GOB \
- DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(2)
-#define DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK_EIGHT_GOB \
- DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(3)
-#define DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK_SIXTEEN_GOB \
- DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(4)
-#define DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK_THIRTYTWO_GOB \
- DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(5)
-
-/*
- * Some Broadcom modifiers take parameters, for example the number of
- * vertical lines in the image. Reserve the lower 32 bits for modifier
- * type, and the next 24 bits for parameters. Top 8 bits are the
- * vendor code.
- */
-#define __fourcc_mod_broadcom_param_shift 8
-#define __fourcc_mod_broadcom_param_bits 48
-#define fourcc_mod_broadcom_code(val, params) \
- fourcc_mod_code(BROADCOM, ((((uint64_t)params) << __fourcc_mod_broadcom_param_shift) | val))
-#define fourcc_mod_broadcom_param(m) \
- ((int)(((m) >> __fourcc_mod_broadcom_param_shift) & \
- ((1ULL << __fourcc_mod_broadcom_param_bits) - 1)))
-#define fourcc_mod_broadcom_mod(m) \
- ((m) & ~(((1ULL << __fourcc_mod_broadcom_param_bits) - 1) << \
- __fourcc_mod_broadcom_param_shift))
-
-/*
- * Broadcom VC4 "T" format
- *
- * This is the primary layout that the V3D GPU can texture from (it
- * can't do linear). The T format has:
- *
- * - 64b utiles of pixels in a raster-order grid according to cpp. It's 4x4
- * pixels at 32 bit depth.
- *
- * - 1k subtiles made of a 4x4 raster-order grid of 64b utiles (so usually
- * 16x16 pixels).
- *
- * - 4k tiles made of a 2x2 grid of 1k subtiles (so usually 32x32 pixels). On
- * even 4k tile rows, they're arranged as (BL, TL, TR, BR), and on odd rows
- * they're (TR, BR, BL, TL), where bottom left is start of memory.
- *
- * - an image made of 4k tiles in rows either left-to-right (even rows of 4k
- * tiles) or right-to-left (odd rows of 4k tiles).
- */
-#define DRM_FORMAT_MOD_BROADCOM_VC4_T_TILED fourcc_mod_code(BROADCOM, 1)
-
-/*
- * Broadcom SAND format
- *
- * This is the native format that the H.264 codec block uses. For VC4
- * HVS, it is only valid for H.264 (NV12/21) and RGBA modes.
- *
- * The image can be considered to be split into columns, and the
- * columns are placed consecutively into memory. The width of those
- * columns can be either 32, 64, 128, or 256 pixels, but in practice
- * only 128 pixel columns are used.
- *
- * The pitch between the start of each column is set to optimally
- * switch between SDRAM banks. This is passed as the number of lines
- * of column width in the modifier (we can't use the stride value due
- * to various core checks that look at it , so you should set the
- * stride to width*cpp).
- *
- * Note that the column height for this format modifier is the same
- * for all of the planes, assuming that each column contains both Y
- * and UV. Some SAND-using hardware stores UV in a separate tiled
- * image from Y to reduce the column height, which is not supported
- * with these modifiers.
- */
-
-#define DRM_FORMAT_MOD_BROADCOM_SAND32_COL_HEIGHT(v) \
- fourcc_mod_broadcom_code(2, v)
-#define DRM_FORMAT_MOD_BROADCOM_SAND64_COL_HEIGHT(v) \
- fourcc_mod_broadcom_code(3, v)
-#define DRM_FORMAT_MOD_BROADCOM_SAND128_COL_HEIGHT(v) \
- fourcc_mod_broadcom_code(4, v)
-#define DRM_FORMAT_MOD_BROADCOM_SAND256_COL_HEIGHT(v) \
- fourcc_mod_broadcom_code(5, v)
-
-#define DRM_FORMAT_MOD_BROADCOM_SAND32 \
- DRM_FORMAT_MOD_BROADCOM_SAND32_COL_HEIGHT(0)
-#define DRM_FORMAT_MOD_BROADCOM_SAND64 \
- DRM_FORMAT_MOD_BROADCOM_SAND64_COL_HEIGHT(0)
-#define DRM_FORMAT_MOD_BROADCOM_SAND128 \
- DRM_FORMAT_MOD_BROADCOM_SAND128_COL_HEIGHT(0)
-#define DRM_FORMAT_MOD_BROADCOM_SAND256 \
- DRM_FORMAT_MOD_BROADCOM_SAND256_COL_HEIGHT(0)
-
-/* Broadcom UIF format
- *
- * This is the common format for the current Broadcom multimedia
- * blocks, including V3D 3.x and newer, newer video codecs, and
- * displays.
- *
- * The image consists of utiles (64b blocks), UIF blocks (2x2 utiles),
- * and macroblocks (4x4 UIF blocks). Those 4x4 UIF block groups are
- * stored in columns, with padding between the columns to ensure that
- * moving from one column to the next doesn't hit the same SDRAM page
- * bank.
- *
- * To calculate the padding, it is assumed that each hardware block
- * and the software driving it knows the platform's SDRAM page size,
- * number of banks, and XOR address, and that it's identical between
- * all blocks using the format. This tiling modifier will use XOR as
- * necessary to reduce the padding. If a hardware block can't do XOR,
- * the assumption is that a no-XOR tiling modifier will be created.
- */
-#define DRM_FORMAT_MOD_BROADCOM_UIF fourcc_mod_code(BROADCOM, 6)
-
-/*
- * Arm Framebuffer Compression (AFBC) modifiers
- *
- * AFBC is a proprietary lossless image compression protocol and format.
- * It provides fine-grained random access and minimizes the amount of data
- * transferred between IP blocks.
- *
- * AFBC has several features which may be supported and/or used, which are
- * represented using bits in the modifier. Not all combinations are valid,
- * and different devices or use-cases may support different combinations.
- *
- * Further information on the use of AFBC modifiers can be found in
- * Documentation/gpu/afbc.rst
- */
-
-/*
- * The top 4 bits (out of the 56 bits alloted for specifying vendor specific
- * modifiers) denote the category for modifiers. Currently we have only two
- * categories of modifiers ie AFBC and MISC. We can have a maximum of sixteen
- * different categories.
- */
-#define DRM_FORMAT_MOD_ARM_CODE(__type, __val) \
- fourcc_mod_code(ARM, ((uint64_t)(__type) << 52) | ((__val) & 0x000fffffffffffffULL))
-
-#define DRM_FORMAT_MOD_ARM_TYPE_AFBC 0x00
-#define DRM_FORMAT_MOD_ARM_TYPE_MISC 0x01
-
-#define DRM_FORMAT_MOD_ARM_AFBC(__afbc_mode) \
- DRM_FORMAT_MOD_ARM_CODE(DRM_FORMAT_MOD_ARM_TYPE_AFBC, __afbc_mode)
-
-/*
- * AFBC superblock size
- *
- * Indicates the superblock size(s) used for the AFBC buffer. The buffer
- * size (in pixels) must be aligned to a multiple of the superblock size.
- * Four lowest significant bits(LSBs) are reserved for block size.
- *
- * Where one superblock size is specified, it applies to all planes of the
- * buffer (e.g. 16x16, 32x8). When multiple superblock sizes are specified,
- * the first applies to the Luma plane and the second applies to the Chroma
- * plane(s). e.g. (32x8_64x4 means 32x8 Luma, with 64x4 Chroma).
- * Multiple superblock sizes are only valid for multi-plane YCbCr formats.
- */
-#define AFBC_FORMAT_MOD_BLOCK_SIZE_MASK 0xf
-#define AFBC_FORMAT_MOD_BLOCK_SIZE_16x16 (1ULL)
-#define AFBC_FORMAT_MOD_BLOCK_SIZE_32x8 (2ULL)
-#define AFBC_FORMAT_MOD_BLOCK_SIZE_64x4 (3ULL)
-#define AFBC_FORMAT_MOD_BLOCK_SIZE_32x8_64x4 (4ULL)
-
-/*
- * AFBC lossless colorspace transform
- *
- * Indicates that the buffer makes use of the AFBC lossless colorspace
- * transform.
- */
-#define AFBC_FORMAT_MOD_YTR (1ULL << 4)
-
-/*
- * AFBC block-split
- *
- * Indicates that the payload of each superblock is split. The second
- * half of the payload is positioned at a predefined offset from the start
- * of the superblock payload.
- */
-#define AFBC_FORMAT_MOD_SPLIT (1ULL << 5)
-
-/*
- * AFBC sparse layout
- *
- * This flag indicates that the payload of each superblock must be stored at a
- * predefined position relative to the other superblocks in the same AFBC
- * buffer. This order is the same order used by the header buffer. In this mode
- * each superblock is given the same amount of space as an uncompressed
- * superblock of the particular format would require, rounding up to the next
- * multiple of 128 bytes in size.
- */
-#define AFBC_FORMAT_MOD_SPARSE (1ULL << 6)
-
-/*
- * AFBC copy-block restrict
- *
- * Buffers with this flag must obey the copy-block restriction. The restriction
- * is such that there are no copy-blocks referring across the border of 8x8
- * blocks. For the subsampled data the 8x8 limitation is also subsampled.
- */
-#define AFBC_FORMAT_MOD_CBR (1ULL << 7)
-
-/*
- * AFBC tiled layout
- *
- * The tiled layout groups superblocks in 8x8 or 4x4 tiles, where all
- * superblocks inside a tile are stored together in memory. 8x8 tiles are used
- * for pixel formats up to and including 32 bpp while 4x4 tiles are used for
- * larger bpp formats. The order between the tiles is scan line.
- * When the tiled layout is used, the buffer size (in pixels) must be aligned
- * to the tile size.
- */
-#define AFBC_FORMAT_MOD_TILED (1ULL << 8)
-
-/*
- * AFBC solid color blocks
- *
- * Indicates that the buffer makes use of solid-color blocks, whereby bandwidth
- * can be reduced if a whole superblock is a single color.
- */
-#define AFBC_FORMAT_MOD_SC (1ULL << 9)
-
-/*
- * AFBC double-buffer
- *
- * Indicates that the buffer is allocated in a layout safe for front-buffer
- * rendering.
- */
-#define AFBC_FORMAT_MOD_DB (1ULL << 10)
-
-/*
- * AFBC buffer content hints
- *
- * Indicates that the buffer includes per-superblock content hints.
- */
-#define AFBC_FORMAT_MOD_BCH (1ULL << 11)
-
-/* AFBC uncompressed storage mode
- *
- * Indicates that the buffer is using AFBC uncompressed storage mode.
- * In this mode all superblock payloads in the buffer use the uncompressed
- * storage mode, which is usually only used for data which cannot be compressed.
- * The buffer layout is the same as for AFBC buffers without USM set, this only
- * affects the storage mode of the individual superblocks. Note that even a
- * buffer without USM set may use uncompressed storage mode for some or all
- * superblocks, USM just guarantees it for all.
- */
-#define AFBC_FORMAT_MOD_USM (1ULL << 12)
-
-/*
- * Arm 16x16 Block U-Interleaved modifier
- *
- * This is used by Arm Mali Utgard and Midgard GPUs. It divides the image
- * into 16x16 pixel blocks. Blocks are stored linearly in order, but pixels
- * in the block are reordered.
- */
-#define DRM_FORMAT_MOD_ARM_16X16_BLOCK_U_INTERLEAVED \
- DRM_FORMAT_MOD_ARM_CODE(DRM_FORMAT_MOD_ARM_TYPE_MISC, 1ULL)
-
-/*
- * Allwinner tiled modifier
- *
- * This tiling mode is implemented by the VPU found on all Allwinner platforms,
- * codenamed sunxi. It is associated with a YUV format that uses either 2 or 3
- * planes.
- *
- * With this tiling, the luminance samples are disposed in tiles representing
- * 32x32 pixels and the chrominance samples in tiles representing 32x64 pixels.
- * The pixel order in each tile is linear and the tiles are disposed linearly,
- * both in row-major order.
- */
-#define DRM_FORMAT_MOD_ALLWINNER_TILED fourcc_mod_code(ALLWINNER, 1)
-
-/*
- * Amlogic Video Framebuffer Compression modifiers
- *
- * Amlogic uses a proprietary lossless image compression protocol and format
- * for their hardware video codec accelerators, either video decoders or
- * video input encoders.
- *
- * It considerably reduces memory bandwidth while writing and reading
- * frames in memory.
- *
- * The underlying storage is considered to be 3 components, 8bit or 10-bit
- * per component YCbCr 420, single plane :
- * - DRM_FORMAT_YUV420_8BIT
- * - DRM_FORMAT_YUV420_10BIT
- *
- * The first 8 bits of the mode defines the layout, then the following 8 bits
- * defines the options changing the layout.
- *
- * Not all combinations are valid, and different SoCs may support different
- * combinations of layout and options.
- */
-#define __fourcc_mod_amlogic_layout_mask 0xf
-#define __fourcc_mod_amlogic_options_shift 8
-#define __fourcc_mod_amlogic_options_mask 0xf
-
-#define DRM_FORMAT_MOD_AMLOGIC_FBC(__layout, __options) \
- fourcc_mod_code(AMLOGIC, \
- ((__layout) & __fourcc_mod_amlogic_layout_mask) | \
- (((__options) & __fourcc_mod_amlogic_options_mask) \
- << __fourcc_mod_amlogic_options_shift))
-
-/* Amlogic FBC Layouts */
-
-/*
- * Amlogic FBC Basic Layout
- *
- * The basic layout is composed of:
- * - a body content organized in 64x32 superblocks with 4096 bytes per
- * superblock in default mode.
- * - a 32 bytes per 128x64 header block
- *
- * This layout is transferrable between Amlogic SoCs supporting this modifier.
- */
-#define AMLOGIC_FBC_LAYOUT_BASIC (1ULL)
-
-/*
- * Amlogic FBC Scatter Memory layout
- *
- * Indicates the header contains IOMMU references to the compressed
- * frames content to optimize memory access and layout.
- *
- * In this mode, only the header memory address is needed, thus the
- * content memory organization is tied to the current producer
- * execution and cannot be saved/dumped neither transferrable between
- * Amlogic SoCs supporting this modifier.
- *
- * Due to the nature of the layout, these buffers are not expected to
- * be accessible by the user-space clients, but only accessible by the
- * hardware producers and consumers.
- *
- * The user-space clients should expect a failure while trying to mmap
- * the DMA-BUF handle returned by the producer.
- */
-#define AMLOGIC_FBC_LAYOUT_SCATTER (2ULL)
-
-/* Amlogic FBC Layout Options Bit Mask */
-
-/*
- * Amlogic FBC Memory Saving mode
- *
- * Indicates the storage is packed when pixel size is multiple of word
- * boudaries, i.e. 8bit should be stored in this mode to save allocation
- * memory.
- *
- * This mode reduces body layout to 3072 bytes per 64x32 superblock with
- * the basic layout and 3200 bytes per 64x32 superblock combined with
- * the scatter layout.
- */
-#define AMLOGIC_FBC_OPTION_MEM_SAVING (1ULL << 0)
-
-/*
- * AMD modifiers
- *
- * Memory layout:
- *
- * without DCC:
- * - main surface
- *
- * with DCC & without DCC_RETILE:
- * - main surface in plane 0
- * - DCC surface in plane 1 (RB-aligned, pipe-aligned if DCC_PIPE_ALIGN is set)
- *
- * with DCC & DCC_RETILE:
- * - main surface in plane 0
- * - displayable DCC surface in plane 1 (not RB-aligned & not pipe-aligned)
- * - pipe-aligned DCC surface in plane 2 (RB-aligned & pipe-aligned)
- *
- * For multi-plane formats the above surfaces get merged into one plane for
- * each format plane, based on the required alignment only.
- *
- * Bits Parameter Notes
- * ----- ------------------------ ---------------------------------------------
- *
- * 7:0 TILE_VERSION Values are AMD_FMT_MOD_TILE_VER_*
- * 12:8 TILE Values are AMD_FMT_MOD_TILE_<version>_*
- * 13 DCC
- * 14 DCC_RETILE
- * 15 DCC_PIPE_ALIGN
- * 16 DCC_INDEPENDENT_64B
- * 17 DCC_INDEPENDENT_128B
- * 19:18 DCC_MAX_COMPRESSED_BLOCK Values are AMD_FMT_MOD_DCC_BLOCK_*
- * 20 DCC_CONSTANT_ENCODE
- * 23:21 PIPE_XOR_BITS Only for some chips
- * 26:24 BANK_XOR_BITS Only for some chips
- * 29:27 PACKERS Only for some chips
- * 32:30 RB Only for some chips
- * 35:33 PIPE Only for some chips
- * 55:36 - Reserved for future use, must be zero
- */
-#define AMD_FMT_MOD fourcc_mod_code(AMD, 0)
-
-#define IS_AMD_FMT_MOD(val) (((val) >> 56) == DRM_FORMAT_MOD_VENDOR_AMD)
-
-/* Reserve 0 for GFX8 and older */
-#define AMD_FMT_MOD_TILE_VER_GFX9 1
-#define AMD_FMT_MOD_TILE_VER_GFX10 2
-#define AMD_FMT_MOD_TILE_VER_GFX10_RBPLUS 3
-
-/*
- * 64K_S is the same for GFX9/GFX10/GFX10_RBPLUS and hence has GFX9 as canonical
- * version.
- */
-#define AMD_FMT_MOD_TILE_GFX9_64K_S 9
-
-/*
- * 64K_D for non-32 bpp is the same for GFX9/GFX10/GFX10_RBPLUS and hence has
- * GFX9 as canonical version.
- */
-#define AMD_FMT_MOD_TILE_GFX9_64K_D 10
-#define AMD_FMT_MOD_TILE_GFX9_64K_S_X 25
-#define AMD_FMT_MOD_TILE_GFX9_64K_D_X 26
-#define AMD_FMT_MOD_TILE_GFX9_64K_R_X 27
-
-#define AMD_FMT_MOD_DCC_BLOCK_64B 0
-#define AMD_FMT_MOD_DCC_BLOCK_128B 1
-#define AMD_FMT_MOD_DCC_BLOCK_256B 2
-
-#define AMD_FMT_MOD_TILE_VERSION_SHIFT 0
-#define AMD_FMT_MOD_TILE_VERSION_MASK 0xFF
-#define AMD_FMT_MOD_TILE_SHIFT 8
-#define AMD_FMT_MOD_TILE_MASK 0x1F
-
-/* Whether DCC compression is enabled. */
-#define AMD_FMT_MOD_DCC_SHIFT 13
-#define AMD_FMT_MOD_DCC_MASK 0x1
-
-/*
- * Whether to include two DCC surfaces, one which is rb & pipe aligned, and
- * one which is not-aligned.
- */
-#define AMD_FMT_MOD_DCC_RETILE_SHIFT 14
-#define AMD_FMT_MOD_DCC_RETILE_MASK 0x1
-
-/* Only set if DCC_RETILE = false */
-#define AMD_FMT_MOD_DCC_PIPE_ALIGN_SHIFT 15
-#define AMD_FMT_MOD_DCC_PIPE_ALIGN_MASK 0x1
-
-#define AMD_FMT_MOD_DCC_INDEPENDENT_64B_SHIFT 16
-#define AMD_FMT_MOD_DCC_INDEPENDENT_64B_MASK 0x1
-#define AMD_FMT_MOD_DCC_INDEPENDENT_128B_SHIFT 17
-#define AMD_FMT_MOD_DCC_INDEPENDENT_128B_MASK 0x1
-#define AMD_FMT_MOD_DCC_MAX_COMPRESSED_BLOCK_SHIFT 18
-#define AMD_FMT_MOD_DCC_MAX_COMPRESSED_BLOCK_MASK 0x3
-
-/*
- * DCC supports embedding some clear colors directly in the DCC surface.
- * However, on older GPUs the rendering HW ignores the embedded clear color
- * and prefers the driver provided color. This necessitates doing a fastclear
- * eliminate operation before a process transfers control.
- *
- * If this bit is set that means the fastclear eliminate is not needed for these
- * embeddable colors.
- */
-#define AMD_FMT_MOD_DCC_CONSTANT_ENCODE_SHIFT 20
-#define AMD_FMT_MOD_DCC_CONSTANT_ENCODE_MASK 0x1
-
-/*
- * The below fields are for accounting for per GPU differences. These are only
- * relevant for GFX9 and later and if the tile field is *_X/_T.
- *
- * PIPE_XOR_BITS = always needed
- * BANK_XOR_BITS = only for TILE_VER_GFX9
- * PACKERS = only for TILE_VER_GFX10_RBPLUS
- * RB = only for TILE_VER_GFX9 & DCC
- * PIPE = only for TILE_VER_GFX9 & DCC & (DCC_RETILE | DCC_PIPE_ALIGN)
- */
-#define AMD_FMT_MOD_PIPE_XOR_BITS_SHIFT 21
-#define AMD_FMT_MOD_PIPE_XOR_BITS_MASK 0x7
-#define AMD_FMT_MOD_BANK_XOR_BITS_SHIFT 24
-#define AMD_FMT_MOD_BANK_XOR_BITS_MASK 0x7
-#define AMD_FMT_MOD_PACKERS_SHIFT 27
-#define AMD_FMT_MOD_PACKERS_MASK 0x7
-#define AMD_FMT_MOD_RB_SHIFT 30
-#define AMD_FMT_MOD_RB_MASK 0x7
-#define AMD_FMT_MOD_PIPE_SHIFT 33
-#define AMD_FMT_MOD_PIPE_MASK 0x7
-
-#define AMD_FMT_MOD_SET(field, value) \
- ((uint64_t)(value) << AMD_FMT_MOD_##field##_SHIFT)
-#define AMD_FMT_MOD_GET(field, value) \
- (((value) >> AMD_FMT_MOD_##field##_SHIFT) & AMD_FMT_MOD_##field##_MASK)
-#define AMD_FMT_MOD_CLEAR(field) \
- (~((uint64_t)AMD_FMT_MOD_##field##_MASK << AMD_FMT_MOD_##field##_SHIFT))
-
-#if defined(__cplusplus)
-}
-#endif
-
-#endif /* DRM_FOURCC_H */
+++ /dev/null
-/* SPDX-License-Identifier: ((GPL-2.0 WITH Linux-syscall-note) OR BSD-2-Clause) */
-/*
- * Copyright (c) 2012-2016 VMware, Inc. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of EITHER the GNU General Public License
- * version 2 as published by the Free Software Foundation or the BSD
- * 2-Clause License. This program is distributed in the hope that it
- * will be useful, but WITHOUT ANY WARRANTY; WITHOUT EVEN THE IMPLIED
- * WARRANTY OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE.
- * See the GNU General Public License version 2 for more details at
- * http://www.gnu.org/licenses/old-licenses/gpl-2.0.en.html.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program available in the file COPYING in the main
- * directory of this source tree.
- *
- * The BSD 2-Clause License
- *
- * Redistribution and use in source and binary forms, with or
- * without modification, are permitted provided that the following
- * conditions are met:
- *
- * - Redistributions of source code must retain the above
- * copyright notice, this list of conditions and the following
- * disclaimer.
- *
- * - Redistributions in binary form must reproduce the above
- * copyright notice, this list of conditions and the following
- * disclaimer in the documentation and/or other materials
- * provided with the distribution.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
- * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
- * COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
- * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
- * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
- * OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-
-#ifndef __VMW_PVRDMA_ABI_H__
-#define __VMW_PVRDMA_ABI_H__
-
-#include "standard-headers/linux/types.h"
-
-#define PVRDMA_UVERBS_ABI_VERSION 3 /* ABI Version. */
-#define PVRDMA_UAR_HANDLE_MASK 0x00FFFFFF /* Bottom 24 bits. */
-#define PVRDMA_UAR_QP_OFFSET 0 /* QP doorbell. */
-#define PVRDMA_UAR_QP_SEND (1 << 30) /* Send bit. */
-#define PVRDMA_UAR_QP_RECV (1 << 31) /* Recv bit. */
-#define PVRDMA_UAR_CQ_OFFSET 4 /* CQ doorbell. */
-#define PVRDMA_UAR_CQ_ARM_SOL (1 << 29) /* Arm solicited bit. */
-#define PVRDMA_UAR_CQ_ARM (1 << 30) /* Arm bit. */
-#define PVRDMA_UAR_CQ_POLL (1 << 31) /* Poll bit. */
-#define PVRDMA_UAR_SRQ_OFFSET 8 /* SRQ doorbell. */
-#define PVRDMA_UAR_SRQ_RECV (1 << 30) /* Recv bit. */
-
-enum pvrdma_wr_opcode {
- PVRDMA_WR_RDMA_WRITE,
- PVRDMA_WR_RDMA_WRITE_WITH_IMM,
- PVRDMA_WR_SEND,
- PVRDMA_WR_SEND_WITH_IMM,
- PVRDMA_WR_RDMA_READ,
- PVRDMA_WR_ATOMIC_CMP_AND_SWP,
- PVRDMA_WR_ATOMIC_FETCH_AND_ADD,
- PVRDMA_WR_LSO,
- PVRDMA_WR_SEND_WITH_INV,
- PVRDMA_WR_RDMA_READ_WITH_INV,
- PVRDMA_WR_LOCAL_INV,
- PVRDMA_WR_FAST_REG_MR,
- PVRDMA_WR_MASKED_ATOMIC_CMP_AND_SWP,
- PVRDMA_WR_MASKED_ATOMIC_FETCH_AND_ADD,
- PVRDMA_WR_BIND_MW,
- PVRDMA_WR_REG_SIG_MR,
- PVRDMA_WR_ERROR,
-};
-
-enum pvrdma_wc_status {
- PVRDMA_WC_SUCCESS,
- PVRDMA_WC_LOC_LEN_ERR,
- PVRDMA_WC_LOC_QP_OP_ERR,
- PVRDMA_WC_LOC_EEC_OP_ERR,
- PVRDMA_WC_LOC_PROT_ERR,
- PVRDMA_WC_WR_FLUSH_ERR,
- PVRDMA_WC_MW_BIND_ERR,
- PVRDMA_WC_BAD_RESP_ERR,
- PVRDMA_WC_LOC_ACCESS_ERR,
- PVRDMA_WC_REM_INV_REQ_ERR,
- PVRDMA_WC_REM_ACCESS_ERR,
- PVRDMA_WC_REM_OP_ERR,
- PVRDMA_WC_RETRY_EXC_ERR,
- PVRDMA_WC_RNR_RETRY_EXC_ERR,
- PVRDMA_WC_LOC_RDD_VIOL_ERR,
- PVRDMA_WC_REM_INV_RD_REQ_ERR,
- PVRDMA_WC_REM_ABORT_ERR,
- PVRDMA_WC_INV_EECN_ERR,
- PVRDMA_WC_INV_EEC_STATE_ERR,
- PVRDMA_WC_FATAL_ERR,
- PVRDMA_WC_RESP_TIMEOUT_ERR,
- PVRDMA_WC_GENERAL_ERR,
-};
-
-enum pvrdma_wc_opcode {
- PVRDMA_WC_SEND,
- PVRDMA_WC_RDMA_WRITE,
- PVRDMA_WC_RDMA_READ,
- PVRDMA_WC_COMP_SWAP,
- PVRDMA_WC_FETCH_ADD,
- PVRDMA_WC_BIND_MW,
- PVRDMA_WC_LSO,
- PVRDMA_WC_LOCAL_INV,
- PVRDMA_WC_FAST_REG_MR,
- PVRDMA_WC_MASKED_COMP_SWAP,
- PVRDMA_WC_MASKED_FETCH_ADD,
- PVRDMA_WC_RECV = 1 << 7,
- PVRDMA_WC_RECV_RDMA_WITH_IMM,
-};
-
-enum pvrdma_wc_flags {
- PVRDMA_WC_GRH = 1 << 0,
- PVRDMA_WC_WITH_IMM = 1 << 1,
- PVRDMA_WC_WITH_INVALIDATE = 1 << 2,
- PVRDMA_WC_IP_CSUM_OK = 1 << 3,
- PVRDMA_WC_WITH_SMAC = 1 << 4,
- PVRDMA_WC_WITH_VLAN = 1 << 5,
- PVRDMA_WC_WITH_NETWORK_HDR_TYPE = 1 << 6,
- PVRDMA_WC_FLAGS_MAX = PVRDMA_WC_WITH_NETWORK_HDR_TYPE,
-};
-
-struct pvrdma_alloc_ucontext_resp {
- uint32_t qp_tab_size;
- uint32_t reserved;
-};
-
-struct pvrdma_alloc_pd_resp {
- uint32_t pdn;
- uint32_t reserved;
-};
-
-struct pvrdma_create_cq {
- uint64_t __attribute__((aligned(8))) buf_addr;
- uint32_t buf_size;
- uint32_t reserved;
-};
-
-struct pvrdma_create_cq_resp {
- uint32_t cqn;
- uint32_t reserved;
-};
-
-struct pvrdma_resize_cq {
- uint64_t __attribute__((aligned(8))) buf_addr;
- uint32_t buf_size;
- uint32_t reserved;
-};
-
-struct pvrdma_create_srq {
- uint64_t __attribute__((aligned(8))) buf_addr;
- uint32_t buf_size;
- uint32_t reserved;
-};
-
-struct pvrdma_create_srq_resp {
- uint32_t srqn;
- uint32_t reserved;
-};
-
-struct pvrdma_create_qp {
- uint64_t __attribute__((aligned(8))) rbuf_addr;
- uint64_t __attribute__((aligned(8))) sbuf_addr;
- uint32_t rbuf_size;
- uint32_t sbuf_size;
- uint64_t __attribute__((aligned(8))) qp_addr;
-};
-
-struct pvrdma_create_qp_resp {
- uint32_t qpn;
- uint32_t qp_handle;
-};
-
-/* PVRDMA masked atomic compare and swap */
-struct pvrdma_ex_cmp_swap {
- uint64_t __attribute__((aligned(8))) swap_val;
- uint64_t __attribute__((aligned(8))) compare_val;
- uint64_t __attribute__((aligned(8))) swap_mask;
- uint64_t __attribute__((aligned(8))) compare_mask;
-};
-
-/* PVRDMA masked atomic fetch and add */
-struct pvrdma_ex_fetch_add {
- uint64_t __attribute__((aligned(8))) add_val;
- uint64_t __attribute__((aligned(8))) field_boundary;
-};
-
-/* PVRDMA address vector. */
-struct pvrdma_av {
- uint32_t port_pd;
- uint32_t sl_tclass_flowlabel;
- uint8_t dgid[16];
- uint8_t src_path_bits;
- uint8_t gid_index;
- uint8_t stat_rate;
- uint8_t hop_limit;
- uint8_t dmac[6];
- uint8_t reserved[6];
-};
-
-/* PVRDMA scatter/gather entry */
-struct pvrdma_sge {
- uint64_t __attribute__((aligned(8))) addr;
- uint32_t length;
- uint32_t lkey;
-};
-
-/* PVRDMA receive queue work request */
-struct pvrdma_rq_wqe_hdr {
- uint64_t __attribute__((aligned(8))) wr_id; /* wr id */
- uint32_t num_sge; /* size of s/g array */
- uint32_t total_len; /* reserved */
-};
-/* Use pvrdma_sge (ib_sge) for receive queue s/g array elements. */
-
-/* PVRDMA send queue work request */
-struct pvrdma_sq_wqe_hdr {
- uint64_t __attribute__((aligned(8))) wr_id; /* wr id */
- uint32_t num_sge; /* size of s/g array */
- uint32_t total_len; /* reserved */
- uint32_t opcode; /* operation type */
- uint32_t send_flags; /* wr flags */
- union {
- uint32_t imm_data;
- uint32_t invalidate_rkey;
- } ex;
- uint32_t reserved;
- union {
- struct {
- uint64_t __attribute__((aligned(8))) remote_addr;
- uint32_t rkey;
- uint8_t reserved[4];
- } rdma;
- struct {
- uint64_t __attribute__((aligned(8))) remote_addr;
- uint64_t __attribute__((aligned(8))) compare_add;
- uint64_t __attribute__((aligned(8))) swap;
- uint32_t rkey;
- uint32_t reserved;
- } atomic;
- struct {
- uint64_t __attribute__((aligned(8))) remote_addr;
- uint32_t log_arg_sz;
- uint32_t rkey;
- union {
- struct pvrdma_ex_cmp_swap cmp_swap;
- struct pvrdma_ex_fetch_add fetch_add;
- } wr_data;
- } masked_atomics;
- struct {
- uint64_t __attribute__((aligned(8))) iova_start;
- uint64_t __attribute__((aligned(8))) pl_pdir_dma;
- uint32_t page_shift;
- uint32_t page_list_len;
- uint32_t length;
- uint32_t access_flags;
- uint32_t rkey;
- uint32_t reserved;
- } fast_reg;
- struct {
- uint32_t remote_qpn;
- uint32_t remote_qkey;
- struct pvrdma_av av;
- } ud;
- } wr;
-};
-/* Use pvrdma_sge (ib_sge) for send queue s/g array elements. */
-
-/* Completion queue element. */
-struct pvrdma_cqe {
- uint64_t __attribute__((aligned(8))) wr_id;
- uint64_t __attribute__((aligned(8))) qp;
- uint32_t opcode;
- uint32_t status;
- uint32_t byte_len;
- uint32_t imm_data;
- uint32_t src_qp;
- uint32_t wc_flags;
- uint32_t vendor_err;
- uint16_t pkey_index;
- uint16_t slid;
- uint8_t sl;
- uint8_t dlid_path_bits;
- uint8_t port_num;
- uint8_t smac[6];
- uint8_t network_hdr_type;
- uint8_t reserved2[6]; /* Pad to next power of 2 (64). */
-};
-
-#endif /* __VMW_PVRDMA_ABI_H__ */
+++ /dev/null
-/*
- * Generic vector operation descriptor
- *
- * Copyright (c) 2018 Linaro
- *
- * This library is free software; you can redistribute it and/or
- * modify it under the terms of the GNU Lesser General Public
- * License as published by the Free Software Foundation; either
- * version 2.1 of the License, or (at your option) any later version.
- *
- * This library is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
- * Lesser General Public License for more details.
- *
- * You should have received a copy of the GNU Lesser General Public
- * License along with this library; if not, see <http://www.gnu.org/licenses/>.
- */
-
-#ifndef TCG_TCG_GVEC_DESC_H
-#define TCG_TCG_GVEC_DESC_H
-
-/*
- * This configuration allows MAXSZ to represent 2048 bytes, and
- * OPRSZ to match MAXSZ, or represent the smaller values 8, 16, or 32.
- *
- * Encode this with:
- * 0, 1, 3 -> 8, 16, 32
- * 2 -> maxsz
- *
- * This steals the input that would otherwise map to 24 to match maxsz.
- */
-#define SIMD_MAXSZ_SHIFT 0
-#define SIMD_MAXSZ_BITS 8
-
-#define SIMD_OPRSZ_SHIFT (SIMD_MAXSZ_SHIFT + SIMD_MAXSZ_BITS)
-#define SIMD_OPRSZ_BITS 2
-
-#define SIMD_DATA_SHIFT (SIMD_OPRSZ_SHIFT + SIMD_OPRSZ_BITS)
-#define SIMD_DATA_BITS (32 - SIMD_DATA_SHIFT)
-
-/* Create a descriptor from components. */
-uint32_t simd_desc(uint32_t oprsz, uint32_t maxsz, int32_t data);
-
-/* Extract the max vector size from a descriptor. */
-static inline intptr_t simd_maxsz(uint32_t desc)
-{
- return extract32(desc, SIMD_MAXSZ_SHIFT, SIMD_MAXSZ_BITS) * 8 + 8;
-}
-
-/* Extract the operation size from a descriptor. */
-static inline intptr_t simd_oprsz(uint32_t desc)
-{
- uint32_t f = extract32(desc, SIMD_OPRSZ_SHIFT, SIMD_OPRSZ_BITS);
- intptr_t o = f * 8 + 8;
- intptr_t m = simd_maxsz(desc);
- return f == 2 ? m : o;
-}
-
-/* Extract the operation-specific data from a descriptor. */
-static inline int32_t simd_data(uint32_t desc)
-{
- return sextract32(desc, SIMD_DATA_SHIFT, SIMD_DATA_BITS);
-}
-
-#endif
+++ /dev/null
-/*
- * Tiny Code Generator for QEMU
- *
- * Copyright (c) 2008 Fabrice Bellard
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
- * furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
- * THE SOFTWARE.
- */
-
-#ifndef TCG_MO_H
-#define TCG_MO_H
-
-typedef enum {
- /* Used to indicate the type of accesses on which ordering
- is to be ensured. Modeled after SPARC barriers.
-
- This is of the form TCG_MO_A_B where A is before B in program order.
- */
- TCG_MO_LD_LD = 0x01,
- TCG_MO_ST_LD = 0x02,
- TCG_MO_LD_ST = 0x04,
- TCG_MO_ST_ST = 0x08,
- TCG_MO_ALL = 0x0F, /* OR of the above */
-
- /* Used to indicate the kind of ordering which is to be ensured by the
- instruction. These types are derived from x86/aarch64 instructions.
- It should be noted that these are different from C11 semantics. */
- TCG_BAR_LDAQ = 0x10, /* Following ops will not come forward */
- TCG_BAR_STRL = 0x20, /* Previous ops will not be delayed */
- TCG_BAR_SC = 0x30, /* No ops cross barrier; OR of the above */
-} TCGBar;
-
-#endif /* TCG_MO_H */
+++ /dev/null
-/*
- * Generic vector operation expansion
- *
- * Copyright (c) 2018 Linaro
- *
- * This library is free software; you can redistribute it and/or
- * modify it under the terms of the GNU Lesser General Public
- * License as published by the Free Software Foundation; either
- * version 2.1 of the License, or (at your option) any later version.
- *
- * This library is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
- * Lesser General Public License for more details.
- *
- * You should have received a copy of the GNU Lesser General Public
- * License along with this library; if not, see <http://www.gnu.org/licenses/>.
- */
-
-#ifndef TCG_TCG_OP_GVEC_H
-#define TCG_TCG_OP_GVEC_H
-
-/*
- * "Generic" vectors. All operands are given as offsets from ENV,
- * and therefore cannot also be allocated via tcg_global_mem_new_*.
- * OPRSZ is the byte size of the vector upon which the operation is performed.
- * MAXSZ is the byte size of the full vector; bytes beyond OPSZ are cleared.
- *
- * All sizes must be 8 or any multiple of 16.
- * When OPRSZ is 8, the alignment may be 8, otherwise must be 16.
- * Operands may completely, but not partially, overlap.
- */
-
-/* Expand a call to a gvec-style helper, with pointers to two vector
- operands, and a descriptor (see tcg-gvec-desc.h). */
-typedef void gen_helper_gvec_2(TCGv_ptr, TCGv_ptr, TCGv_i32);
-void tcg_gen_gvec_2_ool(uint32_t dofs, uint32_t aofs,
- uint32_t oprsz, uint32_t maxsz, int32_t data,
- gen_helper_gvec_2 *fn);
-
-/* Similarly, passing an extra data value. */
-typedef void gen_helper_gvec_2i(TCGv_ptr, TCGv_ptr, TCGv_i64, TCGv_i32);
-void tcg_gen_gvec_2i_ool(uint32_t dofs, uint32_t aofs, TCGv_i64 c,
- uint32_t oprsz, uint32_t maxsz, int32_t data,
- gen_helper_gvec_2i *fn);
-
-/* Similarly, passing an extra pointer (e.g. env or float_status). */
-typedef void gen_helper_gvec_2_ptr(TCGv_ptr, TCGv_ptr, TCGv_ptr, TCGv_i32);
-void tcg_gen_gvec_2_ptr(uint32_t dofs, uint32_t aofs,
- TCGv_ptr ptr, uint32_t oprsz, uint32_t maxsz,
- int32_t data, gen_helper_gvec_2_ptr *fn);
-
-/* Similarly, with three vector operands. */
-typedef void gen_helper_gvec_3(TCGv_ptr, TCGv_ptr, TCGv_ptr, TCGv_i32);
-void tcg_gen_gvec_3_ool(uint32_t dofs, uint32_t aofs, uint32_t bofs,
- uint32_t oprsz, uint32_t maxsz, int32_t data,
- gen_helper_gvec_3 *fn);
-
-/* Similarly, with four vector operands. */
-typedef void gen_helper_gvec_4(TCGv_ptr, TCGv_ptr, TCGv_ptr,
- TCGv_ptr, TCGv_i32);
-void tcg_gen_gvec_4_ool(uint32_t dofs, uint32_t aofs, uint32_t bofs,
- uint32_t cofs, uint32_t oprsz, uint32_t maxsz,
- int32_t data, gen_helper_gvec_4 *fn);
-
-/* Similarly, with five vector operands. */
-typedef void gen_helper_gvec_5(TCGv_ptr, TCGv_ptr, TCGv_ptr, TCGv_ptr,
- TCGv_ptr, TCGv_i32);
-void tcg_gen_gvec_5_ool(uint32_t dofs, uint32_t aofs, uint32_t bofs,
- uint32_t cofs, uint32_t xofs, uint32_t oprsz,
- uint32_t maxsz, int32_t data, gen_helper_gvec_5 *fn);
-
-typedef void gen_helper_gvec_3_ptr(TCGv_ptr, TCGv_ptr, TCGv_ptr,
- TCGv_ptr, TCGv_i32);
-void tcg_gen_gvec_3_ptr(uint32_t dofs, uint32_t aofs, uint32_t bofs,
- TCGv_ptr ptr, uint32_t oprsz, uint32_t maxsz,
- int32_t data, gen_helper_gvec_3_ptr *fn);
-
-typedef void gen_helper_gvec_4_ptr(TCGv_ptr, TCGv_ptr, TCGv_ptr,
- TCGv_ptr, TCGv_ptr, TCGv_i32);
-void tcg_gen_gvec_4_ptr(uint32_t dofs, uint32_t aofs, uint32_t bofs,
- uint32_t cofs, TCGv_ptr ptr, uint32_t oprsz,
- uint32_t maxsz, int32_t data,
- gen_helper_gvec_4_ptr *fn);
-
-typedef void gen_helper_gvec_5_ptr(TCGv_ptr, TCGv_ptr, TCGv_ptr, TCGv_ptr,
- TCGv_ptr, TCGv_ptr, TCGv_i32);
-void tcg_gen_gvec_5_ptr(uint32_t dofs, uint32_t aofs, uint32_t bofs,
- uint32_t cofs, uint32_t eofs, TCGv_ptr ptr,
- uint32_t oprsz, uint32_t maxsz, int32_t data,
- gen_helper_gvec_5_ptr *fn);
-
-/* Expand a gvec operation. Either inline or out-of-line depending on
- the actual vector size and the operations supported by the host. */
-typedef struct {
- /* Expand inline as a 64-bit or 32-bit integer.
- Only one of these will be non-NULL. */
- void (*fni8)(TCGv_i64, TCGv_i64);
- void (*fni4)(TCGv_i32, TCGv_i32);
- /* Expand inline with a host vector type. */
- void (*fniv)(unsigned, TCGv_vec, TCGv_vec);
- /* Expand out-of-line helper w/descriptor. */
- gen_helper_gvec_2 *fno;
- /* The optional opcodes, if any, utilized by .fniv. */
- const TCGOpcode *opt_opc;
- /* The data argument to the out-of-line helper. */
- int32_t data;
- /* The vector element size, if applicable. */
- uint8_t vece;
- /* Prefer i64 to v64. */
- bool prefer_i64;
- /* Load dest as a 2nd source operand. */
- bool load_dest;
-} GVecGen2;
-
-typedef struct {
- /* Expand inline as a 64-bit or 32-bit integer.
- Only one of these will be non-NULL. */
- void (*fni8)(TCGv_i64, TCGv_i64, int64_t);
- void (*fni4)(TCGv_i32, TCGv_i32, int32_t);
- /* Expand inline with a host vector type. */
- void (*fniv)(unsigned, TCGv_vec, TCGv_vec, int64_t);
- /* Expand out-of-line helper w/descriptor, data in descriptor. */
- gen_helper_gvec_2 *fno;
- /* Expand out-of-line helper w/descriptor, data as argument. */
- gen_helper_gvec_2i *fnoi;
- /* The optional opcodes, if any, utilized by .fniv. */
- const TCGOpcode *opt_opc;
- /* The vector element size, if applicable. */
- uint8_t vece;
- /* Prefer i64 to v64. */
- bool prefer_i64;
- /* Load dest as a 3rd source operand. */
- bool load_dest;
-} GVecGen2i;
-
-typedef struct {
- /* Expand inline as a 64-bit or 32-bit integer.
- Only one of these will be non-NULL. */
- void (*fni8)(TCGv_i64, TCGv_i64, TCGv_i64);
- void (*fni4)(TCGv_i32, TCGv_i32, TCGv_i32);
- /* Expand inline with a host vector type. */
- void (*fniv)(unsigned, TCGv_vec, TCGv_vec, TCGv_vec);
- /* Expand out-of-line helper w/descriptor. */
- gen_helper_gvec_2i *fno;
- /* The optional opcodes, if any, utilized by .fniv. */
- const TCGOpcode *opt_opc;
- /* The data argument to the out-of-line helper. */
- uint32_t data;
- /* The vector element size, if applicable. */
- uint8_t vece;
- /* Prefer i64 to v64. */
- bool prefer_i64;
- /* Load scalar as 1st source operand. */
- bool scalar_first;
-} GVecGen2s;
-
-typedef struct {
- /* Expand inline as a 64-bit or 32-bit integer.
- Only one of these will be non-NULL. */
- void (*fni8)(TCGv_i64, TCGv_i64, TCGv_i64);
- void (*fni4)(TCGv_i32, TCGv_i32, TCGv_i32);
- /* Expand inline with a host vector type. */
- void (*fniv)(unsigned, TCGv_vec, TCGv_vec, TCGv_vec);
- /* Expand out-of-line helper w/descriptor. */
- gen_helper_gvec_3 *fno;
- /* The optional opcodes, if any, utilized by .fniv. */
- const TCGOpcode *opt_opc;
- /* The data argument to the out-of-line helper. */
- int32_t data;
- /* The vector element size, if applicable. */
- uint8_t vece;
- /* Prefer i64 to v64. */
- bool prefer_i64;
- /* Load dest as a 3rd source operand. */
- bool load_dest;
-} GVecGen3;
-
-typedef struct {
- /*
- * Expand inline as a 64-bit or 32-bit integer. Only one of these will be
- * non-NULL.
- */
- void (*fni8)(TCGv_i64, TCGv_i64, TCGv_i64, int64_t);
- void (*fni4)(TCGv_i32, TCGv_i32, TCGv_i32, int32_t);
- /* Expand inline with a host vector type. */
- void (*fniv)(unsigned, TCGv_vec, TCGv_vec, TCGv_vec, int64_t);
- /* Expand out-of-line helper w/descriptor, data in descriptor. */
- gen_helper_gvec_3 *fno;
- /* The optional opcodes, if any, utilized by .fniv. */
- const TCGOpcode *opt_opc;
- /* The vector element size, if applicable. */
- uint8_t vece;
- /* Prefer i64 to v64. */
- bool prefer_i64;
- /* Load dest as a 3rd source operand. */
- bool load_dest;
-} GVecGen3i;
-
-typedef struct {
- /* Expand inline as a 64-bit or 32-bit integer.
- Only one of these will be non-NULL. */
- void (*fni8)(TCGv_i64, TCGv_i64, TCGv_i64, TCGv_i64);
- void (*fni4)(TCGv_i32, TCGv_i32, TCGv_i32, TCGv_i32);
- /* Expand inline with a host vector type. */
- void (*fniv)(unsigned, TCGv_vec, TCGv_vec, TCGv_vec, TCGv_vec);
- /* Expand out-of-line helper w/descriptor. */
- gen_helper_gvec_4 *fno;
- /* The optional opcodes, if any, utilized by .fniv. */
- const TCGOpcode *opt_opc;
- /* The data argument to the out-of-line helper. */
- int32_t data;
- /* The vector element size, if applicable. */
- uint8_t vece;
- /* Prefer i64 to v64. */
- bool prefer_i64;
- /* Write aofs as a 2nd dest operand. */
- bool write_aofs;
-} GVecGen4;
-
-void tcg_gen_gvec_2(uint32_t dofs, uint32_t aofs,
- uint32_t oprsz, uint32_t maxsz, const GVecGen2 *);
-void tcg_gen_gvec_2i(uint32_t dofs, uint32_t aofs, uint32_t oprsz,
- uint32_t maxsz, int64_t c, const GVecGen2i *);
-void tcg_gen_gvec_2s(uint32_t dofs, uint32_t aofs, uint32_t oprsz,
- uint32_t maxsz, TCGv_i64 c, const GVecGen2s *);
-void tcg_gen_gvec_3(uint32_t dofs, uint32_t aofs, uint32_t bofs,
- uint32_t oprsz, uint32_t maxsz, const GVecGen3 *);
-void tcg_gen_gvec_3i(uint32_t dofs, uint32_t aofs, uint32_t bofs,
- uint32_t oprsz, uint32_t maxsz, int64_t c,
- const GVecGen3i *);
-void tcg_gen_gvec_4(uint32_t dofs, uint32_t aofs, uint32_t bofs, uint32_t cofs,
- uint32_t oprsz, uint32_t maxsz, const GVecGen4 *);
-
-/* Expand a specific vector operation. */
-
-void tcg_gen_gvec_mov(unsigned vece, uint32_t dofs, uint32_t aofs,
- uint32_t oprsz, uint32_t maxsz);
-void tcg_gen_gvec_not(unsigned vece, uint32_t dofs, uint32_t aofs,
- uint32_t oprsz, uint32_t maxsz);
-void tcg_gen_gvec_neg(unsigned vece, uint32_t dofs, uint32_t aofs,
- uint32_t oprsz, uint32_t maxsz);
-void tcg_gen_gvec_abs(unsigned vece, uint32_t dofs, uint32_t aofs,
- uint32_t oprsz, uint32_t maxsz);
-
-void tcg_gen_gvec_add(unsigned vece, uint32_t dofs, uint32_t aofs,
- uint32_t bofs, uint32_t oprsz, uint32_t maxsz);
-void tcg_gen_gvec_sub(unsigned vece, uint32_t dofs, uint32_t aofs,
- uint32_t bofs, uint32_t oprsz, uint32_t maxsz);
-void tcg_gen_gvec_mul(unsigned vece, uint32_t dofs, uint32_t aofs,
- uint32_t bofs, uint32_t oprsz, uint32_t maxsz);
-
-void tcg_gen_gvec_addi(unsigned vece, uint32_t dofs, uint32_t aofs,
- int64_t c, uint32_t oprsz, uint32_t maxsz);
-void tcg_gen_gvec_muli(unsigned vece, uint32_t dofs, uint32_t aofs,
- int64_t c, uint32_t oprsz, uint32_t maxsz);
-
-void tcg_gen_gvec_adds(unsigned vece, uint32_t dofs, uint32_t aofs,
- TCGv_i64 c, uint32_t oprsz, uint32_t maxsz);
-void tcg_gen_gvec_subs(unsigned vece, uint32_t dofs, uint32_t aofs,
- TCGv_i64 c, uint32_t oprsz, uint32_t maxsz);
-void tcg_gen_gvec_muls(unsigned vece, uint32_t dofs, uint32_t aofs,
- TCGv_i64 c, uint32_t oprsz, uint32_t maxsz);
-
-/* Saturated arithmetic. */
-void tcg_gen_gvec_ssadd(unsigned vece, uint32_t dofs, uint32_t aofs,
- uint32_t bofs, uint32_t oprsz, uint32_t maxsz);
-void tcg_gen_gvec_sssub(unsigned vece, uint32_t dofs, uint32_t aofs,
- uint32_t bofs, uint32_t oprsz, uint32_t maxsz);
-void tcg_gen_gvec_usadd(unsigned vece, uint32_t dofs, uint32_t aofs,
- uint32_t bofs, uint32_t oprsz, uint32_t maxsz);
-void tcg_gen_gvec_ussub(unsigned vece, uint32_t dofs, uint32_t aofs,
- uint32_t bofs, uint32_t oprsz, uint32_t maxsz);
-
-/* Min/max. */
-void tcg_gen_gvec_smin(unsigned vece, uint32_t dofs, uint32_t aofs,
- uint32_t bofs, uint32_t oprsz, uint32_t maxsz);
-void tcg_gen_gvec_umin(unsigned vece, uint32_t dofs, uint32_t aofs,
- uint32_t bofs, uint32_t oprsz, uint32_t maxsz);
-void tcg_gen_gvec_smax(unsigned vece, uint32_t dofs, uint32_t aofs,
- uint32_t bofs, uint32_t oprsz, uint32_t maxsz);
-void tcg_gen_gvec_umax(unsigned vece, uint32_t dofs, uint32_t aofs,
- uint32_t bofs, uint32_t oprsz, uint32_t maxsz);
-
-void tcg_gen_gvec_and(unsigned vece, uint32_t dofs, uint32_t aofs,
- uint32_t bofs, uint32_t oprsz, uint32_t maxsz);
-void tcg_gen_gvec_or(unsigned vece, uint32_t dofs, uint32_t aofs,
- uint32_t bofs, uint32_t oprsz, uint32_t maxsz);
-void tcg_gen_gvec_xor(unsigned vece, uint32_t dofs, uint32_t aofs,
- uint32_t bofs, uint32_t oprsz, uint32_t maxsz);
-void tcg_gen_gvec_andc(unsigned vece, uint32_t dofs, uint32_t aofs,
- uint32_t bofs, uint32_t oprsz, uint32_t maxsz);
-void tcg_gen_gvec_orc(unsigned vece, uint32_t dofs, uint32_t aofs,
- uint32_t bofs, uint32_t oprsz, uint32_t maxsz);
-void tcg_gen_gvec_nand(unsigned vece, uint32_t dofs, uint32_t aofs,
- uint32_t bofs, uint32_t oprsz, uint32_t maxsz);
-void tcg_gen_gvec_nor(unsigned vece, uint32_t dofs, uint32_t aofs,
- uint32_t bofs, uint32_t oprsz, uint32_t maxsz);
-void tcg_gen_gvec_eqv(unsigned vece, uint32_t dofs, uint32_t aofs,
- uint32_t bofs, uint32_t oprsz, uint32_t maxsz);
-
-void tcg_gen_gvec_andi(unsigned vece, uint32_t dofs, uint32_t aofs,
- int64_t c, uint32_t oprsz, uint32_t maxsz);
-void tcg_gen_gvec_xori(unsigned vece, uint32_t dofs, uint32_t aofs,
- int64_t c, uint32_t oprsz, uint32_t maxsz);
-void tcg_gen_gvec_ori(unsigned vece, uint32_t dofs, uint32_t aofs,
- int64_t c, uint32_t oprsz, uint32_t maxsz);
-
-void tcg_gen_gvec_ands(unsigned vece, uint32_t dofs, uint32_t aofs,
- TCGv_i64 c, uint32_t oprsz, uint32_t maxsz);
-void tcg_gen_gvec_xors(unsigned vece, uint32_t dofs, uint32_t aofs,
- TCGv_i64 c, uint32_t oprsz, uint32_t maxsz);
-void tcg_gen_gvec_ors(unsigned vece, uint32_t dofs, uint32_t aofs,
- TCGv_i64 c, uint32_t oprsz, uint32_t maxsz);
-
-void tcg_gen_gvec_dup_mem(unsigned vece, uint32_t dofs, uint32_t aofs,
- uint32_t s, uint32_t m);
-void tcg_gen_gvec_dup_imm(unsigned vece, uint32_t dofs, uint32_t s,
- uint32_t m, uint64_t imm);
-void tcg_gen_gvec_dup_i32(unsigned vece, uint32_t dofs, uint32_t s,
- uint32_t m, TCGv_i32);
-void tcg_gen_gvec_dup_i64(unsigned vece, uint32_t dofs, uint32_t s,
- uint32_t m, TCGv_i64);
-
-#if TARGET_LONG_BITS == 64
-# define tcg_gen_gvec_dup_tl tcg_gen_gvec_dup_i64
-#else
-# define tcg_gen_gvec_dup_tl tcg_gen_gvec_dup_i32
-#endif
-
-void tcg_gen_gvec_shli(unsigned vece, uint32_t dofs, uint32_t aofs,
- int64_t shift, uint32_t oprsz, uint32_t maxsz);
-void tcg_gen_gvec_shri(unsigned vece, uint32_t dofs, uint32_t aofs,
- int64_t shift, uint32_t oprsz, uint32_t maxsz);
-void tcg_gen_gvec_sari(unsigned vece, uint32_t dofs, uint32_t aofs,
- int64_t shift, uint32_t oprsz, uint32_t maxsz);
-void tcg_gen_gvec_rotli(unsigned vece, uint32_t dofs, uint32_t aofs,
- int64_t shift, uint32_t oprsz, uint32_t maxsz);
-void tcg_gen_gvec_rotri(unsigned vece, uint32_t dofs, uint32_t aofs,
- int64_t shift, uint32_t oprsz, uint32_t maxsz);
-
-void tcg_gen_gvec_shls(unsigned vece, uint32_t dofs, uint32_t aofs,
- TCGv_i32 shift, uint32_t oprsz, uint32_t maxsz);
-void tcg_gen_gvec_shrs(unsigned vece, uint32_t dofs, uint32_t aofs,
- TCGv_i32 shift, uint32_t oprsz, uint32_t maxsz);
-void tcg_gen_gvec_sars(unsigned vece, uint32_t dofs, uint32_t aofs,
- TCGv_i32 shift, uint32_t oprsz, uint32_t maxsz);
-void tcg_gen_gvec_rotls(unsigned vece, uint32_t dofs, uint32_t aofs,
- TCGv_i32 shift, uint32_t oprsz, uint32_t maxsz);
-
-/*
- * Perform vector shift by vector element, modulo the element size.
- * E.g. D[i] = A[i] << (B[i] % (8 << vece)).
- */
-void tcg_gen_gvec_shlv(unsigned vece, uint32_t dofs, uint32_t aofs,
- uint32_t bofs, uint32_t oprsz, uint32_t maxsz);
-void tcg_gen_gvec_shrv(unsigned vece, uint32_t dofs, uint32_t aofs,
- uint32_t bofs, uint32_t oprsz, uint32_t maxsz);
-void tcg_gen_gvec_sarv(unsigned vece, uint32_t dofs, uint32_t aofs,
- uint32_t bofs, uint32_t oprsz, uint32_t maxsz);
-void tcg_gen_gvec_rotlv(unsigned vece, uint32_t dofs, uint32_t aofs,
- uint32_t bofs, uint32_t oprsz, uint32_t maxsz);
-void tcg_gen_gvec_rotrv(unsigned vece, uint32_t dofs, uint32_t aofs,
- uint32_t bofs, uint32_t oprsz, uint32_t maxsz);
-
-void tcg_gen_gvec_cmp(TCGCond cond, unsigned vece, uint32_t dofs,
- uint32_t aofs, uint32_t bofs,
- uint32_t oprsz, uint32_t maxsz);
-
-/*
- * Perform vector bit select: d = (b & a) | (c & ~a).
- */
-void tcg_gen_gvec_bitsel(unsigned vece, uint32_t dofs, uint32_t aofs,
- uint32_t bofs, uint32_t cofs,
- uint32_t oprsz, uint32_t maxsz);
-
-/*
- * 64-bit vector operations. Use these when the register has been allocated
- * with tcg_global_mem_new_i64, and so we cannot also address it via pointer.
- * OPRSZ = MAXSZ = 8.
- */
-
-void tcg_gen_vec_neg8_i64(TCGv_i64 d, TCGv_i64 a);
-void tcg_gen_vec_neg16_i64(TCGv_i64 d, TCGv_i64 a);
-void tcg_gen_vec_neg32_i64(TCGv_i64 d, TCGv_i64 a);
-
-void tcg_gen_vec_add8_i64(TCGv_i64 d, TCGv_i64 a, TCGv_i64 b);
-void tcg_gen_vec_add16_i64(TCGv_i64 d, TCGv_i64 a, TCGv_i64 b);
-void tcg_gen_vec_add32_i64(TCGv_i64 d, TCGv_i64 a, TCGv_i64 b);
-
-void tcg_gen_vec_sub8_i64(TCGv_i64 d, TCGv_i64 a, TCGv_i64 b);
-void tcg_gen_vec_sub16_i64(TCGv_i64 d, TCGv_i64 a, TCGv_i64 b);
-void tcg_gen_vec_sub32_i64(TCGv_i64 d, TCGv_i64 a, TCGv_i64 b);
-
-void tcg_gen_vec_shl8i_i64(TCGv_i64 d, TCGv_i64 a, int64_t);
-void tcg_gen_vec_shl16i_i64(TCGv_i64 d, TCGv_i64 a, int64_t);
-void tcg_gen_vec_shr8i_i64(TCGv_i64 d, TCGv_i64 a, int64_t);
-void tcg_gen_vec_shr16i_i64(TCGv_i64 d, TCGv_i64 a, int64_t);
-void tcg_gen_vec_sar8i_i64(TCGv_i64 d, TCGv_i64 a, int64_t);
-void tcg_gen_vec_sar16i_i64(TCGv_i64 d, TCGv_i64 a, int64_t);
-void tcg_gen_vec_rotl8i_i64(TCGv_i64 d, TCGv_i64 a, int64_t c);
-void tcg_gen_vec_rotl16i_i64(TCGv_i64 d, TCGv_i64 a, int64_t c);
-
-#endif
+++ /dev/null
-/*
- * Tiny Code Generator for QEMU
- *
- * Copyright (c) 2008 Fabrice Bellard
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
- * furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
- * THE SOFTWARE.
- */
-
-#ifndef TCG_TCG_OP_H
-#define TCG_TCG_OP_H
-
-#include "tcg/tcg.h"
-#include "exec/helper-proto.h"
-#include "exec/helper-gen.h"
-
-/* Basic output routines. Not for general consumption. */
-
-void tcg_gen_op1(TCGOpcode, TCGArg);
-void tcg_gen_op2(TCGOpcode, TCGArg, TCGArg);
-void tcg_gen_op3(TCGOpcode, TCGArg, TCGArg, TCGArg);
-void tcg_gen_op4(TCGOpcode, TCGArg, TCGArg, TCGArg, TCGArg);
-void tcg_gen_op5(TCGOpcode, TCGArg, TCGArg, TCGArg, TCGArg, TCGArg);
-void tcg_gen_op6(TCGOpcode, TCGArg, TCGArg, TCGArg, TCGArg, TCGArg, TCGArg);
-
-void vec_gen_2(TCGOpcode, TCGType, unsigned, TCGArg, TCGArg);
-void vec_gen_3(TCGOpcode, TCGType, unsigned, TCGArg, TCGArg, TCGArg);
-void vec_gen_4(TCGOpcode, TCGType, unsigned, TCGArg, TCGArg, TCGArg, TCGArg);
-
-static inline void tcg_gen_op1_i32(TCGOpcode opc, TCGv_i32 a1)
-{
- tcg_gen_op1(opc, tcgv_i32_arg(a1));
-}
-
-static inline void tcg_gen_op1_i64(TCGOpcode opc, TCGv_i64 a1)
-{
- tcg_gen_op1(opc, tcgv_i64_arg(a1));
-}
-
-static inline void tcg_gen_op1i(TCGOpcode opc, TCGArg a1)
-{
- tcg_gen_op1(opc, a1);
-}
-
-static inline void tcg_gen_op2_i32(TCGOpcode opc, TCGv_i32 a1, TCGv_i32 a2)
-{
- tcg_gen_op2(opc, tcgv_i32_arg(a1), tcgv_i32_arg(a2));
-}
-
-static inline void tcg_gen_op2_i64(TCGOpcode opc, TCGv_i64 a1, TCGv_i64 a2)
-{
- tcg_gen_op2(opc, tcgv_i64_arg(a1), tcgv_i64_arg(a2));
-}
-
-static inline void tcg_gen_op2i_i32(TCGOpcode opc, TCGv_i32 a1, TCGArg a2)
-{
- tcg_gen_op2(opc, tcgv_i32_arg(a1), a2);
-}
-
-static inline void tcg_gen_op2i_i64(TCGOpcode opc, TCGv_i64 a1, TCGArg a2)
-{
- tcg_gen_op2(opc, tcgv_i64_arg(a1), a2);
-}
-
-static inline void tcg_gen_op2ii(TCGOpcode opc, TCGArg a1, TCGArg a2)
-{
- tcg_gen_op2(opc, a1, a2);
-}
-
-static inline void tcg_gen_op3_i32(TCGOpcode opc, TCGv_i32 a1,
- TCGv_i32 a2, TCGv_i32 a3)
-{
- tcg_gen_op3(opc, tcgv_i32_arg(a1), tcgv_i32_arg(a2), tcgv_i32_arg(a3));
-}
-
-static inline void tcg_gen_op3_i64(TCGOpcode opc, TCGv_i64 a1,
- TCGv_i64 a2, TCGv_i64 a3)
-{
- tcg_gen_op3(opc, tcgv_i64_arg(a1), tcgv_i64_arg(a2), tcgv_i64_arg(a3));
-}
-
-static inline void tcg_gen_op3i_i32(TCGOpcode opc, TCGv_i32 a1,
- TCGv_i32 a2, TCGArg a3)
-{
- tcg_gen_op3(opc, tcgv_i32_arg(a1), tcgv_i32_arg(a2), a3);
-}
-
-static inline void tcg_gen_op3i_i64(TCGOpcode opc, TCGv_i64 a1,
- TCGv_i64 a2, TCGArg a3)
-{
- tcg_gen_op3(opc, tcgv_i64_arg(a1), tcgv_i64_arg(a2), a3);
-}
-
-static inline void tcg_gen_ldst_op_i32(TCGOpcode opc, TCGv_i32 val,
- TCGv_ptr base, TCGArg offset)
-{
- tcg_gen_op3(opc, tcgv_i32_arg(val), tcgv_ptr_arg(base), offset);
-}
-
-static inline void tcg_gen_ldst_op_i64(TCGOpcode opc, TCGv_i64 val,
- TCGv_ptr base, TCGArg offset)
-{
- tcg_gen_op3(opc, tcgv_i64_arg(val), tcgv_ptr_arg(base), offset);
-}
-
-static inline void tcg_gen_op4_i32(TCGOpcode opc, TCGv_i32 a1, TCGv_i32 a2,
- TCGv_i32 a3, TCGv_i32 a4)
-{
- tcg_gen_op4(opc, tcgv_i32_arg(a1), tcgv_i32_arg(a2),
- tcgv_i32_arg(a3), tcgv_i32_arg(a4));
-}
-
-static inline void tcg_gen_op4_i64(TCGOpcode opc, TCGv_i64 a1, TCGv_i64 a2,
- TCGv_i64 a3, TCGv_i64 a4)
-{
- tcg_gen_op4(opc, tcgv_i64_arg(a1), tcgv_i64_arg(a2),
- tcgv_i64_arg(a3), tcgv_i64_arg(a4));
-}
-
-static inline void tcg_gen_op4i_i32(TCGOpcode opc, TCGv_i32 a1, TCGv_i32 a2,
- TCGv_i32 a3, TCGArg a4)
-{
- tcg_gen_op4(opc, tcgv_i32_arg(a1), tcgv_i32_arg(a2),
- tcgv_i32_arg(a3), a4);
-}
-
-static inline void tcg_gen_op4i_i64(TCGOpcode opc, TCGv_i64 a1, TCGv_i64 a2,
- TCGv_i64 a3, TCGArg a4)
-{
- tcg_gen_op4(opc, tcgv_i64_arg(a1), tcgv_i64_arg(a2),
- tcgv_i64_arg(a3), a4);
-}
-
-static inline void tcg_gen_op4ii_i32(TCGOpcode opc, TCGv_i32 a1, TCGv_i32 a2,
- TCGArg a3, TCGArg a4)
-{
- tcg_gen_op4(opc, tcgv_i32_arg(a1), tcgv_i32_arg(a2), a3, a4);
-}
-
-static inline void tcg_gen_op4ii_i64(TCGOpcode opc, TCGv_i64 a1, TCGv_i64 a2,
- TCGArg a3, TCGArg a4)
-{
- tcg_gen_op4(opc, tcgv_i64_arg(a1), tcgv_i64_arg(a2), a3, a4);
-}
-
-static inline void tcg_gen_op5_i32(TCGOpcode opc, TCGv_i32 a1, TCGv_i32 a2,
- TCGv_i32 a3, TCGv_i32 a4, TCGv_i32 a5)
-{
- tcg_gen_op5(opc, tcgv_i32_arg(a1), tcgv_i32_arg(a2),
- tcgv_i32_arg(a3), tcgv_i32_arg(a4), tcgv_i32_arg(a5));
-}
-
-static inline void tcg_gen_op5_i64(TCGOpcode opc, TCGv_i64 a1, TCGv_i64 a2,
- TCGv_i64 a3, TCGv_i64 a4, TCGv_i64 a5)
-{
- tcg_gen_op5(opc, tcgv_i64_arg(a1), tcgv_i64_arg(a2),
- tcgv_i64_arg(a3), tcgv_i64_arg(a4), tcgv_i64_arg(a5));
-}
-
-static inline void tcg_gen_op5i_i32(TCGOpcode opc, TCGv_i32 a1, TCGv_i32 a2,
- TCGv_i32 a3, TCGv_i32 a4, TCGArg a5)
-{
- tcg_gen_op5(opc, tcgv_i32_arg(a1), tcgv_i32_arg(a2),
- tcgv_i32_arg(a3), tcgv_i32_arg(a4), a5);
-}
-
-static inline void tcg_gen_op5i_i64(TCGOpcode opc, TCGv_i64 a1, TCGv_i64 a2,
- TCGv_i64 a3, TCGv_i64 a4, TCGArg a5)
-{
- tcg_gen_op5(opc, tcgv_i64_arg(a1), tcgv_i64_arg(a2),
- tcgv_i64_arg(a3), tcgv_i64_arg(a4), a5);
-}
-
-static inline void tcg_gen_op5ii_i32(TCGOpcode opc, TCGv_i32 a1, TCGv_i32 a2,
- TCGv_i32 a3, TCGArg a4, TCGArg a5)
-{
- tcg_gen_op5(opc, tcgv_i32_arg(a1), tcgv_i32_arg(a2),
- tcgv_i32_arg(a3), a4, a5);
-}
-
-static inline void tcg_gen_op5ii_i64(TCGOpcode opc, TCGv_i64 a1, TCGv_i64 a2,
- TCGv_i64 a3, TCGArg a4, TCGArg a5)
-{
- tcg_gen_op5(opc, tcgv_i64_arg(a1), tcgv_i64_arg(a2),
- tcgv_i64_arg(a3), a4, a5);
-}
-
-static inline void tcg_gen_op6_i32(TCGOpcode opc, TCGv_i32 a1, TCGv_i32 a2,
- TCGv_i32 a3, TCGv_i32 a4,
- TCGv_i32 a5, TCGv_i32 a6)
-{
- tcg_gen_op6(opc, tcgv_i32_arg(a1), tcgv_i32_arg(a2),
- tcgv_i32_arg(a3), tcgv_i32_arg(a4), tcgv_i32_arg(a5),
- tcgv_i32_arg(a6));
-}
-
-static inline void tcg_gen_op6_i64(TCGOpcode opc, TCGv_i64 a1, TCGv_i64 a2,
- TCGv_i64 a3, TCGv_i64 a4,
- TCGv_i64 a5, TCGv_i64 a6)
-{
- tcg_gen_op6(opc, tcgv_i64_arg(a1), tcgv_i64_arg(a2),
- tcgv_i64_arg(a3), tcgv_i64_arg(a4), tcgv_i64_arg(a5),
- tcgv_i64_arg(a6));
-}
-
-static inline void tcg_gen_op6i_i32(TCGOpcode opc, TCGv_i32 a1, TCGv_i32 a2,
- TCGv_i32 a3, TCGv_i32 a4,
- TCGv_i32 a5, TCGArg a6)
-{
- tcg_gen_op6(opc, tcgv_i32_arg(a1), tcgv_i32_arg(a2),
- tcgv_i32_arg(a3), tcgv_i32_arg(a4), tcgv_i32_arg(a5), a6);
-}
-
-static inline void tcg_gen_op6i_i64(TCGOpcode opc, TCGv_i64 a1, TCGv_i64 a2,
- TCGv_i64 a3, TCGv_i64 a4,
- TCGv_i64 a5, TCGArg a6)
-{
- tcg_gen_op6(opc, tcgv_i64_arg(a1), tcgv_i64_arg(a2),
- tcgv_i64_arg(a3), tcgv_i64_arg(a4), tcgv_i64_arg(a5), a6);
-}
-
-static inline void tcg_gen_op6ii_i32(TCGOpcode opc, TCGv_i32 a1, TCGv_i32 a2,
- TCGv_i32 a3, TCGv_i32 a4,
- TCGArg a5, TCGArg a6)
-{
- tcg_gen_op6(opc, tcgv_i32_arg(a1), tcgv_i32_arg(a2),
- tcgv_i32_arg(a3), tcgv_i32_arg(a4), a5, a6);
-}
-
-static inline void tcg_gen_op6ii_i64(TCGOpcode opc, TCGv_i64 a1, TCGv_i64 a2,
- TCGv_i64 a3, TCGv_i64 a4,
- TCGArg a5, TCGArg a6)
-{
- tcg_gen_op6(opc, tcgv_i64_arg(a1), tcgv_i64_arg(a2),
- tcgv_i64_arg(a3), tcgv_i64_arg(a4), a5, a6);
-}
-
-
-/* Generic ops. */
-
-static inline void gen_set_label(TCGLabel *l)
-{
- l->present = 1;
- tcg_gen_op1(INDEX_op_set_label, label_arg(l));
-}
-
-static inline void tcg_gen_br(TCGLabel *l)
-{
- l->refs++;
- tcg_gen_op1(INDEX_op_br, label_arg(l));
-}
-
-void tcg_gen_mb(TCGBar);
-
-/* Helper calls. */
-
-/* 32 bit ops */
-
-void tcg_gen_addi_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2);
-void tcg_gen_subfi_i32(TCGv_i32 ret, int32_t arg1, TCGv_i32 arg2);
-void tcg_gen_subi_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2);
-void tcg_gen_andi_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2);
-void tcg_gen_ori_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2);
-void tcg_gen_xori_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2);
-void tcg_gen_shli_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2);
-void tcg_gen_shri_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2);
-void tcg_gen_sari_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2);
-void tcg_gen_muli_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2);
-void tcg_gen_div_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2);
-void tcg_gen_rem_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2);
-void tcg_gen_divu_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2);
-void tcg_gen_remu_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2);
-void tcg_gen_andc_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2);
-void tcg_gen_eqv_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2);
-void tcg_gen_nand_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2);
-void tcg_gen_nor_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2);
-void tcg_gen_orc_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2);
-void tcg_gen_clz_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2);
-void tcg_gen_ctz_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2);
-void tcg_gen_clzi_i32(TCGv_i32 ret, TCGv_i32 arg1, uint32_t arg2);
-void tcg_gen_ctzi_i32(TCGv_i32 ret, TCGv_i32 arg1, uint32_t arg2);
-void tcg_gen_clrsb_i32(TCGv_i32 ret, TCGv_i32 arg);
-void tcg_gen_ctpop_i32(TCGv_i32 a1, TCGv_i32 a2);
-void tcg_gen_rotl_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2);
-void tcg_gen_rotli_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2);
-void tcg_gen_rotr_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2);
-void tcg_gen_rotri_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2);
-void tcg_gen_deposit_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2,
- unsigned int ofs, unsigned int len);
-void tcg_gen_deposit_z_i32(TCGv_i32 ret, TCGv_i32 arg,
- unsigned int ofs, unsigned int len);
-void tcg_gen_extract_i32(TCGv_i32 ret, TCGv_i32 arg,
- unsigned int ofs, unsigned int len);
-void tcg_gen_sextract_i32(TCGv_i32 ret, TCGv_i32 arg,
- unsigned int ofs, unsigned int len);
-void tcg_gen_extract2_i32(TCGv_i32 ret, TCGv_i32 al, TCGv_i32 ah,
- unsigned int ofs);
-void tcg_gen_brcond_i32(TCGCond cond, TCGv_i32 arg1, TCGv_i32 arg2, TCGLabel *);
-void tcg_gen_brcondi_i32(TCGCond cond, TCGv_i32 arg1, int32_t arg2, TCGLabel *);
-void tcg_gen_setcond_i32(TCGCond cond, TCGv_i32 ret,
- TCGv_i32 arg1, TCGv_i32 arg2);
-void tcg_gen_setcondi_i32(TCGCond cond, TCGv_i32 ret,
- TCGv_i32 arg1, int32_t arg2);
-void tcg_gen_movcond_i32(TCGCond cond, TCGv_i32 ret, TCGv_i32 c1,
- TCGv_i32 c2, TCGv_i32 v1, TCGv_i32 v2);
-void tcg_gen_add2_i32(TCGv_i32 rl, TCGv_i32 rh, TCGv_i32 al,
- TCGv_i32 ah, TCGv_i32 bl, TCGv_i32 bh);
-void tcg_gen_sub2_i32(TCGv_i32 rl, TCGv_i32 rh, TCGv_i32 al,
- TCGv_i32 ah, TCGv_i32 bl, TCGv_i32 bh);
-void tcg_gen_mulu2_i32(TCGv_i32 rl, TCGv_i32 rh, TCGv_i32 arg1, TCGv_i32 arg2);
-void tcg_gen_muls2_i32(TCGv_i32 rl, TCGv_i32 rh, TCGv_i32 arg1, TCGv_i32 arg2);
-void tcg_gen_mulsu2_i32(TCGv_i32 rl, TCGv_i32 rh, TCGv_i32 arg1, TCGv_i32 arg2);
-void tcg_gen_ext8s_i32(TCGv_i32 ret, TCGv_i32 arg);
-void tcg_gen_ext16s_i32(TCGv_i32 ret, TCGv_i32 arg);
-void tcg_gen_ext8u_i32(TCGv_i32 ret, TCGv_i32 arg);
-void tcg_gen_ext16u_i32(TCGv_i32 ret, TCGv_i32 arg);
-void tcg_gen_bswap16_i32(TCGv_i32 ret, TCGv_i32 arg);
-void tcg_gen_bswap32_i32(TCGv_i32 ret, TCGv_i32 arg);
-void tcg_gen_smin_i32(TCGv_i32, TCGv_i32 arg1, TCGv_i32 arg2);
-void tcg_gen_smax_i32(TCGv_i32, TCGv_i32 arg1, TCGv_i32 arg2);
-void tcg_gen_umin_i32(TCGv_i32, TCGv_i32 arg1, TCGv_i32 arg2);
-void tcg_gen_umax_i32(TCGv_i32, TCGv_i32 arg1, TCGv_i32 arg2);
-void tcg_gen_abs_i32(TCGv_i32, TCGv_i32);
-
-static inline void tcg_gen_discard_i32(TCGv_i32 arg)
-{
- tcg_gen_op1_i32(INDEX_op_discard, arg);
-}
-
-static inline void tcg_gen_mov_i32(TCGv_i32 ret, TCGv_i32 arg)
-{
- if (ret != arg) {
- tcg_gen_op2_i32(INDEX_op_mov_i32, ret, arg);
- }
-}
-
-static inline void tcg_gen_movi_i32(TCGv_i32 ret, int32_t arg)
-{
- tcg_gen_op2i_i32(INDEX_op_movi_i32, ret, arg);
-}
-
-static inline void tcg_gen_ld8u_i32(TCGv_i32 ret, TCGv_ptr arg2,
- tcg_target_long offset)
-{
- tcg_gen_ldst_op_i32(INDEX_op_ld8u_i32, ret, arg2, offset);
-}
-
-static inline void tcg_gen_ld8s_i32(TCGv_i32 ret, TCGv_ptr arg2,
- tcg_target_long offset)
-{
- tcg_gen_ldst_op_i32(INDEX_op_ld8s_i32, ret, arg2, offset);
-}
-
-static inline void tcg_gen_ld16u_i32(TCGv_i32 ret, TCGv_ptr arg2,
- tcg_target_long offset)
-{
- tcg_gen_ldst_op_i32(INDEX_op_ld16u_i32, ret, arg2, offset);
-}
-
-static inline void tcg_gen_ld16s_i32(TCGv_i32 ret, TCGv_ptr arg2,
- tcg_target_long offset)
-{
- tcg_gen_ldst_op_i32(INDEX_op_ld16s_i32, ret, arg2, offset);
-}
-
-static inline void tcg_gen_ld_i32(TCGv_i32 ret, TCGv_ptr arg2,
- tcg_target_long offset)
-{
- tcg_gen_ldst_op_i32(INDEX_op_ld_i32, ret, arg2, offset);
-}
-
-static inline void tcg_gen_st8_i32(TCGv_i32 arg1, TCGv_ptr arg2,
- tcg_target_long offset)
-{
- tcg_gen_ldst_op_i32(INDEX_op_st8_i32, arg1, arg2, offset);
-}
-
-static inline void tcg_gen_st16_i32(TCGv_i32 arg1, TCGv_ptr arg2,
- tcg_target_long offset)
-{
- tcg_gen_ldst_op_i32(INDEX_op_st16_i32, arg1, arg2, offset);
-}
-
-static inline void tcg_gen_st_i32(TCGv_i32 arg1, TCGv_ptr arg2,
- tcg_target_long offset)
-{
- tcg_gen_ldst_op_i32(INDEX_op_st_i32, arg1, arg2, offset);
-}
-
-static inline void tcg_gen_add_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
-{
- tcg_gen_op3_i32(INDEX_op_add_i32, ret, arg1, arg2);
-}
-
-static inline void tcg_gen_sub_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
-{
- tcg_gen_op3_i32(INDEX_op_sub_i32, ret, arg1, arg2);
-}
-
-static inline void tcg_gen_and_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
-{
- tcg_gen_op3_i32(INDEX_op_and_i32, ret, arg1, arg2);
-}
-
-static inline void tcg_gen_or_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
-{
- tcg_gen_op3_i32(INDEX_op_or_i32, ret, arg1, arg2);
-}
-
-static inline void tcg_gen_xor_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
-{
- tcg_gen_op3_i32(INDEX_op_xor_i32, ret, arg1, arg2);
-}
-
-static inline void tcg_gen_shl_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
-{
- tcg_gen_op3_i32(INDEX_op_shl_i32, ret, arg1, arg2);
-}
-
-static inline void tcg_gen_shr_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
-{
- tcg_gen_op3_i32(INDEX_op_shr_i32, ret, arg1, arg2);
-}
-
-static inline void tcg_gen_sar_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
-{
- tcg_gen_op3_i32(INDEX_op_sar_i32, ret, arg1, arg2);
-}
-
-static inline void tcg_gen_mul_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
-{
- tcg_gen_op3_i32(INDEX_op_mul_i32, ret, arg1, arg2);
-}
-
-static inline void tcg_gen_neg_i32(TCGv_i32 ret, TCGv_i32 arg)
-{
- if (TCG_TARGET_HAS_neg_i32) {
- tcg_gen_op2_i32(INDEX_op_neg_i32, ret, arg);
- } else {
- tcg_gen_subfi_i32(ret, 0, arg);
- }
-}
-
-static inline void tcg_gen_not_i32(TCGv_i32 ret, TCGv_i32 arg)
-{
- if (TCG_TARGET_HAS_not_i32) {
- tcg_gen_op2_i32(INDEX_op_not_i32, ret, arg);
- } else {
- tcg_gen_xori_i32(ret, arg, -1);
- }
-}
-
-/* 64 bit ops */
-
-void tcg_gen_addi_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2);
-void tcg_gen_subfi_i64(TCGv_i64 ret, int64_t arg1, TCGv_i64 arg2);
-void tcg_gen_subi_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2);
-void tcg_gen_andi_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2);
-void tcg_gen_ori_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2);
-void tcg_gen_xori_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2);
-void tcg_gen_shli_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2);
-void tcg_gen_shri_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2);
-void tcg_gen_sari_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2);
-void tcg_gen_muli_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2);
-void tcg_gen_div_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2);
-void tcg_gen_rem_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2);
-void tcg_gen_divu_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2);
-void tcg_gen_remu_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2);
-void tcg_gen_andc_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2);
-void tcg_gen_eqv_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2);
-void tcg_gen_nand_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2);
-void tcg_gen_nor_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2);
-void tcg_gen_orc_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2);
-void tcg_gen_clz_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2);
-void tcg_gen_ctz_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2);
-void tcg_gen_clzi_i64(TCGv_i64 ret, TCGv_i64 arg1, uint64_t arg2);
-void tcg_gen_ctzi_i64(TCGv_i64 ret, TCGv_i64 arg1, uint64_t arg2);
-void tcg_gen_clrsb_i64(TCGv_i64 ret, TCGv_i64 arg);
-void tcg_gen_ctpop_i64(TCGv_i64 a1, TCGv_i64 a2);
-void tcg_gen_rotl_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2);
-void tcg_gen_rotli_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2);
-void tcg_gen_rotr_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2);
-void tcg_gen_rotri_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2);
-void tcg_gen_deposit_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2,
- unsigned int ofs, unsigned int len);
-void tcg_gen_deposit_z_i64(TCGv_i64 ret, TCGv_i64 arg,
- unsigned int ofs, unsigned int len);
-void tcg_gen_extract_i64(TCGv_i64 ret, TCGv_i64 arg,
- unsigned int ofs, unsigned int len);
-void tcg_gen_sextract_i64(TCGv_i64 ret, TCGv_i64 arg,
- unsigned int ofs, unsigned int len);
-void tcg_gen_extract2_i64(TCGv_i64 ret, TCGv_i64 al, TCGv_i64 ah,
- unsigned int ofs);
-void tcg_gen_brcond_i64(TCGCond cond, TCGv_i64 arg1, TCGv_i64 arg2, TCGLabel *);
-void tcg_gen_brcondi_i64(TCGCond cond, TCGv_i64 arg1, int64_t arg2, TCGLabel *);
-void tcg_gen_setcond_i64(TCGCond cond, TCGv_i64 ret,
- TCGv_i64 arg1, TCGv_i64 arg2);
-void tcg_gen_setcondi_i64(TCGCond cond, TCGv_i64 ret,
- TCGv_i64 arg1, int64_t arg2);
-void tcg_gen_movcond_i64(TCGCond cond, TCGv_i64 ret, TCGv_i64 c1,
- TCGv_i64 c2, TCGv_i64 v1, TCGv_i64 v2);
-void tcg_gen_add2_i64(TCGv_i64 rl, TCGv_i64 rh, TCGv_i64 al,
- TCGv_i64 ah, TCGv_i64 bl, TCGv_i64 bh);
-void tcg_gen_sub2_i64(TCGv_i64 rl, TCGv_i64 rh, TCGv_i64 al,
- TCGv_i64 ah, TCGv_i64 bl, TCGv_i64 bh);
-void tcg_gen_mulu2_i64(TCGv_i64 rl, TCGv_i64 rh, TCGv_i64 arg1, TCGv_i64 arg2);
-void tcg_gen_muls2_i64(TCGv_i64 rl, TCGv_i64 rh, TCGv_i64 arg1, TCGv_i64 arg2);
-void tcg_gen_mulsu2_i64(TCGv_i64 rl, TCGv_i64 rh, TCGv_i64 arg1, TCGv_i64 arg2);
-void tcg_gen_not_i64(TCGv_i64 ret, TCGv_i64 arg);
-void tcg_gen_ext8s_i64(TCGv_i64 ret, TCGv_i64 arg);
-void tcg_gen_ext16s_i64(TCGv_i64 ret, TCGv_i64 arg);
-void tcg_gen_ext32s_i64(TCGv_i64 ret, TCGv_i64 arg);
-void tcg_gen_ext8u_i64(TCGv_i64 ret, TCGv_i64 arg);
-void tcg_gen_ext16u_i64(TCGv_i64 ret, TCGv_i64 arg);
-void tcg_gen_ext32u_i64(TCGv_i64 ret, TCGv_i64 arg);
-void tcg_gen_bswap16_i64(TCGv_i64 ret, TCGv_i64 arg);
-void tcg_gen_bswap32_i64(TCGv_i64 ret, TCGv_i64 arg);
-void tcg_gen_bswap64_i64(TCGv_i64 ret, TCGv_i64 arg);
-void tcg_gen_smin_i64(TCGv_i64, TCGv_i64 arg1, TCGv_i64 arg2);
-void tcg_gen_smax_i64(TCGv_i64, TCGv_i64 arg1, TCGv_i64 arg2);
-void tcg_gen_umin_i64(TCGv_i64, TCGv_i64 arg1, TCGv_i64 arg2);
-void tcg_gen_umax_i64(TCGv_i64, TCGv_i64 arg1, TCGv_i64 arg2);
-void tcg_gen_abs_i64(TCGv_i64, TCGv_i64);
-
-#if TCG_TARGET_REG_BITS == 64
-static inline void tcg_gen_discard_i64(TCGv_i64 arg)
-{
- tcg_gen_op1_i64(INDEX_op_discard, arg);
-}
-
-static inline void tcg_gen_mov_i64(TCGv_i64 ret, TCGv_i64 arg)
-{
- if (ret != arg) {
- tcg_gen_op2_i64(INDEX_op_mov_i64, ret, arg);
- }
-}
-
-static inline void tcg_gen_movi_i64(TCGv_i64 ret, int64_t arg)
-{
- tcg_gen_op2i_i64(INDEX_op_movi_i64, ret, arg);
-}
-
-static inline void tcg_gen_ld8u_i64(TCGv_i64 ret, TCGv_ptr arg2,
- tcg_target_long offset)
-{
- tcg_gen_ldst_op_i64(INDEX_op_ld8u_i64, ret, arg2, offset);
-}
-
-static inline void tcg_gen_ld8s_i64(TCGv_i64 ret, TCGv_ptr arg2,
- tcg_target_long offset)
-{
- tcg_gen_ldst_op_i64(INDEX_op_ld8s_i64, ret, arg2, offset);
-}
-
-static inline void tcg_gen_ld16u_i64(TCGv_i64 ret, TCGv_ptr arg2,
- tcg_target_long offset)
-{
- tcg_gen_ldst_op_i64(INDEX_op_ld16u_i64, ret, arg2, offset);
-}
-
-static inline void tcg_gen_ld16s_i64(TCGv_i64 ret, TCGv_ptr arg2,
- tcg_target_long offset)
-{
- tcg_gen_ldst_op_i64(INDEX_op_ld16s_i64, ret, arg2, offset);
-}
-
-static inline void tcg_gen_ld32u_i64(TCGv_i64 ret, TCGv_ptr arg2,
- tcg_target_long offset)
-{
- tcg_gen_ldst_op_i64(INDEX_op_ld32u_i64, ret, arg2, offset);
-}
-
-static inline void tcg_gen_ld32s_i64(TCGv_i64 ret, TCGv_ptr arg2,
- tcg_target_long offset)
-{
- tcg_gen_ldst_op_i64(INDEX_op_ld32s_i64, ret, arg2, offset);
-}
-
-static inline void tcg_gen_ld_i64(TCGv_i64 ret, TCGv_ptr arg2,
- tcg_target_long offset)
-{
- tcg_gen_ldst_op_i64(INDEX_op_ld_i64, ret, arg2, offset);
-}
-
-static inline void tcg_gen_st8_i64(TCGv_i64 arg1, TCGv_ptr arg2,
- tcg_target_long offset)
-{
- tcg_gen_ldst_op_i64(INDEX_op_st8_i64, arg1, arg2, offset);
-}
-
-static inline void tcg_gen_st16_i64(TCGv_i64 arg1, TCGv_ptr arg2,
- tcg_target_long offset)
-{
- tcg_gen_ldst_op_i64(INDEX_op_st16_i64, arg1, arg2, offset);
-}
-
-static inline void tcg_gen_st32_i64(TCGv_i64 arg1, TCGv_ptr arg2,
- tcg_target_long offset)
-{
- tcg_gen_ldst_op_i64(INDEX_op_st32_i64, arg1, arg2, offset);
-}
-
-static inline void tcg_gen_st_i64(TCGv_i64 arg1, TCGv_ptr arg2,
- tcg_target_long offset)
-{
- tcg_gen_ldst_op_i64(INDEX_op_st_i64, arg1, arg2, offset);
-}
-
-static inline void tcg_gen_add_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
-{
- tcg_gen_op3_i64(INDEX_op_add_i64, ret, arg1, arg2);
-}
-
-static inline void tcg_gen_sub_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
-{
- tcg_gen_op3_i64(INDEX_op_sub_i64, ret, arg1, arg2);
-}
-
-static inline void tcg_gen_and_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
-{
- tcg_gen_op3_i64(INDEX_op_and_i64, ret, arg1, arg2);
-}
-
-static inline void tcg_gen_or_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
-{
- tcg_gen_op3_i64(INDEX_op_or_i64, ret, arg1, arg2);
-}
-
-static inline void tcg_gen_xor_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
-{
- tcg_gen_op3_i64(INDEX_op_xor_i64, ret, arg1, arg2);
-}
-
-static inline void tcg_gen_shl_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
-{
- tcg_gen_op3_i64(INDEX_op_shl_i64, ret, arg1, arg2);
-}
-
-static inline void tcg_gen_shr_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
-{
- tcg_gen_op3_i64(INDEX_op_shr_i64, ret, arg1, arg2);
-}
-
-static inline void tcg_gen_sar_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
-{
- tcg_gen_op3_i64(INDEX_op_sar_i64, ret, arg1, arg2);
-}
-
-static inline void tcg_gen_mul_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
-{
- tcg_gen_op3_i64(INDEX_op_mul_i64, ret, arg1, arg2);
-}
-#else /* TCG_TARGET_REG_BITS == 32 */
-static inline void tcg_gen_st8_i64(TCGv_i64 arg1, TCGv_ptr arg2,
- tcg_target_long offset)
-{
- tcg_gen_st8_i32(TCGV_LOW(arg1), arg2, offset);
-}
-
-static inline void tcg_gen_st16_i64(TCGv_i64 arg1, TCGv_ptr arg2,
- tcg_target_long offset)
-{
- tcg_gen_st16_i32(TCGV_LOW(arg1), arg2, offset);
-}
-
-static inline void tcg_gen_st32_i64(TCGv_i64 arg1, TCGv_ptr arg2,
- tcg_target_long offset)
-{
- tcg_gen_st_i32(TCGV_LOW(arg1), arg2, offset);
-}
-
-static inline void tcg_gen_add_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
-{
- tcg_gen_add2_i32(TCGV_LOW(ret), TCGV_HIGH(ret), TCGV_LOW(arg1),
- TCGV_HIGH(arg1), TCGV_LOW(arg2), TCGV_HIGH(arg2));
-}
-
-static inline void tcg_gen_sub_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
-{
- tcg_gen_sub2_i32(TCGV_LOW(ret), TCGV_HIGH(ret), TCGV_LOW(arg1),
- TCGV_HIGH(arg1), TCGV_LOW(arg2), TCGV_HIGH(arg2));
-}
-
-void tcg_gen_discard_i64(TCGv_i64 arg);
-void tcg_gen_mov_i64(TCGv_i64 ret, TCGv_i64 arg);
-void tcg_gen_movi_i64(TCGv_i64 ret, int64_t arg);
-void tcg_gen_ld8u_i64(TCGv_i64 ret, TCGv_ptr arg2, tcg_target_long offset);
-void tcg_gen_ld8s_i64(TCGv_i64 ret, TCGv_ptr arg2, tcg_target_long offset);
-void tcg_gen_ld16u_i64(TCGv_i64 ret, TCGv_ptr arg2, tcg_target_long offset);
-void tcg_gen_ld16s_i64(TCGv_i64 ret, TCGv_ptr arg2, tcg_target_long offset);
-void tcg_gen_ld32u_i64(TCGv_i64 ret, TCGv_ptr arg2, tcg_target_long offset);
-void tcg_gen_ld32s_i64(TCGv_i64 ret, TCGv_ptr arg2, tcg_target_long offset);
-void tcg_gen_ld_i64(TCGv_i64 ret, TCGv_ptr arg2, tcg_target_long offset);
-void tcg_gen_st_i64(TCGv_i64 arg1, TCGv_ptr arg2, tcg_target_long offset);
-void tcg_gen_and_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2);
-void tcg_gen_or_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2);
-void tcg_gen_xor_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2);
-void tcg_gen_shl_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2);
-void tcg_gen_shr_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2);
-void tcg_gen_sar_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2);
-void tcg_gen_mul_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2);
-#endif /* TCG_TARGET_REG_BITS */
-
-static inline void tcg_gen_neg_i64(TCGv_i64 ret, TCGv_i64 arg)
-{
- if (TCG_TARGET_HAS_neg_i64) {
- tcg_gen_op2_i64(INDEX_op_neg_i64, ret, arg);
- } else {
- tcg_gen_subfi_i64(ret, 0, arg);
- }
-}
-
-/* Size changing operations. */
-
-void tcg_gen_extu_i32_i64(TCGv_i64 ret, TCGv_i32 arg);
-void tcg_gen_ext_i32_i64(TCGv_i64 ret, TCGv_i32 arg);
-void tcg_gen_concat_i32_i64(TCGv_i64 dest, TCGv_i32 low, TCGv_i32 high);
-void tcg_gen_extrl_i64_i32(TCGv_i32 ret, TCGv_i64 arg);
-void tcg_gen_extrh_i64_i32(TCGv_i32 ret, TCGv_i64 arg);
-void tcg_gen_extr_i64_i32(TCGv_i32 lo, TCGv_i32 hi, TCGv_i64 arg);
-void tcg_gen_extr32_i64(TCGv_i64 lo, TCGv_i64 hi, TCGv_i64 arg);
-
-static inline void tcg_gen_concat32_i64(TCGv_i64 ret, TCGv_i64 lo, TCGv_i64 hi)
-{
- tcg_gen_deposit_i64(ret, lo, hi, 32, 32);
-}
-
-/* QEMU specific operations. */
-
-#ifndef TARGET_LONG_BITS
-#error must include QEMU headers
-#endif
-
-#if TARGET_INSN_START_WORDS == 1
-# if TARGET_LONG_BITS <= TCG_TARGET_REG_BITS
-static inline void tcg_gen_insn_start(target_ulong pc)
-{
- tcg_gen_op1(INDEX_op_insn_start, pc);
-}
-# else
-static inline void tcg_gen_insn_start(target_ulong pc)
-{
- tcg_gen_op2(INDEX_op_insn_start, (uint32_t)pc, (uint32_t)(pc >> 32));
-}
-# endif
-#elif TARGET_INSN_START_WORDS == 2
-# if TARGET_LONG_BITS <= TCG_TARGET_REG_BITS
-static inline void tcg_gen_insn_start(target_ulong pc, target_ulong a1)
-{
- tcg_gen_op2(INDEX_op_insn_start, pc, a1);
-}
-# else
-static inline void tcg_gen_insn_start(target_ulong pc, target_ulong a1)
-{
- tcg_gen_op4(INDEX_op_insn_start,
- (uint32_t)pc, (uint32_t)(pc >> 32),
- (uint32_t)a1, (uint32_t)(a1 >> 32));
-}
-# endif
-#elif TARGET_INSN_START_WORDS == 3
-# if TARGET_LONG_BITS <= TCG_TARGET_REG_BITS
-static inline void tcg_gen_insn_start(target_ulong pc, target_ulong a1,
- target_ulong a2)
-{
- tcg_gen_op3(INDEX_op_insn_start, pc, a1, a2);
-}
-# else
-static inline void tcg_gen_insn_start(target_ulong pc, target_ulong a1,
- target_ulong a2)
-{
- tcg_gen_op6(INDEX_op_insn_start,
- (uint32_t)pc, (uint32_t)(pc >> 32),
- (uint32_t)a1, (uint32_t)(a1 >> 32),
- (uint32_t)a2, (uint32_t)(a2 >> 32));
-}
-# endif
-#else
-# error "Unhandled number of operands to insn_start"
-#endif
-
-/**
- * tcg_gen_exit_tb() - output exit_tb TCG operation
- * @tb: The TranslationBlock from which we are exiting
- * @idx: Direct jump slot index, or exit request
- *
- * See tcg/README for more info about this TCG operation.
- * See also tcg.h and the block comment above TB_EXIT_MASK.
- *
- * For a normal exit from the TB, back to the main loop, @tb should
- * be NULL and @idx should be 0. Otherwise, @tb should be valid and
- * @idx should be one of the TB_EXIT_ values.
- */
-void tcg_gen_exit_tb(TranslationBlock *tb, unsigned idx);
-
-/**
- * tcg_gen_goto_tb() - output goto_tb TCG operation
- * @idx: Direct jump slot index (0 or 1)
- *
- * See tcg/README for more info about this TCG operation.
- *
- * NOTE: In softmmu emulation, direct jumps with goto_tb are only safe within
- * the pages this TB resides in because we don't take care of direct jumps when
- * address mapping changes, e.g. in tlb_flush(). In user mode, there's only a
- * static address translation, so the destination address is always valid, TBs
- * are always invalidated properly, and direct jumps are reset when mapping
- * changes.
- */
-void tcg_gen_goto_tb(unsigned idx);
-
-/**
- * tcg_gen_lookup_and_goto_ptr() - look up the current TB, jump to it if valid
- * @addr: Guest address of the target TB
- *
- * If the TB is not valid, jump to the epilogue.
- *
- * This operation is optional. If the TCG backend does not implement goto_ptr,
- * this op is equivalent to calling tcg_gen_exit_tb() with 0 as the argument.
- */
-void tcg_gen_lookup_and_goto_ptr(void);
-
-static inline void tcg_gen_plugin_cb_start(unsigned from, unsigned type,
- unsigned wr)
-{
- tcg_gen_op3(INDEX_op_plugin_cb_start, from, type, wr);
-}
-
-static inline void tcg_gen_plugin_cb_end(void)
-{
- tcg_emit_op(INDEX_op_plugin_cb_end);
-}
-
-#if TARGET_LONG_BITS == 32
-#define tcg_temp_new() tcg_temp_new_i32()
-#define tcg_global_reg_new tcg_global_reg_new_i32
-#define tcg_global_mem_new tcg_global_mem_new_i32
-#define tcg_temp_local_new() tcg_temp_local_new_i32()
-#define tcg_temp_free tcg_temp_free_i32
-#define tcg_gen_qemu_ld_tl tcg_gen_qemu_ld_i32
-#define tcg_gen_qemu_st_tl tcg_gen_qemu_st_i32
-#else
-#define tcg_temp_new() tcg_temp_new_i64()
-#define tcg_global_reg_new tcg_global_reg_new_i64
-#define tcg_global_mem_new tcg_global_mem_new_i64
-#define tcg_temp_local_new() tcg_temp_local_new_i64()
-#define tcg_temp_free tcg_temp_free_i64
-#define tcg_gen_qemu_ld_tl tcg_gen_qemu_ld_i64
-#define tcg_gen_qemu_st_tl tcg_gen_qemu_st_i64
-#endif
-
-void tcg_gen_qemu_ld_i32(TCGv_i32, TCGv, TCGArg, MemOp);
-void tcg_gen_qemu_st_i32(TCGv_i32, TCGv, TCGArg, MemOp);
-void tcg_gen_qemu_ld_i64(TCGv_i64, TCGv, TCGArg, MemOp);
-void tcg_gen_qemu_st_i64(TCGv_i64, TCGv, TCGArg, MemOp);
-
-static inline void tcg_gen_qemu_ld8u(TCGv ret, TCGv addr, int mem_index)
-{
- tcg_gen_qemu_ld_tl(ret, addr, mem_index, MO_UB);
-}
-
-static inline void tcg_gen_qemu_ld8s(TCGv ret, TCGv addr, int mem_index)
-{
- tcg_gen_qemu_ld_tl(ret, addr, mem_index, MO_SB);
-}
-
-static inline void tcg_gen_qemu_ld16u(TCGv ret, TCGv addr, int mem_index)
-{
- tcg_gen_qemu_ld_tl(ret, addr, mem_index, MO_TEUW);
-}
-
-static inline void tcg_gen_qemu_ld16s(TCGv ret, TCGv addr, int mem_index)
-{
- tcg_gen_qemu_ld_tl(ret, addr, mem_index, MO_TESW);
-}
-
-static inline void tcg_gen_qemu_ld32u(TCGv ret, TCGv addr, int mem_index)
-{
- tcg_gen_qemu_ld_tl(ret, addr, mem_index, MO_TEUL);
-}
-
-static inline void tcg_gen_qemu_ld32s(TCGv ret, TCGv addr, int mem_index)
-{
- tcg_gen_qemu_ld_tl(ret, addr, mem_index, MO_TESL);
-}
-
-static inline void tcg_gen_qemu_ld64(TCGv_i64 ret, TCGv addr, int mem_index)
-{
- tcg_gen_qemu_ld_i64(ret, addr, mem_index, MO_TEQ);
-}
-
-static inline void tcg_gen_qemu_st8(TCGv arg, TCGv addr, int mem_index)
-{
- tcg_gen_qemu_st_tl(arg, addr, mem_index, MO_UB);
-}
-
-static inline void tcg_gen_qemu_st16(TCGv arg, TCGv addr, int mem_index)
-{
- tcg_gen_qemu_st_tl(arg, addr, mem_index, MO_TEUW);
-}
-
-static inline void tcg_gen_qemu_st32(TCGv arg, TCGv addr, int mem_index)
-{
- tcg_gen_qemu_st_tl(arg, addr, mem_index, MO_TEUL);
-}
-
-static inline void tcg_gen_qemu_st64(TCGv_i64 arg, TCGv addr, int mem_index)
-{
- tcg_gen_qemu_st_i64(arg, addr, mem_index, MO_TEQ);
-}
-
-void tcg_gen_atomic_cmpxchg_i32(TCGv_i32, TCGv, TCGv_i32, TCGv_i32,
- TCGArg, MemOp);
-void tcg_gen_atomic_cmpxchg_i64(TCGv_i64, TCGv, TCGv_i64, TCGv_i64,
- TCGArg, MemOp);
-
-void tcg_gen_atomic_xchg_i32(TCGv_i32, TCGv, TCGv_i32, TCGArg, MemOp);
-void tcg_gen_atomic_xchg_i64(TCGv_i64, TCGv, TCGv_i64, TCGArg, MemOp);
-
-void tcg_gen_atomic_fetch_add_i32(TCGv_i32, TCGv, TCGv_i32, TCGArg, MemOp);
-void tcg_gen_atomic_fetch_add_i64(TCGv_i64, TCGv, TCGv_i64, TCGArg, MemOp);
-void tcg_gen_atomic_fetch_and_i32(TCGv_i32, TCGv, TCGv_i32, TCGArg, MemOp);
-void tcg_gen_atomic_fetch_and_i64(TCGv_i64, TCGv, TCGv_i64, TCGArg, MemOp);
-void tcg_gen_atomic_fetch_or_i32(TCGv_i32, TCGv, TCGv_i32, TCGArg, MemOp);
-void tcg_gen_atomic_fetch_or_i64(TCGv_i64, TCGv, TCGv_i64, TCGArg, MemOp);
-void tcg_gen_atomic_fetch_xor_i32(TCGv_i32, TCGv, TCGv_i32, TCGArg, MemOp);
-void tcg_gen_atomic_fetch_xor_i64(TCGv_i64, TCGv, TCGv_i64, TCGArg, MemOp);
-void tcg_gen_atomic_fetch_smin_i32(TCGv_i32, TCGv, TCGv_i32, TCGArg, MemOp);
-void tcg_gen_atomic_fetch_smin_i64(TCGv_i64, TCGv, TCGv_i64, TCGArg, MemOp);
-void tcg_gen_atomic_fetch_umin_i32(TCGv_i32, TCGv, TCGv_i32, TCGArg, MemOp);
-void tcg_gen_atomic_fetch_umin_i64(TCGv_i64, TCGv, TCGv_i64, TCGArg, MemOp);
-void tcg_gen_atomic_fetch_smax_i32(TCGv_i32, TCGv, TCGv_i32, TCGArg, MemOp);
-void tcg_gen_atomic_fetch_smax_i64(TCGv_i64, TCGv, TCGv_i64, TCGArg, MemOp);
-void tcg_gen_atomic_fetch_umax_i32(TCGv_i32, TCGv, TCGv_i32, TCGArg, MemOp);
-void tcg_gen_atomic_fetch_umax_i64(TCGv_i64, TCGv, TCGv_i64, TCGArg, MemOp);
-
-void tcg_gen_atomic_add_fetch_i32(TCGv_i32, TCGv, TCGv_i32, TCGArg, MemOp);
-void tcg_gen_atomic_add_fetch_i64(TCGv_i64, TCGv, TCGv_i64, TCGArg, MemOp);
-void tcg_gen_atomic_and_fetch_i32(TCGv_i32, TCGv, TCGv_i32, TCGArg, MemOp);
-void tcg_gen_atomic_and_fetch_i64(TCGv_i64, TCGv, TCGv_i64, TCGArg, MemOp);
-void tcg_gen_atomic_or_fetch_i32(TCGv_i32, TCGv, TCGv_i32, TCGArg, MemOp);
-void tcg_gen_atomic_or_fetch_i64(TCGv_i64, TCGv, TCGv_i64, TCGArg, MemOp);
-void tcg_gen_atomic_xor_fetch_i32(TCGv_i32, TCGv, TCGv_i32, TCGArg, MemOp);
-void tcg_gen_atomic_xor_fetch_i64(TCGv_i64, TCGv, TCGv_i64, TCGArg, MemOp);
-void tcg_gen_atomic_smin_fetch_i32(TCGv_i32, TCGv, TCGv_i32, TCGArg, MemOp);
-void tcg_gen_atomic_smin_fetch_i64(TCGv_i64, TCGv, TCGv_i64, TCGArg, MemOp);
-void tcg_gen_atomic_umin_fetch_i32(TCGv_i32, TCGv, TCGv_i32, TCGArg, MemOp);
-void tcg_gen_atomic_umin_fetch_i64(TCGv_i64, TCGv, TCGv_i64, TCGArg, MemOp);
-void tcg_gen_atomic_smax_fetch_i32(TCGv_i32, TCGv, TCGv_i32, TCGArg, MemOp);
-void tcg_gen_atomic_smax_fetch_i64(TCGv_i64, TCGv, TCGv_i64, TCGArg, MemOp);
-void tcg_gen_atomic_umax_fetch_i32(TCGv_i32, TCGv, TCGv_i32, TCGArg, MemOp);
-void tcg_gen_atomic_umax_fetch_i64(TCGv_i64, TCGv, TCGv_i64, TCGArg, MemOp);
-
-void tcg_gen_mov_vec(TCGv_vec, TCGv_vec);
-void tcg_gen_dup_i32_vec(unsigned vece, TCGv_vec, TCGv_i32);
-void tcg_gen_dup_i64_vec(unsigned vece, TCGv_vec, TCGv_i64);
-void tcg_gen_dup_mem_vec(unsigned vece, TCGv_vec, TCGv_ptr, tcg_target_long);
-void tcg_gen_dup8i_vec(TCGv_vec, uint32_t);
-void tcg_gen_dup16i_vec(TCGv_vec, uint32_t);
-void tcg_gen_dup32i_vec(TCGv_vec, uint32_t);
-void tcg_gen_dup64i_vec(TCGv_vec, uint64_t);
-void tcg_gen_dupi_vec(unsigned vece, TCGv_vec, uint64_t);
-void tcg_gen_add_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b);
-void tcg_gen_sub_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b);
-void tcg_gen_mul_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b);
-void tcg_gen_and_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b);
-void tcg_gen_or_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b);
-void tcg_gen_xor_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b);
-void tcg_gen_andc_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b);
-void tcg_gen_orc_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b);
-void tcg_gen_nand_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b);
-void tcg_gen_nor_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b);
-void tcg_gen_eqv_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b);
-void tcg_gen_not_vec(unsigned vece, TCGv_vec r, TCGv_vec a);
-void tcg_gen_neg_vec(unsigned vece, TCGv_vec r, TCGv_vec a);
-void tcg_gen_abs_vec(unsigned vece, TCGv_vec r, TCGv_vec a);
-void tcg_gen_ssadd_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b);
-void tcg_gen_usadd_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b);
-void tcg_gen_sssub_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b);
-void tcg_gen_ussub_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b);
-void tcg_gen_smin_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b);
-void tcg_gen_umin_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b);
-void tcg_gen_smax_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b);
-void tcg_gen_umax_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b);
-
-void tcg_gen_shli_vec(unsigned vece, TCGv_vec r, TCGv_vec a, int64_t i);
-void tcg_gen_shri_vec(unsigned vece, TCGv_vec r, TCGv_vec a, int64_t i);
-void tcg_gen_sari_vec(unsigned vece, TCGv_vec r, TCGv_vec a, int64_t i);
-void tcg_gen_rotli_vec(unsigned vece, TCGv_vec r, TCGv_vec a, int64_t i);
-void tcg_gen_rotri_vec(unsigned vece, TCGv_vec r, TCGv_vec a, int64_t i);
-
-void tcg_gen_shls_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_i32 s);
-void tcg_gen_shrs_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_i32 s);
-void tcg_gen_sars_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_i32 s);
-void tcg_gen_rotls_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_i32 s);
-
-void tcg_gen_shlv_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec s);
-void tcg_gen_shrv_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec s);
-void tcg_gen_sarv_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec s);
-void tcg_gen_rotlv_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec s);
-void tcg_gen_rotrv_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec s);
-
-void tcg_gen_cmp_vec(TCGCond cond, unsigned vece, TCGv_vec r,
- TCGv_vec a, TCGv_vec b);
-
-void tcg_gen_bitsel_vec(unsigned vece, TCGv_vec r, TCGv_vec a,
- TCGv_vec b, TCGv_vec c);
-void tcg_gen_cmpsel_vec(TCGCond cond, unsigned vece, TCGv_vec r,
- TCGv_vec a, TCGv_vec b, TCGv_vec c, TCGv_vec d);
-
-void tcg_gen_ld_vec(TCGv_vec r, TCGv_ptr base, TCGArg offset);
-void tcg_gen_st_vec(TCGv_vec r, TCGv_ptr base, TCGArg offset);
-void tcg_gen_stl_vec(TCGv_vec r, TCGv_ptr base, TCGArg offset, TCGType t);
-
-#if TARGET_LONG_BITS == 64
-#define tcg_gen_movi_tl tcg_gen_movi_i64
-#define tcg_gen_mov_tl tcg_gen_mov_i64
-#define tcg_gen_ld8u_tl tcg_gen_ld8u_i64
-#define tcg_gen_ld8s_tl tcg_gen_ld8s_i64
-#define tcg_gen_ld16u_tl tcg_gen_ld16u_i64
-#define tcg_gen_ld16s_tl tcg_gen_ld16s_i64
-#define tcg_gen_ld32u_tl tcg_gen_ld32u_i64
-#define tcg_gen_ld32s_tl tcg_gen_ld32s_i64
-#define tcg_gen_ld_tl tcg_gen_ld_i64
-#define tcg_gen_st8_tl tcg_gen_st8_i64
-#define tcg_gen_st16_tl tcg_gen_st16_i64
-#define tcg_gen_st32_tl tcg_gen_st32_i64
-#define tcg_gen_st_tl tcg_gen_st_i64
-#define tcg_gen_add_tl tcg_gen_add_i64
-#define tcg_gen_addi_tl tcg_gen_addi_i64
-#define tcg_gen_sub_tl tcg_gen_sub_i64
-#define tcg_gen_neg_tl tcg_gen_neg_i64
-#define tcg_gen_abs_tl tcg_gen_abs_i64
-#define tcg_gen_subfi_tl tcg_gen_subfi_i64
-#define tcg_gen_subi_tl tcg_gen_subi_i64
-#define tcg_gen_and_tl tcg_gen_and_i64
-#define tcg_gen_andi_tl tcg_gen_andi_i64
-#define tcg_gen_or_tl tcg_gen_or_i64
-#define tcg_gen_ori_tl tcg_gen_ori_i64
-#define tcg_gen_xor_tl tcg_gen_xor_i64
-#define tcg_gen_xori_tl tcg_gen_xori_i64
-#define tcg_gen_not_tl tcg_gen_not_i64
-#define tcg_gen_shl_tl tcg_gen_shl_i64
-#define tcg_gen_shli_tl tcg_gen_shli_i64
-#define tcg_gen_shr_tl tcg_gen_shr_i64
-#define tcg_gen_shri_tl tcg_gen_shri_i64
-#define tcg_gen_sar_tl tcg_gen_sar_i64
-#define tcg_gen_sari_tl tcg_gen_sari_i64
-#define tcg_gen_brcond_tl tcg_gen_brcond_i64
-#define tcg_gen_brcondi_tl tcg_gen_brcondi_i64
-#define tcg_gen_setcond_tl tcg_gen_setcond_i64
-#define tcg_gen_setcondi_tl tcg_gen_setcondi_i64
-#define tcg_gen_mul_tl tcg_gen_mul_i64
-#define tcg_gen_muli_tl tcg_gen_muli_i64
-#define tcg_gen_div_tl tcg_gen_div_i64
-#define tcg_gen_rem_tl tcg_gen_rem_i64
-#define tcg_gen_divu_tl tcg_gen_divu_i64
-#define tcg_gen_remu_tl tcg_gen_remu_i64
-#define tcg_gen_discard_tl tcg_gen_discard_i64
-#define tcg_gen_trunc_tl_i32 tcg_gen_extrl_i64_i32
-#define tcg_gen_trunc_i64_tl tcg_gen_mov_i64
-#define tcg_gen_extu_i32_tl tcg_gen_extu_i32_i64
-#define tcg_gen_ext_i32_tl tcg_gen_ext_i32_i64
-#define tcg_gen_extu_tl_i64 tcg_gen_mov_i64
-#define tcg_gen_ext_tl_i64 tcg_gen_mov_i64
-#define tcg_gen_ext8u_tl tcg_gen_ext8u_i64
-#define tcg_gen_ext8s_tl tcg_gen_ext8s_i64
-#define tcg_gen_ext16u_tl tcg_gen_ext16u_i64
-#define tcg_gen_ext16s_tl tcg_gen_ext16s_i64
-#define tcg_gen_ext32u_tl tcg_gen_ext32u_i64
-#define tcg_gen_ext32s_tl tcg_gen_ext32s_i64
-#define tcg_gen_bswap16_tl tcg_gen_bswap16_i64
-#define tcg_gen_bswap32_tl tcg_gen_bswap32_i64
-#define tcg_gen_bswap64_tl tcg_gen_bswap64_i64
-#define tcg_gen_concat_tl_i64 tcg_gen_concat32_i64
-#define tcg_gen_extr_i64_tl tcg_gen_extr32_i64
-#define tcg_gen_andc_tl tcg_gen_andc_i64
-#define tcg_gen_eqv_tl tcg_gen_eqv_i64
-#define tcg_gen_nand_tl tcg_gen_nand_i64
-#define tcg_gen_nor_tl tcg_gen_nor_i64
-#define tcg_gen_orc_tl tcg_gen_orc_i64
-#define tcg_gen_clz_tl tcg_gen_clz_i64
-#define tcg_gen_ctz_tl tcg_gen_ctz_i64
-#define tcg_gen_clzi_tl tcg_gen_clzi_i64
-#define tcg_gen_ctzi_tl tcg_gen_ctzi_i64
-#define tcg_gen_clrsb_tl tcg_gen_clrsb_i64
-#define tcg_gen_ctpop_tl tcg_gen_ctpop_i64
-#define tcg_gen_rotl_tl tcg_gen_rotl_i64
-#define tcg_gen_rotli_tl tcg_gen_rotli_i64
-#define tcg_gen_rotr_tl tcg_gen_rotr_i64
-#define tcg_gen_rotri_tl tcg_gen_rotri_i64
-#define tcg_gen_deposit_tl tcg_gen_deposit_i64
-#define tcg_gen_deposit_z_tl tcg_gen_deposit_z_i64
-#define tcg_gen_extract_tl tcg_gen_extract_i64
-#define tcg_gen_sextract_tl tcg_gen_sextract_i64
-#define tcg_gen_extract2_tl tcg_gen_extract2_i64
-#define tcg_const_tl tcg_const_i64
-#define tcg_const_local_tl tcg_const_local_i64
-#define tcg_gen_movcond_tl tcg_gen_movcond_i64
-#define tcg_gen_add2_tl tcg_gen_add2_i64
-#define tcg_gen_sub2_tl tcg_gen_sub2_i64
-#define tcg_gen_mulu2_tl tcg_gen_mulu2_i64
-#define tcg_gen_muls2_tl tcg_gen_muls2_i64
-#define tcg_gen_mulsu2_tl tcg_gen_mulsu2_i64
-#define tcg_gen_smin_tl tcg_gen_smin_i64
-#define tcg_gen_umin_tl tcg_gen_umin_i64
-#define tcg_gen_smax_tl tcg_gen_smax_i64
-#define tcg_gen_umax_tl tcg_gen_umax_i64
-#define tcg_gen_atomic_cmpxchg_tl tcg_gen_atomic_cmpxchg_i64
-#define tcg_gen_atomic_xchg_tl tcg_gen_atomic_xchg_i64
-#define tcg_gen_atomic_fetch_add_tl tcg_gen_atomic_fetch_add_i64
-#define tcg_gen_atomic_fetch_and_tl tcg_gen_atomic_fetch_and_i64
-#define tcg_gen_atomic_fetch_or_tl tcg_gen_atomic_fetch_or_i64
-#define tcg_gen_atomic_fetch_xor_tl tcg_gen_atomic_fetch_xor_i64
-#define tcg_gen_atomic_fetch_smin_tl tcg_gen_atomic_fetch_smin_i64
-#define tcg_gen_atomic_fetch_umin_tl tcg_gen_atomic_fetch_umin_i64
-#define tcg_gen_atomic_fetch_smax_tl tcg_gen_atomic_fetch_smax_i64
-#define tcg_gen_atomic_fetch_umax_tl tcg_gen_atomic_fetch_umax_i64
-#define tcg_gen_atomic_add_fetch_tl tcg_gen_atomic_add_fetch_i64
-#define tcg_gen_atomic_and_fetch_tl tcg_gen_atomic_and_fetch_i64
-#define tcg_gen_atomic_or_fetch_tl tcg_gen_atomic_or_fetch_i64
-#define tcg_gen_atomic_xor_fetch_tl tcg_gen_atomic_xor_fetch_i64
-#define tcg_gen_atomic_smin_fetch_tl tcg_gen_atomic_smin_fetch_i64
-#define tcg_gen_atomic_umin_fetch_tl tcg_gen_atomic_umin_fetch_i64
-#define tcg_gen_atomic_smax_fetch_tl tcg_gen_atomic_smax_fetch_i64
-#define tcg_gen_atomic_umax_fetch_tl tcg_gen_atomic_umax_fetch_i64
-#define tcg_gen_dup_tl_vec tcg_gen_dup_i64_vec
-#else
-#define tcg_gen_movi_tl tcg_gen_movi_i32
-#define tcg_gen_mov_tl tcg_gen_mov_i32
-#define tcg_gen_ld8u_tl tcg_gen_ld8u_i32
-#define tcg_gen_ld8s_tl tcg_gen_ld8s_i32
-#define tcg_gen_ld16u_tl tcg_gen_ld16u_i32
-#define tcg_gen_ld16s_tl tcg_gen_ld16s_i32
-#define tcg_gen_ld32u_tl tcg_gen_ld_i32
-#define tcg_gen_ld32s_tl tcg_gen_ld_i32
-#define tcg_gen_ld_tl tcg_gen_ld_i32
-#define tcg_gen_st8_tl tcg_gen_st8_i32
-#define tcg_gen_st16_tl tcg_gen_st16_i32
-#define tcg_gen_st32_tl tcg_gen_st_i32
-#define tcg_gen_st_tl tcg_gen_st_i32
-#define tcg_gen_add_tl tcg_gen_add_i32
-#define tcg_gen_addi_tl tcg_gen_addi_i32
-#define tcg_gen_sub_tl tcg_gen_sub_i32
-#define tcg_gen_neg_tl tcg_gen_neg_i32
-#define tcg_gen_abs_tl tcg_gen_abs_i32
-#define tcg_gen_subfi_tl tcg_gen_subfi_i32
-#define tcg_gen_subi_tl tcg_gen_subi_i32
-#define tcg_gen_and_tl tcg_gen_and_i32
-#define tcg_gen_andi_tl tcg_gen_andi_i32
-#define tcg_gen_or_tl tcg_gen_or_i32
-#define tcg_gen_ori_tl tcg_gen_ori_i32
-#define tcg_gen_xor_tl tcg_gen_xor_i32
-#define tcg_gen_xori_tl tcg_gen_xori_i32
-#define tcg_gen_not_tl tcg_gen_not_i32
-#define tcg_gen_shl_tl tcg_gen_shl_i32
-#define tcg_gen_shli_tl tcg_gen_shli_i32
-#define tcg_gen_shr_tl tcg_gen_shr_i32
-#define tcg_gen_shri_tl tcg_gen_shri_i32
-#define tcg_gen_sar_tl tcg_gen_sar_i32
-#define tcg_gen_sari_tl tcg_gen_sari_i32
-#define tcg_gen_brcond_tl tcg_gen_brcond_i32
-#define tcg_gen_brcondi_tl tcg_gen_brcondi_i32
-#define tcg_gen_setcond_tl tcg_gen_setcond_i32
-#define tcg_gen_setcondi_tl tcg_gen_setcondi_i32
-#define tcg_gen_mul_tl tcg_gen_mul_i32
-#define tcg_gen_muli_tl tcg_gen_muli_i32
-#define tcg_gen_div_tl tcg_gen_div_i32
-#define tcg_gen_rem_tl tcg_gen_rem_i32
-#define tcg_gen_divu_tl tcg_gen_divu_i32
-#define tcg_gen_remu_tl tcg_gen_remu_i32
-#define tcg_gen_discard_tl tcg_gen_discard_i32
-#define tcg_gen_trunc_tl_i32 tcg_gen_mov_i32
-#define tcg_gen_trunc_i64_tl tcg_gen_extrl_i64_i32
-#define tcg_gen_extu_i32_tl tcg_gen_mov_i32
-#define tcg_gen_ext_i32_tl tcg_gen_mov_i32
-#define tcg_gen_extu_tl_i64 tcg_gen_extu_i32_i64
-#define tcg_gen_ext_tl_i64 tcg_gen_ext_i32_i64
-#define tcg_gen_ext8u_tl tcg_gen_ext8u_i32
-#define tcg_gen_ext8s_tl tcg_gen_ext8s_i32
-#define tcg_gen_ext16u_tl tcg_gen_ext16u_i32
-#define tcg_gen_ext16s_tl tcg_gen_ext16s_i32
-#define tcg_gen_ext32u_tl tcg_gen_mov_i32
-#define tcg_gen_ext32s_tl tcg_gen_mov_i32
-#define tcg_gen_bswap16_tl tcg_gen_bswap16_i32
-#define tcg_gen_bswap32_tl tcg_gen_bswap32_i32
-#define tcg_gen_concat_tl_i64 tcg_gen_concat_i32_i64
-#define tcg_gen_extr_i64_tl tcg_gen_extr_i64_i32
-#define tcg_gen_andc_tl tcg_gen_andc_i32
-#define tcg_gen_eqv_tl tcg_gen_eqv_i32
-#define tcg_gen_nand_tl tcg_gen_nand_i32
-#define tcg_gen_nor_tl tcg_gen_nor_i32
-#define tcg_gen_orc_tl tcg_gen_orc_i32
-#define tcg_gen_clz_tl tcg_gen_clz_i32
-#define tcg_gen_ctz_tl tcg_gen_ctz_i32
-#define tcg_gen_clzi_tl tcg_gen_clzi_i32
-#define tcg_gen_ctzi_tl tcg_gen_ctzi_i32
-#define tcg_gen_clrsb_tl tcg_gen_clrsb_i32
-#define tcg_gen_ctpop_tl tcg_gen_ctpop_i32
-#define tcg_gen_rotl_tl tcg_gen_rotl_i32
-#define tcg_gen_rotli_tl tcg_gen_rotli_i32
-#define tcg_gen_rotr_tl tcg_gen_rotr_i32
-#define tcg_gen_rotri_tl tcg_gen_rotri_i32
-#define tcg_gen_deposit_tl tcg_gen_deposit_i32
-#define tcg_gen_deposit_z_tl tcg_gen_deposit_z_i32
-#define tcg_gen_extract_tl tcg_gen_extract_i32
-#define tcg_gen_sextract_tl tcg_gen_sextract_i32
-#define tcg_gen_extract2_tl tcg_gen_extract2_i32
-#define tcg_const_tl tcg_const_i32
-#define tcg_const_local_tl tcg_const_local_i32
-#define tcg_gen_movcond_tl tcg_gen_movcond_i32
-#define tcg_gen_add2_tl tcg_gen_add2_i32
-#define tcg_gen_sub2_tl tcg_gen_sub2_i32
-#define tcg_gen_mulu2_tl tcg_gen_mulu2_i32
-#define tcg_gen_muls2_tl tcg_gen_muls2_i32
-#define tcg_gen_mulsu2_tl tcg_gen_mulsu2_i32
-#define tcg_gen_smin_tl tcg_gen_smin_i32
-#define tcg_gen_umin_tl tcg_gen_umin_i32
-#define tcg_gen_smax_tl tcg_gen_smax_i32
-#define tcg_gen_umax_tl tcg_gen_umax_i32
-#define tcg_gen_atomic_cmpxchg_tl tcg_gen_atomic_cmpxchg_i32
-#define tcg_gen_atomic_xchg_tl tcg_gen_atomic_xchg_i32
-#define tcg_gen_atomic_fetch_add_tl tcg_gen_atomic_fetch_add_i32
-#define tcg_gen_atomic_fetch_and_tl tcg_gen_atomic_fetch_and_i32
-#define tcg_gen_atomic_fetch_or_tl tcg_gen_atomic_fetch_or_i32
-#define tcg_gen_atomic_fetch_xor_tl tcg_gen_atomic_fetch_xor_i32
-#define tcg_gen_atomic_fetch_smin_tl tcg_gen_atomic_fetch_smin_i32
-#define tcg_gen_atomic_fetch_umin_tl tcg_gen_atomic_fetch_umin_i32
-#define tcg_gen_atomic_fetch_smax_tl tcg_gen_atomic_fetch_smax_i32
-#define tcg_gen_atomic_fetch_umax_tl tcg_gen_atomic_fetch_umax_i32
-#define tcg_gen_atomic_add_fetch_tl tcg_gen_atomic_add_fetch_i32
-#define tcg_gen_atomic_and_fetch_tl tcg_gen_atomic_and_fetch_i32
-#define tcg_gen_atomic_or_fetch_tl tcg_gen_atomic_or_fetch_i32
-#define tcg_gen_atomic_xor_fetch_tl tcg_gen_atomic_xor_fetch_i32
-#define tcg_gen_atomic_smin_fetch_tl tcg_gen_atomic_smin_fetch_i32
-#define tcg_gen_atomic_umin_fetch_tl tcg_gen_atomic_umin_fetch_i32
-#define tcg_gen_atomic_smax_fetch_tl tcg_gen_atomic_smax_fetch_i32
-#define tcg_gen_atomic_umax_fetch_tl tcg_gen_atomic_umax_fetch_i32
-#define tcg_gen_dup_tl_vec tcg_gen_dup_i32_vec
-#endif
-
-#if UINTPTR_MAX == UINT32_MAX
-# define PTR i32
-# define NAT TCGv_i32
-#else
-# define PTR i64
-# define NAT TCGv_i64
-#endif
-
-static inline void tcg_gen_ld_ptr(TCGv_ptr r, TCGv_ptr a, intptr_t o)
-{
- glue(tcg_gen_ld_,PTR)((NAT)r, a, o);
-}
-
-static inline void tcg_gen_st_ptr(TCGv_ptr r, TCGv_ptr a, intptr_t o)
-{
- glue(tcg_gen_st_, PTR)((NAT)r, a, o);
-}
-
-static inline void tcg_gen_discard_ptr(TCGv_ptr a)
-{
- glue(tcg_gen_discard_,PTR)((NAT)a);
-}
-
-static inline void tcg_gen_add_ptr(TCGv_ptr r, TCGv_ptr a, TCGv_ptr b)
-{
- glue(tcg_gen_add_,PTR)((NAT)r, (NAT)a, (NAT)b);
-}
-
-static inline void tcg_gen_addi_ptr(TCGv_ptr r, TCGv_ptr a, intptr_t b)
-{
- glue(tcg_gen_addi_,PTR)((NAT)r, (NAT)a, b);
-}
-
-static inline void tcg_gen_brcondi_ptr(TCGCond cond, TCGv_ptr a,
- intptr_t b, TCGLabel *label)
-{
- glue(tcg_gen_brcondi_,PTR)(cond, (NAT)a, b, label);
-}
-
-static inline void tcg_gen_ext_i32_ptr(TCGv_ptr r, TCGv_i32 a)
-{
-#if UINTPTR_MAX == UINT32_MAX
- tcg_gen_mov_i32((NAT)r, a);
-#else
- tcg_gen_ext_i32_i64((NAT)r, a);
-#endif
-}
-
-static inline void tcg_gen_trunc_i64_ptr(TCGv_ptr r, TCGv_i64 a)
-{
-#if UINTPTR_MAX == UINT32_MAX
- tcg_gen_extrl_i64_i32((NAT)r, a);
-#else
- tcg_gen_mov_i64((NAT)r, a);
-#endif
-}
-
-static inline void tcg_gen_extu_ptr_i64(TCGv_i64 r, TCGv_ptr a)
-{
-#if UINTPTR_MAX == UINT32_MAX
- tcg_gen_extu_i32_i64(r, (NAT)a);
-#else
- tcg_gen_mov_i64(r, (NAT)a);
-#endif
-}
-
-static inline void tcg_gen_trunc_ptr_i32(TCGv_i32 r, TCGv_ptr a)
-{
-#if UINTPTR_MAX == UINT32_MAX
- tcg_gen_mov_i32(r, (NAT)a);
-#else
- tcg_gen_extrl_i64_i32(r, (NAT)a);
-#endif
-}
-
-#undef PTR
-#undef NAT
-
-#endif /* TCG_TCG_OP_H */
+++ /dev/null
-/*
- * Tiny Code Generator for QEMU
- *
- * Copyright (c) 2008 Fabrice Bellard
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
- * furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
- * THE SOFTWARE.
- */
-
-/*
- * DEF(name, oargs, iargs, cargs, flags)
- */
-
-/* predefined ops */
-DEF(discard, 1, 0, 0, TCG_OPF_NOT_PRESENT)
-DEF(set_label, 0, 0, 1, TCG_OPF_BB_END | TCG_OPF_NOT_PRESENT)
-
-/* variable number of parameters */
-DEF(call, 0, 0, 3, TCG_OPF_CALL_CLOBBER | TCG_OPF_NOT_PRESENT)
-
-DEF(br, 0, 0, 1, TCG_OPF_BB_END)
-
-#define IMPL(X) (__builtin_constant_p(X) && (X) <= 0 ? TCG_OPF_NOT_PRESENT : 0)
-#if TCG_TARGET_REG_BITS == 32
-# define IMPL64 TCG_OPF_64BIT | TCG_OPF_NOT_PRESENT
-#else
-# define IMPL64 TCG_OPF_64BIT
-#endif
-
-DEF(mb, 0, 0, 1, 0)
-
-DEF(mov_i32, 1, 1, 0, TCG_OPF_NOT_PRESENT)
-DEF(movi_i32, 1, 0, 1, TCG_OPF_NOT_PRESENT)
-DEF(setcond_i32, 1, 2, 1, 0)
-DEF(movcond_i32, 1, 4, 1, IMPL(TCG_TARGET_HAS_movcond_i32))
-/* load/store */
-DEF(ld8u_i32, 1, 1, 1, 0)
-DEF(ld8s_i32, 1, 1, 1, 0)
-DEF(ld16u_i32, 1, 1, 1, 0)
-DEF(ld16s_i32, 1, 1, 1, 0)
-DEF(ld_i32, 1, 1, 1, 0)
-DEF(st8_i32, 0, 2, 1, 0)
-DEF(st16_i32, 0, 2, 1, 0)
-DEF(st_i32, 0, 2, 1, 0)
-/* arith */
-DEF(add_i32, 1, 2, 0, 0)
-DEF(sub_i32, 1, 2, 0, 0)
-DEF(mul_i32, 1, 2, 0, 0)
-DEF(div_i32, 1, 2, 0, IMPL(TCG_TARGET_HAS_div_i32))
-DEF(divu_i32, 1, 2, 0, IMPL(TCG_TARGET_HAS_div_i32))
-DEF(rem_i32, 1, 2, 0, IMPL(TCG_TARGET_HAS_rem_i32))
-DEF(remu_i32, 1, 2, 0, IMPL(TCG_TARGET_HAS_rem_i32))
-DEF(div2_i32, 2, 3, 0, IMPL(TCG_TARGET_HAS_div2_i32))
-DEF(divu2_i32, 2, 3, 0, IMPL(TCG_TARGET_HAS_div2_i32))
-DEF(and_i32, 1, 2, 0, 0)
-DEF(or_i32, 1, 2, 0, 0)
-DEF(xor_i32, 1, 2, 0, 0)
-/* shifts/rotates */
-DEF(shl_i32, 1, 2, 0, 0)
-DEF(shr_i32, 1, 2, 0, 0)
-DEF(sar_i32, 1, 2, 0, 0)
-DEF(rotl_i32, 1, 2, 0, IMPL(TCG_TARGET_HAS_rot_i32))
-DEF(rotr_i32, 1, 2, 0, IMPL(TCG_TARGET_HAS_rot_i32))
-DEF(deposit_i32, 1, 2, 2, IMPL(TCG_TARGET_HAS_deposit_i32))
-DEF(extract_i32, 1, 1, 2, IMPL(TCG_TARGET_HAS_extract_i32))
-DEF(sextract_i32, 1, 1, 2, IMPL(TCG_TARGET_HAS_sextract_i32))
-DEF(extract2_i32, 1, 2, 1, IMPL(TCG_TARGET_HAS_extract2_i32))
-
-DEF(brcond_i32, 0, 2, 2, TCG_OPF_BB_END | TCG_OPF_COND_BRANCH)
-
-DEF(add2_i32, 2, 4, 0, IMPL(TCG_TARGET_HAS_add2_i32))
-DEF(sub2_i32, 2, 4, 0, IMPL(TCG_TARGET_HAS_sub2_i32))
-DEF(mulu2_i32, 2, 2, 0, IMPL(TCG_TARGET_HAS_mulu2_i32))
-DEF(muls2_i32, 2, 2, 0, IMPL(TCG_TARGET_HAS_muls2_i32))
-DEF(muluh_i32, 1, 2, 0, IMPL(TCG_TARGET_HAS_muluh_i32))
-DEF(mulsh_i32, 1, 2, 0, IMPL(TCG_TARGET_HAS_mulsh_i32))
-DEF(brcond2_i32, 0, 4, 2,
- TCG_OPF_BB_END | TCG_OPF_COND_BRANCH | IMPL(TCG_TARGET_REG_BITS == 32))
-DEF(setcond2_i32, 1, 4, 1, IMPL(TCG_TARGET_REG_BITS == 32))
-
-DEF(ext8s_i32, 1, 1, 0, IMPL(TCG_TARGET_HAS_ext8s_i32))
-DEF(ext16s_i32, 1, 1, 0, IMPL(TCG_TARGET_HAS_ext16s_i32))
-DEF(ext8u_i32, 1, 1, 0, IMPL(TCG_TARGET_HAS_ext8u_i32))
-DEF(ext16u_i32, 1, 1, 0, IMPL(TCG_TARGET_HAS_ext16u_i32))
-DEF(bswap16_i32, 1, 1, 0, IMPL(TCG_TARGET_HAS_bswap16_i32))
-DEF(bswap32_i32, 1, 1, 0, IMPL(TCG_TARGET_HAS_bswap32_i32))
-DEF(not_i32, 1, 1, 0, IMPL(TCG_TARGET_HAS_not_i32))
-DEF(neg_i32, 1, 1, 0, IMPL(TCG_TARGET_HAS_neg_i32))
-DEF(andc_i32, 1, 2, 0, IMPL(TCG_TARGET_HAS_andc_i32))
-DEF(orc_i32, 1, 2, 0, IMPL(TCG_TARGET_HAS_orc_i32))
-DEF(eqv_i32, 1, 2, 0, IMPL(TCG_TARGET_HAS_eqv_i32))
-DEF(nand_i32, 1, 2, 0, IMPL(TCG_TARGET_HAS_nand_i32))
-DEF(nor_i32, 1, 2, 0, IMPL(TCG_TARGET_HAS_nor_i32))
-DEF(clz_i32, 1, 2, 0, IMPL(TCG_TARGET_HAS_clz_i32))
-DEF(ctz_i32, 1, 2, 0, IMPL(TCG_TARGET_HAS_ctz_i32))
-DEF(ctpop_i32, 1, 1, 0, IMPL(TCG_TARGET_HAS_ctpop_i32))
-
-DEF(mov_i64, 1, 1, 0, TCG_OPF_64BIT | TCG_OPF_NOT_PRESENT)
-DEF(movi_i64, 1, 0, 1, TCG_OPF_64BIT | TCG_OPF_NOT_PRESENT)
-DEF(setcond_i64, 1, 2, 1, IMPL64)
-DEF(movcond_i64, 1, 4, 1, IMPL64 | IMPL(TCG_TARGET_HAS_movcond_i64))
-/* load/store */
-DEF(ld8u_i64, 1, 1, 1, IMPL64)
-DEF(ld8s_i64, 1, 1, 1, IMPL64)
-DEF(ld16u_i64, 1, 1, 1, IMPL64)
-DEF(ld16s_i64, 1, 1, 1, IMPL64)
-DEF(ld32u_i64, 1, 1, 1, IMPL64)
-DEF(ld32s_i64, 1, 1, 1, IMPL64)
-DEF(ld_i64, 1, 1, 1, IMPL64)
-DEF(st8_i64, 0, 2, 1, IMPL64)
-DEF(st16_i64, 0, 2, 1, IMPL64)
-DEF(st32_i64, 0, 2, 1, IMPL64)
-DEF(st_i64, 0, 2, 1, IMPL64)
-/* arith */
-DEF(add_i64, 1, 2, 0, IMPL64)
-DEF(sub_i64, 1, 2, 0, IMPL64)
-DEF(mul_i64, 1, 2, 0, IMPL64)
-DEF(div_i64, 1, 2, 0, IMPL64 | IMPL(TCG_TARGET_HAS_div_i64))
-DEF(divu_i64, 1, 2, 0, IMPL64 | IMPL(TCG_TARGET_HAS_div_i64))
-DEF(rem_i64, 1, 2, 0, IMPL64 | IMPL(TCG_TARGET_HAS_rem_i64))
-DEF(remu_i64, 1, 2, 0, IMPL64 | IMPL(TCG_TARGET_HAS_rem_i64))
-DEF(div2_i64, 2, 3, 0, IMPL64 | IMPL(TCG_TARGET_HAS_div2_i64))
-DEF(divu2_i64, 2, 3, 0, IMPL64 | IMPL(TCG_TARGET_HAS_div2_i64))
-DEF(and_i64, 1, 2, 0, IMPL64)
-DEF(or_i64, 1, 2, 0, IMPL64)
-DEF(xor_i64, 1, 2, 0, IMPL64)
-/* shifts/rotates */
-DEF(shl_i64, 1, 2, 0, IMPL64)
-DEF(shr_i64, 1, 2, 0, IMPL64)
-DEF(sar_i64, 1, 2, 0, IMPL64)
-DEF(rotl_i64, 1, 2, 0, IMPL64 | IMPL(TCG_TARGET_HAS_rot_i64))
-DEF(rotr_i64, 1, 2, 0, IMPL64 | IMPL(TCG_TARGET_HAS_rot_i64))
-DEF(deposit_i64, 1, 2, 2, IMPL64 | IMPL(TCG_TARGET_HAS_deposit_i64))
-DEF(extract_i64, 1, 1, 2, IMPL64 | IMPL(TCG_TARGET_HAS_extract_i64))
-DEF(sextract_i64, 1, 1, 2, IMPL64 | IMPL(TCG_TARGET_HAS_sextract_i64))
-DEF(extract2_i64, 1, 2, 1, IMPL64 | IMPL(TCG_TARGET_HAS_extract2_i64))
-
-/* size changing ops */
-DEF(ext_i32_i64, 1, 1, 0, IMPL64)
-DEF(extu_i32_i64, 1, 1, 0, IMPL64)
-DEF(extrl_i64_i32, 1, 1, 0,
- IMPL(TCG_TARGET_HAS_extrl_i64_i32)
- | (TCG_TARGET_REG_BITS == 32 ? TCG_OPF_NOT_PRESENT : 0))
-DEF(extrh_i64_i32, 1, 1, 0,
- IMPL(TCG_TARGET_HAS_extrh_i64_i32)
- | (TCG_TARGET_REG_BITS == 32 ? TCG_OPF_NOT_PRESENT : 0))
-
-DEF(brcond_i64, 0, 2, 2, TCG_OPF_BB_END | TCG_OPF_COND_BRANCH | IMPL64)
-DEF(ext8s_i64, 1, 1, 0, IMPL64 | IMPL(TCG_TARGET_HAS_ext8s_i64))
-DEF(ext16s_i64, 1, 1, 0, IMPL64 | IMPL(TCG_TARGET_HAS_ext16s_i64))
-DEF(ext32s_i64, 1, 1, 0, IMPL64 | IMPL(TCG_TARGET_HAS_ext32s_i64))
-DEF(ext8u_i64, 1, 1, 0, IMPL64 | IMPL(TCG_TARGET_HAS_ext8u_i64))
-DEF(ext16u_i64, 1, 1, 0, IMPL64 | IMPL(TCG_TARGET_HAS_ext16u_i64))
-DEF(ext32u_i64, 1, 1, 0, IMPL64 | IMPL(TCG_TARGET_HAS_ext32u_i64))
-DEF(bswap16_i64, 1, 1, 0, IMPL64 | IMPL(TCG_TARGET_HAS_bswap16_i64))
-DEF(bswap32_i64, 1, 1, 0, IMPL64 | IMPL(TCG_TARGET_HAS_bswap32_i64))
-DEF(bswap64_i64, 1, 1, 0, IMPL64 | IMPL(TCG_TARGET_HAS_bswap64_i64))
-DEF(not_i64, 1, 1, 0, IMPL64 | IMPL(TCG_TARGET_HAS_not_i64))
-DEF(neg_i64, 1, 1, 0, IMPL64 | IMPL(TCG_TARGET_HAS_neg_i64))
-DEF(andc_i64, 1, 2, 0, IMPL64 | IMPL(TCG_TARGET_HAS_andc_i64))
-DEF(orc_i64, 1, 2, 0, IMPL64 | IMPL(TCG_TARGET_HAS_orc_i64))
-DEF(eqv_i64, 1, 2, 0, IMPL64 | IMPL(TCG_TARGET_HAS_eqv_i64))
-DEF(nand_i64, 1, 2, 0, IMPL64 | IMPL(TCG_TARGET_HAS_nand_i64))
-DEF(nor_i64, 1, 2, 0, IMPL64 | IMPL(TCG_TARGET_HAS_nor_i64))
-DEF(clz_i64, 1, 2, 0, IMPL64 | IMPL(TCG_TARGET_HAS_clz_i64))
-DEF(ctz_i64, 1, 2, 0, IMPL64 | IMPL(TCG_TARGET_HAS_ctz_i64))
-DEF(ctpop_i64, 1, 1, 0, IMPL64 | IMPL(TCG_TARGET_HAS_ctpop_i64))
-
-DEF(add2_i64, 2, 4, 0, IMPL64 | IMPL(TCG_TARGET_HAS_add2_i64))
-DEF(sub2_i64, 2, 4, 0, IMPL64 | IMPL(TCG_TARGET_HAS_sub2_i64))
-DEF(mulu2_i64, 2, 2, 0, IMPL64 | IMPL(TCG_TARGET_HAS_mulu2_i64))
-DEF(muls2_i64, 2, 2, 0, IMPL64 | IMPL(TCG_TARGET_HAS_muls2_i64))
-DEF(muluh_i64, 1, 2, 0, IMPL64 | IMPL(TCG_TARGET_HAS_muluh_i64))
-DEF(mulsh_i64, 1, 2, 0, IMPL64 | IMPL(TCG_TARGET_HAS_mulsh_i64))
-
-#define TLADDR_ARGS (TARGET_LONG_BITS <= TCG_TARGET_REG_BITS ? 1 : 2)
-#define DATA64_ARGS (TCG_TARGET_REG_BITS == 64 ? 1 : 2)
-
-/* QEMU specific */
-DEF(insn_start, 0, 0, TLADDR_ARGS * TARGET_INSN_START_WORDS,
- TCG_OPF_NOT_PRESENT)
-DEF(exit_tb, 0, 0, 1, TCG_OPF_BB_EXIT | TCG_OPF_BB_END)
-DEF(goto_tb, 0, 0, 1, TCG_OPF_BB_EXIT | TCG_OPF_BB_END)
-DEF(goto_ptr, 0, 1, 0,
- TCG_OPF_BB_EXIT | TCG_OPF_BB_END | IMPL(TCG_TARGET_HAS_goto_ptr))
-
-DEF(plugin_cb_start, 0, 0, 3, TCG_OPF_NOT_PRESENT)
-DEF(plugin_cb_end, 0, 0, 0, TCG_OPF_NOT_PRESENT)
-
-DEF(qemu_ld_i32, 1, TLADDR_ARGS, 1,
- TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS)
-DEF(qemu_st_i32, 0, TLADDR_ARGS + 1, 1,
- TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS)
-DEF(qemu_ld_i64, DATA64_ARGS, TLADDR_ARGS, 1,
- TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS | TCG_OPF_64BIT)
-DEF(qemu_st_i64, 0, TLADDR_ARGS + DATA64_ARGS, 1,
- TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS | TCG_OPF_64BIT)
-
-/* Host vector support. */
-
-#define IMPLVEC TCG_OPF_VECTOR | IMPL(TCG_TARGET_MAYBE_vec)
-
-DEF(mov_vec, 1, 1, 0, TCG_OPF_VECTOR | TCG_OPF_NOT_PRESENT)
-DEF(dupi_vec, 1, 0, 1, TCG_OPF_VECTOR | TCG_OPF_NOT_PRESENT)
-
-DEF(dup_vec, 1, 1, 0, IMPLVEC)
-DEF(dup2_vec, 1, 2, 0, IMPLVEC | IMPL(TCG_TARGET_REG_BITS == 32))
-
-DEF(ld_vec, 1, 1, 1, IMPLVEC)
-DEF(st_vec, 0, 2, 1, IMPLVEC)
-DEF(dupm_vec, 1, 1, 1, IMPLVEC)
-
-DEF(add_vec, 1, 2, 0, IMPLVEC)
-DEF(sub_vec, 1, 2, 0, IMPLVEC)
-DEF(mul_vec, 1, 2, 0, IMPLVEC | IMPL(TCG_TARGET_HAS_mul_vec))
-DEF(neg_vec, 1, 1, 0, IMPLVEC | IMPL(TCG_TARGET_HAS_neg_vec))
-DEF(abs_vec, 1, 1, 0, IMPLVEC | IMPL(TCG_TARGET_HAS_abs_vec))
-DEF(ssadd_vec, 1, 2, 0, IMPLVEC | IMPL(TCG_TARGET_HAS_sat_vec))
-DEF(usadd_vec, 1, 2, 0, IMPLVEC | IMPL(TCG_TARGET_HAS_sat_vec))
-DEF(sssub_vec, 1, 2, 0, IMPLVEC | IMPL(TCG_TARGET_HAS_sat_vec))
-DEF(ussub_vec, 1, 2, 0, IMPLVEC | IMPL(TCG_TARGET_HAS_sat_vec))
-DEF(smin_vec, 1, 2, 0, IMPLVEC | IMPL(TCG_TARGET_HAS_minmax_vec))
-DEF(umin_vec, 1, 2, 0, IMPLVEC | IMPL(TCG_TARGET_HAS_minmax_vec))
-DEF(smax_vec, 1, 2, 0, IMPLVEC | IMPL(TCG_TARGET_HAS_minmax_vec))
-DEF(umax_vec, 1, 2, 0, IMPLVEC | IMPL(TCG_TARGET_HAS_minmax_vec))
-
-DEF(and_vec, 1, 2, 0, IMPLVEC)
-DEF(or_vec, 1, 2, 0, IMPLVEC)
-DEF(xor_vec, 1, 2, 0, IMPLVEC)
-DEF(andc_vec, 1, 2, 0, IMPLVEC | IMPL(TCG_TARGET_HAS_andc_vec))
-DEF(orc_vec, 1, 2, 0, IMPLVEC | IMPL(TCG_TARGET_HAS_orc_vec))
-DEF(not_vec, 1, 1, 0, IMPLVEC | IMPL(TCG_TARGET_HAS_not_vec))
-
-DEF(shli_vec, 1, 1, 1, IMPLVEC | IMPL(TCG_TARGET_HAS_shi_vec))
-DEF(shri_vec, 1, 1, 1, IMPLVEC | IMPL(TCG_TARGET_HAS_shi_vec))
-DEF(sari_vec, 1, 1, 1, IMPLVEC | IMPL(TCG_TARGET_HAS_shi_vec))
-DEF(rotli_vec, 1, 1, 1, IMPLVEC | IMPL(TCG_TARGET_HAS_roti_vec))
-
-DEF(shls_vec, 1, 2, 0, IMPLVEC | IMPL(TCG_TARGET_HAS_shs_vec))
-DEF(shrs_vec, 1, 2, 0, IMPLVEC | IMPL(TCG_TARGET_HAS_shs_vec))
-DEF(sars_vec, 1, 2, 0, IMPLVEC | IMPL(TCG_TARGET_HAS_shs_vec))
-DEF(rotls_vec, 1, 2, 0, IMPLVEC | IMPL(TCG_TARGET_HAS_rots_vec))
-
-DEF(shlv_vec, 1, 2, 0, IMPLVEC | IMPL(TCG_TARGET_HAS_shv_vec))
-DEF(shrv_vec, 1, 2, 0, IMPLVEC | IMPL(TCG_TARGET_HAS_shv_vec))
-DEF(sarv_vec, 1, 2, 0, IMPLVEC | IMPL(TCG_TARGET_HAS_shv_vec))
-DEF(rotlv_vec, 1, 2, 0, IMPLVEC | IMPL(TCG_TARGET_HAS_rotv_vec))
-DEF(rotrv_vec, 1, 2, 0, IMPLVEC | IMPL(TCG_TARGET_HAS_rotv_vec))
-
-DEF(cmp_vec, 1, 2, 1, IMPLVEC)
-
-DEF(bitsel_vec, 1, 3, 0, IMPLVEC | IMPL(TCG_TARGET_HAS_bitsel_vec))
-DEF(cmpsel_vec, 1, 4, 1, IMPLVEC | IMPL(TCG_TARGET_HAS_cmpsel_vec))
-
-DEF(last_generic, 0, 0, 0, TCG_OPF_NOT_PRESENT)
-
-#if TCG_TARGET_MAYBE_vec
-#include "tcg-target.opc.h"
-#endif
-
-#undef TLADDR_ARGS
-#undef DATA64_ARGS
-#undef IMPL
-#undef IMPL64
-#undef IMPLVEC
-#undef DEF
+++ /dev/null
-/*
- * Tiny Code Generator for QEMU
- *
- * Copyright (c) 2008 Fabrice Bellard
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
- * furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
- * THE SOFTWARE.
- */
-
-#ifndef TCG_H
-#define TCG_H
-
-#include "cpu.h"
-#include "exec/memop.h"
-#include "exec/tb-context.h"
-#include "qemu/bitops.h"
-#include "qemu/plugin.h"
-#include "qemu/queue.h"
-#include "tcg/tcg-mo.h"
-#include "tcg-target.h"
-#include "qemu/int128.h"
-
-/* XXX: make safe guess about sizes */
-#define MAX_OP_PER_INSTR 266
-
-#if HOST_LONG_BITS == 32
-#define MAX_OPC_PARAM_PER_ARG 2
-#else
-#define MAX_OPC_PARAM_PER_ARG 1
-#endif
-#define MAX_OPC_PARAM_IARGS 6
-#define MAX_OPC_PARAM_OARGS 1
-#define MAX_OPC_PARAM_ARGS (MAX_OPC_PARAM_IARGS + MAX_OPC_PARAM_OARGS)
-
-/* A Call op needs up to 4 + 2N parameters on 32-bit archs,
- * and up to 4 + N parameters on 64-bit archs
- * (N = number of input arguments + output arguments). */
-#define MAX_OPC_PARAM (4 + (MAX_OPC_PARAM_PER_ARG * MAX_OPC_PARAM_ARGS))
-
-#define CPU_TEMP_BUF_NLONGS 128
-
-/* Default target word size to pointer size. */
-#ifndef TCG_TARGET_REG_BITS
-# if UINTPTR_MAX == UINT32_MAX
-# define TCG_TARGET_REG_BITS 32
-# elif UINTPTR_MAX == UINT64_MAX
-# define TCG_TARGET_REG_BITS 64
-# else
-# error Unknown pointer size for tcg target
-# endif
-#endif
-
-#if TCG_TARGET_REG_BITS == 32
-typedef int32_t tcg_target_long;
-typedef uint32_t tcg_target_ulong;
-#define TCG_PRIlx PRIx32
-#define TCG_PRIld PRId32
-#elif TCG_TARGET_REG_BITS == 64
-typedef int64_t tcg_target_long;
-typedef uint64_t tcg_target_ulong;
-#define TCG_PRIlx PRIx64
-#define TCG_PRIld PRId64
-#else
-#error unsupported
-#endif
-
-/* Oversized TCG guests make things like MTTCG hard
- * as we can't use atomics for cputlb updates.
- */
-#if TARGET_LONG_BITS > TCG_TARGET_REG_BITS
-#define TCG_OVERSIZED_GUEST 1
-#else
-#define TCG_OVERSIZED_GUEST 0
-#endif
-
-#if TCG_TARGET_NB_REGS <= 32
-typedef uint32_t TCGRegSet;
-#elif TCG_TARGET_NB_REGS <= 64
-typedef uint64_t TCGRegSet;
-#else
-#error unsupported
-#endif
-
-#if TCG_TARGET_REG_BITS == 32
-/* Turn some undef macros into false macros. */
-#define TCG_TARGET_HAS_extrl_i64_i32 0
-#define TCG_TARGET_HAS_extrh_i64_i32 0
-#define TCG_TARGET_HAS_div_i64 0
-#define TCG_TARGET_HAS_rem_i64 0
-#define TCG_TARGET_HAS_div2_i64 0
-#define TCG_TARGET_HAS_rot_i64 0
-#define TCG_TARGET_HAS_ext8s_i64 0
-#define TCG_TARGET_HAS_ext16s_i64 0
-#define TCG_TARGET_HAS_ext32s_i64 0
-#define TCG_TARGET_HAS_ext8u_i64 0
-#define TCG_TARGET_HAS_ext16u_i64 0
-#define TCG_TARGET_HAS_ext32u_i64 0
-#define TCG_TARGET_HAS_bswap16_i64 0
-#define TCG_TARGET_HAS_bswap32_i64 0
-#define TCG_TARGET_HAS_bswap64_i64 0
-#define TCG_TARGET_HAS_neg_i64 0
-#define TCG_TARGET_HAS_not_i64 0
-#define TCG_TARGET_HAS_andc_i64 0
-#define TCG_TARGET_HAS_orc_i64 0
-#define TCG_TARGET_HAS_eqv_i64 0
-#define TCG_TARGET_HAS_nand_i64 0
-#define TCG_TARGET_HAS_nor_i64 0
-#define TCG_TARGET_HAS_clz_i64 0
-#define TCG_TARGET_HAS_ctz_i64 0
-#define TCG_TARGET_HAS_ctpop_i64 0
-#define TCG_TARGET_HAS_deposit_i64 0
-#define TCG_TARGET_HAS_extract_i64 0
-#define TCG_TARGET_HAS_sextract_i64 0
-#define TCG_TARGET_HAS_extract2_i64 0
-#define TCG_TARGET_HAS_movcond_i64 0
-#define TCG_TARGET_HAS_add2_i64 0
-#define TCG_TARGET_HAS_sub2_i64 0
-#define TCG_TARGET_HAS_mulu2_i64 0
-#define TCG_TARGET_HAS_muls2_i64 0
-#define TCG_TARGET_HAS_muluh_i64 0
-#define TCG_TARGET_HAS_mulsh_i64 0
-/* Turn some undef macros into true macros. */
-#define TCG_TARGET_HAS_add2_i32 1
-#define TCG_TARGET_HAS_sub2_i32 1
-#endif
-
-#ifndef TCG_TARGET_deposit_i32_valid
-#define TCG_TARGET_deposit_i32_valid(ofs, len) 1
-#endif
-#ifndef TCG_TARGET_deposit_i64_valid
-#define TCG_TARGET_deposit_i64_valid(ofs, len) 1
-#endif
-#ifndef TCG_TARGET_extract_i32_valid
-#define TCG_TARGET_extract_i32_valid(ofs, len) 1
-#endif
-#ifndef TCG_TARGET_extract_i64_valid
-#define TCG_TARGET_extract_i64_valid(ofs, len) 1
-#endif
-
-/* Only one of DIV or DIV2 should be defined. */
-#if defined(TCG_TARGET_HAS_div_i32)
-#define TCG_TARGET_HAS_div2_i32 0
-#elif defined(TCG_TARGET_HAS_div2_i32)
-#define TCG_TARGET_HAS_div_i32 0
-#define TCG_TARGET_HAS_rem_i32 0
-#endif
-#if defined(TCG_TARGET_HAS_div_i64)
-#define TCG_TARGET_HAS_div2_i64 0
-#elif defined(TCG_TARGET_HAS_div2_i64)
-#define TCG_TARGET_HAS_div_i64 0
-#define TCG_TARGET_HAS_rem_i64 0
-#endif
-
-/* For 32-bit targets, some sort of unsigned widening multiply is required. */
-#if TCG_TARGET_REG_BITS == 32 \
- && !(defined(TCG_TARGET_HAS_mulu2_i32) \
- || defined(TCG_TARGET_HAS_muluh_i32))
-# error "Missing unsigned widening multiply"
-#endif
-
-#if !defined(TCG_TARGET_HAS_v64) \
- && !defined(TCG_TARGET_HAS_v128) \
- && !defined(TCG_TARGET_HAS_v256)
-#define TCG_TARGET_MAYBE_vec 0
-#define TCG_TARGET_HAS_abs_vec 0
-#define TCG_TARGET_HAS_neg_vec 0
-#define TCG_TARGET_HAS_not_vec 0
-#define TCG_TARGET_HAS_andc_vec 0
-#define TCG_TARGET_HAS_orc_vec 0
-#define TCG_TARGET_HAS_roti_vec 0
-#define TCG_TARGET_HAS_rots_vec 0
-#define TCG_TARGET_HAS_rotv_vec 0
-#define TCG_TARGET_HAS_shi_vec 0
-#define TCG_TARGET_HAS_shs_vec 0
-#define TCG_TARGET_HAS_shv_vec 0
-#define TCG_TARGET_HAS_mul_vec 0
-#define TCG_TARGET_HAS_sat_vec 0
-#define TCG_TARGET_HAS_minmax_vec 0
-#define TCG_TARGET_HAS_bitsel_vec 0
-#define TCG_TARGET_HAS_cmpsel_vec 0
-#else
-#define TCG_TARGET_MAYBE_vec 1
-#endif
-#ifndef TCG_TARGET_HAS_v64
-#define TCG_TARGET_HAS_v64 0
-#endif
-#ifndef TCG_TARGET_HAS_v128
-#define TCG_TARGET_HAS_v128 0
-#endif
-#ifndef TCG_TARGET_HAS_v256
-#define TCG_TARGET_HAS_v256 0
-#endif
-
-#ifndef TARGET_INSN_START_EXTRA_WORDS
-# define TARGET_INSN_START_WORDS 1
-#else
-# define TARGET_INSN_START_WORDS (1 + TARGET_INSN_START_EXTRA_WORDS)
-#endif
-
-typedef enum TCGOpcode {
-#define DEF(name, oargs, iargs, cargs, flags) INDEX_op_ ## name,
-#include "tcg/tcg-opc.h"
-#undef DEF
- NB_OPS,
-} TCGOpcode;
-
-#define tcg_regset_set_reg(d, r) ((d) |= (TCGRegSet)1 << (r))
-#define tcg_regset_reset_reg(d, r) ((d) &= ~((TCGRegSet)1 << (r)))
-#define tcg_regset_test_reg(d, r) (((d) >> (r)) & 1)
-
-#ifndef TCG_TARGET_INSN_UNIT_SIZE
-# error "Missing TCG_TARGET_INSN_UNIT_SIZE"
-#elif TCG_TARGET_INSN_UNIT_SIZE == 1
-typedef uint8_t tcg_insn_unit;
-#elif TCG_TARGET_INSN_UNIT_SIZE == 2
-typedef uint16_t tcg_insn_unit;
-#elif TCG_TARGET_INSN_UNIT_SIZE == 4
-typedef uint32_t tcg_insn_unit;
-#elif TCG_TARGET_INSN_UNIT_SIZE == 8
-typedef uint64_t tcg_insn_unit;
-#else
-/* The port better have done this. */
-#endif
-
-
-#if defined CONFIG_DEBUG_TCG || defined QEMU_STATIC_ANALYSIS
-# define tcg_debug_assert(X) do { assert(X); } while (0)
-#else
-# define tcg_debug_assert(X) \
- do { if (!(X)) { __builtin_unreachable(); } } while (0)
-#endif
-
-typedef struct TCGRelocation TCGRelocation;
-struct TCGRelocation {
- QSIMPLEQ_ENTRY(TCGRelocation) next;
- tcg_insn_unit *ptr;
- intptr_t addend;
- int type;
-};
-
-typedef struct TCGLabel TCGLabel;
-struct TCGLabel {
- unsigned present : 1;
- unsigned has_value : 1;
- unsigned id : 14;
- unsigned refs : 16;
- union {
- uintptr_t value;
- tcg_insn_unit *value_ptr;
- } u;
- QSIMPLEQ_HEAD(, TCGRelocation) relocs;
- QSIMPLEQ_ENTRY(TCGLabel) next;
-};
-
-typedef struct TCGPool {
- struct TCGPool *next;
- int size;
- uint8_t data[] __attribute__ ((aligned));
-} TCGPool;
-
-#define TCG_POOL_CHUNK_SIZE 32768
-
-#define TCG_MAX_TEMPS 512
-#define TCG_MAX_INSNS 512
-
-/* when the size of the arguments of a called function is smaller than
- this value, they are statically allocated in the TB stack frame */
-#define TCG_STATIC_CALL_ARGS_SIZE 128
-
-typedef enum TCGType {
- TCG_TYPE_I32,
- TCG_TYPE_I64,
-
- TCG_TYPE_V64,
- TCG_TYPE_V128,
- TCG_TYPE_V256,
-
- TCG_TYPE_COUNT, /* number of different types */
-
- /* An alias for the size of the host register. */
-#if TCG_TARGET_REG_BITS == 32
- TCG_TYPE_REG = TCG_TYPE_I32,
-#else
- TCG_TYPE_REG = TCG_TYPE_I64,
-#endif
-
- /* An alias for the size of the native pointer. */
-#if UINTPTR_MAX == UINT32_MAX
- TCG_TYPE_PTR = TCG_TYPE_I32,
-#else
- TCG_TYPE_PTR = TCG_TYPE_I64,
-#endif
-
- /* An alias for the size of the target "long", aka register. */
-#if TARGET_LONG_BITS == 64
- TCG_TYPE_TL = TCG_TYPE_I64,
-#else
- TCG_TYPE_TL = TCG_TYPE_I32,
-#endif
-} TCGType;
-
-/**
- * get_alignment_bits
- * @memop: MemOp value
- *
- * Extract the alignment size from the memop.
- */
-static inline unsigned get_alignment_bits(MemOp memop)
-{
- unsigned a = memop & MO_AMASK;
-
- if (a == MO_UNALN) {
- /* No alignment required. */
- a = 0;
- } else if (a == MO_ALIGN) {
- /* A natural alignment requirement. */
- a = memop & MO_SIZE;
- } else {
- /* A specific alignment requirement. */
- a = a >> MO_ASHIFT;
- }
-#if defined(CONFIG_SOFTMMU)
- /* The requested alignment cannot overlap the TLB flags. */
- tcg_debug_assert((TLB_FLAGS_MASK & ((1 << a) - 1)) == 0);
-#endif
- return a;
-}
-
-typedef tcg_target_ulong TCGArg;
-
-/* Define type and accessor macros for TCG variables.
-
- TCG variables are the inputs and outputs of TCG ops, as described
- in tcg/README. Target CPU front-end code uses these types to deal
- with TCG variables as it emits TCG code via the tcg_gen_* functions.
- They come in several flavours:
- * TCGv_i32 : 32 bit integer type
- * TCGv_i64 : 64 bit integer type
- * TCGv_ptr : a host pointer type
- * TCGv_vec : a host vector type; the exact size is not exposed
- to the CPU front-end code.
- * TCGv : an integer type the same size as target_ulong
- (an alias for either TCGv_i32 or TCGv_i64)
- The compiler's type checking will complain if you mix them
- up and pass the wrong sized TCGv to a function.
-
- Users of tcg_gen_* don't need to know about any of the internal
- details of these, and should treat them as opaque types.
- You won't be able to look inside them in a debugger either.
-
- Internal implementation details follow:
-
- Note that there is no definition of the structs TCGv_i32_d etc anywhere.
- This is deliberate, because the values we store in variables of type
- TCGv_i32 are not really pointers-to-structures. They're just small
- integers, but keeping them in pointer types like this means that the
- compiler will complain if you accidentally pass a TCGv_i32 to a
- function which takes a TCGv_i64, and so on. Only the internals of
- TCG need to care about the actual contents of the types. */
-
-typedef struct TCGv_i32_d *TCGv_i32;
-typedef struct TCGv_i64_d *TCGv_i64;
-typedef struct TCGv_ptr_d *TCGv_ptr;
-typedef struct TCGv_vec_d *TCGv_vec;
-typedef TCGv_ptr TCGv_env;
-#if TARGET_LONG_BITS == 32
-#define TCGv TCGv_i32
-#elif TARGET_LONG_BITS == 64
-#define TCGv TCGv_i64
-#else
-#error Unhandled TARGET_LONG_BITS value
-#endif
-
-/* call flags */
-/* Helper does not read globals (either directly or through an exception). It
- implies TCG_CALL_NO_WRITE_GLOBALS. */
-#define TCG_CALL_NO_READ_GLOBALS 0x0001
-/* Helper does not write globals */
-#define TCG_CALL_NO_WRITE_GLOBALS 0x0002
-/* Helper can be safely suppressed if the return value is not used. */
-#define TCG_CALL_NO_SIDE_EFFECTS 0x0004
-/* Helper is QEMU_NORETURN. */
-#define TCG_CALL_NO_RETURN 0x0008
-
-/* convenience version of most used call flags */
-#define TCG_CALL_NO_RWG TCG_CALL_NO_READ_GLOBALS
-#define TCG_CALL_NO_WG TCG_CALL_NO_WRITE_GLOBALS
-#define TCG_CALL_NO_SE TCG_CALL_NO_SIDE_EFFECTS
-#define TCG_CALL_NO_RWG_SE (TCG_CALL_NO_RWG | TCG_CALL_NO_SE)
-#define TCG_CALL_NO_WG_SE (TCG_CALL_NO_WG | TCG_CALL_NO_SE)
-
-/* Used to align parameters. See the comment before tcgv_i32_temp. */
-#define TCG_CALL_DUMMY_ARG ((TCGArg)0)
-
-/* Conditions. Note that these are laid out for easy manipulation by
- the functions below:
- bit 0 is used for inverting;
- bit 1 is signed,
- bit 2 is unsigned,
- bit 3 is used with bit 0 for swapping signed/unsigned. */
-typedef enum {
- /* non-signed */
- TCG_COND_NEVER = 0 | 0 | 0 | 0,
- TCG_COND_ALWAYS = 0 | 0 | 0 | 1,
- TCG_COND_EQ = 8 | 0 | 0 | 0,
- TCG_COND_NE = 8 | 0 | 0 | 1,
- /* signed */
- TCG_COND_LT = 0 | 0 | 2 | 0,
- TCG_COND_GE = 0 | 0 | 2 | 1,
- TCG_COND_LE = 8 | 0 | 2 | 0,
- TCG_COND_GT = 8 | 0 | 2 | 1,
- /* unsigned */
- TCG_COND_LTU = 0 | 4 | 0 | 0,
- TCG_COND_GEU = 0 | 4 | 0 | 1,
- TCG_COND_LEU = 8 | 4 | 0 | 0,
- TCG_COND_GTU = 8 | 4 | 0 | 1,
-} TCGCond;
-
-/* Invert the sense of the comparison. */
-static inline TCGCond tcg_invert_cond(TCGCond c)
-{
- return (TCGCond)(c ^ 1);
-}
-
-/* Swap the operands in a comparison. */
-static inline TCGCond tcg_swap_cond(TCGCond c)
-{
- return c & 6 ? (TCGCond)(c ^ 9) : c;
-}
-
-/* Create an "unsigned" version of a "signed" comparison. */
-static inline TCGCond tcg_unsigned_cond(TCGCond c)
-{
- return c & 2 ? (TCGCond)(c ^ 6) : c;
-}
-
-/* Create a "signed" version of an "unsigned" comparison. */
-static inline TCGCond tcg_signed_cond(TCGCond c)
-{
- return c & 4 ? (TCGCond)(c ^ 6) : c;
-}
-
-/* Must a comparison be considered unsigned? */
-static inline bool is_unsigned_cond(TCGCond c)
-{
- return (c & 4) != 0;
-}
-
-/* Create a "high" version of a double-word comparison.
- This removes equality from a LTE or GTE comparison. */
-static inline TCGCond tcg_high_cond(TCGCond c)
-{
- switch (c) {
- case TCG_COND_GE:
- case TCG_COND_LE:
- case TCG_COND_GEU:
- case TCG_COND_LEU:
- return (TCGCond)(c ^ 8);
- default:
- return c;
- }
-}
-
-typedef enum TCGTempVal {
- TEMP_VAL_DEAD,
- TEMP_VAL_REG,
- TEMP_VAL_MEM,
- TEMP_VAL_CONST,
-} TCGTempVal;
-
-typedef struct TCGTemp {
- TCGReg reg:8;
- TCGTempVal val_type:8;
- TCGType base_type:8;
- TCGType type:8;
- unsigned int fixed_reg:1;
- unsigned int indirect_reg:1;
- unsigned int indirect_base:1;
- unsigned int mem_coherent:1;
- unsigned int mem_allocated:1;
- /* If true, the temp is saved across both basic blocks and
- translation blocks. */
- unsigned int temp_global:1;
- /* If true, the temp is saved across basic blocks but dead
- at the end of translation blocks. If false, the temp is
- dead at the end of basic blocks. */
- unsigned int temp_local:1;
- unsigned int temp_allocated:1;
-
- tcg_target_long val;
- struct TCGTemp *mem_base;
- intptr_t mem_offset;
- const char *name;
-
- /* Pass-specific information that can be stored for a temporary.
- One word worth of integer data, and one pointer to data
- allocated separately. */
- uintptr_t state;
- void *state_ptr;
-} TCGTemp;
-
-typedef struct TCGContext TCGContext;
-
-typedef struct TCGTempSet {
- unsigned long l[BITS_TO_LONGS(TCG_MAX_TEMPS)];
-} TCGTempSet;
-
-/* While we limit helpers to 6 arguments, for 32-bit hosts, with padding,
- this imples a max of 6*2 (64-bit in) + 2 (64-bit out) = 14 operands.
- There are never more than 2 outputs, which means that we can store all
- dead + sync data within 16 bits. */
-#define DEAD_ARG 4
-#define SYNC_ARG 1
-typedef uint16_t TCGLifeData;
-
-/* The layout here is designed to avoid a bitfield crossing of
- a 32-bit boundary, which would cause GCC to add extra padding. */
-typedef struct TCGOp {
- TCGOpcode opc : 8; /* 8 */
-
- /* Parameters for this opcode. See below. */
- unsigned param1 : 4; /* 12 */
- unsigned param2 : 4; /* 16 */
-
- /* Lifetime data of the operands. */
- unsigned life : 16; /* 32 */
-
- /* Next and previous opcodes. */
- QTAILQ_ENTRY(TCGOp) link;
-#ifdef CONFIG_PLUGIN
- QSIMPLEQ_ENTRY(TCGOp) plugin_link;
-#endif
-
- /* Arguments for the opcode. */
- TCGArg args[MAX_OPC_PARAM];
-
- /* Register preferences for the output(s). */
- TCGRegSet output_pref[2];
-} TCGOp;
-
-#define TCGOP_CALLI(X) (X)->param1
-#define TCGOP_CALLO(X) (X)->param2
-
-#define TCGOP_VECL(X) (X)->param1
-#define TCGOP_VECE(X) (X)->param2
-
-/* Make sure operands fit in the bitfields above. */
-QEMU_BUILD_BUG_ON(NB_OPS > (1 << 8));
-
-typedef struct TCGProfile {
- int64_t cpu_exec_time;
- int64_t tb_count1;
- int64_t tb_count;
- int64_t op_count; /* total insn count */
- int op_count_max; /* max insn per TB */
- int temp_count_max;
- int64_t temp_count;
- int64_t del_op_count;
- int64_t code_in_len;
- int64_t code_out_len;
- int64_t search_out_len;
- int64_t interm_time;
- int64_t code_time;
- int64_t la_time;
- int64_t opt_time;
- int64_t restore_count;
- int64_t restore_time;
- int64_t table_op_count[NB_OPS];
-} TCGProfile;
-
-struct TCGContext {
- uint8_t *pool_cur, *pool_end;
- TCGPool *pool_first, *pool_current, *pool_first_large;
- int nb_labels;
- int nb_globals;
- int nb_temps;
- int nb_indirects;
- int nb_ops;
-
- /* goto_tb support */
- tcg_insn_unit *code_buf;
- uint16_t *tb_jmp_reset_offset; /* tb->jmp_reset_offset */
- uintptr_t *tb_jmp_insn_offset; /* tb->jmp_target_arg if direct_jump */
- uintptr_t *tb_jmp_target_addr; /* tb->jmp_target_arg if !direct_jump */
-
- TCGRegSet reserved_regs;
- uint32_t tb_cflags; /* cflags of the current TB */
- intptr_t current_frame_offset;
- intptr_t frame_start;
- intptr_t frame_end;
- TCGTemp *frame_temp;
-
- tcg_insn_unit *code_ptr;
-
-#ifdef CONFIG_PROFILER
- TCGProfile prof;
-#endif
-
-#ifdef CONFIG_DEBUG_TCG
- int temps_in_use;
- int goto_tb_issue_mask;
- const TCGOpcode *vecop_list;
-#endif
-
- /* Code generation. Note that we specifically do not use tcg_insn_unit
- here, because there's too much arithmetic throughout that relies
- on addition and subtraction working on bytes. Rely on the GCC
- extension that allows arithmetic on void*. */
- void *code_gen_prologue;
- void *code_gen_epilogue;
- void *code_gen_buffer;
- size_t code_gen_buffer_size;
- void *code_gen_ptr;
- void *data_gen_ptr;
-
- /* Threshold to flush the translated code buffer. */
- void *code_gen_highwater;
-
- size_t tb_phys_invalidate_count;
-
- /* Track which vCPU triggers events */
- CPUState *cpu; /* *_trans */
-
- /* These structures are private to tcg-target.c.inc. */
-#ifdef TCG_TARGET_NEED_LDST_LABELS
- QSIMPLEQ_HEAD(, TCGLabelQemuLdst) ldst_labels;
-#endif
-#ifdef TCG_TARGET_NEED_POOL_LABELS
- struct TCGLabelPoolData *pool_labels;
-#endif
-
- TCGLabel *exitreq_label;
-
-#ifdef CONFIG_PLUGIN
- /*
- * We keep one plugin_tb struct per TCGContext. Note that on every TB
- * translation we clear but do not free its contents; this way we
- * avoid a lot of malloc/free churn, since after a few TB's it's
- * unlikely that we'll need to allocate either more instructions or more
- * space for instructions (for variable-instruction-length ISAs).
- */
- struct qemu_plugin_tb *plugin_tb;
-
- /* descriptor of the instruction being translated */
- struct qemu_plugin_insn *plugin_insn;
-
- /* list to quickly access the injected ops */
- QSIMPLEQ_HEAD(, TCGOp) plugin_ops;
-#endif
-
- TCGTempSet free_temps[TCG_TYPE_COUNT * 2];
- TCGTemp temps[TCG_MAX_TEMPS]; /* globals first, temps after */
-
- QTAILQ_HEAD(, TCGOp) ops, free_ops;
- QSIMPLEQ_HEAD(, TCGLabel) labels;
-
- /* Tells which temporary holds a given register.
- It does not take into account fixed registers */
- TCGTemp *reg_to_temp[TCG_TARGET_NB_REGS];
-
- uint16_t gen_insn_end_off[TCG_MAX_INSNS];
- target_ulong gen_insn_data[TCG_MAX_INSNS][TARGET_INSN_START_WORDS];
-};
-
-extern TCGContext tcg_init_ctx;
-extern __thread TCGContext *tcg_ctx;
-extern TCGv_env cpu_env;
-
-static inline size_t temp_idx(TCGTemp *ts)
-{
- ptrdiff_t n = ts - tcg_ctx->temps;
- tcg_debug_assert(n >= 0 && n < tcg_ctx->nb_temps);
- return n;
-}
-
-static inline TCGArg temp_arg(TCGTemp *ts)
-{
- return (uintptr_t)ts;
-}
-
-static inline TCGTemp *arg_temp(TCGArg a)
-{
- return (TCGTemp *)(uintptr_t)a;
-}
-
-/* Using the offset of a temporary, relative to TCGContext, rather than
- its index means that we don't use 0. That leaves offset 0 free for
- a NULL representation without having to leave index 0 unused. */
-static inline TCGTemp *tcgv_i32_temp(TCGv_i32 v)
-{
- uintptr_t o = (uintptr_t)v;
- TCGTemp *t = (void *)tcg_ctx + o;
- tcg_debug_assert(offsetof(TCGContext, temps[temp_idx(t)]) == o);
- return t;
-}
-
-static inline TCGTemp *tcgv_i64_temp(TCGv_i64 v)
-{
- return tcgv_i32_temp((TCGv_i32)v);
-}
-
-static inline TCGTemp *tcgv_ptr_temp(TCGv_ptr v)
-{
- return tcgv_i32_temp((TCGv_i32)v);
-}
-
-static inline TCGTemp *tcgv_vec_temp(TCGv_vec v)
-{
- return tcgv_i32_temp((TCGv_i32)v);
-}
-
-static inline TCGArg tcgv_i32_arg(TCGv_i32 v)
-{
- return temp_arg(tcgv_i32_temp(v));
-}
-
-static inline TCGArg tcgv_i64_arg(TCGv_i64 v)
-{
- return temp_arg(tcgv_i64_temp(v));
-}
-
-static inline TCGArg tcgv_ptr_arg(TCGv_ptr v)
-{
- return temp_arg(tcgv_ptr_temp(v));
-}
-
-static inline TCGArg tcgv_vec_arg(TCGv_vec v)
-{
- return temp_arg(tcgv_vec_temp(v));
-}
-
-static inline TCGv_i32 temp_tcgv_i32(TCGTemp *t)
-{
- (void)temp_idx(t); /* trigger embedded assert */
- return (TCGv_i32)((void *)t - (void *)tcg_ctx);
-}
-
-static inline TCGv_i64 temp_tcgv_i64(TCGTemp *t)
-{
- return (TCGv_i64)temp_tcgv_i32(t);
-}
-
-static inline TCGv_ptr temp_tcgv_ptr(TCGTemp *t)
-{
- return (TCGv_ptr)temp_tcgv_i32(t);
-}
-
-static inline TCGv_vec temp_tcgv_vec(TCGTemp *t)
-{
- return (TCGv_vec)temp_tcgv_i32(t);
-}
-
-#if TCG_TARGET_REG_BITS == 32
-static inline TCGv_i32 TCGV_LOW(TCGv_i64 t)
-{
- return temp_tcgv_i32(tcgv_i64_temp(t));
-}
-
-static inline TCGv_i32 TCGV_HIGH(TCGv_i64 t)
-{
- return temp_tcgv_i32(tcgv_i64_temp(t) + 1);
-}
-#endif
-
-static inline TCGArg tcg_get_insn_param(TCGOp *op, int arg)
-{
- return op->args[arg];
-}
-
-static inline void tcg_set_insn_param(TCGOp *op, int arg, TCGArg v)
-{
- op->args[arg] = v;
-}
-
-static inline target_ulong tcg_get_insn_start_param(TCGOp *op, int arg)
-{
-#if TARGET_LONG_BITS <= TCG_TARGET_REG_BITS
- return tcg_get_insn_param(op, arg);
-#else
- return tcg_get_insn_param(op, arg * 2) |
- ((uint64_t)tcg_get_insn_param(op, arg * 2 + 1) << 32);
-#endif
-}
-
-static inline void tcg_set_insn_start_param(TCGOp *op, int arg, target_ulong v)
-{
-#if TARGET_LONG_BITS <= TCG_TARGET_REG_BITS
- tcg_set_insn_param(op, arg, v);
-#else
- tcg_set_insn_param(op, arg * 2, v);
- tcg_set_insn_param(op, arg * 2 + 1, v >> 32);
-#endif
-}
-
-/* The last op that was emitted. */
-static inline TCGOp *tcg_last_op(void)
-{
- return QTAILQ_LAST(&tcg_ctx->ops);
-}
-
-/* Test for whether to terminate the TB for using too many opcodes. */
-static inline bool tcg_op_buf_full(void)
-{
- /* This is not a hard limit, it merely stops translation when
- * we have produced "enough" opcodes. We want to limit TB size
- * such that a RISC host can reasonably use a 16-bit signed
- * branch within the TB. We also need to be mindful of the
- * 16-bit unsigned offsets, TranslationBlock.jmp_reset_offset[]
- * and TCGContext.gen_insn_end_off[].
- */
- return tcg_ctx->nb_ops >= 4000;
-}
-
-/* pool based memory allocation */
-
-/* user-mode: mmap_lock must be held for tcg_malloc_internal. */
-void *tcg_malloc_internal(TCGContext *s, int size);
-void tcg_pool_reset(TCGContext *s);
-TranslationBlock *tcg_tb_alloc(TCGContext *s);
-
-void tcg_region_init(void);
-void tb_destroy(TranslationBlock *tb);
-void tcg_region_reset_all(void);
-
-size_t tcg_code_size(void);
-size_t tcg_code_capacity(void);
-
-void tcg_tb_insert(TranslationBlock *tb);
-void tcg_tb_remove(TranslationBlock *tb);
-size_t tcg_tb_phys_invalidate_count(void);
-TranslationBlock *tcg_tb_lookup(uintptr_t tc_ptr);
-void tcg_tb_foreach(GTraverseFunc func, gpointer user_data);
-size_t tcg_nb_tbs(void);
-
-/* user-mode: Called with mmap_lock held. */
-static inline void *tcg_malloc(int size)
-{
- TCGContext *s = tcg_ctx;
- uint8_t *ptr, *ptr_end;
-
- /* ??? This is a weak placeholder for minimum malloc alignment. */
- size = QEMU_ALIGN_UP(size, 8);
-
- ptr = s->pool_cur;
- ptr_end = ptr + size;
- if (unlikely(ptr_end > s->pool_end)) {
- return tcg_malloc_internal(tcg_ctx, size);
- } else {
- s->pool_cur = ptr_end;
- return ptr;
- }
-}
-
-void tcg_context_init(TCGContext *s);
-void tcg_register_thread(void);
-void tcg_prologue_init(TCGContext *s);
-void tcg_func_start(TCGContext *s);
-
-int tcg_gen_code(TCGContext *s, TranslationBlock *tb);
-
-void tcg_set_frame(TCGContext *s, TCGReg reg, intptr_t start, intptr_t size);
-
-TCGTemp *tcg_global_mem_new_internal(TCGType, TCGv_ptr,
- intptr_t, const char *);
-TCGTemp *tcg_temp_new_internal(TCGType, bool);
-void tcg_temp_free_internal(TCGTemp *);
-TCGv_vec tcg_temp_new_vec(TCGType type);
-TCGv_vec tcg_temp_new_vec_matching(TCGv_vec match);
-
-static inline void tcg_temp_free_i32(TCGv_i32 arg)
-{
- tcg_temp_free_internal(tcgv_i32_temp(arg));
-}
-
-static inline void tcg_temp_free_i64(TCGv_i64 arg)
-{
- tcg_temp_free_internal(tcgv_i64_temp(arg));
-}
-
-static inline void tcg_temp_free_ptr(TCGv_ptr arg)
-{
- tcg_temp_free_internal(tcgv_ptr_temp(arg));
-}
-
-static inline void tcg_temp_free_vec(TCGv_vec arg)
-{
- tcg_temp_free_internal(tcgv_vec_temp(arg));
-}
-
-static inline TCGv_i32 tcg_global_mem_new_i32(TCGv_ptr reg, intptr_t offset,
- const char *name)
-{
- TCGTemp *t = tcg_global_mem_new_internal(TCG_TYPE_I32, reg, offset, name);
- return temp_tcgv_i32(t);
-}
-
-static inline TCGv_i32 tcg_temp_new_i32(void)
-{
- TCGTemp *t = tcg_temp_new_internal(TCG_TYPE_I32, false);
- return temp_tcgv_i32(t);
-}
-
-static inline TCGv_i32 tcg_temp_local_new_i32(void)
-{
- TCGTemp *t = tcg_temp_new_internal(TCG_TYPE_I32, true);
- return temp_tcgv_i32(t);
-}
-
-static inline TCGv_i64 tcg_global_mem_new_i64(TCGv_ptr reg, intptr_t offset,
- const char *name)
-{
- TCGTemp *t = tcg_global_mem_new_internal(TCG_TYPE_I64, reg, offset, name);
- return temp_tcgv_i64(t);
-}
-
-static inline TCGv_i64 tcg_temp_new_i64(void)
-{
- TCGTemp *t = tcg_temp_new_internal(TCG_TYPE_I64, false);
- return temp_tcgv_i64(t);
-}
-
-static inline TCGv_i64 tcg_temp_local_new_i64(void)
-{
- TCGTemp *t = tcg_temp_new_internal(TCG_TYPE_I64, true);
- return temp_tcgv_i64(t);
-}
-
-static inline TCGv_ptr tcg_global_mem_new_ptr(TCGv_ptr reg, intptr_t offset,
- const char *name)
-{
- TCGTemp *t = tcg_global_mem_new_internal(TCG_TYPE_PTR, reg, offset, name);
- return temp_tcgv_ptr(t);
-}
-
-static inline TCGv_ptr tcg_temp_new_ptr(void)
-{
- TCGTemp *t = tcg_temp_new_internal(TCG_TYPE_PTR, false);
- return temp_tcgv_ptr(t);
-}
-
-static inline TCGv_ptr tcg_temp_local_new_ptr(void)
-{
- TCGTemp *t = tcg_temp_new_internal(TCG_TYPE_PTR, true);
- return temp_tcgv_ptr(t);
-}
-
-#if defined(CONFIG_DEBUG_TCG)
-/* If you call tcg_clear_temp_count() at the start of a section of
- * code which is not supposed to leak any TCG temporaries, then
- * calling tcg_check_temp_count() at the end of the section will
- * return 1 if the section did in fact leak a temporary.
- */
-void tcg_clear_temp_count(void);
-int tcg_check_temp_count(void);
-#else
-#define tcg_clear_temp_count() do { } while (0)
-#define tcg_check_temp_count() 0
-#endif
-
-int64_t tcg_cpu_exec_time(void);
-void tcg_dump_info(void);
-void tcg_dump_op_count(void);
-
-#define TCG_CT_CONST 1 /* any constant of register size */
-
-typedef struct TCGArgConstraint {
- unsigned ct : 16;
- unsigned alias_index : 4;
- unsigned sort_index : 4;
- bool oalias : 1;
- bool ialias : 1;
- bool newreg : 1;
- TCGRegSet regs;
-} TCGArgConstraint;
-
-#define TCG_MAX_OP_ARGS 16
-
-/* Bits for TCGOpDef->flags, 8 bits available, all used. */
-enum {
- /* Instruction exits the translation block. */
- TCG_OPF_BB_EXIT = 0x01,
- /* Instruction defines the end of a basic block. */
- TCG_OPF_BB_END = 0x02,
- /* Instruction clobbers call registers and potentially update globals. */
- TCG_OPF_CALL_CLOBBER = 0x04,
- /* Instruction has side effects: it cannot be removed if its outputs
- are not used, and might trigger exceptions. */
- TCG_OPF_SIDE_EFFECTS = 0x08,
- /* Instruction operands are 64-bits (otherwise 32-bits). */
- TCG_OPF_64BIT = 0x10,
- /* Instruction is optional and not implemented by the host, or insn
- is generic and should not be implemened by the host. */
- TCG_OPF_NOT_PRESENT = 0x20,
- /* Instruction operands are vectors. */
- TCG_OPF_VECTOR = 0x40,
- /* Instruction is a conditional branch. */
- TCG_OPF_COND_BRANCH = 0x80
-};
-
-typedef struct TCGOpDef {
- const char *name;
- uint8_t nb_oargs, nb_iargs, nb_cargs, nb_args;
- uint8_t flags;
- TCGArgConstraint *args_ct;
-} TCGOpDef;
-
-extern TCGOpDef tcg_op_defs[];
-extern const size_t tcg_op_defs_max;
-
-typedef struct TCGTargetOpDef {
- TCGOpcode op;
- const char *args_ct_str[TCG_MAX_OP_ARGS];
-} TCGTargetOpDef;
-
-#define tcg_abort() \
-do {\
- fprintf(stderr, "%s:%d: tcg fatal error\n", __FILE__, __LINE__);\
- abort();\
-} while (0)
-
-bool tcg_op_supported(TCGOpcode op);
-
-void tcg_gen_callN(void *func, TCGTemp *ret, int nargs, TCGTemp **args);
-
-TCGOp *tcg_emit_op(TCGOpcode opc);
-void tcg_op_remove(TCGContext *s, TCGOp *op);
-TCGOp *tcg_op_insert_before(TCGContext *s, TCGOp *op, TCGOpcode opc);
-TCGOp *tcg_op_insert_after(TCGContext *s, TCGOp *op, TCGOpcode opc);
-
-void tcg_optimize(TCGContext *s);
-
-TCGv_i32 tcg_const_i32(int32_t val);
-TCGv_i64 tcg_const_i64(int64_t val);
-TCGv_i32 tcg_const_local_i32(int32_t val);
-TCGv_i64 tcg_const_local_i64(int64_t val);
-TCGv_vec tcg_const_zeros_vec(TCGType);
-TCGv_vec tcg_const_ones_vec(TCGType);
-TCGv_vec tcg_const_zeros_vec_matching(TCGv_vec);
-TCGv_vec tcg_const_ones_vec_matching(TCGv_vec);
-
-#if UINTPTR_MAX == UINT32_MAX
-# define tcg_const_ptr(x) ((TCGv_ptr)tcg_const_i32((intptr_t)(x)))
-# define tcg_const_local_ptr(x) ((TCGv_ptr)tcg_const_local_i32((intptr_t)(x)))
-#else
-# define tcg_const_ptr(x) ((TCGv_ptr)tcg_const_i64((intptr_t)(x)))
-# define tcg_const_local_ptr(x) ((TCGv_ptr)tcg_const_local_i64((intptr_t)(x)))
-#endif
-
-TCGLabel *gen_new_label(void);
-
-/**
- * label_arg
- * @l: label
- *
- * Encode a label for storage in the TCG opcode stream.
- */
-
-static inline TCGArg label_arg(TCGLabel *l)
-{
- return (uintptr_t)l;
-}
-
-/**
- * arg_label
- * @i: value
- *
- * The opposite of label_arg. Retrieve a label from the
- * encoding of the TCG opcode stream.
- */
-
-static inline TCGLabel *arg_label(TCGArg i)
-{
- return (TCGLabel *)(uintptr_t)i;
-}
-
-/**
- * tcg_ptr_byte_diff
- * @a, @b: addresses to be differenced
- *
- * There are many places within the TCG backends where we need a byte
- * difference between two pointers. While this can be accomplished
- * with local casting, it's easy to get wrong -- especially if one is
- * concerned with the signedness of the result.
- *
- * This version relies on GCC's void pointer arithmetic to get the
- * correct result.
- */
-
-static inline ptrdiff_t tcg_ptr_byte_diff(void *a, void *b)
-{
- return a - b;
-}
-
-/**
- * tcg_pcrel_diff
- * @s: the tcg context
- * @target: address of the target
- *
- * Produce a pc-relative difference, from the current code_ptr
- * to the destination address.
- */
-
-static inline ptrdiff_t tcg_pcrel_diff(TCGContext *s, void *target)
-{
- return tcg_ptr_byte_diff(target, s->code_ptr);
-}
-
-/**
- * tcg_current_code_size
- * @s: the tcg context
- *
- * Compute the current code size within the translation block.
- * This is used to fill in qemu's data structures for goto_tb.
- */
-
-static inline size_t tcg_current_code_size(TCGContext *s)
-{
- return tcg_ptr_byte_diff(s->code_ptr, s->code_buf);
-}
-
-/* Combine the MemOp and mmu_idx parameters into a single value. */
-typedef uint32_t TCGMemOpIdx;
-
-/**
- * make_memop_idx
- * @op: memory operation
- * @idx: mmu index
- *
- * Encode these values into a single parameter.
- */
-static inline TCGMemOpIdx make_memop_idx(MemOp op, unsigned idx)
-{
- tcg_debug_assert(idx <= 15);
- return (op << 4) | idx;
-}
-
-/**
- * get_memop
- * @oi: combined op/idx parameter
- *
- * Extract the memory operation from the combined value.
- */
-static inline MemOp get_memop(TCGMemOpIdx oi)
-{
- return oi >> 4;
-}
-
-/**
- * get_mmuidx
- * @oi: combined op/idx parameter
- *
- * Extract the mmu index from the combined value.
- */
-static inline unsigned get_mmuidx(TCGMemOpIdx oi)
-{
- return oi & 15;
-}
-
-/**
- * tcg_qemu_tb_exec:
- * @env: pointer to CPUArchState for the CPU
- * @tb_ptr: address of generated code for the TB to execute
- *
- * Start executing code from a given translation block.
- * Where translation blocks have been linked, execution
- * may proceed from the given TB into successive ones.
- * Control eventually returns only when some action is needed
- * from the top-level loop: either control must pass to a TB
- * which has not yet been directly linked, or an asynchronous
- * event such as an interrupt needs handling.
- *
- * Return: The return value is the value passed to the corresponding
- * tcg_gen_exit_tb() at translation time of the last TB attempted to execute.
- * The value is either zero or a 4-byte aligned pointer to that TB combined
- * with additional information in its two least significant bits. The
- * additional information is encoded as follows:
- * 0, 1: the link between this TB and the next is via the specified
- * TB index (0 or 1). That is, we left the TB via (the equivalent
- * of) "goto_tb <index>". The main loop uses this to determine
- * how to link the TB just executed to the next.
- * 2: we are using instruction counting code generation, and we
- * did not start executing this TB because the instruction counter
- * would hit zero midway through it. In this case the pointer
- * returned is the TB we were about to execute, and the caller must
- * arrange to execute the remaining count of instructions.
- * 3: we stopped because the CPU's exit_request flag was set
- * (usually meaning that there is an interrupt that needs to be
- * handled). The pointer returned is the TB we were about to execute
- * when we noticed the pending exit request.
- *
- * If the bottom two bits indicate an exit-via-index then the CPU
- * state is correctly synchronised and ready for execution of the next
- * TB (and in particular the guest PC is the address to execute next).
- * Otherwise, we gave up on execution of this TB before it started, and
- * the caller must fix up the CPU state by calling the CPU's
- * synchronize_from_tb() method with the TB pointer we return (falling
- * back to calling the CPU's set_pc method with tb->pb if no
- * synchronize_from_tb() method exists).
- *
- * Note that TCG targets may use a different definition of tcg_qemu_tb_exec
- * to this default (which just calls the prologue.code emitted by
- * tcg_target_qemu_prologue()).
- */
-#define TB_EXIT_MASK 3
-#define TB_EXIT_IDX0 0
-#define TB_EXIT_IDX1 1
-#define TB_EXIT_IDXMAX 1
-#define TB_EXIT_REQUESTED 3
-
-#ifdef HAVE_TCG_QEMU_TB_EXEC
-uintptr_t tcg_qemu_tb_exec(CPUArchState *env, uint8_t *tb_ptr);
-#else
-# define tcg_qemu_tb_exec(env, tb_ptr) \
- ((uintptr_t (*)(void *, void *))tcg_ctx->code_gen_prologue)(env, tb_ptr)
-#endif
-
-void tcg_register_jit(void *buf, size_t buf_size);
-
-#if TCG_TARGET_MAYBE_vec
-/* Return zero if the tuple (opc, type, vece) is unsupportable;
- return > 0 if it is directly supportable;
- return < 0 if we must call tcg_expand_vec_op. */
-int tcg_can_emit_vec_op(TCGOpcode, TCGType, unsigned);
-#else
-static inline int tcg_can_emit_vec_op(TCGOpcode o, TCGType t, unsigned ve)
-{
- return 0;
-}
-#endif
-
-/* Expand the tuple (opc, type, vece) on the given arguments. */
-void tcg_expand_vec_op(TCGOpcode, TCGType, unsigned, TCGArg, ...);
-
-/* Replicate a constant C accoring to the log2 of the element size. */
-uint64_t dup_const(unsigned vece, uint64_t c);
-
-#define dup_const(VECE, C) \
- (__builtin_constant_p(VECE) \
- ? ( (VECE) == MO_8 ? 0x0101010101010101ull * (uint8_t)(C) \
- : (VECE) == MO_16 ? 0x0001000100010001ull * (uint16_t)(C) \
- : (VECE) == MO_32 ? 0x0000000100000001ull * (uint32_t)(C) \
- : dup_const(VECE, C)) \
- : dup_const(VECE, C))
-
-
-/*
- * Memory helpers that will be used by TCG generated code.
- */
-#ifdef CONFIG_SOFTMMU
-/* Value zero-extended to tcg register size. */
-tcg_target_ulong helper_ret_ldub_mmu(CPUArchState *env, target_ulong addr,
- TCGMemOpIdx oi, uintptr_t retaddr);
-tcg_target_ulong helper_le_lduw_mmu(CPUArchState *env, target_ulong addr,
- TCGMemOpIdx oi, uintptr_t retaddr);
-tcg_target_ulong helper_le_ldul_mmu(CPUArchState *env, target_ulong addr,
- TCGMemOpIdx oi, uintptr_t retaddr);
-uint64_t helper_le_ldq_mmu(CPUArchState *env, target_ulong addr,
- TCGMemOpIdx oi, uintptr_t retaddr);
-tcg_target_ulong helper_be_lduw_mmu(CPUArchState *env, target_ulong addr,
- TCGMemOpIdx oi, uintptr_t retaddr);
-tcg_target_ulong helper_be_ldul_mmu(CPUArchState *env, target_ulong addr,
- TCGMemOpIdx oi, uintptr_t retaddr);
-uint64_t helper_be_ldq_mmu(CPUArchState *env, target_ulong addr,
- TCGMemOpIdx oi, uintptr_t retaddr);
-
-/* Value sign-extended to tcg register size. */
-tcg_target_ulong helper_ret_ldsb_mmu(CPUArchState *env, target_ulong addr,
- TCGMemOpIdx oi, uintptr_t retaddr);
-tcg_target_ulong helper_le_ldsw_mmu(CPUArchState *env, target_ulong addr,
- TCGMemOpIdx oi, uintptr_t retaddr);
-tcg_target_ulong helper_le_ldsl_mmu(CPUArchState *env, target_ulong addr,
- TCGMemOpIdx oi, uintptr_t retaddr);
-tcg_target_ulong helper_be_ldsw_mmu(CPUArchState *env, target_ulong addr,
- TCGMemOpIdx oi, uintptr_t retaddr);
-tcg_target_ulong helper_be_ldsl_mmu(CPUArchState *env, target_ulong addr,
- TCGMemOpIdx oi, uintptr_t retaddr);
-
-void helper_ret_stb_mmu(CPUArchState *env, target_ulong addr, uint8_t val,
- TCGMemOpIdx oi, uintptr_t retaddr);
-void helper_le_stw_mmu(CPUArchState *env, target_ulong addr, uint16_t val,
- TCGMemOpIdx oi, uintptr_t retaddr);
-void helper_le_stl_mmu(CPUArchState *env, target_ulong addr, uint32_t val,
- TCGMemOpIdx oi, uintptr_t retaddr);
-void helper_le_stq_mmu(CPUArchState *env, target_ulong addr, uint64_t val,
- TCGMemOpIdx oi, uintptr_t retaddr);
-void helper_be_stw_mmu(CPUArchState *env, target_ulong addr, uint16_t val,
- TCGMemOpIdx oi, uintptr_t retaddr);
-void helper_be_stl_mmu(CPUArchState *env, target_ulong addr, uint32_t val,
- TCGMemOpIdx oi, uintptr_t retaddr);
-void helper_be_stq_mmu(CPUArchState *env, target_ulong addr, uint64_t val,
- TCGMemOpIdx oi, uintptr_t retaddr);
-
-/* Temporary aliases until backends are converted. */
-#ifdef TARGET_WORDS_BIGENDIAN
-# define helper_ret_ldsw_mmu helper_be_ldsw_mmu
-# define helper_ret_lduw_mmu helper_be_lduw_mmu
-# define helper_ret_ldsl_mmu helper_be_ldsl_mmu
-# define helper_ret_ldul_mmu helper_be_ldul_mmu
-# define helper_ret_ldl_mmu helper_be_ldul_mmu
-# define helper_ret_ldq_mmu helper_be_ldq_mmu
-# define helper_ret_stw_mmu helper_be_stw_mmu
-# define helper_ret_stl_mmu helper_be_stl_mmu
-# define helper_ret_stq_mmu helper_be_stq_mmu
-#else
-# define helper_ret_ldsw_mmu helper_le_ldsw_mmu
-# define helper_ret_lduw_mmu helper_le_lduw_mmu
-# define helper_ret_ldsl_mmu helper_le_ldsl_mmu
-# define helper_ret_ldul_mmu helper_le_ldul_mmu
-# define helper_ret_ldl_mmu helper_le_ldul_mmu
-# define helper_ret_ldq_mmu helper_le_ldq_mmu
-# define helper_ret_stw_mmu helper_le_stw_mmu
-# define helper_ret_stl_mmu helper_le_stl_mmu
-# define helper_ret_stq_mmu helper_le_stq_mmu
-#endif
-
-uint32_t helper_atomic_cmpxchgb_mmu(CPUArchState *env, target_ulong addr,
- uint32_t cmpv, uint32_t newv,
- TCGMemOpIdx oi, uintptr_t retaddr);
-uint32_t helper_atomic_cmpxchgw_le_mmu(CPUArchState *env, target_ulong addr,
- uint32_t cmpv, uint32_t newv,
- TCGMemOpIdx oi, uintptr_t retaddr);
-uint32_t helper_atomic_cmpxchgl_le_mmu(CPUArchState *env, target_ulong addr,
- uint32_t cmpv, uint32_t newv,
- TCGMemOpIdx oi, uintptr_t retaddr);
-uint64_t helper_atomic_cmpxchgq_le_mmu(CPUArchState *env, target_ulong addr,
- uint64_t cmpv, uint64_t newv,
- TCGMemOpIdx oi, uintptr_t retaddr);
-uint32_t helper_atomic_cmpxchgw_be_mmu(CPUArchState *env, target_ulong addr,
- uint32_t cmpv, uint32_t newv,
- TCGMemOpIdx oi, uintptr_t retaddr);
-uint32_t helper_atomic_cmpxchgl_be_mmu(CPUArchState *env, target_ulong addr,
- uint32_t cmpv, uint32_t newv,
- TCGMemOpIdx oi, uintptr_t retaddr);
-uint64_t helper_atomic_cmpxchgq_be_mmu(CPUArchState *env, target_ulong addr,
- uint64_t cmpv, uint64_t newv,
- TCGMemOpIdx oi, uintptr_t retaddr);
-
-#define GEN_ATOMIC_HELPER(NAME, TYPE, SUFFIX) \
-TYPE helper_atomic_ ## NAME ## SUFFIX ## _mmu \
- (CPUArchState *env, target_ulong addr, TYPE val, \
- TCGMemOpIdx oi, uintptr_t retaddr);
-
-#ifdef CONFIG_ATOMIC64
-#define GEN_ATOMIC_HELPER_ALL(NAME) \
- GEN_ATOMIC_HELPER(NAME, uint32_t, b) \
- GEN_ATOMIC_HELPER(NAME, uint32_t, w_le) \
- GEN_ATOMIC_HELPER(NAME, uint32_t, w_be) \
- GEN_ATOMIC_HELPER(NAME, uint32_t, l_le) \
- GEN_ATOMIC_HELPER(NAME, uint32_t, l_be) \
- GEN_ATOMIC_HELPER(NAME, uint64_t, q_le) \
- GEN_ATOMIC_HELPER(NAME, uint64_t, q_be)
-#else
-#define GEN_ATOMIC_HELPER_ALL(NAME) \
- GEN_ATOMIC_HELPER(NAME, uint32_t, b) \
- GEN_ATOMIC_HELPER(NAME, uint32_t, w_le) \
- GEN_ATOMIC_HELPER(NAME, uint32_t, w_be) \
- GEN_ATOMIC_HELPER(NAME, uint32_t, l_le) \
- GEN_ATOMIC_HELPER(NAME, uint32_t, l_be)
-#endif
-
-GEN_ATOMIC_HELPER_ALL(fetch_add)
-GEN_ATOMIC_HELPER_ALL(fetch_sub)
-GEN_ATOMIC_HELPER_ALL(fetch_and)
-GEN_ATOMIC_HELPER_ALL(fetch_or)
-GEN_ATOMIC_HELPER_ALL(fetch_xor)
-GEN_ATOMIC_HELPER_ALL(fetch_smin)
-GEN_ATOMIC_HELPER_ALL(fetch_umin)
-GEN_ATOMIC_HELPER_ALL(fetch_smax)
-GEN_ATOMIC_HELPER_ALL(fetch_umax)
-
-GEN_ATOMIC_HELPER_ALL(add_fetch)
-GEN_ATOMIC_HELPER_ALL(sub_fetch)
-GEN_ATOMIC_HELPER_ALL(and_fetch)
-GEN_ATOMIC_HELPER_ALL(or_fetch)
-GEN_ATOMIC_HELPER_ALL(xor_fetch)
-GEN_ATOMIC_HELPER_ALL(smin_fetch)
-GEN_ATOMIC_HELPER_ALL(umin_fetch)
-GEN_ATOMIC_HELPER_ALL(smax_fetch)
-GEN_ATOMIC_HELPER_ALL(umax_fetch)
-
-GEN_ATOMIC_HELPER_ALL(xchg)
-
-#undef GEN_ATOMIC_HELPER_ALL
-#undef GEN_ATOMIC_HELPER
-#endif /* CONFIG_SOFTMMU */
-
-/*
- * These aren't really a "proper" helpers because TCG cannot manage Int128.
- * However, use the same format as the others, for use by the backends.
- *
- * The cmpxchg functions are only defined if HAVE_CMPXCHG128;
- * the ld/st functions are only defined if HAVE_ATOMIC128,
- * as defined by <qemu/atomic128.h>.
- */
-Int128 helper_atomic_cmpxchgo_le_mmu(CPUArchState *env, target_ulong addr,
- Int128 cmpv, Int128 newv,
- TCGMemOpIdx oi, uintptr_t retaddr);
-Int128 helper_atomic_cmpxchgo_be_mmu(CPUArchState *env, target_ulong addr,
- Int128 cmpv, Int128 newv,
- TCGMemOpIdx oi, uintptr_t retaddr);
-
-Int128 helper_atomic_ldo_le_mmu(CPUArchState *env, target_ulong addr,
- TCGMemOpIdx oi, uintptr_t retaddr);
-Int128 helper_atomic_ldo_be_mmu(CPUArchState *env, target_ulong addr,
- TCGMemOpIdx oi, uintptr_t retaddr);
-void helper_atomic_sto_le_mmu(CPUArchState *env, target_ulong addr, Int128 val,
- TCGMemOpIdx oi, uintptr_t retaddr);
-void helper_atomic_sto_be_mmu(CPUArchState *env, target_ulong addr, Int128 val,
- TCGMemOpIdx oi, uintptr_t retaddr);
-
-#ifdef CONFIG_DEBUG_TCG
-void tcg_assert_listed_vecop(TCGOpcode);
-#else
-static inline void tcg_assert_listed_vecop(TCGOpcode op) { }
-#endif
-
-static inline const TCGOpcode *tcg_swap_vecop_list(const TCGOpcode *n)
-{
-#ifdef CONFIG_DEBUG_TCG
- const TCGOpcode *o = tcg_ctx->vecop_list;
- tcg_ctx->vecop_list = n;
- return o;
-#else
- return NULL;
-#endif
-}
-
-bool tcg_can_emit_vecop_list(const TCGOpcode *, TCGType, unsigned);
-
-#endif /* TCG_H */
+++ /dev/null
-/*
- * Common System Call Tracing Wrappers for *-user
- *
- * Copyright (c) 2019 Linaro
- * Written by Alex Bennée <alex.bennee@linaro.org>
- *
- * SPDX-License-Identifier: GPL-2.0-or-later
- */
-
-#ifndef _SYSCALL_TRACE_H_
-#define _SYSCALL_TRACE_H_
-
-#include "trace/trace-root.h"
-
-/*
- * These helpers just provide a common place for the various
- * subsystems that want to track syscalls to put their hooks in. We
- * could potentially unify the -strace code here as well.
- */
-
-static inline void record_syscall_start(void *cpu, int num,
- abi_long arg1, abi_long arg2,
- abi_long arg3, abi_long arg4,
- abi_long arg5, abi_long arg6,
- abi_long arg7, abi_long arg8)
-{
- trace_guest_user_syscall(cpu, num,
- arg1, arg2, arg3, arg4,
- arg5, arg6, arg7, arg8);
- qemu_plugin_vcpu_syscall(cpu, num,
- arg1, arg2, arg3, arg4,
- arg5, arg6, arg7, arg8);
-}
-
-static inline void record_syscall_return(void *cpu, int num, abi_long ret)
-{
- trace_guest_user_syscall_ret(cpu, num, ret);
- qemu_plugin_vcpu_syscall_ret(cpu, num, ret);
-}
-
-
-#endif /* _SYSCALL_TRACE_H_ */
projects / tools / qemu-tools.git / commitdiff