mddrc_config = &default_mddrc_config;
if (dram_init_seq == NULL) {
dram_init_seq = default_init_seq;
- seq_sz = sizeof(default_init_seq)/sizeof(u32);
+ seq_sz = ARRAY_SIZE(default_init_seq);
}
/* Initialize IO Control */
RSR_ESRS, "External Soft"}, {
RSR_EHRS, "External Hard"}
};
- static int n = sizeof bits / sizeof bits[0];
+ static int n = ARRAY_SIZE(bits);
ulong rsr = gd->arch.reset_status;
int i;
char *sep;
struct eth_device* dev;
int i;
- for (i = 0; i < sizeof(ether_fcc_info) / sizeof(ether_fcc_info[0]); i++)
+ for (i = 0; i < ARRAY_SIZE(ether_fcc_info); i++)
{
dev = (struct eth_device*) malloc(sizeof *dev);
memset(dev, 0, sizeof *dev);
{ offsetof(elbt_rxeacc, badlen), "Bad Frame Length" },
{ offsetof(elbt_rxeacc, badbit), "Data Compare Errors" },
};
-static int rxeacc_ndesc = sizeof (rxeacc_descs) / sizeof (rxeacc_descs[0]);
+static int rxeacc_ndesc = ARRAY_SIZE(rxeacc_descs);
typedef
struct {
{ offsetof(elbt_txeacc, un), "Underrun" },
{ offsetof(elbt_txeacc, csl), "Carrier Sense Lost" },
};
-static int txeacc_ndesc = sizeof (txeacc_descs) / sizeof (txeacc_descs[0]);
+static int txeacc_ndesc = ARRAY_SIZE(txeacc_descs);
typedef
struct {
{ offsetof(fcc_enet_t, fen_p512c), "512-1023 Octet Frames" },
{ offsetof(fcc_enet_t, fen_p1024c), "1024-1518 Octet Frames"},
};
-static int epram_ndesc = sizeof (epram_descs) / sizeof (epram_descs[0]);
+static int epram_ndesc = ARRAY_SIZE(epram_descs);
/*
* given an elbt_prdesc array and an array of base addresses, print
RSR_SRS, "External/Internal Soft"}, {
RSR_HRS, "External/Internal Hard"}
};
- static int n = sizeof bits / sizeof bits[0];
+ static int n = ARRAY_SIZE(bits);
ulong rsr = gd->arch.reset_status;
int i;
char *sep;
#endif
corecnf_tab_index = ((corepll & 0x1F) << 2) | ((corepll & 0x60) >> 5);
- if (corecnf_tab_index > (sizeof(corecnf_tab) / sizeof(corecnf_t))) {
+ if (corecnf_tab_index > (ARRAY_SIZE(corecnf_tab))) {
/* corecnf_tab_index is too high, possibly wrong value */
return -11;
}
struct eth_device* dev;
int i;
- for (i = 0; i < sizeof(ether_fcc_info) / sizeof(ether_fcc_info[0]); i++)
+ for (i = 0; i < ARRAY_SIZE(ether_fcc_info); i++)
{
dev = (struct eth_device*) malloc(sizeof *dev);
memset(dev, 0, sizeof *dev);
struct ether_fcc_info_s *efis;
int i;
- for (i = 0; i < sizeof(ether_fcc_info) / sizeof(ether_fcc_info[0]); i++) {
+ for (i = 0; i < ARRAY_SIZE(ether_fcc_info); i++) {
dev = malloc(sizeof(*dev));
if (dev == NULL)
/* Setup the pin configuration of the FEC(s)
*/
- for (i = 0; i < sizeof(ether_fcc_info) / sizeof(ether_fcc_info[0]); i++)
+ for (i = 0; i < ARRAY_SIZE(ether_fcc_info); i++)
fec_pin_init(ether_fcc_info[i].ether_index);
}
PRINT_DCR(OPB2PLB40_BCTRL);
PRINT_DCR(P4P3BO0_CFG);
#endif
- n = sizeof(ppc4xx_reg) / sizeof(ppc4xx_reg[0]);
+ n = ARRAY_SIZE(ppc4xx_reg);
for (i = 0; i < n; i++) {
value = 0;
type = ppc4xx_reg[i].type;
sdram_conf_t mb0cf[] = CONFIG_SYS_SDRAM_TABLE;
#endif
-#define N_MB0CF (sizeof(mb0cf) / sizeof(mb0cf[0]))
+#define N_MB0CF (ARRAY_SIZE(mb0cf))
#ifdef CONFIG_SYS_SDRAM_CASL
static ulong ns2clks(ulong ns)
#define CONFIG_SYS_SDRAM0_CFG0 0x82000000 /* DCEN=1, PMUD=0, 64-bit */
#endif
-#define N_MB0CF (sizeof(mb0cf) / sizeof(mb0cf[0]))
+#define N_MB0CF (ARRAY_SIZE(mb0cf))
#define NUM_TRIES 64
#define NUM_READS 10