$(DRMDRVDIR)/psb_sgx.o \
$(DRMDRVDIR)/psb_socket.o \
$(DRMDRVDIR)/psb_umevents.o \
- $(DRMDRVDIR)/tc35876x-dsi-lvds.o \
- $(DRMDRVDIR)/tmd_vid.o \
- $(DRMDRVDIR)/tpo_cmd.o \
- $(DRMDRVDIR)/tpo_vid.o
+ $(DRMDRVDIR)/tmd_6x10_vid.o
medfield_gfx-y += \
$(IMGVDIR)/msvdx_power.o \
#ifndef CONFIG_MDFLD_DSI_DPU
if((!(dev_priv->dsr_fb_update & MDFLD_DSR_MIPI_CONTROL)) &&
(dev_priv->dbi_panel_on || dev_priv->dbi_panel_on2)){
- mdfld_dsi_dbi_exit_dsr(dev,MDFLD_DSR_MIPI_CONTROL);
+ mdfld_dsi_dbi_exit_dsr(dev,MDFLD_DSR_MIPI_CONTROL, 0, 0);
PSB_DEBUG_ENTRY("Out of DSR before set brightness to %d.\n",
dev_priv->brightness_adjusted);
}
#endif
- if (get_panel_type(dev, 0) == TC35876X) {
- if (dev_priv->dpi_panel_on || dev_priv->dpi_panel_on2)
- tc35876x_brightness_control(dev,
- dev_priv->brightness_adjusted);
- } else {
+ {
if (dev_priv->dbi_panel_on || dev_priv->dpi_panel_on)
mdfld_dsi_brightness_control(dev, 0,
dev_priv->brightness_adjusted);
#include "android_hdmi.h"
int drm_psb_debug;
+int drm_psb_enable_pr2_cabc = 1;
/*EXPORT_SYMBOL(drm_psb_debug); */
static int drm_psb_trap_pagefaults;
int drm_topaz_pmpolicy = PSB_PMPOLICY_NOPM;
int drm_topaz_sbuswa;
int drm_psb_topaz_clockgating = 0;
-static int PanelID = TC35876X;
+static int PanelID = TMD_6X10_VID;
char HDMI_EDID[HDMI_MONITOR_NAME_LENGTH];
static int psb_probe(struct pci_dev *pdev, const struct pci_device_id *ent);
#if defined(CONFIG_MDFLD_DSI_DPU)
mdfld_dbi_dpu_report_fullscreen_damage(dev);
#elif defined(CONFIG_MDFLD_DSI_DSR)
- mdfld_dsi_dbi_exit_dsr(dev, MDFLD_DSR_2D_3D);
+ mdfld_dsi_dbi_exit_dsr(dev, MDFLD_DSR_2D_3D, 0, 0);
#endif
return 0;
} else if (*param == DRM_PSB_DSR_ENABLE) {
pipe++;
if ((dev_priv->dsr_fb_update & MDFLD_DSR_2D_3D) != MDFLD_DSR_2D_3D) {
- mdfld_dsi_dbi_exit_dsr(dev, MDFLD_DSR_2D_3D);
+ mdfld_dsi_dbi_exit_dsr(dev, MDFLD_DSR_2D_3D, 0, 0);
}
if (pipe > 0) {
if ((((arg->overlay.OVADD & OV_PIPE_SELECT) >> OV_PIPE_SELECT_POS) == OV_PIPE_A)) {
#ifndef CONFIG_MDFLD_DSI_DPU
- mdfld_dsi_dbi_exit_dsr(dev, MDFLD_DSR_OVERLAY_0);
+ mdfld_dsi_dbi_exit_dsr(dev, MDFLD_DSR_OVERLAY_0, 0, 0);
#else
/*TODO: report overlay damage*/
#endif
if ((((arg->overlay.OVADD & OV_PIPE_SELECT) >> OV_PIPE_SELECT_POS) == OV_PIPE_C)) {
#ifndef CONFIG_MDFLD_DSI_DPU
- mdfld_dsi_dbi_exit_dsr(dev, MDFLD_DSR_OVERLAY_2);
+ mdfld_dsi_dbi_exit_dsr(dev, MDFLD_DSR_OVERLAY_2, 0, 0);
#else
/*TODO: report overlay damage*/
#endif
PanelID = TMD_CMD;
else if (!strcasecmp(arg, "TPO_CMD"))
PanelID = TPO_CMD;
+ else if (!strcasecmp(arg, "PYR_CMD"))
+ PanelID = PYR_CMD;
else if (!strcasecmp(arg, "TMD_VID"))
PanelID = TMD_VID;
else if (!strcasecmp(arg, "TPO_VID"))
PanelID = TPO_VID;
- else if (!strcasecmp(arg, "TC35876X"))
- PanelID = TC35876X;
+ else if (!strcasecmp(arg, "PYR_VID"))
+ PanelID = PYR_VID;
+ else if (!strcasecmp(arg, "H8C7_VID"))
+ PanelID = H8C7_VID;
+ else if (!strcasecmp(arg, "H8C7_CMD"))
+ PanelID = H8C7_CMD;
else
PanelID = GCT_DETECT;
TPO_VID,
TMD_CMD,
TMD_VID,
+ TMD_6X10_VID,
+ H8C7_VID,
+ H8C7_CMD,
+ AUO_SC1_VID,
+ AUO_SC1_CMD,
+ GI_SONY_VID,
+ GI_SONY_CMD,
+ PYR_CMD,
+ PYR_VID,
TPO,
TMD,
+ PYR,
HDMI,
- TC35876X,
GCT_DETECT
};
#endif
extern int drm_psb_debug;
+extern int drm_psb_enable_pr2_cabc ;
extern int drm_tc35876x_debug;
extern int drm_psb_no_fb;
extern int drm_topaz_sbuswa;
#define IS_PENWELL(dev) 0 /* FIXME */
+#define IS_CTP(dev) (((dev->pci_device & 0xffff) == 0x08c0) || \
+ ((dev->pci_device & 0xffff) == 0x08c7) || \
+ ((dev->pci_device & 0xffff) == 0x08c8))
+
extern int drm_psb_cpurelax;
extern int drm_psb_udelaydivider;
extern int drm_psb_udelaymultiplier;
case 0:
#ifndef CONFIG_MDFLD_DSI_DPU
if (!(dev_priv->dsr_fb_update & MDFLD_DSR_CURSOR_0))
- mdfld_dsi_dbi_exit_dsr (dev, MDFLD_DSR_CURSOR_0);
+ mdfld_dsi_dbi_exit_dsr (dev, MDFLD_DSR_CURSOR_0, 0, 0);
#else /*CONFIG_MDFLD_DSI_DPU*/
rect.x = x;
rect.y = y;
case 2:
#ifndef CONFIG_MDFLD_DSI_DPU
if (!(dev_priv->dsr_fb_update & MDFLD_DSR_CURSOR_2))
- mdfld_dsi_dbi_exit_dsr (dev, MDFLD_DSR_CURSOR_2);
+ mdfld_dsi_dbi_exit_dsr (dev, MDFLD_DSR_CURSOR_2, 0, 0);
#else /*CONFIG_MDFLD_DSI_DPU*/
mdfld_dbi_dpu_report_damage(dev, MDFLD_CURSORC, &rect);
mdfld_dpu_exit_dsr(dev);
int dspcntr_reg = PSB_DSPCNTR(PSB_PIPE_A);
int dspbase_reg = PSB_DSPBASE(PSB_PIPE_A);
int pipeconf_reg = PSB_PIPECONF(PSB_PIPE_A);
+ u32 gen_fifo_stat_reg = GEN_FIFO_STAT_REG;
u32 temp;
PSB_DEBUG_ENTRY("pipe = %d \n", pipe);
+ /**
+ * NOTE: this path only works for TMD panel now. update it to
+ * support all MIPI panels later.
+ */
+ if (pipe != 1 && (get_panel_type(dev, pipe) == TMD_6X10_VID))
+ return;
switch (pipe) {
case 0:
dspcntr_reg = PSB_DSPCNTR(PSB_PIPE_C);
dspbase_reg = PSB_DSPBASE(PSB_PIPE_C);
pipeconf_reg = PSB_PIPECONF(PSB_PIPE_C);
+ gen_fifo_stat_reg = GEN_FIFO_STAT_REG + MIPIC_REG_OFFSET;
break;
default:
DRM_ERROR("Illegal Pipe Number. \n");
}
if (pipe != 1)
- mdfld_dsi_gen_fifo_ready(dev, MIPI_GEN_FIFO_STAT_REG(pipe), HS_CTRL_FIFO_EMPTY | HS_DATA_FIFO_EMPTY);
+ mdfld_dsi_gen_fifo_ready (dev, gen_fifo_stat_reg, HS_CTRL_FIFO_EMPTY | HS_DATA_FIFO_EMPTY);
/* Disable display plane */
temp = REG_READ(dspcntr_reg);
int dspbase_reg = PSB_DSPBASE(PSB_PIPE_A);
int pipeconf_reg = PSB_PIPECONF(PSB_PIPE_A);
u32 pipestat_reg = PSB_PIPESTAT(PSB_PIPE_A);
+ u32 gen_fifo_stat_reg = GEN_FIFO_STAT_REG;
u32 pipeconf = dev_priv->pipeconf;
u32 dspcntr = dev_priv->dspcntr;
+ u32 mipi_enable_reg = MIPIA_DEVICE_READY_REG;
u32 temp;
bool enabled;
int timeout = 0;
PSB_DEBUG_ENTRY("mode = %d, pipe = %d \n", mode, pipe);
+ /**
+ * MIPI dpms
+ * NOTE: this path only works for TMD panel now. update it to
+ * support all MIPI panels later.
+ */
+ if (pipe != 1 && (get_panel_type(dev, pipe) == TMD_6X10_VID))
+ return;
+
/* FIXME_JLIU7 MDFLD_PO replaced w/ the following function */
/* mdfld_dbi_dpms (struct drm_device *dev, int pipe, bool enabled) */
pipestat_reg = PSB_PIPESTAT(PSB_PIPE_C);
pipeconf = dev_priv->pipeconf2;
dspcntr = dev_priv->dspcntr2;
+ gen_fifo_stat_reg = GEN_FIFO_STAT_REG + MIPIC_REG_OFFSET;
+ mipi_enable_reg = MIPIA_DEVICE_READY_REG + MIPIC_REG_OFFSET;
break;
default:
DRM_ERROR("Illegal Pipe Number. \n");
msleep(100); /*wait for pipe disable*/
/*printk(KERN_ALERT "70008 is %x\n", REG_READ(0x70008));
printk(KERN_ALERT "b074 is %x\n", REG_READ(0xb074));*/
- REG_WRITE(MIPI_DEVICE_READY_REG(pipe), 0);
+ REG_WRITE(mipi_enable_reg, 0);
msleep(100);
printk(KERN_ALERT "70008 is %x\n", REG_READ(0x70008));
printk(KERN_ALERT "b074 is %x\n", REG_READ(0xb074));
REG_WRITE(0xb004, REG_READ(0xb004));
/* try to bring the controller back up again*/
- REG_WRITE(MIPI_DEVICE_READY_REG(pipe), 1);
+ REG_WRITE(mipi_enable_reg, 1);
temp = REG_READ(dspcntr_reg);
REG_WRITE(dspcntr_reg, temp | DISPLAY_PLANE_ENABLE);
REG_WRITE(dspbase_reg, REG_READ(dspbase_reg));
* if it's on this pipe */
/* psb_intel_crtc_dpms_video(crtc, FALSE); TODO */
if (pipe != 1)
- mdfld_dsi_gen_fifo_ready(dev, MIPI_GEN_FIFO_STAT_REG(pipe), HS_CTRL_FIFO_EMPTY | HS_DATA_FIFO_EMPTY);
+ mdfld_dsi_gen_fifo_ready (dev, gen_fifo_stat_reg, HS_CTRL_FIFO_EMPTY | HS_DATA_FIFO_EMPTY);
/* Disable the VGA plane that we never use */
REG_WRITE(VGACNTRL, VGA_DISP_DISABLE);
return err != target;
}
+static int mdfld_crtc_dsi_pll_calc(struct drm_crtc *crtc,
+ struct mdfld_dsi_config *dsi_config,
+ struct drm_device *dev,
+ u32 *out_dpll,
+ u32 *out_fp,
+ struct drm_display_mode *adjusted_mode)
+{
+ DRM_DRIVER_PRIVATE_T *dev_priv = dev->dev_private;
+ struct mrst_clock_t clock;
+ u32 dpll = 0, fp = 0;
+ int refclk = 0;
+ int clk_n = 0, clk_p2 = 0, clk_byte = 1, clk = 0, m_conv = 0, clk_tmp = 0;
+ bool ok;
+
+ if ((dev_priv->ksel == KSEL_CRYSTAL_19) || (dev_priv->ksel == KSEL_BYPASS_19))
+ {
+ refclk = 19200;
+ clk_n = 1, clk_p2 = 8;
+ } else if (dev_priv->ksel == KSEL_BYPASS_25) {
+ refclk = 25000;
+ clk_n = 1, clk_p2 = 8;
+ } else if (dev_priv->ksel == KSEL_CRYSTAL_38) {
+ refclk = 38400;
+ clk_n = 1, clk_p2 = 8;
+ } else if ((dev_priv->ksel == KSEL_BYPASS_83_100) && (dev_priv->core_freq == 166)) {
+ refclk = 83000;
+ clk_n = 4, clk_p2 = 8;
+ } else if ((dev_priv->ksel == KSEL_BYPASS_83_100) &&
+ (dev_priv->core_freq == 100 || dev_priv->core_freq == 200)) {
+ refclk = 100000;
+ clk_n = 4, clk_p2 = 8;
+ }else{
+ refclk = 19200;
+ clk_n = 1, clk_p2 = 8;
+ }
+
+ dev_priv->bpp = 24;
+ clk_byte = dev_priv->bpp / 8;
+
+ if (dsi_config->lane_count)
+ clk = adjusted_mode->clock / dsi_config->lane_count;
+ else
+ clk = adjusted_mode->clock;
+
+ clk_tmp = clk * clk_n * clk_p2 * clk_byte;
+
+ PSB_DEBUG_ENTRY("ref_clk: %d, clk = %d, clk_n = %d, clk_p2 = %d. \n", refclk, clk, clk_n, clk_p2);
+ PSB_DEBUG_ENTRY("adjusted_mode->clock = %d, clk_tmp = %d. \n", adjusted_mode->clock, clk_tmp);
+
+ ok = mdfldFindBestPLL(crtc, clk_tmp, refclk, &clock);
+ dev_priv->tmds_clock_khz = clock.dot / (clk_n * clk_p2 * clk_byte);
+
+ if (!ok) {
+ DRM_ERROR
+ ("mdfldFindBestPLL fail in mdfld_crtc_mode_set. \n");
+ } else {
+ m_conv = mdfld_m_converts[(clock.m - MDFLD_M_MIN)];
+ PSB_DEBUG_ENTRY("dot clock = %d,"
+ "m = %d, p1 = %d, m_conv = %d. \n", clock.dot, clock.m,
+ clock.p1, m_conv);
+ }
+
+ dpll = 0x00000000;
+ fp = (clk_n / 2) << 16;
+ fp |= m_conv;
+
+ /* compute bitmask from p1 value */
+ dpll |= (1 << (clock.p1 - 2)) << 17;
+
+ *(out_dpll) = dpll;
+ *(out_fp) = fp;
+
+ PSB_DEBUG_ENTRY("dsi dpll = 0x%x fp = 0x%x\n", dpll, fp);
+ return 0;
+}
+
+static int mdfld_crtc_dsi_mode_set(struct drm_crtc *crtc,
+ struct mdfld_dsi_config *dsi_config,
+ struct drm_display_mode *mode,
+ struct drm_display_mode *adjusted_mode,
+ int x, int y,
+ struct drm_framebuffer *old_fb)
+{
+ struct drm_device *dev;
+ struct psb_intel_crtc *mdfld_dsi_crtc;
+ struct psb_framebuffer *mdfld_fb;
+ struct psb_intel_mode_device *mode_dev;
+ struct mdfld_dsi_hw_context *ctx;
+ struct drm_psb_private *dev_priv;
+ int fb_bpp;
+ int fb_pitch;
+ int fb_depth;
+ int hdelay;
+ static int init_flag = 1; /*bootstrap flag*/
+
+ if (!crtc || !crtc->fb) {
+ DRM_ERROR("Invalid CRTC\n");
+ return -EINVAL;
+ }
+
+ if (!dsi_config) {
+ DRM_ERROR("Invalid DSI config\n");
+ return -EINVAL;
+ }
+
+ mdfld_dsi_crtc = to_psb_intel_crtc(crtc);
+ mdfld_fb = to_psb_fb(crtc->fb);
+ mode_dev = mdfld_dsi_crtc->mode_dev;
+ mode = adjusted_mode;
+ ctx = &dsi_config->dsi_hw_context;
+ fb_bpp = crtc->fb->bits_per_pixel;
+ fb_pitch = crtc->fb->pitches[0];
+ fb_depth = crtc->fb->depth;
+ dev = crtc->dev;
+ dev_priv = (struct drm_psb_private *)dev->dev_private;
+
+ mutex_lock(&dsi_config->context_lock);
+
+ ctx->vgacntr = 0x80000000;
+
+ /*setup pll*/
+ mdfld_crtc_dsi_pll_calc(crtc, dsi_config, dev,
+ &ctx->dpll,
+ &ctx->fp,
+ adjusted_mode);
+
+ /*set up pipe timings*/
+ ctx->htotal = (mode->crtc_hdisplay - 1) |
+ ((mode->crtc_htotal - 1) << 16);
+ ctx->hblank = (mode->crtc_hblank_start - 1) |
+ ((mode->crtc_hblank_end - 1) << 16);
+ ctx->hsync = (mode->crtc_hsync_start - 1) |
+ ((mode->crtc_hsync_end - 1) << 16);
+ ctx->vtotal = (mode->crtc_vdisplay - 1) |
+ ((mode->crtc_vtotal - 1) << 16);
+ ctx->vblank = (mode->crtc_vblank_start - 1) |
+ ((mode->crtc_vblank_end - 1) << 16);
+ ctx->vsync = (mode->crtc_vsync_start - 1) |
+ ((mode->crtc_vsync_end - 1) << 16);
+
+ /*pipe source*/
+ ctx->pipesrc = ((mode->crtc_hdisplay - 1) << 16) |
+ (mode->crtc_vdisplay - 1);
+
+ /*setup dsp plane*/
+ ctx->dsppos = 0;
+ ctx->dspsize = ((mode->crtc_vdisplay - 1) << 16) | (mode->crtc_hdisplay - 1);
+
+ ctx->dspstride = fb_pitch;
+ ctx->dspsurf = mdfld_fb->offset;
+ ctx->dsplinoff = y * fb_pitch + x * (fb_bpp / 8);
+
+ if (init_flag == 1) {
+ printk(KERN_DEBUG"%s: ctx->dspsurf = 0x%x, ctx->dsplinoff = 0x%x\n",
+ __func__, ctx->dsplinoff, ctx->dspsurf);
+ init_flag = 0;
+ }
+
+ switch (fb_bpp) {
+ case 8:
+ ctx->dspcntr = DISPPLANE_8BPP;
+ break;
+ case 16:
+ if (fb_depth == 15)
+ ctx->dspcntr = DISPPLANE_15_16BPP;
+ else
+ ctx->dspcntr = DISPPLANE_16BPP;
+ break;
+ case 24:
+ case 32:
+ ctx->dspcntr = DISPPLANE_32BPP_NO_ALPHA;
+ break;
+ default:
+ DRM_ERROR("Unknown color depth\n");
+ mutex_unlock(&dsi_config->context_lock);
+ return -EINVAL;
+ }
+
+ if (dsi_config->pipe == 2)
+ ctx->dspcntr |= (0x2 << 24);
+
+ /*
+ * Setup pipe configuration for different panels
+ * The formula recommended from hw team is as below:
+ * (htotal * 5ns * hdelay) >= 8000ns
+ * hdelay is the count of delayed HBLANK scan lines
+ * And the max hdelay is 4
+ * by programming of PIPE(A/C) CONF bit 28:27:
+ * 00 = 1 scan line, 01 = 2 scan line,
+ * 02 = 3 scan line, 03 = 4 scan line
+ */
+ ctx->pipeconf &= ~(BIT27 | BIT28);
+
+ hdelay = 8000/mode->crtc_htotal/5;
+ if (8000%(mode->crtc_htotal*5) > 0)
+ hdelay += 1;
+
+ if (hdelay > 4) {
+ DRM_ERROR("Do not support such panel setting yet\n");
+ hdelay = 4; /* Use the max hdelay instead*/
+ }
+
+ ctx->pipeconf |= ((hdelay-1) << 27);
+
+ mutex_unlock(&dsi_config->context_lock);
+ return 0;
+}
+
static int mdfld_crtc_mode_set(struct drm_crtc *crtc,
struct drm_display_mode *mode,
struct drm_display_mode *adjusted_mode,
struct drm_encoder *encoder;
struct drm_connector * connector;
int timeout = 0;
+ struct mdfld_dsi_config *dsi_config;
int ret;
PSB_DEBUG_ENTRY("pipe = 0x%x\n", pipe);
if (ret)
return ret;
+ /**
+ * MIPI panel mode setting
+ * NOTE: this path only works for TMD panel now. update it to
+ * support all MIPI panels later.
+ */
+ if (pipe != 1 && ((get_panel_type(dev, pipe) == TMD_VID) ||
+ (get_panel_type(dev, pipe) == TMD_6X10_VID) ||
+ (get_panel_type(dev, pipe) == H8C7_VID) ||
+ (get_panel_type(dev, pipe) == GI_SONY_VID) ||
+ /* SC1 setting */
+ (get_panel_type(dev, pipe) == AUO_SC1_VID))) {
+ if (pipe == 0)
+ dsi_config = dev_priv->dsi_configs[0];
+ else if (pipe == 2)
+ dsi_config = dev_priv->dsi_configs[1];
+ else
+ return -EINVAL;
+ return mdfld_crtc_dsi_mode_set(crtc, dsi_config, mode,
+ adjusted_mode, x, y, old_fb);
+ }
+
if (pipe == 1) {
if (!ospm_power_using_hw_begin(OSPM_DISPLAY_ISLAND, true))
return 0;
#define KSEL_CRYSTAL_19 1
#define KSEL_BYPASS_19 5
#define KSEL_BYPASS_25 6
+#define KSEL_CRYSTAL_38 3
#define KSEL_BYPASS_83_100 7
/*
* MOORESTOWN defines
};
#define PSB_HTOTAL(pipe) (0x60000 + PSB_PREG_OFFSET(pipe))
+#define HTOTAL_A PSB_HTOTAL(PSB_PIPE_A)
+#define HTOTAL_C PSB_HTOTAL(PSB_PIPE_C)
+
#define PSB_HBLANK(pipe) (0x60004 + PSB_PREG_OFFSET(pipe))
+#define HBLANK_A PSB_HBLANK(PSB_PIPE_A)
+#define HBLANK_C PSB_HBLANK(PSB_PIPE_C)
+
#define PSB_HSYNC(pipe) (0x60008 + PSB_PREG_OFFSET(pipe))
+#define HSYNC_A PSB_HSYNC(PSB_PIPE_A)
+#define HSYNC_C PSB_HSYNC(PSB_PIPE_C)
+
#define PSB_VTOTAL(pipe) (0x6000C + PSB_PREG_OFFSET(pipe))
+#define VTOTAL_A PSB_VTOTAL(PSB_PIPE_A)
+#define VTOTAL_C PSB_VTOTAL(PSB_PIPE_C)
+
#define PSB_VBLANK(pipe) (0x60010 + PSB_PREG_OFFSET(pipe))
+#define VBLANK_A PSB_VBLANK(PSB_PIPE_A)
+#define VBLANK_C PSB_VBLANK(PSB_PIPE_C)
+
#define PSB_VSYNC(pipe) (0x60014 + PSB_PREG_OFFSET(pipe))
+#define VSYNC_A PSB_VSYNC(PSB_PIPE_A)
+#define VSYNC_C PSB_VSYNC(PSB_PIPE_C)
+
#define PSB_PIPESRC(pipe) (0x6001C + PSB_PREG_OFFSET(pipe))
+#define PIPEASRC PSB_PIPESRC(PSB_PIPE_A)
+#define PIPECSRC PSB_PIPESRC(PSB_PIPE_C)
+
#define PSB_BCLRPAT(pipe) (0x60020 + PSB_PREG_OFFSET(pipe))
#define PSB_VSYNCSHIFT(pipe) (0x60028 + PSB_PREG_OFFSET(pipe))
#define PSB_PIPE_DSL(pipe) (0x70000 + PSB_PREG_OFFSET(pipe))
#define PSB_PIPECONF(pipe) (0x70008 + PSB_PREG_OFFSET(pipe))
+#define PIPEACONF PSB_PIPECONF(PSB_PIPE_A)
+#define PIPEBCONF PSB_PIPECONF(PSB_PIPE_B)
+#define PIPECCONF PSB_PIPECONF(PSB_PIPE_C)
#define PIPEACONF_ENABLE (1<<31)
#define PIPEACONF_DISABLE 0
#define PIPECONF_PROGRESSIVE (0 << 21)
#define PIPECONF_INTERLACE_W_FIELD_INDICATION (6 << 21)
#define PIPECONF_INTERLACE_FIELD_0_ONLY (7 << 21)
+#define PIPEACONF_COLOR_MATRIX_ENABLE (1 << 20)
#define PIPECONF_PLANE_OFF (1<<19)
#define PIPECONF_CURSOR_OFF (1<<18)
#define PIPEBGCMAXBLUE 0x71018
#define PSB_PIPESTAT(pipe) (0x70024 + PSB_PREG_OFFSET(pipe))
+#define PIPEASTAT PSB_PIPESTAT(PSB_PIPE_A)
+#define PIPEBSTAT PSB_PIPESTAT(PSB_PIPE_B)
+#define PIPECSTAT PSB_PIPESTAT(PSB_PIPE_C)
#define PIPE_VBLANK_INTERRUPT_STATUS (1UL<<1)
#define PIPE_START_VBLANK_INTERRUPT_STATUS (1UL<<2)
#define DSPCHICKENBIT 0x70400
#define PSB_DSPCNTR(pipe) (0x70180 + PSB_PREG_OFFSET(pipe))
+#define DSPACNTR PSB_DSPCNTR(PSB_PIPE_A)
+#define DSPBCNTR PSB_DSPCNTR(PSB_PIPE_B)
+#define DSPCCNTR PSB_DSPCNTR(PSB_PIPE_C)
+
#define DISPLAY_PLANE_ENABLE (1<<31)
#define DISPLAY_PLANE_DISABLE 0
#define DISPPLANE_GAMMA_ENABLE (1<<30)
#define DISPPLANE_BOTTOM (4)
#define PSB_DSPLINOFF(pipe) (0x70184 + PSB_PREG_OFFSET(pipe))
+#define DSPALINOFF PSB_DSPLINOFF(PSB_PIPE_A)
+#define DSPCLINOFF PSB_DSPLINOFF(PSB_PIPE_C)
+
#define PSB_DSPBASE(pipe) PSB_DSPLINOFF(pipe)
#define PSB_DSPSTRIDE(pipe) (0x70188 + PSB_PREG_OFFSET(pipe))
+#define DSPASTRIDE PSB_DSPSTRIDE(PSB_PIPE_A)
+#define DSPCSTRIDE PSB_DSPSTRIDE(PSB_PIPE_C)
#define DSPAKEYVAL 0x70194
#define DSPAKEYMASK 0x70198
#define PSB_DSPPOS(pipe) (0x7018C + PSB_PREG_OFFSET(pipe))
+#define DSPAPOS PSB_DSPPOS(PSB_PIPE_A)
+#define DSPCPOS PSB_DSPPOS(PSB_PIPE_C)
+
#define PSB_DSPSIZE(pipe) (0x70190 + PSB_PREG_OFFSET(pipe))
+#define DSPASIZE PSB_DSPSIZE(PSB_PIPE_A)
+#define DSPCSIZE PSB_DSPSIZE(PSB_PIPE_C)
+
#define PSB_DSPSURF(pipe) (0x7019C + PSB_PREG_OFFSET(pipe))
+#define DSPASURF PSB_DSPSURF(PSB_PIPE_A)
+#define DSPBSURF PSB_DSPSURF(PSB_PIPE_B)
+#define DSPCSURF PSB_DSPSURF(PSB_PIPE_C)
+
#define PSB_DSPTILEOFF(pipe) (0x701A4 + PSB_PREG_OFFSET(pipe))
#define DSPCKEYMAXVAL 0x721A0
__pipe ? 0x800 + 0x400 * (__pipe - 1) : 0; \
})
+/*
+ * Palette registers
+ */
#define PSB_PALETTE(pipe) (0x0a000 + PSB_PALETTE_OFFSET(pipe))
+#define PALETTE_A PSB_PALETTE(PSB_PIPE_A)
+#define PALETTE_B PSB_PALETTE(PSB_PIPE_B)
+#define PALETTE_C PSB_PALETTE(PSB_PIPE_C)
+
+/*Gamma max register*/
+#define GAMMA_RED_MAX_A 0x70010
+#define GAMMA_GREEN_MAX_A 0x70014
+#define GAMMA_BLUE_MAX_A 0x70018
+
+#define GAMMA_RED_MAX_C 0x72010
+#define GAMMA_GREEN_MAX_C 0x72014
+#define GAMMA_BLUE_MAX_C 0x72018
#define IS_I830(dev) ((dev)->pci_device == PCI_DEVICE_ID_INTEL_82830_CGC)
#define IS_845G(dev) ((dev)->pci_device == PCI_DEVICE_ID_INTEL_82845G_IG)
* MOORESTOWN delta registers
*/
#define PSB_DSI_PLL_CTRL 0x0f014
+#define MRST_DPLL_A 0x0f014
#define PSB_DPLL_CTRL 0x0f018
#define MDFLD_INPUT_REF_SEL (1 << 14)
#define MDFLD_VCO_SEL (1 << 16)
#define MDFLD_PWR_GATE_EN (1 << 30)
#define MDFLD_P1_MASK (0x1FF << 17)
#define PSB_DSI_PLL_DIV_M1 0x0f040
+#define MRST_FPA0 0x0f040
#define PSB_DPLL_DIV0 0x0f048
#define MRST_PERF_MODE 0x020f4
* Moorestown registers.
*/
/*===========================================================================
+; General Constants
+;--------------------------------------------------------------------------*/
+#define BIT0 0x00000001
+#define BIT1 0x00000002
+#define BIT2 0x00000004
+#define BIT3 0x00000008
+#define BIT4 0x00000010
+#define BIT5 0x00000020
+#define BIT6 0x00000040
+#define BIT7 0x00000080
+#define BIT8 0x00000100
+#define BIT9 0x00000200
+#define BIT10 0x00000400
+#define BIT11 0x00000800
+#define BIT12 0x00001000
+#define BIT13 0x00002000
+#define BIT14 0x00004000
+#define BIT15 0x00008000
+#define BIT16 0x00010000
+#define BIT17 0x00020000
+#define BIT18 0x00040000
+#define BIT19 0x00080000
+#define BIT20 0x00100000
+#define BIT21 0x00200000
+#define BIT22 0x00400000
+#define BIT23 0x00800000
+#define BIT24 0x01000000
+#define BIT25 0x02000000
+#define BIT26 0x04000000
+#define BIT27 0x08000000
+#define BIT28 0x10000000
+#define BIT29 0x20000000
+#define BIT30 0x40000000
+#define BIT31 0x80000000
+/*===========================================================================
; MIPI IP registers
;--------------------------------------------------------------------------*/
#define MIPIC_REG_OFFSET 0x800
#define SKU_100 0x02
#define SKU_100L 0x04
#define SKU_BYPASS 0x08
+
+/* MDFLD delta registers */
+#define PIPEB 0x1
+#define PIPEC 0x2
+#define PIPEB_OFFSET 0x1000
+#define PIPEC_OFFSET 0x2000
+#define PIPEA_COLOR_COEF0 0x60070
+ #define CC_1_POS 16
+ #define CC_0_POS 0
+#define PIPEA_COLOR_COEF2 0x60074
+#define PIPEA_COLOR_COEF11 0x60078
+#define PIPEA_COLOR_COEF12 0x6007c
+#define PIPEA_COLOR_COEF21 0x60080
+#define PIPEA_COLOR_COEF22 0x60084
+#define PIPEB_COLOR_COEF0 0x61070
+#define PIPEB_COLOR_COEF2 0x61074
+#define PIPEB_COLOR_COEF11 0x61078
+#define PIPEB_COLOR_COEF12 0x6107c
+#define PIPEB_COLOR_COEF21 0x61080
+#define PIPEB_COLOR_COEF22 0x61084
+#define PIPEC_COLOR_COEF0 0x62070
+#define PIPEC_COLOR_COEF2 0x62074
+#define PIPEC_COLOR_COEF11 0x62078
+#define PIPEC_COLOR_COEF12 0x6207c
+#define PIPEC_COLOR_COEF21 0x62080
+#define PIPEC_COLOR_COEF22 0x62084
+
#if 0
/* ************************************************************************* *\
DSI command data structure
*/
static int mdfld_save_pipe_registers(struct drm_device *dev, int pipe)
{
+#if 0
struct drm_psb_private *dev_priv = dev->dev_private;
struct psb_pipe_regs *pr = &dev_priv->pipe_regs[pipe];
int i;
/*save palette (gamma) */
for (i = 0; i < ARRAY_SIZE(pr->palette); i++)
pr->palette[i] = PSB_RVDC32(palette_reg(pipe, i));
-
+#endif
return 0;
}
/*
*/
static int mdfld_restore_pipe_registers(struct drm_device *dev, int pipe)
{
+#if 0
//to get panel out of ULPS mode.
u32 temp = 0;
struct drm_psb_private *dev_priv = dev->dev_private;
/*DRM_UDELAY(50000); */
for (i = 0; i < ARRAY_SIZE(pr->palette); i++)
PSB_WVDC32(pr->palette[i], palette_reg(pipe, i));
-
+#endif
return 0;
}
#define IPC_CMD_PANEL_ON 1
#define IPC_CMD_PANEL_OFF 0
+typedef enum _UHBUsage
+{
+ OSPM_UHB_ONLY_IF_ON = 0,
+ OSPM_UHB_FORCE_POWER_ON,
+} UHBUsage;
+
//extern int psb_check_msvdx_idle(struct drm_device *dev);
//extern int lnc_check_topaz_idle(struct drm_device *dev);
/* Use these functions to power down video HW for D0i3 purpose */
projects / platform / kernel / kernel-mfld-blackbay.git / commitdiff