msm:disp:dpu1: add scaler support on SC7180 display

Add scaler support for display driver.

This patch has dependency on the below series

https://patchwork.kernel.org/patch/11260267/

Co-developed-by: Raviteja Tamatam <travitej@codeaurora.org>
Signed-off-by: Raviteja Tamatam <travitej@codeaurora.org>
Signed-off-by: Shubhashree Dhar <dhar@codeaurora.org>
Signed-off-by: Rob Clark <robdclark@chromium.org>

diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
index 69de2c3..c567917 100644 (file)
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
@@ -183,7 +183,7 @@ static const struct dpu_sspp_blks_common sdm845_sspp_common = {
        .maxvdeciexp = MAX_VERT_DECIMATION,
 };
 
-#define _VIG_SBLK(num, sdma_pri) \
+#define _VIG_SBLK(num, sdma_pri, qseed_ver) \
        { \
        .common = &sdm845_sspp_common, \
        .maxdwnscale = MAX_DOWNSCALE_RATIO, \
@@ -192,7 +192,7 @@ static const struct dpu_sspp_blks_common sdm845_sspp_common = {
        .src_blk = {.name = STRCAT("sspp_src_", num), \
                .id = DPU_SSPP_SRC, .base = 0x00, .len = 0x150,}, \
        .scaler_blk = {.name = STRCAT("sspp_scaler", num), \
-               .id = DPU_SSPP_SCALER_QSEED3, \
+               .id = qseed_ver, \
                .base = 0xa00, .len = 0xa0,}, \
        .csc_blk = {.name = STRCAT("sspp_csc", num), \
                .id = DPU_SSPP_CSC_10BIT, \
@@ -217,10 +217,14 @@ static const struct dpu_sspp_blks_common sdm845_sspp_common = {
        .virt_num_formats = ARRAY_SIZE(plane_formats), \
        }
 
-static const struct dpu_sspp_sub_blks sdm845_vig_sblk_0 = _VIG_SBLK("0", 5);
-static const struct dpu_sspp_sub_blks sdm845_vig_sblk_1 = _VIG_SBLK("1", 6);
-static const struct dpu_sspp_sub_blks sdm845_vig_sblk_2 = _VIG_SBLK("2", 7);
-static const struct dpu_sspp_sub_blks sdm845_vig_sblk_3 = _VIG_SBLK("3", 8);
+static const struct dpu_sspp_sub_blks sdm845_vig_sblk_0 =
+                               _VIG_SBLK("0", 5, DPU_SSPP_SCALER_QSEED3);
+static const struct dpu_sspp_sub_blks sdm845_vig_sblk_1 =
+                               _VIG_SBLK("1", 6, DPU_SSPP_SCALER_QSEED3);
+static const struct dpu_sspp_sub_blks sdm845_vig_sblk_2 =
+                               _VIG_SBLK("2", 7, DPU_SSPP_SCALER_QSEED3);
+static const struct dpu_sspp_sub_blks sdm845_vig_sblk_3 =
+                               _VIG_SBLK("3", 8, DPU_SSPP_SCALER_QSEED3);
 
 static const struct dpu_sspp_sub_blks sdm845_dma_sblk_0 = _DMA_SBLK("8", 1);
 static const struct dpu_sspp_sub_blks sdm845_dma_sblk_1 = _DMA_SBLK("9", 2);
@@ -258,9 +262,12 @@ static const struct dpu_sspp_cfg sdm845_sspp[] = {
                sdm845_dma_sblk_3, 13, SSPP_TYPE_DMA, DPU_CLK_CTRL_CURSOR1),
 };
 
+static const struct dpu_sspp_sub_blks sc7180_vig_sblk_0 =
+                               _VIG_SBLK("0", 4, DPU_SSPP_SCALER_QSEED4);
+
 static const struct dpu_sspp_cfg sc7180_sspp[] = {
        SSPP_BLK("sspp_0", SSPP_VIG0, 0x4000, VIG_SC7180_MASK,
-               sdm845_vig_sblk_0, 0,  SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG0),
+               sc7180_vig_sblk_0, 0,  SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG0),
        SSPP_BLK("sspp_8", SSPP_DMA0, 0x24000,  DMA_SDM845_MASK,
                sdm845_dma_sblk_0, 1, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA0),
        SSPP_BLK("sspp_9", SSPP_DMA1, 0x26000,  DMA_SDM845_MASK,

diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
index 8ff532a..09df7d8 100644 (file)
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
@@ -94,6 +94,7 @@ enum {
  * @DPU_SSPP_SRC             Src and fetch part of the pipes,
  * @DPU_SSPP_SCALER_QSEED2,  QSEED2 algorithm support
  * @DPU_SSPP_SCALER_QSEED3,  QSEED3 alogorithm support
+ * @DPU_SSPP_SCALER_QSEED4,  QSEED4 algorithm support
  * @DPU_SSPP_SCALER_RGB,     RGB Scaler, supported by RGB pipes
  * @DPU_SSPP_CSC,            Support of Color space converion
  * @DPU_SSPP_CSC_10BIT,      Support of 10-bit Color space conversion
@@ -326,6 +327,7 @@ struct dpu_sspp_blks_common {
  * @maxupscale:  maxupscale ratio supported
  * @smart_dma_priority: hw priority of rect1 of multirect pipe
  * @max_per_pipe_bw: maximum allowable bandwidth of this pipe in kBps
+ * @qseed_ver: qseed version
  * @src_blk:
  * @scaler_blk:
  * @csc_blk:
@@ -346,6 +348,7 @@ struct dpu_sspp_sub_blks {
        u32 maxupscale;
        u32 smart_dma_priority;
        u32 max_per_pipe_bw;
+       u32 qseed_ver;
        struct dpu_src_blk src_blk;
        struct dpu_scaler_blk scaler_blk;
        struct dpu_pp_blk csc_blk;

diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c
index a315c54..82c5dbf 100644 (file)
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c
@@ -132,6 +132,7 @@
 /* traffic shaper clock in Hz */
 #define TS_CLK                 19200000
 
+
 static int _sspp_subblk_offset(struct dpu_hw_pipe *ctx,
                int s_id,
                u32 *idx)
@@ -657,7 +658,8 @@ static void _setup_layer_ops(struct dpu_hw_pipe *c,
                test_bit(DPU_SSPP_SMART_DMA_V2, &c->cap->features))
                c->ops.setup_multirect = dpu_hw_sspp_setup_multirect;
 
-       if (test_bit(DPU_SSPP_SCALER_QSEED3, &features)) {
+       if (test_bit(DPU_SSPP_SCALER_QSEED3, &features) ||
+                       test_bit(DPU_SSPP_SCALER_QSEED4, &features)) {
                c->ops.setup_scaler = _dpu_hw_sspp_setup_scaler3;
                c->ops.get_scaler_ver = _dpu_hw_sspp_get_scaler3_ver;
        }

diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h
index 31ec12d..85b018a 100644 (file)
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h
@@ -27,7 +27,8 @@ struct dpu_hw_pipe;
  */
 #define DPU_SSPP_SCALER ((1UL << DPU_SSPP_SCALER_RGB) | \
        (1UL << DPU_SSPP_SCALER_QSEED2) | \
-       (1UL << DPU_SSPP_SCALER_QSEED3))
+        (1UL << DPU_SSPP_SCALER_QSEED3) | \
+         (1UL << DPU_SSPP_SCALER_QSEED4))
 
 /**
  * Component indices

diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
index 58d5acb..3914753 100644 (file)
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
@@ -53,8 +53,13 @@ enum {
        R_MAX
 };
 
+/*
+ * Default Preload Values
+ */
 #define DPU_QSEED3_DEFAULT_PRELOAD_H 0x4
 #define DPU_QSEED3_DEFAULT_PRELOAD_V 0x3
+#define DPU_QSEED4_DEFAULT_PRELOAD_V 0x2
+#define DPU_QSEED4_DEFAULT_PRELOAD_H 0x4
 
 #define DEFAULT_REFRESH_RATE   60
 
@@ -477,8 +482,16 @@ static void _dpu_plane_setup_scaler3(struct dpu_plane *pdpu,
                        scale_cfg->src_width[i] /= chroma_subsmpl_h;
                        scale_cfg->src_height[i] /= chroma_subsmpl_v;
                }
-               scale_cfg->preload_x[i] = DPU_QSEED3_DEFAULT_PRELOAD_H;
-               scale_cfg->preload_y[i] = DPU_QSEED3_DEFAULT_PRELOAD_V;
+
+               if (pdpu->pipe_hw->cap->features &
+                       BIT(DPU_SSPP_SCALER_QSEED4)) {
+                       scale_cfg->preload_x[i] = DPU_QSEED4_DEFAULT_PRELOAD_H;
+                       scale_cfg->preload_y[i] = DPU_QSEED4_DEFAULT_PRELOAD_V;
+               } else {
+                       scale_cfg->preload_x[i] = DPU_QSEED3_DEFAULT_PRELOAD_H;
+                       scale_cfg->preload_y[i] = DPU_QSEED3_DEFAULT_PRELOAD_V;
+               }
+
                pstate->pixel_ext.num_ext_pxls_top[i] =
                        scale_cfg->src_height[i];
                pstate->pixel_ext.num_ext_pxls_left[i] =
@@ -1337,7 +1350,8 @@ static int _dpu_plane_init_debugfs(struct drm_plane *plane)
                        pdpu->debugfs_root, &pdpu->debugfs_src);
 
        if (cfg->features & BIT(DPU_SSPP_SCALER_QSEED3) ||
-                       cfg->features & BIT(DPU_SSPP_SCALER_QSEED2)) {
+                       cfg->features & BIT(DPU_SSPP_SCALER_QSEED2) ||
+                       cfg->features & BIT(DPU_SSPP_SCALER_QSEED4)) {
                dpu_debugfs_setup_regset32(&pdpu->debugfs_scaler,
                                sblk->scaler_blk.base + cfg->base,
                                sblk->scaler_blk.len,