[MIPS] Malta: Fix for SOCitSC based Maltas

And an attempt to tidy up the core/controller differences.

Signed-off-by: Chris Dearman <chris@mips.com>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>

diff --git a/arch/mips/mips-boards/generic/init.c b/arch/mips/mips-boards/generic/init.c
index 88e9c2a..4eabc1e 100644 (file)
--- a/arch/mips/mips-boards/generic/init.c
+++ b/arch/mips/mips-boards/generic/init.c
@@ -57,7 +57,8 @@ int *_prom_argv, *_prom_envp;
 
 int init_debug = 0;
 
-unsigned int mips_revision_corid;
+int mips_revision_corid;
+int mips_revision_sconid;
 
 /* Bonito64 system controller register base. */
 unsigned long _pcictrl_bonito;
@@ -275,13 +276,38 @@ void __init prom_init(void)
                else
                        mips_revision_corid = MIPS_REVISION_CORID_CORE_EMUL_MSC;
        }
-       switch(mips_revision_corid) {
+
+       mips_revision_sconid = MIPS_REVISION_SCONID;
+       if (mips_revision_sconid == MIPS_REVISION_SCON_OTHER) {
+               switch (mips_revision_corid) {
+               case MIPS_REVISION_CORID_QED_RM5261:
+               case MIPS_REVISION_CORID_CORE_LV:
+               case MIPS_REVISION_CORID_CORE_FPGA:
+               case MIPS_REVISION_CORID_CORE_FPGAR2:
+                       mips_revision_sconid = MIPS_REVISION_SCON_GT64120;
+                       break;
+               case MIPS_REVISION_CORID_CORE_EMUL_BON:
+               case MIPS_REVISION_CORID_BONITO64:
+               case MIPS_REVISION_CORID_CORE_20K:
+                       mips_revision_sconid = MIPS_REVISION_SCON_BONITO;
+                       break;
+               case MIPS_REVISION_CORID_CORE_MSC:
+               case MIPS_REVISION_CORID_CORE_FPGA2:
+               case MIPS_REVISION_CORID_CORE_FPGA3:
+               case MIPS_REVISION_CORID_CORE_24K:
+               case MIPS_REVISION_CORID_CORE_EMUL_MSC:
+                       mips_revision_sconid = MIPS_REVISION_SCON_SOCIT;
+                       break;
+               default:
+                       mips_display_message("CC Error");
+                       while (1);   /* We die here... */
+               }
+       }
+
+       switch (mips_revision_sconid) {
                u32 start, map, mask, data;
 
-       case MIPS_REVISION_CORID_QED_RM5261:
-       case MIPS_REVISION_CORID_CORE_LV:
-       case MIPS_REVISION_CORID_CORE_FPGA:
-       case MIPS_REVISION_CORID_CORE_FPGAR2:
+       case MIPS_REVISION_SCON_GT64120:
                /*
                 * Setup the North bridge to do Master byte-lane swapping
                 * when running in bigendian.
@@ -305,9 +331,7 @@ void __init prom_init(void)
                set_io_port_base(MALTA_GT_PORT_BASE);
                break;
 
-       case MIPS_REVISION_CORID_CORE_EMUL_BON:
-       case MIPS_REVISION_CORID_BONITO64:
-       case MIPS_REVISION_CORID_CORE_20K:
+       case MIPS_REVISION_SCON_BONITO:
                _pcictrl_bonito_pcicfg = (unsigned long)ioremap(BONITO_PCICFG_BASE, BONITO_PCICFG_SIZE);
 
                /*
@@ -334,13 +358,10 @@ void __init prom_init(void)
                set_io_port_base(MALTA_BONITO_PORT_BASE);
                break;
 
-       case MIPS_REVISION_CORID_CORE_MSC:
-       case MIPS_REVISION_CORID_CORE_FPGA2:
-       case MIPS_REVISION_CORID_CORE_FPGA3:
-       case MIPS_REVISION_CORID_CORE_24K:
-       case MIPS_REVISION_CORID_CORE_EMUL_MSC:
+       case MIPS_REVISION_SCON_SOCIT:
+       case MIPS_REVISION_SCON_ROCIT:
                _pcictrl_msc = (unsigned long)ioremap(MIPS_MSC01_PCI_REG_BASE, 0x2000);
-
+       mips_pci_controller:
                mb();
                MSC_READ(MSC01_PCI_CFG, data);
                MSC_WRITE(MSC01_PCI_CFG, data & ~MSC01_PCI_CFG_EN_BIT);
@@ -374,10 +395,15 @@ void __init prom_init(void)
                set_io_port_base(MALTA_MSC_PORT_BASE);
                break;
 
+       case MIPS_REVISION_SCON_SOCITSC:
+       case MIPS_REVISION_SCON_SOCITSCP:
+               _pcictrl_msc = (unsigned long)ioremap(MIPS_SOCITSC_PCI_REG_BASE, 0x2000);
+               goto mips_pci_controller;
+
        default:
-               /* Unknown Core card */
-               mips_display_message("CC Error");
-               while(1);   /* We die here... */
+               /* Unknown system controller */
+               mips_display_message("SC Error");
+               while (1);   /* We die here... */
        }
 #endif
        board_nmi_handler_setup = mips_nmi_setup;

diff --git a/arch/mips/mips-boards/generic/pci.c b/arch/mips/mips-boards/generic/pci.c
index f98d60f..c985220 100644 (file)
--- a/arch/mips/mips-boards/generic/pci.c
+++ b/arch/mips/mips-boards/generic/pci.c
@@ -92,11 +92,8 @@ void __init mips_pcibios_init(void)
        struct pci_controller *controller;
        resource_size_t start, end, map, start1, end1, map1, map2, map3, mask;
 
-       switch (mips_revision_corid) {
-       case MIPS_REVISION_CORID_QED_RM5261:
-       case MIPS_REVISION_CORID_CORE_LV:
-       case MIPS_REVISION_CORID_CORE_FPGA:
-       case MIPS_REVISION_CORID_CORE_FPGAR2:
+       switch (mips_revision_sconid) {
+       case MIPS_REVISION_SCON_GT64120:
                /*
                 * Due to a bug in the Galileo system controller, we need
                 * to setup the PCI BAR for the Galileo internal registers.
@@ -161,9 +158,7 @@ void __init mips_pcibios_init(void)
                controller = &gt64120_controller;
                break;
 
-       case MIPS_REVISION_CORID_BONITO64:
-       case MIPS_REVISION_CORID_CORE_20K:
-       case MIPS_REVISION_CORID_CORE_EMUL_BON:
+       case MIPS_REVISION_SCON_BONITO:
                /* Set up resource ranges from the controller's registers.  */
                map = BONITO_PCIMAP;
                map1 = (BONITO_PCIMAP & BONITO_PCIMAP_PCIMAP_LO0) >>
@@ -195,11 +190,10 @@ void __init mips_pcibios_init(void)
                controller = &bonito64_controller;
                break;
 
-       case MIPS_REVISION_CORID_CORE_MSC:
-       case MIPS_REVISION_CORID_CORE_FPGA2:
-       case MIPS_REVISION_CORID_CORE_FPGA3:
-       case MIPS_REVISION_CORID_CORE_24K:
-       case MIPS_REVISION_CORID_CORE_EMUL_MSC:
+       case MIPS_REVISION_SCON_SOCIT:
+       case MIPS_REVISION_SCON_ROCIT:
+       case MIPS_REVISION_SCON_SOCITSC:
+       case MIPS_REVISION_SCON_SOCITSCP:
                /* Set up resource ranges from the controller's registers.  */
                MSC_READ(MSC01_PCI_SC2PMBASL, start);
                MSC_READ(MSC01_PCI_SC2PMMSKL, mask);

diff --git a/arch/mips/mips-boards/malta/malta_int.c b/arch/mips/mips-boards/malta/malta_int.c
index 1cd830e..1668cc2 100644 (file)
--- a/arch/mips/mips-boards/malta/malta_int.c
+++ b/arch/mips/mips-boards/malta/malta_int.c
@@ -53,25 +53,19 @@ static inline int mips_pcibios_iack(void)
         * Determine highest priority pending interrupt by performing
         * a PCI Interrupt Acknowledge cycle.
         */
-       switch(mips_revision_corid) {
-       case MIPS_REVISION_CORID_CORE_MSC:
-       case MIPS_REVISION_CORID_CORE_FPGA2:
-       case MIPS_REVISION_CORID_CORE_FPGA3:
-       case MIPS_REVISION_CORID_CORE_24K:
-       case MIPS_REVISION_CORID_CORE_EMUL_MSC:
+       switch (mips_revision_sconid) {
+       case MIPS_REVISION_SCON_SOCIT:
+       case MIPS_REVISION_SCON_ROCIT:
+       case MIPS_REVISION_SCON_SOCITSC:
+       case MIPS_REVISION_SCON_SOCITSCP:
                MSC_READ(MSC01_PCI_IACK, irq);
                irq &= 0xff;
                break;
-       case MIPS_REVISION_CORID_QED_RM5261:
-       case MIPS_REVISION_CORID_CORE_LV:
-       case MIPS_REVISION_CORID_CORE_FPGA:
-       case MIPS_REVISION_CORID_CORE_FPGAR2:
+       case MIPS_REVISION_SCON_GT64120:
                irq = GT_READ(GT_PCI0_IACK_OFS);
                irq &= 0xff;
                break;
-       case MIPS_REVISION_CORID_BONITO64:
-       case MIPS_REVISION_CORID_CORE_20K:
-       case MIPS_REVISION_CORID_CORE_EMUL_BON:
+       case MIPS_REVISION_SCON_BONITO:
                /* The following will generate a PCI IACK cycle on the
                 * Bonito controller. It's a little bit kludgy, but it
                 * was the easiest way to implement it in hardware at
@@ -89,7 +83,7 @@ static inline int mips_pcibios_iack(void)
                BONITO_PCIMAP_CFG = 0;
                break;
        default:
-               printk("Unknown Core card, don't know the system controller.\n");
+               printk("Unknown system controller.\n");
                return -1;
        }
        return irq;
@@ -144,27 +138,21 @@ static void corehi_irqdispatch(void)
           Do it for the others too.
        */
 
-        switch(mips_revision_corid) {
-        case MIPS_REVISION_CORID_CORE_MSC:
-        case MIPS_REVISION_CORID_CORE_FPGA2:
-        case MIPS_REVISION_CORID_CORE_FPGA3:
-        case MIPS_REVISION_CORID_CORE_24K:
-        case MIPS_REVISION_CORID_CORE_EMUL_MSC:
+       switch (mips_revision_sconid) {
+        case MIPS_REVISION_SCON_SOCIT:
+       case MIPS_REVISION_SCON_ROCIT:
+       case MIPS_REVISION_SCON_SOCITSC:
+       case MIPS_REVISION_SCON_SOCITSCP:
                 ll_msc_irq();
                 break;
-        case MIPS_REVISION_CORID_QED_RM5261:
-        case MIPS_REVISION_CORID_CORE_LV:
-        case MIPS_REVISION_CORID_CORE_FPGA:
-        case MIPS_REVISION_CORID_CORE_FPGAR2:
+        case MIPS_REVISION_SCON_GT64120:
                 intrcause = GT_READ(GT_INTRCAUSE_OFS);
                 datalo = GT_READ(GT_CPUERR_ADDRLO_OFS);
                 datahi = GT_READ(GT_CPUERR_ADDRHI_OFS);
                 printk("GT_INTRCAUSE = %08x\n", intrcause);
                 printk("GT_CPUERR_ADDR = %02x%08x\n", datahi, datalo);
                 break;
-        case MIPS_REVISION_CORID_BONITO64:
-        case MIPS_REVISION_CORID_CORE_20K:
-        case MIPS_REVISION_CORID_CORE_EMUL_BON:
+        case MIPS_REVISION_SCON_BONITO:
                 pcibadaddr = BONITO_PCIBADADDR;
                 pcimstat = BONITO_PCIMSTAT;
                 intisr = BONITO_INTISR;

diff --git a/arch/mips/mips-boards/malta/malta_setup.c b/arch/mips/mips-boards/malta/malta_setup.c
index c14b7bf..8f1b78d 100644 (file)
--- a/arch/mips/mips-boards/malta/malta_setup.c
+++ b/arch/mips/mips-boards/malta/malta_setup.c
@@ -103,9 +103,7 @@ void __init plat_mem_setup(void)
        kgdb_config ();
 #endif
 
-       if ((mips_revision_corid == MIPS_REVISION_CORID_BONITO64) ||
-           (mips_revision_corid == MIPS_REVISION_CORID_CORE_20K) ||
-           (mips_revision_corid == MIPS_REVISION_CORID_CORE_EMUL_BON)) {
+       if (mips_revision_sconid == MIPS_REVISION_SCON_BONITO) {
                char *argptr;
 
                argptr = prom_getcmdline();

diff --git a/include/asm-mips/mips-boards/generic.h b/include/asm-mips/mips-boards/generic.h
index b98f165..c8ebcc3 100644 (file)
--- a/include/asm-mips/mips-boards/generic.h
+++ b/include/asm-mips/mips-boards/generic.h
@@ -73,12 +73,28 @@
  *  CoreEMUL with   Bonito   System Controller is treated like a Core20K
  *  CoreEMUL with SOC-it 101 System Controller is treated like a CoreMSC
  */
-#define MIPS_REVISION_CORID_CORE_EMUL_BON  0x63
-#define MIPS_REVISION_CORID_CORE_EMUL_MSC  0x65
+#define MIPS_REVISION_CORID_CORE_EMUL_BON  -1
+#define MIPS_REVISION_CORID_CORE_EMUL_MSC  -2
 
 #define MIPS_REVISION_CORID (((*(volatile u32 *)ioremap(MIPS_REVISION_REG, 4)) >> 10) & 0x3f)
 
-extern unsigned int mips_revision_corid;
+extern int mips_revision_corid;
+
+#define MIPS_REVISION_SCON_OTHER          0
+#define MIPS_REVISION_SCON_SOCITSC        1
+#define MIPS_REVISION_SCON_SOCITSCP       2
+
+/* Artificial SCON defines for MIPS_REVISION_SCON_OTHER */
+#define MIPS_REVISION_SCON_UNKNOWN        -1
+#define MIPS_REVISION_SCON_GT64120        -2
+#define MIPS_REVISION_SCON_BONITO         -3
+#define MIPS_REVISION_SCON_BRTL                   -4
+#define MIPS_REVISION_SCON_SOCIT          -5
+#define MIPS_REVISION_SCON_ROCIT          -6
+
+#define MIPS_REVISION_SCONID (((*(volatile u32 *)ioremap(MIPS_REVISION_REG, 4)) >> 24) & 0xff)
+
+extern int mips_revision_sconid;
 
 #ifdef CONFIG_PCI
 extern void mips_pcibios_init(void);

diff --git a/include/asm-mips/mips-boards/msc01_pci.h b/include/asm-mips/mips-boards/msc01_pci.h
index 8eaefb8..e036b7d 100644 (file)
--- a/include/asm-mips/mips-boards/msc01_pci.h
+++ b/include/asm-mips/mips-boards/msc01_pci.h
@@ -208,6 +208,7 @@
  * latter, they should be moved elsewhere.
  */
 #define MIPS_MSC01_PCI_REG_BASE                0x1bd00000
+#define MIPS_SOCITSC_PCI_REG_BASE      0x1ff10000
 
 extern unsigned long _pcictrl_msc;