ARM: dts: Augment panel setting for Integrator/CP

This adds the actual VGA DAC bridge that is used in the
Versatile AB, and sets the mode to 640x480 VGA and
routes the CLCD pads appropriately.

Cc: Liviu Dudau <liviu.dudau@arm.com>
Cc: Mali DP Maintainers <malidp@foss.arm.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>

diff --git a/arch/arm/boot/dts/integratorcp.dts b/arch/arm/boot/dts/integratorcp.dts
index a185ab8..01fa229 100644 (file)
--- a/arch/arm/boot/dts/integratorcp.dts
+++ b/arch/arm/boot/dts/integratorcp.dts
@@ -192,6 +192,43 @@
                interrupts = <27>;
        };
 
+       bridge {
+               compatible = "ti,ths8134a", "ti,ths8134";
+               #address-cells = <1>;
+               #size-cells = <0>;
+
+               ports {
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+
+                       port@0 {
+                               reg = <0>;
+
+                               vga_bridge_in: endpoint {
+                                       remote-endpoint = <&clcd_pads_vga_dac>;
+                               };
+                       };
+
+                       port@1 {
+                               reg = <1>;
+
+                               vga_bridge_out: endpoint {
+                                       remote-endpoint = <&vga_con_in>;
+                               };
+                       };
+               };
+       };
+
+       vga {
+               compatible = "vga-connector";
+
+               port {
+                       vga_con_in: endpoint {
+                               remote-endpoint = <&vga_bridge_out>;
+                       };
+               };
+       };
+
        fpga {
                /*
                 * These PrimeCells are at the same location and using
@@ -254,39 +291,27 @@
                        interrupts = <22>;
                        clocks = <&auxosc>, <&pclk>;
                        clock-names = "clcdclk", "apb_pclk";
+                       /* 640x480 16bpp @ 25.175MHz is 36827428 bytes/s */
+                       max-memory-bandwidth = <40000000>;
 
-                       port {
-                               /*
-                                * The VGA connected is implemented with a
-                                * THS8134A triple DAC that can be run in 24bit
-                                * or 16bit RGB mode.
-                                */
-                               clcd_pads: endpoint {
-                                       remote-endpoint = <&clcd_panel>;
-                                       arm,pl11x,tft-r0g0b0-pads = <1 7 13>;
-                               };
-                       };
-
-                       panel {
-                               compatible = "panel-dpi";
-
-                               port {
-                                       clcd_panel: endpoint {
-                                               remote-endpoint = <&clcd_pads>;
-                                       };
-                               };
-
-                               /* Standard 640x480 VGA timings */
-                               panel-timing {
-                                       clock-frequency = <25175000>;
-                                       hactive = <640>;
-                                       hback-porch = <48>;
-                                       hfront-porch = <16>;
-                                       hsync-len = <96>;
-                                       vactive = <480>;
-                                       vback-porch = <33>;
-                                       vfront-porch = <10>;
-                                       vsync-len = <2>;
+                       /*
+                        * This port is routed through a PLD (Programmable
+                        * Logic Device) that routes the output from the CLCD
+                        * (after transformations) to the VGA DAC and also an
+                        * external panel connector. The PLD is essential for
+                        * supporting RGB565/BGR565.
+                        *
+                        * The signals from the port thus reaches two endpoints.
+                        * The PLD is managed through a few special bits in the
+                        * FPGA "sysreg".
+                        *
+                        * This arrangement can be clearly seen in
+                        * ARM DUI 0225D, page 3-41, figure 3-19.
+                        */
+                       port@0 {
+                               clcd_pads_vga_dac: endpoint {
+                                       remote-endpoint = <&vga_bridge_in>;
+                                       arm,pl11x,tft-r0g0b0-pads = <0 8 16>;
                                };
                        };
                };