;; Instructions generated through builtins
(define_insn "clrsbsi2"
- [(set (match_operand:SI 0 "dest_reg_operand" "=w,w")
- (clrsb:SI (match_operand:SI 1 "general_operand" "cL,Cal")))]
+ [(set (match_operand:SI 0 "dest_reg_operand" "=r,r")
+ (clrsb:SI (match_operand:SI 1 "general_operand" "rL,Cal")))]
"TARGET_NORM"
- "@
- norm \t%0, %1
- norm \t%0, %1"
+ "norm\\t%0,%1"
[(set_attr "length" "4,8")
(set_attr "type" "two_cycle_core,two_cycle_core")])
(define_insn "norm_f"
- [(set (match_operand:SI 0 "dest_reg_operand" "=w,w")
- (clrsb:SI (match_operand:SI 1 "general_operand" "cL,Cal")))
+ [(set (match_operand:SI 0 "dest_reg_operand" "=r,r")
+ (clrsb:SI (match_operand:SI 1 "general_operand" "rL,Cal")))
(set (reg:CC_ZN CC_REG)
(compare:CC_ZN (match_dup 1) (const_int 0)))]
"TARGET_NORM"
- "@
- norm.f\t%0, %1
- norm.f\t%0, %1"
+ "norm.f\\t%0,%1"
[(set_attr "length" "4,8")
(set_attr "type" "two_cycle_core,two_cycle_core")])
(clz:SI (match_operand:SI 1 "register_operand" "")))
(clobber (match_dup 2))])]
"TARGET_NORM"
- "operands[2] = gen_rtx_REG (CC_ZNmode, CC_REG);")
+ "
+ if (TARGET_V2)
+ {
+ /* ARCv2's FLS is a bit more optimal than using norm. */
+ rtx tmp = gen_reg_rtx (SImode);
+ emit_insn (gen_fls (tmp, operands[1]));
+ emit_insn (gen_subsi3 (operands[0], GEN_INT (31), tmp));
+ DONE;
+ }
+ operands[2] = gen_rtx_REG (CC_ZNmode, CC_REG);
+ ")
(define_insn_and_split "*arc_clzsi2"
[(set (match_operand:SI 0 "register_operand" "=r")
(match_operand:SI 1 "register_operand" "")]
"TARGET_NORM"
"
- emit_insn (gen_arc_ctzsi2 (operands[0], operands[1]));
- DONE;
+ if (TARGET_V2)
+ {
+ emit_insn (gen_ffs (operands[0], operands[1]));
+ DONE;
+ }
+ emit_insn (gen_arc_ctzsi2 (operands[0], operands[1]));
+ DONE;
")
(define_insn_and_split "arc_ctzsi2"
(set_attr "type" "misc")])
(define_insn "ffs"
- [(set (match_operand:SI 0 "dest_reg_operand" "=w,w")
- (unspec:SI [(match_operand:SI 1 "general_operand" "cL,Cal")]
+ [(set (match_operand:SI 0 "dest_reg_operand" "=r,r")
+ (unspec:SI [(match_operand:SI 1 "general_operand" "rL,Cal")]
UNSPEC_ARC_FFS))]
"TARGET_NORM && TARGET_V2"
- "@
- ffs \t%0, %1
- ffs \t%0, %1"
+ "ffs\\t%0,%1"
[(set_attr "length" "4,8")
(set_attr "type" "two_cycle_core,two_cycle_core")])
(define_insn "ffs_f"
- [(set (match_operand:SI 0 "dest_reg_operand" "=w,w")
- (unspec:SI [(match_operand:SI 1 "general_operand" "cL,Cal")]
+ [(set (match_operand:SI 0 "dest_reg_operand" "=r,r")
+ (unspec:SI [(match_operand:SI 1 "general_operand" "rL,Cal")]
UNSPEC_ARC_FFS))
(set (reg:CC_ZN CC_REG)
(compare:CC_ZN (match_dup 1) (const_int 0)))]
"TARGET_NORM && TARGET_V2"
- "@
- ffs.f\t%0, %1
- ffs.f\t%0, %1"
+ "ffs.f\\t%0,%1"
[(set_attr "length" "4,8")
(set_attr "type" "two_cycle_core,two_cycle_core")])