ddr: altera: stratix10: Move SDRAM size check to SDRAM driver

Move SDRAM size check to SDRAM driver. sdram_calculate_size()
is called in SDRAM initialization already, avoid calling
twice in size check function.

Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>

diff --git a/arch/arm/mach-socfpga/spl_s10.c b/arch/arm/mach-socfpga/spl_s10.c
index a3db20a..a141ffe 100644 (file)
--- a/arch/arm/mach-socfpga/spl_s10.c
+++ b/arch/arm/mach-socfpga/spl_s10.c
@@ -181,17 +181,6 @@ void board_init_f(ulong dummy)
                hang();
        }
 
-       gd->ram_size = sdram_calculate_size();
-       printf("DDR: %d MiB\n", (int)(gd->ram_size >> 20));
-
-       /* Sanity check ensure correct SDRAM size specified */
-       debug("DDR: Running SDRAM size sanity check\n");
-       if (get_ram_size(0, gd->ram_size) != gd->ram_size) {
-               puts("DDR: SDRAM size check failed!\n");
-               hang();
-       }
-       debug("DDR: SDRAM size check passed!\n");
-
        mbox_init();
 
 #ifdef CONFIG_CADENCE_QSPI

diff --git a/drivers/ddr/altera/sdram_s10.c b/drivers/ddr/altera/sdram_s10.c
index a48567c..033ccca 100644 (file)
--- a/drivers/ddr/altera/sdram_s10.c
+++ b/drivers/ddr/altera/sdram_s10.c
@@ -134,6 +134,17 @@ static int poll_hmc_clock_status(void)
                                 SYSMGR_HMC_CLK_STATUS_MSK, true, 1000, false);
 }
 
+static void sdram_size_check(void)
+{
+       /* Sanity check ensure correct SDRAM size specified */
+       debug("DDR: Running SDRAM size sanity check\n");
+       if (get_ram_size(0, gd->ram_size) != gd->ram_size) {
+               puts("DDR: SDRAM size check failed!\n");
+               hang();
+       }
+       debug("DDR: SDRAM size check passed!\n");
+}
+
 /**
  * sdram_mmr_init_full() - Function to initialize SDRAM MMR
  *
@@ -339,6 +350,8 @@ int sdram_mmr_init_full(unsigned int unused)
        else
                gd->ram_size = size;
 
+       printf("DDR: %lld MiB\n", gd->ram_size >> 20);
+
        /* Enable or disable the SDRAM ECC */
        if (CTRLCFG1_CFG_CTRL_EN_ECC(ctrlcfg1)) {
                setbits_le32(SOCFPGA_SDR_ADDRESS + ECCCTRL1,
@@ -361,6 +374,8 @@ int sdram_mmr_init_full(unsigned int unused)
                              DDR_HMC_ECCCTL2_AWB_EN_SET_MSK));
        }
 
+       sdram_size_check();
+
        debug("DDR: HMC init success\n");
        return 0;
 }