}
bool
-radv_image_is_renderable(struct radv_device *device, struct radv_image *image)
+radv_image_is_renderable(const struct radv_device *device, const struct radv_image *image)
{
if (image->vk.format == VK_FORMAT_R32G32B32_UINT ||
image->vk.format == VK_FORMAT_R32G32B32_SINT ||
}
enum amd_ip_type
-radv_queue_family_to_ring(struct radv_physical_device *physical_device,
+radv_queue_family_to_ring(const struct radv_physical_device *physical_device,
enum radv_queue_family f)
{
switch (f) {
{
assert(size % 4 == 0);
- struct radeon_info *rad_info = &cmd_buffer->device->physical_device->rad_info;
+ const struct radeon_info *rad_info = &cmd_buffer->device->physical_device->rad_info;
/* Align to the scalar cache line size if it results in this allocation
* being placed in less of them.
bool indirect_draw, bool count_from_stream_output,
uint32_t draw_vertex_count)
{
- struct radeon_info *info = &cmd_buffer->device->physical_device->rad_info;
+ const struct radeon_info *info = &cmd_buffer->device->physical_device->rad_info;
struct radv_cmd_state *state = &cmd_buffer->state;
- unsigned patch_control_points = state->dynamic.vk.ts.patch_control_points;
- unsigned topology = state->dynamic.vk.ia.primitive_topology;
- bool prim_restart_enable = state->dynamic.vk.ia.primitive_restart_enable;
+ const unsigned patch_control_points = state->dynamic.vk.ts.patch_control_points;
+ const unsigned topology = state->dynamic.vk.ia.primitive_topology;
+ const bool prim_restart_enable = state->dynamic.vk.ia.primitive_restart_enable;
struct radeon_cmdbuf *cs = cmd_buffer->cs;
unsigned ia_multi_vgt_param;
static void
radv_emit_draw_registers(struct radv_cmd_buffer *cmd_buffer, const struct radv_draw_info *draw_info)
{
- struct radeon_info *info = &cmd_buffer->device->physical_device->rad_info;
+ const struct radeon_info *info = &cmd_buffer->device->physical_device->rad_info;
struct radv_cmd_state *state = &cmd_buffer->state;
struct radeon_cmdbuf *cs = cmd_buffer->cs;
uint32_t topology = state->dynamic.vk.ia.primitive_topology;
struct radv_queue_state *queue_state)
{
struct radeon_winsys *ws = device->ws;
- struct radeon_info *info = &device->physical_device->rad_info;
+ const struct radeon_info *info = &device->physical_device->rad_info;
VkResult result;
struct radeon_cmdbuf *cs = ws->cs_create(ws, AMD_IP_GFX, false);
VkResult
radv_init_shadowed_regs_buffer_state(const struct radv_device *device, struct radv_queue *queue)
{
- struct radeon_info *info = &device->physical_device->rad_info;
+ const struct radeon_info *info = &device->physical_device->rad_info;
struct radeon_winsys *ws = device->ws;
struct radeon_cmdbuf *cs;
VkResult result;
}
static void
-radv_dump_trace(struct radv_device *device, struct radeon_cmdbuf *cs, FILE *f)
+radv_dump_trace(const struct radv_device *device, struct radeon_cmdbuf *cs, FILE *f)
{
fprintf(f, "Trace ID: %x\n", *device->trace_id_ptr);
device->ws->cs_dump(cs, f, (const int *)device->trace_id_ptr, 2);
}
static void
-radv_dump_mmapped_reg(struct radv_device *device, FILE *f, unsigned offset)
+radv_dump_mmapped_reg(const struct radv_device *device, FILE *f, unsigned offset)
{
struct radeon_winsys *ws = device->ws;
uint32_t value;
}
static void
-radv_dump_debug_registers(struct radv_device *device, FILE *f)
+radv_dump_debug_registers(const struct radv_device *device, FILE *f)
{
- struct radeon_info *info = &device->physical_device->rad_info;
+ const struct radeon_info *info = &device->physical_device->rad_info;
fprintf(f, "Memory-mapped registers:\n");
radv_dump_mmapped_reg(device, f, R_008010_GRBM_STATUS);
}
static void
-radv_dump_descriptor_set(struct radv_device *device, struct radv_descriptor_set *set, unsigned id,
+radv_dump_descriptor_set(const struct radv_device *device, const struct radv_descriptor_set *set, unsigned id,
FILE *f)
{
enum amd_gfx_level gfx_level = device->physical_device->rad_info.gfx_level;
}
static void
-radv_dump_annotated_shader(struct radv_shader *shader, gl_shader_stage stage,
+radv_dump_annotated_shader(const struct radv_shader *shader, gl_shader_stage stage,
struct ac_wave_info *waves, unsigned num_waves, FILE *f)
{
uint64_t start_addr, end_addr;
}
static void
-radv_dump_spirv(struct radv_shader *shader, const char *sha1, const char *dump_dir)
+radv_dump_spirv(const struct radv_shader *shader, const char *sha1, const char *dump_dir)
{
char dump_path[512];
FILE *f;
static void
radv_dump_vertex_descriptors(const struct radv_device *device,
- struct radv_graphics_pipeline *pipeline, FILE *f)
+ const struct radv_graphics_pipeline *pipeline, FILE *f)
{
struct radv_shader *vs = radv_get_shader(pipeline->base.shaders, MESA_SHADER_VERTEX);
void *ptr = (uint64_t *)device->trace_id_ptr;
}
static void
-radv_dump_vs_prolog(const struct radv_device *device, struct radv_graphics_pipeline *pipeline,
+radv_dump_vs_prolog(const struct radv_device *device, const struct radv_graphics_pipeline *pipeline,
FILE *f)
{
struct radv_shader_part *vs_prolog = radv_get_saved_vs_prolog(device);
}
void
-radv_dump_enabled_options(struct radv_device *device, FILE *f)
+radv_dump_enabled_options(const struct radv_device *device, FILE *f)
{
uint64_t mask;
}
static void
-radv_dump_app_info(struct radv_device *device, FILE *f)
+radv_dump_app_info(const struct radv_device *device, FILE *f)
{
- struct radv_instance *instance = device->instance;
+ const struct radv_instance *instance = device->instance;
fprintf(f, "Application name: %s\n", instance->vk.app_info.app_name);
fprintf(f, "Application version: %d\n", instance->vk.app_info.app_version);
}
static void
-radv_dump_device_name(struct radv_device *device, FILE *f)
+radv_dump_device_name(const struct radv_device *device, FILE *f)
{
- struct radeon_info *info = &device->physical_device->rad_info;
+ const struct radeon_info *info = &device->physical_device->rad_info;
#ifndef _WIN32
char kernel_version[128] = {0};
struct utsname uname_data;
}
static void
-radv_dump_umr_ring(struct radv_queue *queue, FILE *f)
+radv_dump_umr_ring(const struct radv_queue *queue, FILE *f)
{
- enum amd_ip_type ring = radv_queue_ring(queue);
- struct radv_device *device = queue->device;
+ const enum amd_ip_type ring = radv_queue_ring(queue);
+ const struct radv_device *device = queue->device;
char cmd[128];
/* TODO: Dump compute ring. */
void radv_print_spirv(const char *data, uint32_t size, FILE *fp);
-void radv_dump_enabled_options(struct radv_device *device, FILE *f);
+void radv_dump_enabled_options(const struct radv_device *device, FILE *f);
bool radv_trap_handler_init(struct radv_device *device);
void radv_trap_handler_finish(struct radv_device *device);
}
static unsigned
-radv_calc_decompress_on_z_planes(struct radv_device *device, struct radv_image_view *iview)
+radv_calc_decompress_on_z_planes(const struct radv_device *device, struct radv_image_view *iview)
{
unsigned max_zplanes = 0;
}
void
-radv_initialise_ds_surface(struct radv_device *device, struct radv_ds_buffer_info *ds,
+radv_initialise_ds_surface(const struct radv_device *device, struct radv_ds_buffer_info *ds,
struct radv_image_view *iview)
{
unsigned level = iview->vk.base_mip_level;
ds->db_z_info |= S_028040_NUM_SAMPLES(util_logbase2(iview->image->vk.samples));
if (device->physical_device->rad_info.gfx_level >= GFX7) {
- struct radeon_info *info = &device->physical_device->rad_info;
+ const struct radeon_info *info = &device->physical_device->rad_info;
unsigned tiling_index = surf->u.legacy.tiling_index[level];
unsigned stencil_index = surf->u.legacy.zs.stencil_tiling_index[level];
unsigned macro_index = surf->u.legacy.macro_tile_index;
}
bool
-radv_is_storage_image_format_supported(struct radv_physical_device *physical_device,
+radv_is_storage_image_format_supported(const struct radv_physical_device *physical_device,
VkFormat format)
{
const struct util_format_description *desc = vk_format_description(format);
static bool
radv_image_is_pipe_misaligned(const struct radv_device *device, const struct radv_image *image)
{
- struct radeon_info *rad_info = &device->physical_device->rad_info;
+ const struct radeon_info *rad_info = &device->physical_device->rad_info;
int log2_samples = util_logbase2(image->vk.samples);
assert(rad_info->gfx_level >= GFX10);
}
static void
-radv_get_device_uuid(struct radeon_info *info, void *uuid)
+radv_get_device_uuid(const struct radeon_info *info, void *uuid)
{
ac_compute_device_uuid(info, uuid, VK_UUID_SIZE);
}
}
uint32_t
-radv_find_memory_index(struct radv_physical_device *pdevice, VkMemoryPropertyFlags flags)
+radv_find_memory_index(const struct radv_physical_device *pdevice, VkMemoryPropertyFlags flags)
{
- VkPhysicalDeviceMemoryProperties *mem_properties = &pdevice->memory_properties;
+ const VkPhysicalDeviceMemoryProperties *mem_properties = &pdevice->memory_properties;
for (uint32_t i = 0; i < mem_properties->memoryTypeCount; ++i) {
if (mem_properties->memoryTypes[i].propertyFlags == flags) {
return i;
uint32_t vid_addr_gfx_mode;
};
-uint32_t radv_find_memory_index(struct radv_physical_device *pdevice, VkMemoryPropertyFlags flags);
+uint32_t radv_find_memory_index(const struct radv_physical_device *pdevice, VkMemoryPropertyFlags flags);
VkResult create_null_physical_device(struct vk_instance *vk_instance);
return phys_dev->vk_queue_to_radv[queue_family_index];
}
-enum amd_ip_type radv_queue_family_to_ring(struct radv_physical_device *physical_device,
+enum amd_ip_type radv_queue_family_to_ring(const struct radv_physical_device *physical_device,
enum radv_queue_family f);
static inline bool
void radv_initialise_color_surface(struct radv_device *device, struct radv_color_buffer_info *cb,
struct radv_image_view *iview);
-void radv_initialise_ds_surface(struct radv_device *device, struct radv_ds_buffer_info *ds,
+void radv_initialise_ds_surface(const struct radv_device *device, struct radv_ds_buffer_info *ds,
struct radv_image_view *iview);
void radv_initialise_vrs_surface(struct radv_image *image, struct radv_buffer *htile_buffer,
struct radv_ds_buffer_info *ds);
int first_non_void);
bool radv_format_pack_clear_color(VkFormat format, uint32_t clear_vals[2],
VkClearColorValue *value);
-bool radv_is_storage_image_format_supported(struct radv_physical_device *physical_device,
+bool radv_is_storage_image_format_supported(const struct radv_physical_device *physical_device,
VkFormat format);
bool radv_is_colorbuffer_format_supported(const struct radv_physical_device *pdevice,
VkFormat format, bool *blendable);
}
static inline bool
-radv_image_get_iterate256(struct radv_device *device, struct radv_image *image)
+radv_image_get_iterate256(const struct radv_device *device, struct radv_image *image)
{
/* ITERATE_256 is required for depth or stencil MSAA images that are TC-compatible HTILE. */
return device->physical_device->rad_info.gfx_level >= GFX10 &&
enum radv_queue_family family,
enum radv_queue_family queue_family);
-bool radv_image_is_renderable(struct radv_device *device, struct radv_image *image);
+bool radv_image_is_renderable(const struct radv_device *device, const struct radv_image *image);
struct radeon_bo_metadata;
void radv_init_metadata(struct radv_device *device, struct radv_image *image,
bool radv_end_sqtt(struct radv_queue *queue);
bool radv_get_sqtt_trace(struct radv_queue *queue, struct ac_sqtt_trace *sqtt_trace);
void radv_reset_sqtt_trace(struct radv_device *device);
-void radv_emit_sqtt_userdata(struct radv_cmd_buffer *cmd_buffer, const void *data,
+void radv_emit_sqtt_userdata(const struct radv_cmd_buffer *cmd_buffer, const void *data,
uint32_t num_dwords);
bool radv_is_instruction_timing_enabled(void);
bool radv_sqtt_sample_clocks(struct radv_device *device);
-void radv_emit_inhibit_clockgating(struct radv_device *device, struct radeon_cmdbuf *cs,
+void radv_emit_inhibit_clockgating(const struct radv_device *device, struct radeon_cmdbuf *cs,
bool inhibit);
-void radv_emit_spi_config_cntl(struct radv_device *device, struct radeon_cmdbuf *cs, bool enable);
+void radv_emit_spi_config_cntl(const struct radv_device *device, struct radeon_cmdbuf *cs, bool enable);
int radv_rra_trace_frame(void);
char *radv_rra_trace_trigger_file(void);
bool is_internal);
void radv_rmv_log_resource_destroy(struct radv_device *device, uint64_t handle);
void radv_rmv_log_submit(struct radv_device *device, enum amd_ip_type type);
-void radv_rmv_fill_device_info(struct radv_physical_device *device,
+void radv_rmv_fill_device_info(const struct radv_physical_device *device,
struct vk_rmv_device_info *info);
void radv_rmv_collect_trace_events(struct radv_device *device);
void radv_memory_trace_finish(struct radv_device *device);
* placed here as it needs queue + device structs.
*/
static inline enum amd_ip_type
-radv_queue_ring(struct radv_queue *queue)
+radv_queue_ring(const struct radv_queue *queue)
{
return radv_queue_family_to_ring(queue->device->physical_device, queue->state.qf);
}
uint32_t size_per_wave, uint32_t waves,
struct radeon_winsys_bo *scratch_bo)
{
- struct radeon_info *info = &device->physical_device->rad_info;
+ const struct radeon_info *info = &device->physical_device->rad_info;
if (!scratch_bo)
return;
uint32_t size_per_wave, uint32_t waves,
struct radeon_winsys_bo *compute_scratch_bo)
{
- struct radeon_info *info = &device->physical_device->rad_info;
+ const struct radeon_info *info = &device->physical_device->rad_info;
uint64_t scratch_va;
uint32_t rsrc1;
}
static void
-fill_memory_info(struct radeon_info *info, struct vk_rmv_memory_info *out_info, int32_t index)
+fill_memory_info(const struct radeon_info *info, struct vk_rmv_memory_info *out_info, int32_t index)
{
switch (index) {
case VK_RMV_MEMORY_LOCATION_DEVICE:
}
void
-radv_rmv_fill_device_info(struct radv_physical_device *device, struct vk_rmv_device_info *info)
+radv_rmv_fill_device_info(const struct radv_physical_device *device, struct vk_rmv_device_info *info)
{
- struct radeon_info *rad_info = &device->rad_info;
+ const struct radeon_info *rad_info = &device->rad_info;
for (int32_t i = 0; i < VK_RMV_MEMORY_LOCATION_COUNT; ++i) {
fill_memory_info(rad_info, &info->memory_infos[i], i);
}
static void
-rra_dump_asic_info(struct radeon_info *rad_info, FILE *output)
+rra_dump_asic_info(const struct radeon_info *rad_info, FILE *output)
{
struct rra_asic_info asic_info = {
/* All frequencies are in Hz */
radv_get_max_waves(const struct radv_device *device, struct radv_shader *shader,
gl_shader_stage stage)
{
- struct radeon_info *info = &device->physical_device->rad_info;
- enum amd_gfx_level gfx_level = info->gfx_level;
- uint8_t wave_size = shader->info.wave_size;
- struct ac_shader_config *conf = &shader->config;
+ const struct radeon_info *info = &device->physical_device->rad_info;
+ const enum amd_gfx_level gfx_level = info->gfx_level;
+ const uint8_t wave_size = shader->info.wave_size;
+ const struct ac_shader_config *conf = &shader->config;
unsigned max_simd_waves;
unsigned lds_per_wave = 0;
}
static uint32_t
-gfx11_get_sqtt_ctrl(struct radv_device *device, bool enable)
+gfx11_get_sqtt_ctrl(const struct radv_device *device, bool enable)
{
return S_0367B0_MODE(enable) | S_0367B0_HIWATER(5) | S_0367B0_UTIL_TIMER(1) |
S_0367B0_RT_FREQ(2) | /* 4096 clk */
}
static uint32_t
-gfx10_get_sqtt_ctrl(struct radv_device *device, bool enable)
+gfx10_get_sqtt_ctrl(const struct radv_device *device, bool enable)
{
uint32_t sqtt_ctrl = S_008D1C_MODE(enable) | S_008D1C_HIWATER(5) | S_008D1C_UTIL_TIMER(1) |
S_008D1C_RT_FREQ(2) | /* 4096 clk */
}
static void
-radv_emit_wait_for_idle(struct radv_device *device, struct radeon_cmdbuf *cs, int family)
+radv_emit_wait_for_idle(const struct radv_device *device, struct radeon_cmdbuf *cs, int family)
{
enum rgp_flush_bits sqtt_flush_bits = 0;
si_cs_emit_cache_flush(
}
static void
-radv_emit_sqtt_start(struct radv_device *device, struct radeon_cmdbuf *cs,
+radv_emit_sqtt_start(const struct radv_device *device, struct radeon_cmdbuf *cs,
enum radv_queue_family qf)
{
uint32_t shifted_size = device->sqtt.buffer_size >> SQTT_BUFFER_ALIGN_SHIFT;
- struct radeon_info *rad_info = &device->physical_device->rad_info;
+ const struct radeon_info *rad_info = &device->physical_device->rad_info;
unsigned max_se = rad_info->max_se;
for (unsigned se = 0; se < max_se; se++) {
R_0367E8_SQ_THREAD_TRACE_DROPPED_CNTR,
};
static void
-radv_copy_sqtt_info_regs(struct radv_device *device, struct radeon_cmdbuf *cs, unsigned se_index)
+radv_copy_sqtt_info_regs(const struct radv_device *device, struct radeon_cmdbuf *cs, unsigned se_index)
{
const struct radv_physical_device *pdevice = device->physical_device;
const uint32_t *sqtt_info_regs = NULL;
}
static void
-radv_emit_sqtt_stop(struct radv_device *device, struct radeon_cmdbuf *cs, enum radv_queue_family qf)
+radv_emit_sqtt_stop(const struct radv_device *device, struct radeon_cmdbuf *cs, enum radv_queue_family qf)
{
unsigned max_se = device->physical_device->rad_info.max_se;
}
void
-radv_emit_sqtt_userdata(struct radv_cmd_buffer *cmd_buffer, const void *data, uint32_t num_dwords)
+radv_emit_sqtt_userdata(const struct radv_cmd_buffer *cmd_buffer, const void *data, uint32_t num_dwords)
{
struct radv_device *device = cmd_buffer->device;
struct radeon_cmdbuf *cs = cmd_buffer->cs;
}
void
-radv_emit_spi_config_cntl(struct radv_device *device, struct radeon_cmdbuf *cs, bool enable)
+radv_emit_spi_config_cntl(const struct radv_device *device, struct radeon_cmdbuf *cs, bool enable)
{
if (device->physical_device->rad_info.gfx_level >= GFX9) {
uint32_t spi_config_cntl =
}
void
-radv_emit_inhibit_clockgating(struct radv_device *device, struct radeon_cmdbuf *cs, bool inhibit)
+radv_emit_inhibit_clockgating(const struct radv_device *device, struct radeon_cmdbuf *cs, bool inhibit)
{
if (device->physical_device->rad_info.gfx_level >= GFX11)
return; /* not needed */
radv_get_sqtt_trace(struct radv_queue *queue, struct ac_sqtt_trace *sqtt_trace)
{
struct radv_device *device = queue->device;
- struct radeon_info *rad_info = &device->physical_device->rad_info;
+ const struct radeon_info *rad_info = &device->physical_device->rad_info;
if (!ac_sqtt_get_trace(&device->sqtt, rad_info, sqtt_trace)) {
if (!radv_sqtt_resize_bo(device))
VkVideoCapabilitiesKHR *pCapabilities)
{
RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
- struct video_codec_cap *cap = NULL;
+ const struct video_codec_cap *cap = NULL;
switch (pVideoProfile->videoCodecOperation) {
case VK_VIDEO_CODEC_OPERATION_DECODE_H264_BIT_KHR:
&ptr);
msg_bo = cmd_buffer->upload.upload_bo;
- uint32_t slice_offset;
+ uint32_t slice_offset;
rvcn_dec_message_decode(cmd_buffer, vid, params, ptr, it_ptr, &slice_offset, frame_info);
rvcn_dec_message_feedback(fb_ptr);
send_cmd(cmd_buffer, RDECODE_CMD_SESSION_CONTEXT_BUFFER, vid->sessionctx.mem->bo, vid->sessionctx.offset);