define i64 @rotl_64(i64 %x, i64 %y) nounwind {
; RV32I-LABEL: rotl_64:
; RV32I: # %bb.0:
+; RV32I-NEXT: addi a5, a2, -32
; RV32I-NEXT: sll a4, a0, a2
-; RV32I-NEXT: addi a3, a2, -32
-; RV32I-NEXT: slti a5, a3, 0
-; RV32I-NEXT: neg a5, a5
-; RV32I-NEXT: bltz a3, .LBB2_2
+; RV32I-NEXT: bltz a5, .LBB2_2
; RV32I-NEXT: # %bb.1:
; RV32I-NEXT: mv a3, a4
; RV32I-NEXT: j .LBB2_3
; RV32I-NEXT: srl a6, a7, a6
; RV32I-NEXT: or a3, a3, a6
; RV32I-NEXT: .LBB2_3:
+; RV32I-NEXT: srai a5, a5, 31
; RV32I-NEXT: and a4, a5, a4
; RV32I-NEXT: neg a7, a2
; RV32I-NEXT: li a5, 32
-; RV32I-NEXT: sub a6, a5, a2
-; RV32I-NEXT: srl a5, a1, a7
-; RV32I-NEXT: bltz a6, .LBB2_5
+; RV32I-NEXT: sub a5, a5, a2
+; RV32I-NEXT: srl a6, a1, a7
+; RV32I-NEXT: bltz a5, .LBB2_5
; RV32I-NEXT: # %bb.4:
-; RV32I-NEXT: mv a0, a5
+; RV32I-NEXT: mv a0, a6
; RV32I-NEXT: j .LBB2_6
; RV32I-NEXT: .LBB2_5:
; RV32I-NEXT: srl a0, a0, a7
; RV32I-NEXT: sll a1, a1, a2
; RV32I-NEXT: or a0, a0, a1
; RV32I-NEXT: .LBB2_6:
-; RV32I-NEXT: slti a1, a6, 0
-; RV32I-NEXT: neg a1, a1
-; RV32I-NEXT: and a1, a1, a5
+; RV32I-NEXT: srai a5, a5, 31
+; RV32I-NEXT: and a1, a5, a6
; RV32I-NEXT: or a1, a3, a1
; RV32I-NEXT: or a0, a4, a0
; RV32I-NEXT: ret
;
; RV32ZBB-LABEL: rotl_64:
; RV32ZBB: # %bb.0:
+; RV32ZBB-NEXT: addi a5, a2, -32
; RV32ZBB-NEXT: sll a4, a0, a2
-; RV32ZBB-NEXT: addi a3, a2, -32
-; RV32ZBB-NEXT: slti a5, a3, 0
-; RV32ZBB-NEXT: neg a5, a5
-; RV32ZBB-NEXT: bltz a3, .LBB2_2
+; RV32ZBB-NEXT: bltz a5, .LBB2_2
; RV32ZBB-NEXT: # %bb.1:
; RV32ZBB-NEXT: mv a3, a4
; RV32ZBB-NEXT: j .LBB2_3
; RV32ZBB-NEXT: srl a6, a7, a6
; RV32ZBB-NEXT: or a3, a3, a6
; RV32ZBB-NEXT: .LBB2_3:
+; RV32ZBB-NEXT: srai a5, a5, 31
; RV32ZBB-NEXT: and a4, a5, a4
; RV32ZBB-NEXT: neg a7, a2
; RV32ZBB-NEXT: li a5, 32
-; RV32ZBB-NEXT: sub a6, a5, a2
-; RV32ZBB-NEXT: srl a5, a1, a7
-; RV32ZBB-NEXT: bltz a6, .LBB2_5
+; RV32ZBB-NEXT: sub a5, a5, a2
+; RV32ZBB-NEXT: srl a6, a1, a7
+; RV32ZBB-NEXT: bltz a5, .LBB2_5
; RV32ZBB-NEXT: # %bb.4:
-; RV32ZBB-NEXT: mv a0, a5
+; RV32ZBB-NEXT: mv a0, a6
; RV32ZBB-NEXT: j .LBB2_6
; RV32ZBB-NEXT: .LBB2_5:
; RV32ZBB-NEXT: srl a0, a0, a7
; RV32ZBB-NEXT: sll a1, a1, a2
; RV32ZBB-NEXT: or a0, a0, a1
; RV32ZBB-NEXT: .LBB2_6:
-; RV32ZBB-NEXT: slti a1, a6, 0
-; RV32ZBB-NEXT: neg a1, a1
-; RV32ZBB-NEXT: and a1, a1, a5
+; RV32ZBB-NEXT: srai a5, a5, 31
+; RV32ZBB-NEXT: and a1, a5, a6
; RV32ZBB-NEXT: or a1, a3, a1
; RV32ZBB-NEXT: or a0, a4, a0
; RV32ZBB-NEXT: ret
;
; RV32XTHEADBB-LABEL: rotl_64:
; RV32XTHEADBB: # %bb.0:
+; RV32XTHEADBB-NEXT: addi a5, a2, -32
; RV32XTHEADBB-NEXT: sll a4, a0, a2
-; RV32XTHEADBB-NEXT: addi a3, a2, -32
-; RV32XTHEADBB-NEXT: slti a5, a3, 0
-; RV32XTHEADBB-NEXT: neg a5, a5
-; RV32XTHEADBB-NEXT: bltz a3, .LBB2_2
+; RV32XTHEADBB-NEXT: bltz a5, .LBB2_2
; RV32XTHEADBB-NEXT: # %bb.1:
; RV32XTHEADBB-NEXT: mv a3, a4
; RV32XTHEADBB-NEXT: j .LBB2_3
; RV32XTHEADBB-NEXT: srl a6, a7, a6
; RV32XTHEADBB-NEXT: or a3, a3, a6
; RV32XTHEADBB-NEXT: .LBB2_3:
+; RV32XTHEADBB-NEXT: srai a5, a5, 31
; RV32XTHEADBB-NEXT: and a4, a5, a4
; RV32XTHEADBB-NEXT: neg a7, a2
; RV32XTHEADBB-NEXT: li a5, 32
-; RV32XTHEADBB-NEXT: sub a6, a5, a2
-; RV32XTHEADBB-NEXT: srl a5, a1, a7
-; RV32XTHEADBB-NEXT: bltz a6, .LBB2_5
+; RV32XTHEADBB-NEXT: sub a5, a5, a2
+; RV32XTHEADBB-NEXT: srl a6, a1, a7
+; RV32XTHEADBB-NEXT: bltz a5, .LBB2_5
; RV32XTHEADBB-NEXT: # %bb.4:
-; RV32XTHEADBB-NEXT: mv a0, a5
+; RV32XTHEADBB-NEXT: mv a0, a6
; RV32XTHEADBB-NEXT: j .LBB2_6
; RV32XTHEADBB-NEXT: .LBB2_5:
; RV32XTHEADBB-NEXT: srl a0, a0, a7
; RV32XTHEADBB-NEXT: sll a1, a1, a2
; RV32XTHEADBB-NEXT: or a0, a0, a1
; RV32XTHEADBB-NEXT: .LBB2_6:
-; RV32XTHEADBB-NEXT: slti a1, a6, 0
-; RV32XTHEADBB-NEXT: neg a1, a1
-; RV32XTHEADBB-NEXT: and a1, a1, a5
+; RV32XTHEADBB-NEXT: srai a5, a5, 31
+; RV32XTHEADBB-NEXT: and a1, a5, a6
; RV32XTHEADBB-NEXT: or a1, a3, a1
; RV32XTHEADBB-NEXT: or a0, a4, a0
; RV32XTHEADBB-NEXT: ret
define i64 @rotr_64(i64 %x, i64 %y) nounwind {
; RV32I-LABEL: rotr_64:
; RV32I: # %bb.0:
+; RV32I-NEXT: addi a5, a2, -32
; RV32I-NEXT: srl a4, a1, a2
-; RV32I-NEXT: addi a3, a2, -32
-; RV32I-NEXT: slti a5, a3, 0
-; RV32I-NEXT: neg a5, a5
-; RV32I-NEXT: bltz a3, .LBB3_2
+; RV32I-NEXT: bltz a5, .LBB3_2
; RV32I-NEXT: # %bb.1:
; RV32I-NEXT: mv a3, a4
; RV32I-NEXT: j .LBB3_3
; RV32I-NEXT: sll a6, a7, a6
; RV32I-NEXT: or a3, a3, a6
; RV32I-NEXT: .LBB3_3:
+; RV32I-NEXT: srai a5, a5, 31
; RV32I-NEXT: and a4, a5, a4
; RV32I-NEXT: neg a7, a2
; RV32I-NEXT: li a5, 32
-; RV32I-NEXT: sub a6, a5, a2
-; RV32I-NEXT: sll a5, a0, a7
-; RV32I-NEXT: bltz a6, .LBB3_5
+; RV32I-NEXT: sub a5, a5, a2
+; RV32I-NEXT: sll a6, a0, a7
+; RV32I-NEXT: bltz a5, .LBB3_5
; RV32I-NEXT: # %bb.4:
-; RV32I-NEXT: mv a1, a5
+; RV32I-NEXT: mv a1, a6
; RV32I-NEXT: j .LBB3_6
; RV32I-NEXT: .LBB3_5:
; RV32I-NEXT: sll a1, a1, a7
; RV32I-NEXT: srl a0, a0, a2
; RV32I-NEXT: or a1, a1, a0
; RV32I-NEXT: .LBB3_6:
-; RV32I-NEXT: slti a0, a6, 0
-; RV32I-NEXT: neg a0, a0
-; RV32I-NEXT: and a0, a0, a5
+; RV32I-NEXT: srai a5, a5, 31
+; RV32I-NEXT: and a0, a5, a6
; RV32I-NEXT: or a0, a3, a0
; RV32I-NEXT: or a1, a4, a1
; RV32I-NEXT: ret
;
; RV32ZBB-LABEL: rotr_64:
; RV32ZBB: # %bb.0:
+; RV32ZBB-NEXT: addi a5, a2, -32
; RV32ZBB-NEXT: srl a4, a1, a2
-; RV32ZBB-NEXT: addi a3, a2, -32
-; RV32ZBB-NEXT: slti a5, a3, 0
-; RV32ZBB-NEXT: neg a5, a5
-; RV32ZBB-NEXT: bltz a3, .LBB3_2
+; RV32ZBB-NEXT: bltz a5, .LBB3_2
; RV32ZBB-NEXT: # %bb.1:
; RV32ZBB-NEXT: mv a3, a4
; RV32ZBB-NEXT: j .LBB3_3
; RV32ZBB-NEXT: sll a6, a7, a6
; RV32ZBB-NEXT: or a3, a3, a6
; RV32ZBB-NEXT: .LBB3_3:
+; RV32ZBB-NEXT: srai a5, a5, 31
; RV32ZBB-NEXT: and a4, a5, a4
; RV32ZBB-NEXT: neg a7, a2
; RV32ZBB-NEXT: li a5, 32
-; RV32ZBB-NEXT: sub a6, a5, a2
-; RV32ZBB-NEXT: sll a5, a0, a7
-; RV32ZBB-NEXT: bltz a6, .LBB3_5
+; RV32ZBB-NEXT: sub a5, a5, a2
+; RV32ZBB-NEXT: sll a6, a0, a7
+; RV32ZBB-NEXT: bltz a5, .LBB3_5
; RV32ZBB-NEXT: # %bb.4:
-; RV32ZBB-NEXT: mv a1, a5
+; RV32ZBB-NEXT: mv a1, a6
; RV32ZBB-NEXT: j .LBB3_6
; RV32ZBB-NEXT: .LBB3_5:
; RV32ZBB-NEXT: sll a1, a1, a7
; RV32ZBB-NEXT: srl a0, a0, a2
; RV32ZBB-NEXT: or a1, a1, a0
; RV32ZBB-NEXT: .LBB3_6:
-; RV32ZBB-NEXT: slti a0, a6, 0
-; RV32ZBB-NEXT: neg a0, a0
-; RV32ZBB-NEXT: and a0, a0, a5
+; RV32ZBB-NEXT: srai a5, a5, 31
+; RV32ZBB-NEXT: and a0, a5, a6
; RV32ZBB-NEXT: or a0, a3, a0
; RV32ZBB-NEXT: or a1, a4, a1
; RV32ZBB-NEXT: ret
;
; RV32XTHEADBB-LABEL: rotr_64:
; RV32XTHEADBB: # %bb.0:
+; RV32XTHEADBB-NEXT: addi a5, a2, -32
; RV32XTHEADBB-NEXT: srl a4, a1, a2
-; RV32XTHEADBB-NEXT: addi a3, a2, -32
-; RV32XTHEADBB-NEXT: slti a5, a3, 0
-; RV32XTHEADBB-NEXT: neg a5, a5
-; RV32XTHEADBB-NEXT: bltz a3, .LBB3_2
+; RV32XTHEADBB-NEXT: bltz a5, .LBB3_2
; RV32XTHEADBB-NEXT: # %bb.1:
; RV32XTHEADBB-NEXT: mv a3, a4
; RV32XTHEADBB-NEXT: j .LBB3_3
; RV32XTHEADBB-NEXT: sll a6, a7, a6
; RV32XTHEADBB-NEXT: or a3, a3, a6
; RV32XTHEADBB-NEXT: .LBB3_3:
+; RV32XTHEADBB-NEXT: srai a5, a5, 31
; RV32XTHEADBB-NEXT: and a4, a5, a4
; RV32XTHEADBB-NEXT: neg a7, a2
; RV32XTHEADBB-NEXT: li a5, 32
-; RV32XTHEADBB-NEXT: sub a6, a5, a2
-; RV32XTHEADBB-NEXT: sll a5, a0, a7
-; RV32XTHEADBB-NEXT: bltz a6, .LBB3_5
+; RV32XTHEADBB-NEXT: sub a5, a5, a2
+; RV32XTHEADBB-NEXT: sll a6, a0, a7
+; RV32XTHEADBB-NEXT: bltz a5, .LBB3_5
; RV32XTHEADBB-NEXT: # %bb.4:
-; RV32XTHEADBB-NEXT: mv a1, a5
+; RV32XTHEADBB-NEXT: mv a1, a6
; RV32XTHEADBB-NEXT: j .LBB3_6
; RV32XTHEADBB-NEXT: .LBB3_5:
; RV32XTHEADBB-NEXT: sll a1, a1, a7
; RV32XTHEADBB-NEXT: srl a0, a0, a2
; RV32XTHEADBB-NEXT: or a1, a1, a0
; RV32XTHEADBB-NEXT: .LBB3_6:
-; RV32XTHEADBB-NEXT: slti a0, a6, 0
-; RV32XTHEADBB-NEXT: neg a0, a0
-; RV32XTHEADBB-NEXT: and a0, a0, a5
+; RV32XTHEADBB-NEXT: srai a5, a5, 31
+; RV32XTHEADBB-NEXT: and a0, a5, a6
; RV32XTHEADBB-NEXT: or a0, a3, a0
; RV32XTHEADBB-NEXT: or a1, a4, a1
; RV32XTHEADBB-NEXT: ret
; RV32I-NEXT: srl a6, a7, a6
; RV32I-NEXT: or a3, a3, a6
; RV32I-NEXT: .LBB10_3:
-; RV32I-NEXT: slti a5, a5, 0
-; RV32I-NEXT: neg a5, a5
-; RV32I-NEXT: and a4, a5, a4
-; RV32I-NEXT: neg a6, a2
-; RV32I-NEXT: srl a2, a1, a6
-; RV32I-NEXT: andi a5, a6, 63
-; RV32I-NEXT: addi a7, a5, -32
-; RV32I-NEXT: slti t0, a7, 0
-; RV32I-NEXT: neg t0, t0
-; RV32I-NEXT: and a2, t0, a2
-; RV32I-NEXT: bltz a7, .LBB10_5
+; RV32I-NEXT: srai t0, a5, 31
+; RV32I-NEXT: neg a5, a2
+; RV32I-NEXT: andi a7, a5, 63
+; RV32I-NEXT: addi a6, a7, -32
+; RV32I-NEXT: and a2, t0, a4
+; RV32I-NEXT: bltz a6, .LBB10_5
; RV32I-NEXT: # %bb.4:
-; RV32I-NEXT: srl a0, a1, a5
+; RV32I-NEXT: srl a0, a1, a7
; RV32I-NEXT: j .LBB10_6
; RV32I-NEXT: .LBB10_5:
-; RV32I-NEXT: srl a0, a0, a6
-; RV32I-NEXT: not a5, a5
-; RV32I-NEXT: slli a1, a1, 1
-; RV32I-NEXT: sll a1, a1, a5
-; RV32I-NEXT: or a0, a0, a1
+; RV32I-NEXT: srl a0, a0, a5
+; RV32I-NEXT: not a4, a7
+; RV32I-NEXT: slli a7, a1, 1
+; RV32I-NEXT: sll a4, a7, a4
+; RV32I-NEXT: or a0, a0, a4
; RV32I-NEXT: .LBB10_6:
-; RV32I-NEXT: or a0, a4, a0
-; RV32I-NEXT: or a1, a3, a2
+; RV32I-NEXT: srl a1, a1, a5
+; RV32I-NEXT: srai a4, a6, 31
+; RV32I-NEXT: and a1, a4, a1
+; RV32I-NEXT: or a1, a3, a1
+; RV32I-NEXT: or a0, a2, a0
; RV32I-NEXT: ret
;
; RV64I-LABEL: rotl_64_mask:
; RV32ZBB-NEXT: srl a6, a7, a6
; RV32ZBB-NEXT: or a3, a3, a6
; RV32ZBB-NEXT: .LBB10_3:
-; RV32ZBB-NEXT: slti a5, a5, 0
-; RV32ZBB-NEXT: neg a5, a5
-; RV32ZBB-NEXT: and a4, a5, a4
-; RV32ZBB-NEXT: neg a6, a2
-; RV32ZBB-NEXT: srl a2, a1, a6
-; RV32ZBB-NEXT: andi a5, a6, 63
-; RV32ZBB-NEXT: addi a7, a5, -32
-; RV32ZBB-NEXT: slti t0, a7, 0
-; RV32ZBB-NEXT: neg t0, t0
-; RV32ZBB-NEXT: and a2, t0, a2
-; RV32ZBB-NEXT: bltz a7, .LBB10_5
+; RV32ZBB-NEXT: srai t0, a5, 31
+; RV32ZBB-NEXT: neg a5, a2
+; RV32ZBB-NEXT: andi a7, a5, 63
+; RV32ZBB-NEXT: addi a6, a7, -32
+; RV32ZBB-NEXT: and a2, t0, a4
+; RV32ZBB-NEXT: bltz a6, .LBB10_5
; RV32ZBB-NEXT: # %bb.4:
-; RV32ZBB-NEXT: srl a0, a1, a5
+; RV32ZBB-NEXT: srl a0, a1, a7
; RV32ZBB-NEXT: j .LBB10_6
; RV32ZBB-NEXT: .LBB10_5:
-; RV32ZBB-NEXT: srl a0, a0, a6
-; RV32ZBB-NEXT: not a5, a5
-; RV32ZBB-NEXT: slli a1, a1, 1
-; RV32ZBB-NEXT: sll a1, a1, a5
-; RV32ZBB-NEXT: or a0, a0, a1
+; RV32ZBB-NEXT: srl a0, a0, a5
+; RV32ZBB-NEXT: not a4, a7
+; RV32ZBB-NEXT: slli a7, a1, 1
+; RV32ZBB-NEXT: sll a4, a7, a4
+; RV32ZBB-NEXT: or a0, a0, a4
; RV32ZBB-NEXT: .LBB10_6:
-; RV32ZBB-NEXT: or a0, a4, a0
-; RV32ZBB-NEXT: or a1, a3, a2
+; RV32ZBB-NEXT: srl a1, a1, a5
+; RV32ZBB-NEXT: srai a4, a6, 31
+; RV32ZBB-NEXT: and a1, a4, a1
+; RV32ZBB-NEXT: or a1, a3, a1
+; RV32ZBB-NEXT: or a0, a2, a0
; RV32ZBB-NEXT: ret
;
; RV64ZBB-LABEL: rotl_64_mask:
; RV32XTHEADBB-NEXT: srl a6, a7, a6
; RV32XTHEADBB-NEXT: or a3, a3, a6
; RV32XTHEADBB-NEXT: .LBB10_3:
-; RV32XTHEADBB-NEXT: slti a5, a5, 0
-; RV32XTHEADBB-NEXT: neg a5, a5
-; RV32XTHEADBB-NEXT: and a4, a5, a4
-; RV32XTHEADBB-NEXT: neg a6, a2
-; RV32XTHEADBB-NEXT: srl a2, a1, a6
-; RV32XTHEADBB-NEXT: andi a5, a6, 63
-; RV32XTHEADBB-NEXT: addi a7, a5, -32
-; RV32XTHEADBB-NEXT: slti t0, a7, 0
-; RV32XTHEADBB-NEXT: neg t0, t0
-; RV32XTHEADBB-NEXT: and a2, t0, a2
-; RV32XTHEADBB-NEXT: bltz a7, .LBB10_5
+; RV32XTHEADBB-NEXT: srai t0, a5, 31
+; RV32XTHEADBB-NEXT: neg a5, a2
+; RV32XTHEADBB-NEXT: andi a7, a5, 63
+; RV32XTHEADBB-NEXT: addi a6, a7, -32
+; RV32XTHEADBB-NEXT: and a2, t0, a4
+; RV32XTHEADBB-NEXT: bltz a6, .LBB10_5
; RV32XTHEADBB-NEXT: # %bb.4:
-; RV32XTHEADBB-NEXT: srl a0, a1, a5
+; RV32XTHEADBB-NEXT: srl a0, a1, a7
; RV32XTHEADBB-NEXT: j .LBB10_6
; RV32XTHEADBB-NEXT: .LBB10_5:
-; RV32XTHEADBB-NEXT: srl a0, a0, a6
-; RV32XTHEADBB-NEXT: not a5, a5
-; RV32XTHEADBB-NEXT: slli a1, a1, 1
-; RV32XTHEADBB-NEXT: sll a1, a1, a5
-; RV32XTHEADBB-NEXT: or a0, a0, a1
+; RV32XTHEADBB-NEXT: srl a0, a0, a5
+; RV32XTHEADBB-NEXT: not a4, a7
+; RV32XTHEADBB-NEXT: slli a7, a1, 1
+; RV32XTHEADBB-NEXT: sll a4, a7, a4
+; RV32XTHEADBB-NEXT: or a0, a0, a4
; RV32XTHEADBB-NEXT: .LBB10_6:
-; RV32XTHEADBB-NEXT: or a0, a4, a0
-; RV32XTHEADBB-NEXT: or a1, a3, a2
+; RV32XTHEADBB-NEXT: srl a1, a1, a5
+; RV32XTHEADBB-NEXT: srai a4, a6, 31
+; RV32XTHEADBB-NEXT: and a1, a4, a1
+; RV32XTHEADBB-NEXT: or a1, a3, a1
+; RV32XTHEADBB-NEXT: or a0, a2, a0
; RV32XTHEADBB-NEXT: ret
;
; RV64XTHEADBB-LABEL: rotl_64_mask:
; RV32I-NEXT: srl a3, a6, a3
; RV32I-NEXT: or a3, a5, a3
; RV32I-NEXT: .LBB11_3:
-; RV32I-NEXT: sll a5, a0, a2
-; RV32I-NEXT: slti a4, a4, 0
-; RV32I-NEXT: neg a4, a4
-; RV32I-NEXT: and a4, a4, a5
-; RV32I-NEXT: neg a6, a2
-; RV32I-NEXT: srl a2, a1, a6
-; RV32I-NEXT: andi a5, a6, 63
-; RV32I-NEXT: addi a7, a5, -32
-; RV32I-NEXT: slti t0, a7, 0
-; RV32I-NEXT: neg t0, t0
-; RV32I-NEXT: and a2, t0, a2
-; RV32I-NEXT: bltz a7, .LBB11_5
+; RV32I-NEXT: sll a7, a0, a2
+; RV32I-NEXT: srai t0, a4, 31
+; RV32I-NEXT: neg a4, a2
+; RV32I-NEXT: andi a6, a4, 63
+; RV32I-NEXT: addi a5, a6, -32
+; RV32I-NEXT: and a2, t0, a7
+; RV32I-NEXT: bltz a5, .LBB11_5
; RV32I-NEXT: # %bb.4:
-; RV32I-NEXT: srl a0, a1, a5
+; RV32I-NEXT: srl a0, a1, a6
; RV32I-NEXT: j .LBB11_6
; RV32I-NEXT: .LBB11_5:
-; RV32I-NEXT: srl a0, a0, a6
-; RV32I-NEXT: not a5, a5
-; RV32I-NEXT: slli a1, a1, 1
-; RV32I-NEXT: sll a1, a1, a5
-; RV32I-NEXT: or a0, a0, a1
+; RV32I-NEXT: srl a0, a0, a4
+; RV32I-NEXT: not a6, a6
+; RV32I-NEXT: slli a7, a1, 1
+; RV32I-NEXT: sll a6, a7, a6
+; RV32I-NEXT: or a0, a0, a6
; RV32I-NEXT: .LBB11_6:
-; RV32I-NEXT: or a0, a4, a0
-; RV32I-NEXT: or a1, a3, a2
+; RV32I-NEXT: srl a1, a1, a4
+; RV32I-NEXT: srai a5, a5, 31
+; RV32I-NEXT: and a1, a5, a1
+; RV32I-NEXT: or a1, a3, a1
+; RV32I-NEXT: or a0, a2, a0
; RV32I-NEXT: ret
;
; RV64I-LABEL: rotl_64_mask_and_127_and_63:
; RV32ZBB-NEXT: srl a3, a6, a3
; RV32ZBB-NEXT: or a3, a5, a3
; RV32ZBB-NEXT: .LBB11_3:
-; RV32ZBB-NEXT: sll a5, a0, a2
-; RV32ZBB-NEXT: slti a4, a4, 0
-; RV32ZBB-NEXT: neg a4, a4
-; RV32ZBB-NEXT: and a4, a4, a5
-; RV32ZBB-NEXT: neg a6, a2
-; RV32ZBB-NEXT: srl a2, a1, a6
-; RV32ZBB-NEXT: andi a5, a6, 63
-; RV32ZBB-NEXT: addi a7, a5, -32
-; RV32ZBB-NEXT: slti t0, a7, 0
-; RV32ZBB-NEXT: neg t0, t0
-; RV32ZBB-NEXT: and a2, t0, a2
-; RV32ZBB-NEXT: bltz a7, .LBB11_5
+; RV32ZBB-NEXT: sll a7, a0, a2
+; RV32ZBB-NEXT: srai t0, a4, 31
+; RV32ZBB-NEXT: neg a4, a2
+; RV32ZBB-NEXT: andi a6, a4, 63
+; RV32ZBB-NEXT: addi a5, a6, -32
+; RV32ZBB-NEXT: and a2, t0, a7
+; RV32ZBB-NEXT: bltz a5, .LBB11_5
; RV32ZBB-NEXT: # %bb.4:
-; RV32ZBB-NEXT: srl a0, a1, a5
+; RV32ZBB-NEXT: srl a0, a1, a6
; RV32ZBB-NEXT: j .LBB11_6
; RV32ZBB-NEXT: .LBB11_5:
-; RV32ZBB-NEXT: srl a0, a0, a6
-; RV32ZBB-NEXT: not a5, a5
-; RV32ZBB-NEXT: slli a1, a1, 1
-; RV32ZBB-NEXT: sll a1, a1, a5
-; RV32ZBB-NEXT: or a0, a0, a1
+; RV32ZBB-NEXT: srl a0, a0, a4
+; RV32ZBB-NEXT: not a6, a6
+; RV32ZBB-NEXT: slli a7, a1, 1
+; RV32ZBB-NEXT: sll a6, a7, a6
+; RV32ZBB-NEXT: or a0, a0, a6
; RV32ZBB-NEXT: .LBB11_6:
-; RV32ZBB-NEXT: or a0, a4, a0
-; RV32ZBB-NEXT: or a1, a3, a2
+; RV32ZBB-NEXT: srl a1, a1, a4
+; RV32ZBB-NEXT: srai a5, a5, 31
+; RV32ZBB-NEXT: and a1, a5, a1
+; RV32ZBB-NEXT: or a1, a3, a1
+; RV32ZBB-NEXT: or a0, a2, a0
; RV32ZBB-NEXT: ret
;
; RV64ZBB-LABEL: rotl_64_mask_and_127_and_63:
; RV32XTHEADBB-NEXT: srl a3, a6, a3
; RV32XTHEADBB-NEXT: or a3, a5, a3
; RV32XTHEADBB-NEXT: .LBB11_3:
-; RV32XTHEADBB-NEXT: sll a5, a0, a2
-; RV32XTHEADBB-NEXT: slti a4, a4, 0
-; RV32XTHEADBB-NEXT: neg a4, a4
-; RV32XTHEADBB-NEXT: and a4, a4, a5
-; RV32XTHEADBB-NEXT: neg a6, a2
-; RV32XTHEADBB-NEXT: srl a2, a1, a6
-; RV32XTHEADBB-NEXT: andi a5, a6, 63
-; RV32XTHEADBB-NEXT: addi a7, a5, -32
-; RV32XTHEADBB-NEXT: slti t0, a7, 0
-; RV32XTHEADBB-NEXT: neg t0, t0
-; RV32XTHEADBB-NEXT: and a2, t0, a2
-; RV32XTHEADBB-NEXT: bltz a7, .LBB11_5
+; RV32XTHEADBB-NEXT: sll a7, a0, a2
+; RV32XTHEADBB-NEXT: srai t0, a4, 31
+; RV32XTHEADBB-NEXT: neg a4, a2
+; RV32XTHEADBB-NEXT: andi a6, a4, 63
+; RV32XTHEADBB-NEXT: addi a5, a6, -32
+; RV32XTHEADBB-NEXT: and a2, t0, a7
+; RV32XTHEADBB-NEXT: bltz a5, .LBB11_5
; RV32XTHEADBB-NEXT: # %bb.4:
-; RV32XTHEADBB-NEXT: srl a0, a1, a5
+; RV32XTHEADBB-NEXT: srl a0, a1, a6
; RV32XTHEADBB-NEXT: j .LBB11_6
; RV32XTHEADBB-NEXT: .LBB11_5:
-; RV32XTHEADBB-NEXT: srl a0, a0, a6
-; RV32XTHEADBB-NEXT: not a5, a5
-; RV32XTHEADBB-NEXT: slli a1, a1, 1
-; RV32XTHEADBB-NEXT: sll a1, a1, a5
-; RV32XTHEADBB-NEXT: or a0, a0, a1
+; RV32XTHEADBB-NEXT: srl a0, a0, a4
+; RV32XTHEADBB-NEXT: not a6, a6
+; RV32XTHEADBB-NEXT: slli a7, a1, 1
+; RV32XTHEADBB-NEXT: sll a6, a7, a6
+; RV32XTHEADBB-NEXT: or a0, a0, a6
; RV32XTHEADBB-NEXT: .LBB11_6:
-; RV32XTHEADBB-NEXT: or a0, a4, a0
-; RV32XTHEADBB-NEXT: or a1, a3, a2
+; RV32XTHEADBB-NEXT: srl a1, a1, a4
+; RV32XTHEADBB-NEXT: srai a5, a5, 31
+; RV32XTHEADBB-NEXT: and a1, a5, a1
+; RV32XTHEADBB-NEXT: or a1, a3, a1
+; RV32XTHEADBB-NEXT: or a0, a2, a0
; RV32XTHEADBB-NEXT: ret
;
; RV64XTHEADBB-LABEL: rotl_64_mask_and_127_and_63:
define i64 @rotr_64_mask(i64 %x, i64 %y) nounwind {
; RV32I-LABEL: rotr_64_mask:
; RV32I: # %bb.0:
+; RV32I-NEXT: addi a5, a2, -32
; RV32I-NEXT: srl a4, a1, a2
-; RV32I-NEXT: addi a3, a2, -32
-; RV32I-NEXT: slti a5, a3, 0
-; RV32I-NEXT: neg a5, a5
-; RV32I-NEXT: bltz a3, .LBB13_2
+; RV32I-NEXT: bltz a5, .LBB13_2
; RV32I-NEXT: # %bb.1:
; RV32I-NEXT: mv a3, a4
; RV32I-NEXT: j .LBB13_3
; RV32I-NEXT: sll a6, a7, a6
; RV32I-NEXT: or a3, a3, a6
; RV32I-NEXT: .LBB13_3:
-; RV32I-NEXT: neg a6, a2
-; RV32I-NEXT: andi t0, a6, 63
-; RV32I-NEXT: addi a7, t0, -32
-; RV32I-NEXT: and a2, a5, a4
-; RV32I-NEXT: bltz a7, .LBB13_5
+; RV32I-NEXT: srai t0, a5, 31
+; RV32I-NEXT: neg a5, a2
+; RV32I-NEXT: andi a7, a5, 63
+; RV32I-NEXT: addi a6, a7, -32
+; RV32I-NEXT: and a2, t0, a4
+; RV32I-NEXT: bltz a6, .LBB13_5
; RV32I-NEXT: # %bb.4:
-; RV32I-NEXT: sll a1, a0, t0
+; RV32I-NEXT: sll a1, a0, a7
; RV32I-NEXT: j .LBB13_6
; RV32I-NEXT: .LBB13_5:
-; RV32I-NEXT: sll a1, a1, a6
-; RV32I-NEXT: not a4, t0
-; RV32I-NEXT: srli a5, a0, 1
-; RV32I-NEXT: srl a4, a5, a4
+; RV32I-NEXT: sll a1, a1, a5
+; RV32I-NEXT: not a4, a7
+; RV32I-NEXT: srli a7, a0, 1
+; RV32I-NEXT: srl a4, a7, a4
; RV32I-NEXT: or a1, a1, a4
; RV32I-NEXT: .LBB13_6:
-; RV32I-NEXT: sll a0, a0, a6
-; RV32I-NEXT: slti a4, a7, 0
-; RV32I-NEXT: neg a4, a4
+; RV32I-NEXT: sll a0, a0, a5
+; RV32I-NEXT: srai a4, a6, 31
; RV32I-NEXT: and a0, a4, a0
; RV32I-NEXT: or a0, a3, a0
; RV32I-NEXT: or a1, a2, a1
;
; RV32ZBB-LABEL: rotr_64_mask:
; RV32ZBB: # %bb.0:
+; RV32ZBB-NEXT: addi a5, a2, -32
; RV32ZBB-NEXT: srl a4, a1, a2
-; RV32ZBB-NEXT: addi a3, a2, -32
-; RV32ZBB-NEXT: slti a5, a3, 0
-; RV32ZBB-NEXT: neg a5, a5
-; RV32ZBB-NEXT: bltz a3, .LBB13_2
+; RV32ZBB-NEXT: bltz a5, .LBB13_2
; RV32ZBB-NEXT: # %bb.1:
; RV32ZBB-NEXT: mv a3, a4
; RV32ZBB-NEXT: j .LBB13_3
; RV32ZBB-NEXT: sll a6, a7, a6
; RV32ZBB-NEXT: or a3, a3, a6
; RV32ZBB-NEXT: .LBB13_3:
-; RV32ZBB-NEXT: neg a6, a2
-; RV32ZBB-NEXT: andi t0, a6, 63
-; RV32ZBB-NEXT: addi a7, t0, -32
-; RV32ZBB-NEXT: and a2, a5, a4
-; RV32ZBB-NEXT: bltz a7, .LBB13_5
+; RV32ZBB-NEXT: srai t0, a5, 31
+; RV32ZBB-NEXT: neg a5, a2
+; RV32ZBB-NEXT: andi a7, a5, 63
+; RV32ZBB-NEXT: addi a6, a7, -32
+; RV32ZBB-NEXT: and a2, t0, a4
+; RV32ZBB-NEXT: bltz a6, .LBB13_5
; RV32ZBB-NEXT: # %bb.4:
-; RV32ZBB-NEXT: sll a1, a0, t0
+; RV32ZBB-NEXT: sll a1, a0, a7
; RV32ZBB-NEXT: j .LBB13_6
; RV32ZBB-NEXT: .LBB13_5:
-; RV32ZBB-NEXT: sll a1, a1, a6
-; RV32ZBB-NEXT: not a4, t0
-; RV32ZBB-NEXT: srli a5, a0, 1
-; RV32ZBB-NEXT: srl a4, a5, a4
+; RV32ZBB-NEXT: sll a1, a1, a5
+; RV32ZBB-NEXT: not a4, a7
+; RV32ZBB-NEXT: srli a7, a0, 1
+; RV32ZBB-NEXT: srl a4, a7, a4
; RV32ZBB-NEXT: or a1, a1, a4
; RV32ZBB-NEXT: .LBB13_6:
-; RV32ZBB-NEXT: sll a0, a0, a6
-; RV32ZBB-NEXT: slti a4, a7, 0
-; RV32ZBB-NEXT: neg a4, a4
+; RV32ZBB-NEXT: sll a0, a0, a5
+; RV32ZBB-NEXT: srai a4, a6, 31
; RV32ZBB-NEXT: and a0, a4, a0
; RV32ZBB-NEXT: or a0, a3, a0
; RV32ZBB-NEXT: or a1, a2, a1
;
; RV32XTHEADBB-LABEL: rotr_64_mask:
; RV32XTHEADBB: # %bb.0:
+; RV32XTHEADBB-NEXT: addi a5, a2, -32
; RV32XTHEADBB-NEXT: srl a4, a1, a2
-; RV32XTHEADBB-NEXT: addi a3, a2, -32
-; RV32XTHEADBB-NEXT: slti a5, a3, 0
-; RV32XTHEADBB-NEXT: neg a5, a5
-; RV32XTHEADBB-NEXT: bltz a3, .LBB13_2
+; RV32XTHEADBB-NEXT: bltz a5, .LBB13_2
; RV32XTHEADBB-NEXT: # %bb.1:
; RV32XTHEADBB-NEXT: mv a3, a4
; RV32XTHEADBB-NEXT: j .LBB13_3
; RV32XTHEADBB-NEXT: sll a6, a7, a6
; RV32XTHEADBB-NEXT: or a3, a3, a6
; RV32XTHEADBB-NEXT: .LBB13_3:
-; RV32XTHEADBB-NEXT: neg a6, a2
-; RV32XTHEADBB-NEXT: andi t0, a6, 63
-; RV32XTHEADBB-NEXT: addi a7, t0, -32
-; RV32XTHEADBB-NEXT: and a2, a5, a4
-; RV32XTHEADBB-NEXT: bltz a7, .LBB13_5
+; RV32XTHEADBB-NEXT: srai t0, a5, 31
+; RV32XTHEADBB-NEXT: neg a5, a2
+; RV32XTHEADBB-NEXT: andi a7, a5, 63
+; RV32XTHEADBB-NEXT: addi a6, a7, -32
+; RV32XTHEADBB-NEXT: and a2, t0, a4
+; RV32XTHEADBB-NEXT: bltz a6, .LBB13_5
; RV32XTHEADBB-NEXT: # %bb.4:
-; RV32XTHEADBB-NEXT: sll a1, a0, t0
+; RV32XTHEADBB-NEXT: sll a1, a0, a7
; RV32XTHEADBB-NEXT: j .LBB13_6
; RV32XTHEADBB-NEXT: .LBB13_5:
-; RV32XTHEADBB-NEXT: sll a1, a1, a6
-; RV32XTHEADBB-NEXT: not a4, t0
-; RV32XTHEADBB-NEXT: srli a5, a0, 1
-; RV32XTHEADBB-NEXT: srl a4, a5, a4
+; RV32XTHEADBB-NEXT: sll a1, a1, a5
+; RV32XTHEADBB-NEXT: not a4, a7
+; RV32XTHEADBB-NEXT: srli a7, a0, 1
+; RV32XTHEADBB-NEXT: srl a4, a7, a4
; RV32XTHEADBB-NEXT: or a1, a1, a4
; RV32XTHEADBB-NEXT: .LBB13_6:
-; RV32XTHEADBB-NEXT: sll a0, a0, a6
-; RV32XTHEADBB-NEXT: slti a4, a7, 0
-; RV32XTHEADBB-NEXT: neg a4, a4
+; RV32XTHEADBB-NEXT: sll a0, a0, a5
+; RV32XTHEADBB-NEXT: srai a4, a6, 31
; RV32XTHEADBB-NEXT: and a0, a4, a0
; RV32XTHEADBB-NEXT: or a0, a3, a0
; RV32XTHEADBB-NEXT: or a1, a2, a1
define i64 @rotr_64_mask_and_127_and_63(i64 %x, i64 %y) nounwind {
; RV32I-LABEL: rotr_64_mask_and_127_and_63:
; RV32I: # %bb.0:
-; RV32I-NEXT: srl a4, a1, a2
; RV32I-NEXT: andi a3, a2, 127
-; RV32I-NEXT: addi a6, a3, -32
-; RV32I-NEXT: slti a5, a6, 0
-; RV32I-NEXT: neg a5, a5
-; RV32I-NEXT: bltz a6, .LBB14_2
+; RV32I-NEXT: addi a4, a3, -32
+; RV32I-NEXT: bltz a4, .LBB14_2
; RV32I-NEXT: # %bb.1:
; RV32I-NEXT: srl a3, a1, a3
; RV32I-NEXT: j .LBB14_3
; RV32I-NEXT: .LBB14_2:
-; RV32I-NEXT: srl a6, a0, a2
-; RV32I-NEXT: slli a7, a1, 1
+; RV32I-NEXT: srl a5, a0, a2
+; RV32I-NEXT: slli a6, a1, 1
; RV32I-NEXT: not a3, a3
-; RV32I-NEXT: sll a3, a7, a3
-; RV32I-NEXT: or a3, a6, a3
+; RV32I-NEXT: sll a3, a6, a3
+; RV32I-NEXT: or a3, a5, a3
; RV32I-NEXT: .LBB14_3:
-; RV32I-NEXT: neg a6, a2
-; RV32I-NEXT: andi t0, a6, 63
-; RV32I-NEXT: addi a7, t0, -32
-; RV32I-NEXT: and a2, a5, a4
-; RV32I-NEXT: bltz a7, .LBB14_5
+; RV32I-NEXT: srl a7, a1, a2
+; RV32I-NEXT: srai t0, a4, 31
+; RV32I-NEXT: neg a4, a2
+; RV32I-NEXT: andi a6, a4, 63
+; RV32I-NEXT: addi a5, a6, -32
+; RV32I-NEXT: and a2, t0, a7
+; RV32I-NEXT: bltz a5, .LBB14_5
; RV32I-NEXT: # %bb.4:
-; RV32I-NEXT: sll a1, a0, t0
+; RV32I-NEXT: sll a1, a0, a6
; RV32I-NEXT: j .LBB14_6
; RV32I-NEXT: .LBB14_5:
-; RV32I-NEXT: sll a1, a1, a6
-; RV32I-NEXT: not a4, t0
-; RV32I-NEXT: srli a5, a0, 1
-; RV32I-NEXT: srl a4, a5, a4
-; RV32I-NEXT: or a1, a1, a4
+; RV32I-NEXT: sll a1, a1, a4
+; RV32I-NEXT: not a6, a6
+; RV32I-NEXT: srli a7, a0, 1
+; RV32I-NEXT: srl a6, a7, a6
+; RV32I-NEXT: or a1, a1, a6
; RV32I-NEXT: .LBB14_6:
-; RV32I-NEXT: sll a0, a0, a6
-; RV32I-NEXT: slti a4, a7, 0
-; RV32I-NEXT: neg a4, a4
-; RV32I-NEXT: and a0, a4, a0
+; RV32I-NEXT: sll a0, a0, a4
+; RV32I-NEXT: srai a5, a5, 31
+; RV32I-NEXT: and a0, a5, a0
; RV32I-NEXT: or a0, a3, a0
; RV32I-NEXT: or a1, a2, a1
; RV32I-NEXT: ret
;
; RV32ZBB-LABEL: rotr_64_mask_and_127_and_63:
; RV32ZBB: # %bb.0:
-; RV32ZBB-NEXT: srl a4, a1, a2
; RV32ZBB-NEXT: andi a3, a2, 127
-; RV32ZBB-NEXT: addi a6, a3, -32
-; RV32ZBB-NEXT: slti a5, a6, 0
-; RV32ZBB-NEXT: neg a5, a5
-; RV32ZBB-NEXT: bltz a6, .LBB14_2
+; RV32ZBB-NEXT: addi a4, a3, -32
+; RV32ZBB-NEXT: bltz a4, .LBB14_2
; RV32ZBB-NEXT: # %bb.1:
; RV32ZBB-NEXT: srl a3, a1, a3
; RV32ZBB-NEXT: j .LBB14_3
; RV32ZBB-NEXT: .LBB14_2:
-; RV32ZBB-NEXT: srl a6, a0, a2
-; RV32ZBB-NEXT: slli a7, a1, 1
+; RV32ZBB-NEXT: srl a5, a0, a2
+; RV32ZBB-NEXT: slli a6, a1, 1
; RV32ZBB-NEXT: not a3, a3
-; RV32ZBB-NEXT: sll a3, a7, a3
-; RV32ZBB-NEXT: or a3, a6, a3
+; RV32ZBB-NEXT: sll a3, a6, a3
+; RV32ZBB-NEXT: or a3, a5, a3
; RV32ZBB-NEXT: .LBB14_3:
-; RV32ZBB-NEXT: neg a6, a2
-; RV32ZBB-NEXT: andi t0, a6, 63
-; RV32ZBB-NEXT: addi a7, t0, -32
-; RV32ZBB-NEXT: and a2, a5, a4
-; RV32ZBB-NEXT: bltz a7, .LBB14_5
+; RV32ZBB-NEXT: srl a7, a1, a2
+; RV32ZBB-NEXT: srai t0, a4, 31
+; RV32ZBB-NEXT: neg a4, a2
+; RV32ZBB-NEXT: andi a6, a4, 63
+; RV32ZBB-NEXT: addi a5, a6, -32
+; RV32ZBB-NEXT: and a2, t0, a7
+; RV32ZBB-NEXT: bltz a5, .LBB14_5
; RV32ZBB-NEXT: # %bb.4:
-; RV32ZBB-NEXT: sll a1, a0, t0
+; RV32ZBB-NEXT: sll a1, a0, a6
; RV32ZBB-NEXT: j .LBB14_6
; RV32ZBB-NEXT: .LBB14_5:
-; RV32ZBB-NEXT: sll a1, a1, a6
-; RV32ZBB-NEXT: not a4, t0
-; RV32ZBB-NEXT: srli a5, a0, 1
-; RV32ZBB-NEXT: srl a4, a5, a4
-; RV32ZBB-NEXT: or a1, a1, a4
+; RV32ZBB-NEXT: sll a1, a1, a4
+; RV32ZBB-NEXT: not a6, a6
+; RV32ZBB-NEXT: srli a7, a0, 1
+; RV32ZBB-NEXT: srl a6, a7, a6
+; RV32ZBB-NEXT: or a1, a1, a6
; RV32ZBB-NEXT: .LBB14_6:
-; RV32ZBB-NEXT: sll a0, a0, a6
-; RV32ZBB-NEXT: slti a4, a7, 0
-; RV32ZBB-NEXT: neg a4, a4
-; RV32ZBB-NEXT: and a0, a4, a0
+; RV32ZBB-NEXT: sll a0, a0, a4
+; RV32ZBB-NEXT: srai a5, a5, 31
+; RV32ZBB-NEXT: and a0, a5, a0
; RV32ZBB-NEXT: or a0, a3, a0
; RV32ZBB-NEXT: or a1, a2, a1
; RV32ZBB-NEXT: ret
;
; RV32XTHEADBB-LABEL: rotr_64_mask_and_127_and_63:
; RV32XTHEADBB: # %bb.0:
-; RV32XTHEADBB-NEXT: srl a4, a1, a2
; RV32XTHEADBB-NEXT: andi a3, a2, 127
-; RV32XTHEADBB-NEXT: addi a6, a3, -32
-; RV32XTHEADBB-NEXT: slti a5, a6, 0
-; RV32XTHEADBB-NEXT: neg a5, a5
-; RV32XTHEADBB-NEXT: bltz a6, .LBB14_2
+; RV32XTHEADBB-NEXT: addi a4, a3, -32
+; RV32XTHEADBB-NEXT: bltz a4, .LBB14_2
; RV32XTHEADBB-NEXT: # %bb.1:
; RV32XTHEADBB-NEXT: srl a3, a1, a3
; RV32XTHEADBB-NEXT: j .LBB14_3
; RV32XTHEADBB-NEXT: .LBB14_2:
-; RV32XTHEADBB-NEXT: srl a6, a0, a2
-; RV32XTHEADBB-NEXT: slli a7, a1, 1
+; RV32XTHEADBB-NEXT: srl a5, a0, a2
+; RV32XTHEADBB-NEXT: slli a6, a1, 1
; RV32XTHEADBB-NEXT: not a3, a3
-; RV32XTHEADBB-NEXT: sll a3, a7, a3
-; RV32XTHEADBB-NEXT: or a3, a6, a3
+; RV32XTHEADBB-NEXT: sll a3, a6, a3
+; RV32XTHEADBB-NEXT: or a3, a5, a3
; RV32XTHEADBB-NEXT: .LBB14_3:
-; RV32XTHEADBB-NEXT: neg a6, a2
-; RV32XTHEADBB-NEXT: andi t0, a6, 63
-; RV32XTHEADBB-NEXT: addi a7, t0, -32
-; RV32XTHEADBB-NEXT: and a2, a5, a4
-; RV32XTHEADBB-NEXT: bltz a7, .LBB14_5
+; RV32XTHEADBB-NEXT: srl a7, a1, a2
+; RV32XTHEADBB-NEXT: srai t0, a4, 31
+; RV32XTHEADBB-NEXT: neg a4, a2
+; RV32XTHEADBB-NEXT: andi a6, a4, 63
+; RV32XTHEADBB-NEXT: addi a5, a6, -32
+; RV32XTHEADBB-NEXT: and a2, t0, a7
+; RV32XTHEADBB-NEXT: bltz a5, .LBB14_5
; RV32XTHEADBB-NEXT: # %bb.4:
-; RV32XTHEADBB-NEXT: sll a1, a0, t0
+; RV32XTHEADBB-NEXT: sll a1, a0, a6
; RV32XTHEADBB-NEXT: j .LBB14_6
; RV32XTHEADBB-NEXT: .LBB14_5:
-; RV32XTHEADBB-NEXT: sll a1, a1, a6
-; RV32XTHEADBB-NEXT: not a4, t0
-; RV32XTHEADBB-NEXT: srli a5, a0, 1
-; RV32XTHEADBB-NEXT: srl a4, a5, a4
-; RV32XTHEADBB-NEXT: or a1, a1, a4
+; RV32XTHEADBB-NEXT: sll a1, a1, a4
+; RV32XTHEADBB-NEXT: not a6, a6
+; RV32XTHEADBB-NEXT: srli a7, a0, 1
+; RV32XTHEADBB-NEXT: srl a6, a7, a6
+; RV32XTHEADBB-NEXT: or a1, a1, a6
; RV32XTHEADBB-NEXT: .LBB14_6:
-; RV32XTHEADBB-NEXT: sll a0, a0, a6
-; RV32XTHEADBB-NEXT: slti a4, a7, 0
-; RV32XTHEADBB-NEXT: neg a4, a4
-; RV32XTHEADBB-NEXT: and a0, a4, a0
+; RV32XTHEADBB-NEXT: sll a0, a0, a4
+; RV32XTHEADBB-NEXT: srai a5, a5, 31
+; RV32XTHEADBB-NEXT: and a0, a5, a0
; RV32XTHEADBB-NEXT: or a0, a3, a0
; RV32XTHEADBB-NEXT: or a1, a2, a1
; RV32XTHEADBB-NEXT: ret
; RV32I-NEXT: or a3, a3, a6
; RV32I-NEXT: .LBB17_7:
; RV32I-NEXT: sll a2, a2, a4
-; RV32I-NEXT: slti a0, a0, 0
-; RV32I-NEXT: neg a0, a0
+; RV32I-NEXT: srai a0, a0, 31
; RV32I-NEXT: and a0, a0, a2
; RV32I-NEXT: add a0, a1, a0
; RV32I-NEXT: sltu a1, a0, a1
; RV32ZBB-NEXT: or a3, a3, a6
; RV32ZBB-NEXT: .LBB17_7:
; RV32ZBB-NEXT: sll a2, a2, a4
-; RV32ZBB-NEXT: slti a0, a0, 0
-; RV32ZBB-NEXT: neg a0, a0
+; RV32ZBB-NEXT: srai a0, a0, 31
; RV32ZBB-NEXT: and a0, a0, a2
; RV32ZBB-NEXT: add a0, a1, a0
; RV32ZBB-NEXT: sltu a1, a0, a1
; RV32XTHEADBB-NEXT: or a3, a3, a6
; RV32XTHEADBB-NEXT: .LBB17_7:
; RV32XTHEADBB-NEXT: sll a2, a2, a4
-; RV32XTHEADBB-NEXT: slti a0, a0, 0
-; RV32XTHEADBB-NEXT: neg a0, a0
+; RV32XTHEADBB-NEXT: srai a0, a0, 31
; RV32XTHEADBB-NEXT: and a0, a0, a2
; RV32XTHEADBB-NEXT: add a0, a1, a0
; RV32XTHEADBB-NEXT: sltu a1, a0, a1
; RV32I-NEXT: or a3, a3, a5
; RV32I-NEXT: .LBB19_7:
; RV32I-NEXT: sll a2, a2, a4
-; RV32I-NEXT: slti a0, a0, 0
-; RV32I-NEXT: neg a0, a0
+; RV32I-NEXT: srai a0, a0, 31
; RV32I-NEXT: and a0, a0, a2
; RV32I-NEXT: add a0, a6, a0
; RV32I-NEXT: sltu a2, a0, a6
; RV32ZBB-NEXT: or a3, a3, a5
; RV32ZBB-NEXT: .LBB19_7:
; RV32ZBB-NEXT: sll a2, a2, a4
-; RV32ZBB-NEXT: slti a0, a0, 0
-; RV32ZBB-NEXT: neg a0, a0
+; RV32ZBB-NEXT: srai a0, a0, 31
; RV32ZBB-NEXT: and a0, a0, a2
; RV32ZBB-NEXT: add a0, a6, a0
; RV32ZBB-NEXT: sltu a2, a0, a6
; RV32XTHEADBB-NEXT: or a3, a3, a5
; RV32XTHEADBB-NEXT: .LBB19_7:
; RV32XTHEADBB-NEXT: sll a2, a2, a4
-; RV32XTHEADBB-NEXT: slti a0, a0, 0
-; RV32XTHEADBB-NEXT: neg a0, a0
+; RV32XTHEADBB-NEXT: srai a0, a0, 31
; RV32XTHEADBB-NEXT: and a0, a0, a2
; RV32XTHEADBB-NEXT: add a0, a6, a0
; RV32XTHEADBB-NEXT: sltu a2, a0, a6
; RV32I-LABEL: rotl_64_zext:
; RV32I: # %bb.0:
; RV32I-NEXT: neg a4, a2
+; RV32I-NEXT: addi a6, a2, -32
; RV32I-NEXT: sll a5, a0, a2
-; RV32I-NEXT: addi a3, a2, -32
-; RV32I-NEXT: slti a6, a3, 0
-; RV32I-NEXT: neg a6, a6
-; RV32I-NEXT: bltz a3, .LBB24_2
+; RV32I-NEXT: bltz a6, .LBB24_2
; RV32I-NEXT: # %bb.1:
; RV32I-NEXT: mv a3, a5
; RV32I-NEXT: j .LBB24_3
; RV32I-NEXT: srl a7, t0, a7
; RV32I-NEXT: or a3, a3, a7
; RV32I-NEXT: .LBB24_3:
+; RV32I-NEXT: srai a6, a6, 31
; RV32I-NEXT: and a5, a6, a5
; RV32I-NEXT: li a6, 32
-; RV32I-NEXT: sub a7, a6, a2
-; RV32I-NEXT: srl a6, a1, a4
-; RV32I-NEXT: bltz a7, .LBB24_5
+; RV32I-NEXT: sub a6, a6, a2
+; RV32I-NEXT: srl a7, a1, a4
+; RV32I-NEXT: bltz a6, .LBB24_5
; RV32I-NEXT: # %bb.4:
-; RV32I-NEXT: mv a0, a6
+; RV32I-NEXT: mv a0, a7
; RV32I-NEXT: j .LBB24_6
; RV32I-NEXT: .LBB24_5:
; RV32I-NEXT: li t0, 64
; RV32I-NEXT: sll a1, a1, a2
; RV32I-NEXT: or a0, a0, a1
; RV32I-NEXT: .LBB24_6:
-; RV32I-NEXT: slti a1, a7, 0
-; RV32I-NEXT: neg a1, a1
-; RV32I-NEXT: and a1, a1, a6
+; RV32I-NEXT: srai a1, a6, 31
+; RV32I-NEXT: and a1, a1, a7
; RV32I-NEXT: or a1, a3, a1
; RV32I-NEXT: or a0, a5, a0
; RV32I-NEXT: ret
; RV32ZBB-LABEL: rotl_64_zext:
; RV32ZBB: # %bb.0:
; RV32ZBB-NEXT: neg a4, a2
+; RV32ZBB-NEXT: addi a6, a2, -32
; RV32ZBB-NEXT: sll a5, a0, a2
-; RV32ZBB-NEXT: addi a3, a2, -32
-; RV32ZBB-NEXT: slti a6, a3, 0
-; RV32ZBB-NEXT: neg a6, a6
-; RV32ZBB-NEXT: bltz a3, .LBB24_2
+; RV32ZBB-NEXT: bltz a6, .LBB24_2
; RV32ZBB-NEXT: # %bb.1:
; RV32ZBB-NEXT: mv a3, a5
; RV32ZBB-NEXT: j .LBB24_3
; RV32ZBB-NEXT: srl a7, t0, a7
; RV32ZBB-NEXT: or a3, a3, a7
; RV32ZBB-NEXT: .LBB24_3:
+; RV32ZBB-NEXT: srai a6, a6, 31
; RV32ZBB-NEXT: and a5, a6, a5
; RV32ZBB-NEXT: li a6, 32
-; RV32ZBB-NEXT: sub a7, a6, a2
-; RV32ZBB-NEXT: srl a6, a1, a4
-; RV32ZBB-NEXT: bltz a7, .LBB24_5
+; RV32ZBB-NEXT: sub a6, a6, a2
+; RV32ZBB-NEXT: srl a7, a1, a4
+; RV32ZBB-NEXT: bltz a6, .LBB24_5
; RV32ZBB-NEXT: # %bb.4:
-; RV32ZBB-NEXT: mv a0, a6
+; RV32ZBB-NEXT: mv a0, a7
; RV32ZBB-NEXT: j .LBB24_6
; RV32ZBB-NEXT: .LBB24_5:
; RV32ZBB-NEXT: li t0, 64
; RV32ZBB-NEXT: sll a1, a1, a2
; RV32ZBB-NEXT: or a0, a0, a1
; RV32ZBB-NEXT: .LBB24_6:
-; RV32ZBB-NEXT: slti a1, a7, 0
-; RV32ZBB-NEXT: neg a1, a1
-; RV32ZBB-NEXT: and a1, a1, a6
+; RV32ZBB-NEXT: srai a1, a6, 31
+; RV32ZBB-NEXT: and a1, a1, a7
; RV32ZBB-NEXT: or a1, a3, a1
; RV32ZBB-NEXT: or a0, a5, a0
; RV32ZBB-NEXT: ret
; RV32XTHEADBB-LABEL: rotl_64_zext:
; RV32XTHEADBB: # %bb.0:
; RV32XTHEADBB-NEXT: neg a4, a2
+; RV32XTHEADBB-NEXT: addi a6, a2, -32
; RV32XTHEADBB-NEXT: sll a5, a0, a2
-; RV32XTHEADBB-NEXT: addi a3, a2, -32
-; RV32XTHEADBB-NEXT: slti a6, a3, 0
-; RV32XTHEADBB-NEXT: neg a6, a6
-; RV32XTHEADBB-NEXT: bltz a3, .LBB24_2
+; RV32XTHEADBB-NEXT: bltz a6, .LBB24_2
; RV32XTHEADBB-NEXT: # %bb.1:
; RV32XTHEADBB-NEXT: mv a3, a5
; RV32XTHEADBB-NEXT: j .LBB24_3
; RV32XTHEADBB-NEXT: srl a7, t0, a7
; RV32XTHEADBB-NEXT: or a3, a3, a7
; RV32XTHEADBB-NEXT: .LBB24_3:
+; RV32XTHEADBB-NEXT: srai a6, a6, 31
; RV32XTHEADBB-NEXT: and a5, a6, a5
; RV32XTHEADBB-NEXT: li a6, 32
-; RV32XTHEADBB-NEXT: sub a7, a6, a2
-; RV32XTHEADBB-NEXT: srl a6, a1, a4
-; RV32XTHEADBB-NEXT: bltz a7, .LBB24_5
+; RV32XTHEADBB-NEXT: sub a6, a6, a2
+; RV32XTHEADBB-NEXT: srl a7, a1, a4
+; RV32XTHEADBB-NEXT: bltz a6, .LBB24_5
; RV32XTHEADBB-NEXT: # %bb.4:
-; RV32XTHEADBB-NEXT: mv a0, a6
+; RV32XTHEADBB-NEXT: mv a0, a7
; RV32XTHEADBB-NEXT: j .LBB24_6
; RV32XTHEADBB-NEXT: .LBB24_5:
; RV32XTHEADBB-NEXT: li t0, 64
; RV32XTHEADBB-NEXT: sll a1, a1, a2
; RV32XTHEADBB-NEXT: or a0, a0, a1
; RV32XTHEADBB-NEXT: .LBB24_6:
-; RV32XTHEADBB-NEXT: slti a1, a7, 0
-; RV32XTHEADBB-NEXT: neg a1, a1
-; RV32XTHEADBB-NEXT: and a1, a1, a6
+; RV32XTHEADBB-NEXT: srai a1, a6, 31
+; RV32XTHEADBB-NEXT: and a1, a1, a7
; RV32XTHEADBB-NEXT: or a1, a3, a1
; RV32XTHEADBB-NEXT: or a0, a5, a0
; RV32XTHEADBB-NEXT: ret
; RV32I-LABEL: rotr_64_zext:
; RV32I: # %bb.0:
; RV32I-NEXT: neg a4, a2
+; RV32I-NEXT: addi a6, a2, -32
; RV32I-NEXT: srl a5, a1, a2
-; RV32I-NEXT: addi a3, a2, -32
-; RV32I-NEXT: slti a6, a3, 0
-; RV32I-NEXT: neg a6, a6
-; RV32I-NEXT: bltz a3, .LBB25_2
+; RV32I-NEXT: bltz a6, .LBB25_2
; RV32I-NEXT: # %bb.1:
; RV32I-NEXT: mv a3, a5
; RV32I-NEXT: j .LBB25_3
; RV32I-NEXT: sll a7, t0, a7
; RV32I-NEXT: or a3, a3, a7
; RV32I-NEXT: .LBB25_3:
+; RV32I-NEXT: srai a6, a6, 31
; RV32I-NEXT: and a5, a6, a5
; RV32I-NEXT: li a6, 32
-; RV32I-NEXT: sub a7, a6, a2
-; RV32I-NEXT: sll a6, a0, a4
-; RV32I-NEXT: bltz a7, .LBB25_5
+; RV32I-NEXT: sub a6, a6, a2
+; RV32I-NEXT: sll a7, a0, a4
+; RV32I-NEXT: bltz a6, .LBB25_5
; RV32I-NEXT: # %bb.4:
-; RV32I-NEXT: mv a1, a6
+; RV32I-NEXT: mv a1, a7
; RV32I-NEXT: j .LBB25_6
; RV32I-NEXT: .LBB25_5:
; RV32I-NEXT: li t0, 64
; RV32I-NEXT: srl a0, a0, a2
; RV32I-NEXT: or a1, a1, a0
; RV32I-NEXT: .LBB25_6:
-; RV32I-NEXT: slti a0, a7, 0
-; RV32I-NEXT: neg a0, a0
-; RV32I-NEXT: and a0, a0, a6
+; RV32I-NEXT: srai a0, a6, 31
+; RV32I-NEXT: and a0, a0, a7
; RV32I-NEXT: or a0, a3, a0
; RV32I-NEXT: or a1, a5, a1
; RV32I-NEXT: ret
; RV32ZBB-LABEL: rotr_64_zext:
; RV32ZBB: # %bb.0:
; RV32ZBB-NEXT: neg a4, a2
+; RV32ZBB-NEXT: addi a6, a2, -32
; RV32ZBB-NEXT: srl a5, a1, a2
-; RV32ZBB-NEXT: addi a3, a2, -32
-; RV32ZBB-NEXT: slti a6, a3, 0
-; RV32ZBB-NEXT: neg a6, a6
-; RV32ZBB-NEXT: bltz a3, .LBB25_2
+; RV32ZBB-NEXT: bltz a6, .LBB25_2
; RV32ZBB-NEXT: # %bb.1:
; RV32ZBB-NEXT: mv a3, a5
; RV32ZBB-NEXT: j .LBB25_3
; RV32ZBB-NEXT: sll a7, t0, a7
; RV32ZBB-NEXT: or a3, a3, a7
; RV32ZBB-NEXT: .LBB25_3:
+; RV32ZBB-NEXT: srai a6, a6, 31
; RV32ZBB-NEXT: and a5, a6, a5
; RV32ZBB-NEXT: li a6, 32
-; RV32ZBB-NEXT: sub a7, a6, a2
-; RV32ZBB-NEXT: sll a6, a0, a4
-; RV32ZBB-NEXT: bltz a7, .LBB25_5
+; RV32ZBB-NEXT: sub a6, a6, a2
+; RV32ZBB-NEXT: sll a7, a0, a4
+; RV32ZBB-NEXT: bltz a6, .LBB25_5
; RV32ZBB-NEXT: # %bb.4:
-; RV32ZBB-NEXT: mv a1, a6
+; RV32ZBB-NEXT: mv a1, a7
; RV32ZBB-NEXT: j .LBB25_6
; RV32ZBB-NEXT: .LBB25_5:
; RV32ZBB-NEXT: li t0, 64
; RV32ZBB-NEXT: srl a0, a0, a2
; RV32ZBB-NEXT: or a1, a1, a0
; RV32ZBB-NEXT: .LBB25_6:
-; RV32ZBB-NEXT: slti a0, a7, 0
-; RV32ZBB-NEXT: neg a0, a0
-; RV32ZBB-NEXT: and a0, a0, a6
+; RV32ZBB-NEXT: srai a0, a6, 31
+; RV32ZBB-NEXT: and a0, a0, a7
; RV32ZBB-NEXT: or a0, a3, a0
; RV32ZBB-NEXT: or a1, a5, a1
; RV32ZBB-NEXT: ret
; RV32XTHEADBB-LABEL: rotr_64_zext:
; RV32XTHEADBB: # %bb.0:
; RV32XTHEADBB-NEXT: neg a4, a2
+; RV32XTHEADBB-NEXT: addi a6, a2, -32
; RV32XTHEADBB-NEXT: srl a5, a1, a2
-; RV32XTHEADBB-NEXT: addi a3, a2, -32
-; RV32XTHEADBB-NEXT: slti a6, a3, 0
-; RV32XTHEADBB-NEXT: neg a6, a6
-; RV32XTHEADBB-NEXT: bltz a3, .LBB25_2
+; RV32XTHEADBB-NEXT: bltz a6, .LBB25_2
; RV32XTHEADBB-NEXT: # %bb.1:
; RV32XTHEADBB-NEXT: mv a3, a5
; RV32XTHEADBB-NEXT: j .LBB25_3
; RV32XTHEADBB-NEXT: sll a7, t0, a7
; RV32XTHEADBB-NEXT: or a3, a3, a7
; RV32XTHEADBB-NEXT: .LBB25_3:
+; RV32XTHEADBB-NEXT: srai a6, a6, 31
; RV32XTHEADBB-NEXT: and a5, a6, a5
; RV32XTHEADBB-NEXT: li a6, 32
-; RV32XTHEADBB-NEXT: sub a7, a6, a2
-; RV32XTHEADBB-NEXT: sll a6, a0, a4
-; RV32XTHEADBB-NEXT: bltz a7, .LBB25_5
+; RV32XTHEADBB-NEXT: sub a6, a6, a2
+; RV32XTHEADBB-NEXT: sll a7, a0, a4
+; RV32XTHEADBB-NEXT: bltz a6, .LBB25_5
; RV32XTHEADBB-NEXT: # %bb.4:
-; RV32XTHEADBB-NEXT: mv a1, a6
+; RV32XTHEADBB-NEXT: mv a1, a7
; RV32XTHEADBB-NEXT: j .LBB25_6
; RV32XTHEADBB-NEXT: .LBB25_5:
; RV32XTHEADBB-NEXT: li t0, 64
; RV32XTHEADBB-NEXT: srl a0, a0, a2
; RV32XTHEADBB-NEXT: or a1, a1, a0
; RV32XTHEADBB-NEXT: .LBB25_6:
-; RV32XTHEADBB-NEXT: slti a0, a7, 0
-; RV32XTHEADBB-NEXT: neg a0, a0
-; RV32XTHEADBB-NEXT: and a0, a0, a6
+; RV32XTHEADBB-NEXT: srai a0, a6, 31
+; RV32XTHEADBB-NEXT: and a0, a0, a7
; RV32XTHEADBB-NEXT: or a0, a3, a0
; RV32XTHEADBB-NEXT: or a1, a5, a1
; RV32XTHEADBB-NEXT: ret