#ifdef I915_HAVE_BUFFER
#define I915_MAX_VALIDATE_BUFFERS 4096
+ struct drm_i915_validate_buffer;
#endif
-typedef struct _drm_i915_ring_buffer {
+struct drm_i915_ring_buffer {
int tail_mask;
unsigned long Start;
unsigned long End;
void *agp_iomap;
unsigned int max_validate_buffers;
struct mutex cmdbuf_mutex;
+ size_t stolen_base;
+ struct drm_i915_validate_buffer *val_bufs;
#endif
DRM_SPINTYPE swaps_lock;
#define PIPE_PIXEL_MASK 0x00ffffff
#define PIPE_PIXEL_SHIFT 0
+#define GPIOA 0x5010
+#define GPIOB 0x5014
+#define GPIOC 0x5018
+#define GPIOD 0x501c
+#define GPIOE 0x5020
+#define GPIOF 0x5024
+#define GPIOG 0x5028
+#define GPIOH 0x502c
+# define GPIO_CLOCK_DIR_MASK (1 << 0)
+# define GPIO_CLOCK_DIR_IN (0 << 1)
+# define GPIO_CLOCK_DIR_OUT (1 << 1)
+# define GPIO_CLOCK_VAL_MASK (1 << 2)
+# define GPIO_CLOCK_VAL_OUT (1 << 3)
+# define GPIO_CLOCK_VAL_IN (1 << 4)
+# define GPIO_CLOCK_PULLUP_DISABLE (1 << 5)
+# define GPIO_DATA_DIR_MASK (1 << 8)
+# define GPIO_DATA_DIR_IN (0 << 9)
+# define GPIO_DATA_DIR_OUT (1 << 9)
+# define GPIO_DATA_VAL_MASK (1 << 10)
+# define GPIO_DATA_VAL_OUT (1 << 11)
+# define GPIO_DATA_VAL_IN (1 << 12)
+# define GPIO_DATA_PULLUP_DISABLE (1 << 13)
+
+/* p317, 319
+ */
+#define VCLK2_VCO_M 0x6008 /* treat as 16 bit? (includes msbs) */
+#define VCLK2_VCO_N 0x600a
+#define VCLK2_VCO_DIV_SEL 0x6012
+
+#define VCLK_DIVISOR_VGA0 0x6000
+#define VCLK_DIVISOR_VGA1 0x6004
+#define VCLK_POST_DIV 0x6010
+/** Selects a post divisor of 4 instead of 2. */
+# define VGA1_PD_P2_DIV_4 (1 << 15)
+/** Overrides the p2 post divisor field */
+# define VGA1_PD_P1_DIV_2 (1 << 13)
+# define VGA1_PD_P1_SHIFT 8
+/** P1 value is 2 greater than this field */
+# define VGA1_PD_P1_MASK (0x1f << 8)
+/** Selects a post divisor of 4 instead of 2. */
+# define VGA0_PD_P2_DIV_4 (1 << 7)
+/** Overrides the p2 post divisor field */
+# define VGA0_PD_P1_DIV_2 (1 << 5)
+# define VGA0_PD_P1_SHIFT 0
+/** P1 value is 2 greater than this field */
+# define VGA0_PD_P1_MASK (0x1f << 0)
+
+#define POST_DIV_SELECT 0x70
+#define POST_DIV_1 0x00
+#define POST_DIV_2 0x10
+#define POST_DIV_4 0x20
+#define POST_DIV_8 0x30
+#define POST_DIV_16 0x40
+#define POST_DIV_32 0x50
+#define VCO_LOOP_DIV_BY_4M 0x00
+#define VCO_LOOP_DIV_BY_16M 0x04
+
+ #define I915_FIFO_UNDERRUN_STATUS (1UL<<31)
+ #define I915_CRC_ERROR_ENABLE (1UL<<29)
+ #define I915_CRC_DONE_ENABLE (1UL<<28)
+ #define I915_GMBUS_EVENT_ENABLE (1UL<<27)
++#define I915_HOTPLUG_INTERRUPT_ENABLE (1UL<<26)
+ #define I915_VSYNC_INTERRUPT_ENABLE (1UL<<25)
+ #define I915_DISPLAY_LINE_COMPARE_ENABLE (1UL<<24)
+ #define I915_DPST_EVENT_ENABLE (1UL<<23)
+ #define I915_LEGACY_BLC_EVENT_ENABLE (1UL<<22)
+ #define I915_ODD_FIELD_INTERRUPT_ENABLE (1UL<<21)
+ #define I915_EVEN_FIELD_INTERRUPT_ENABLE (1UL<<20)
+ #define I915_START_VBLANK_INTERRUPT_ENABLE (1UL<<18) /* 965 or later */
+ #define I915_VBLANK_INTERRUPT_ENABLE (1UL<<17)
+ #define I915_OVERLAY_UPDATED_ENABLE (1UL<<16)
+ #define I915_CRC_ERROR_INTERRUPT_STATUS (1UL<<13)
+ #define I915_CRC_DONE_INTERRUPT_STATUS (1UL<<12)
+ #define I915_GMBUS_INTERRUPT_STATUS (1UL<<11)
++#define I915_HOTPLUG_INTERRUPT_STATUS (1UL<<10)
+ #define I915_VSYNC_INTERRUPT_STATUS (1UL<<9)
+ #define I915_DISPLAY_LINE_COMPARE_STATUS (1UL<<8)
+ #define I915_DPST_EVENT_STATUS (1UL<<7)
+ #define I915_LEGACY_BLC_EVENT_STATUS (1UL<<6)
+ #define I915_ODD_FIELD_INTERRUPT_STATUS (1UL<<5)
+ #define I915_EVEN_FIELD_INTERRUPT_STATUS (1UL<<4)
+ #define I915_START_VBLANK_INTERRUPT_STATUS (1UL<<2) /* 965 or later */
+ #define I915_VBLANK_INTERRUPT_STATUS (1UL<<1)
+ #define I915_OVERLAY_UPDATED_STATUS (1UL<<0)
+
#define SRX_INDEX 0x3c4
#define SRX_DATA 0x3c5
#define SR01 1
#include "drm.h"
#include "i915_drm.h"
#include "i915_drv.h"
-
+#include "intel_drv.h"
- #define USER_INT_FLAG (1<<1)
- #define EVENT_PIPEB_FLAG (1<<4)
- #define VSYNC_PIPEB_FLAG (1<<5)
- #define EVENT_PIPEA_FLAG (1<<6)
- #define VSYNC_PIPEA_FLAG (1<<7)
- #define HOTPLUG_FLAG (1 << 17)
-
#define MAX_NOPID ((u32)~0)
/**
irqreturn_t i915_driver_irq_handler(DRM_IRQ_ARGS)
{
struct drm_device *dev = (struct drm_device *) arg;
- drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
+ struct drm_i915_master_private *master_priv;
+ struct drm_i915_private *dev_priv = (struct drm_i915_private *) dev->dev_private;
- u32 temp = 0;
+ u32 iir;
u32 pipea_stats, pipeb_stats;
+ int hotplug = 0;
+ int vblank = 0;
- iir = I915_READ(I915REG_INT_IDENTITY_R);
+ /* On i8xx/i915 hw the IIR and IER are 16bit on i9xx its 32bit */
+ if (IS_I9XX(dev) && !IS_I915G(dev) && !IS_I915GM(dev))
- temp = I915_READ(I915REG_INT_IDENTITY_R);
++ iir = I915_READ(I915REG_INT_IDENTITY_R);
+ else
- temp = I915_READ16(I915REG_INT_IDENTITY_R);
++ iir = I915_READ16(I915REG_INT_IDENTITY_R);
+
- temp &= (dev_priv->irq_enable_reg | USER_INT_FLAG);
++ iir &= (dev_priv->irq_enable_reg | I915_USER_INTERRUPT);
+
- if (temp == 0)
+ #if 0
+ DRM_DEBUG("flag=%08x\n", iir);
+ #endif
+ if (iir == 0) {
+ DRM_DEBUG ("iir 0x%08x im 0x%08x ie 0x%08x pipea 0x%08x pipeb 0x%08x\n",
+ iir,
+ I915_READ(I915REG_INT_MASK_R),
+ I915_READ(I915REG_INT_ENABLE_R),
+ I915_READ(I915REG_PIPEASTAT),
+ I915_READ(I915REG_PIPEBSTAT));
return IRQ_NONE;
-
- pipea_stats = I915_READ(I915REG_PIPEASTAT);
- pipeb_stats = I915_READ(I915REG_PIPEBSTAT);
+ }
/*
* Clear the PIPE(A|B)STAT regs before the IIR otherwise
* we may get extra interrupts.
*/
- if (temp & VSYNC_PIPEA_FLAG) {
- drm_handle_vblank(dev, i915_get_plane(dev, 0));
-
- pipea_stats |= I915_VBLANK_INTERRUPT_ENABLE |
- I915_VBLANK_CLEAR;
- }
-
- if (temp & VSYNC_PIPEB_FLAG) {
- drm_handle_vblank(dev, i915_get_plane(dev, 1));
-
- pipeb_stats |= I915_VBLANK_INTERRUPT_ENABLE |
- I915_VBLANK_CLEAR;
- }
+ if (iir & I915_DISPLAY_PIPE_A_EVENT_INTERRUPT) {
+ pipea_stats = I915_READ(I915REG_PIPEASTAT);
+ if (pipea_stats & (I915_START_VBLANK_INTERRUPT_STATUS|
+ I915_VBLANK_INTERRUPT_STATUS))
+ {
+ vblank++;
+ drm_handle_vblank(dev, i915_get_plane(dev, 0));
+ }
+
- /* This is a global event, and not a pipe A event */
- if (temp & EVENT_PIPEA_FLAG) {
- if (pipea_stats & I915_HOTPLUG_CLEAR)
++ /* This is a global event, and not a pipe A event */
++ if (pipea_stats & I915_HOTPLUG_INTERRUPT_STATUS)
+ hotplug = 1;
+
- pipea_stats |= I915_HOTPLUG_INTERRUPT_ENABLE |
- I915_HOTPLUG_CLEAR;
-
+ I915_WRITE(I915REG_PIPEASTAT, pipea_stats);
}
- I915_WRITE(I915REG_PIPEASTAT, pipea_stats);
- (void) I915_READ(I915REG_PIPEASTAT);
- I915_WRITE(I915REG_PIPEBSTAT, pipeb_stats);
- (void) I915_READ(I915REG_PIPEBSTAT);
+
+ if (iir & I915_DISPLAY_PIPE_B_EVENT_INTERRUPT) {
+ pipeb_stats = I915_READ(I915REG_PIPEBSTAT);
+ if (pipeb_stats & (I915_START_VBLANK_INTERRUPT_STATUS|
+ I915_VBLANK_INTERRUPT_STATUS))
+ {
+ vblank++;
+ drm_handle_vblank(dev, i915_get_plane(dev, 1));
+ }
+ I915_WRITE(I915REG_PIPEBSTAT, pipeb_stats);
+ }
- if (dev_priv->sarea_priv)
- dev_priv->sarea_priv->last_dispatch = READ_BREADCRUMB(dev_priv);
+ /* Clear the generated interrupt */
+ if (IS_I9XX(dev) && !IS_I915G(dev) && !IS_I915GM(dev)) {
- I915_WRITE(I915REG_INT_IDENTITY_R, temp);
++ I915_WRITE(I915REG_INT_IDENTITY_R, iir);
+ (void) I915_READ(I915REG_INT_IDENTITY_R);
+ } else {
- I915_WRITE16(I915REG_INT_IDENTITY_R, temp);
++ I915_WRITE16(I915REG_INT_IDENTITY_R, iir);
+ (void) I915_READ16(I915REG_INT_IDENTITY_R);
+ }
-
- I915_WRITE(I915REG_INT_IDENTITY_R, iir);
- (void) I915_READ(I915REG_INT_IDENTITY_R); /* Flush posted write */
+ if (dev->primary->master) {
+ master_priv = dev->primary->master->driver_priv;
+ master_priv->sarea_priv->last_dispatch = READ_BREADCRUMB(dev_priv);
+ }
- if (temp & USER_INT_FLAG) {
+ if (iir & I915_USER_INTERRUPT) {
DRM_WAKEUP(&dev_priv->irq_queue);
#ifdef I915_HAVE_FENCE
i915_fence_handler(dev);
drm_locked_tasklet(dev, i915_vblank_tasklet);
}
- if ((temp & HOTPLUG_FLAG) || hotplug) {
++ if ((iir & I915_DISPLAY_PORT_INTERRUPT) || hotplug) {
+ u32 temp2 = 0;
+
+ DRM_INFO("Hotplug event received\n");
+
+ if (!IS_I9XX(dev) || IS_I915G(dev) || IS_I915GM(dev)) {
+ temp2 |= SDVOB_HOTPLUG_INT_STATUS |
+ SDVOC_HOTPLUG_INT_STATUS;
+ } else {
+ temp2 = I915_READ(PORT_HOTPLUG_STAT);
+
+ I915_WRITE(PORT_HOTPLUG_STAT, temp2);
+ }
+ i915_run_hotplug_tasklet(dev, temp2);
+ }
+
return IRQ_HANDLED;
}
return dev_priv->counter;
}
-void i915_user_irq_on(drm_i915_private_t *dev_priv)
+void i915_user_irq_on(struct drm_device *dev)
{
+ struct drm_i915_private *dev_priv = (struct drm_i915_private *) dev->dev_private;
+
DRM_SPINLOCK(&dev_priv->user_irq_lock);
if (dev_priv->irq_enabled && (++dev_priv->user_irq_refcount == 1)){
- dev_priv->irq_enable_reg |= USER_INT_FLAG;
+ dev_priv->irq_enable_reg |= I915_USER_INTERRUPT;
- I915_WRITE(I915REG_INT_ENABLE_R, dev_priv->irq_enable_reg);
+ if (IS_I9XX(dev) && !IS_I915G(dev) && !IS_I915GM(dev))
+ I915_WRITE(I915REG_INT_ENABLE_R, dev_priv->irq_enable_reg);
+ else
+ I915_WRITE16(I915REG_INT_ENABLE_R, dev_priv->irq_enable_reg);
}
DRM_SPINUNLOCK(&dev_priv->user_irq_lock);
}
-
-void i915_user_irq_off(drm_i915_private_t *dev_priv)
+
+void i915_user_irq_off(struct drm_device *dev)
{
+ struct drm_i915_private *dev_priv = (struct drm_i915_private *) dev->dev_private;
+
DRM_SPINLOCK(&dev_priv->user_irq_lock);
if (dev_priv->irq_enabled && (--dev_priv->user_irq_refcount == 0)) {
-- // dev_priv->irq_enable_reg &= ~USER_INT_FLAG;
- // I915_WRITE(I915REG_INT_ENABLE_R, dev_priv->irq_enable_reg);
++ // dev_priv->irq_enable_reg &= ~I915_USER_INTERRUPT;
+ // if (IS_I9XX(dev) && !IS_I915G(dev) && !IS_I915GM(dev))
+ // I915_WRITE(I915REG_INT_ENABLE_R, dev_priv->irq_enable_reg);
+ // else
+ // I915_WRITE16(I915REG_INT_ENABLE_R, dev_priv->irq_enable_reg);
}
DRM_SPINUNLOCK(&dev_priv->user_irq_lock);
}
int i915_enable_vblank(struct drm_device *dev, int plane)
{
- drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
+ struct drm_i915_private *dev_priv = (struct drm_i915_private *) dev->dev_private;
int pipe = i915_get_pipe(dev, plane);
-
+ u32 pipestat_reg = 0;
+ u32 pipestat;
+
switch (pipe) {
case 0:
- dev_priv->irq_enable_reg |= VSYNC_PIPEA_FLAG;
+ pipestat_reg = I915REG_PIPEASTAT;
+ dev_priv->irq_enable_reg |= I915_DISPLAY_PIPE_A_EVENT_INTERRUPT;
break;
case 1:
- dev_priv->irq_enable_reg |= VSYNC_PIPEB_FLAG;
+ pipestat_reg = I915REG_PIPEBSTAT;
+ dev_priv->irq_enable_reg |= I915_DISPLAY_PIPE_B_EVENT_INTERRUPT;
break;
default:
DRM_ERROR("tried to enable vblank on non-existent pipe %d\n",
break;
}
- I915_WRITE(I915REG_INT_ENABLE_R, dev_priv->irq_enable_reg);
+ if (pipestat_reg)
+ {
+ pipestat = I915_READ (pipestat_reg);
+ /*
+ * Older chips didn't have the start vblank interrupt,
+ * but
+ */
+ if (IS_I965G (dev))
+ pipestat |= I915_START_VBLANK_INTERRUPT_ENABLE;
+ else
+ pipestat |= I915_VBLANK_INTERRUPT_ENABLE;
+ /*
+ * Clear any pending status
+ */
+ pipestat |= (I915_START_VBLANK_INTERRUPT_STATUS |
+ I915_VBLANK_INTERRUPT_STATUS);
+ I915_WRITE(pipestat_reg, pipestat);
+ }
++
+ if (IS_I9XX(dev) && !IS_I915G(dev) && !IS_I915GM(dev))
+ I915_WRITE(I915REG_INT_ENABLE_R, dev_priv->irq_enable_reg);
+ else
+ I915_WRITE16(I915REG_INT_ENABLE_R, dev_priv->irq_enable_reg);
+
+
return 0;
}
void i915_disable_vblank(struct drm_device *dev, int plane)
{
- drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
+ struct drm_i915_private *dev_priv = (struct drm_i915_private *) dev->dev_private;
int pipe = i915_get_pipe(dev, plane);
+ u32 pipestat_reg = 0;
+ u32 pipestat;
switch (pipe) {
case 0:
break;
}
- I915_WRITE(I915REG_INT_ENABLE_R, dev_priv->irq_enable_reg);
+ if (IS_I9XX(dev) && !IS_I915G(dev) && !IS_I915GM(dev))
+ I915_WRITE(I915REG_INT_ENABLE_R, dev_priv->irq_enable_reg);
+ else
+ I915_WRITE16(I915REG_INT_ENABLE_R, dev_priv->irq_enable_reg);
++
+ if (pipestat_reg)
+ {
+ pipestat = I915_READ (pipestat_reg);
+ pipestat &= ~(I915_START_VBLANK_INTERRUPT_ENABLE |
+ I915_VBLANK_INTERRUPT_ENABLE);
+ /*
+ * Clear any pending status
+ */
+ pipestat |= (I915_START_VBLANK_INTERRUPT_STATUS |
+ I915_VBLANK_INTERRUPT_STATUS);
+ I915_WRITE(pipestat_reg, pipestat);
+ }
}
-static void i915_enable_interrupt (struct drm_device *dev)
+void i915_enable_interrupt (struct drm_device *dev)
{
- drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
-
+ struct drm_i915_private *dev_priv = (struct drm_i915_private *) dev->dev_private;
+ struct drm_output *o;
+
- dev_priv->irq_enable_reg |= USER_INT_FLAG;
+ dev_priv->irq_enable_reg |= I915_USER_INTERRUPT;
- I915_WRITE(I915REG_INT_ENABLE_R, dev_priv->irq_enable_reg);
+ if (IS_I9XX(dev) && !IS_I915G(dev) && !IS_I915GM(dev)) {
+ if (dev->mode_config.num_output)
- dev_priv->irq_enable_reg |= HOTPLUG_FLAG;
++ dev_priv->irq_enable_reg |= I915_DISPLAY_PORT_INTERRUPT;
+ } else {
+ if (dev->mode_config.num_output)
- dev_priv->irq_enable_reg |= EVENT_PIPEA_FLAG | EVENT_PIPEB_FLAG;
++ dev_priv->irq_enable_reg |= I915_DISPLAY_PIPE_A_EVENT_INTERRUPT;
+
+ /* Enable global interrupts for hotplug - not a pipeA event */
+ I915_WRITE(I915REG_PIPEASTAT, I915_READ(I915REG_PIPEASTAT) | I915_HOTPLUG_INTERRUPT_ENABLE | I915_HOTPLUG_CLEAR);
+ }
+
- if (dev_priv->irq_enable_reg & (HOTPLUG_FLAG | EVENT_PIPEA_FLAG | EVENT_PIPEB_FLAG)) {
++ if (dev_priv->irq_enable_reg & (I915_DISPLAY_PORT_INTERRUPT | I915_DISPLAY_PIPE_A_EVENT_INTERRUPT)) {
+ u32 temp = 0;
+
+ if (IS_I9XX(dev) && !IS_I915G(dev) && !IS_I915GM(dev)) {
+ temp = I915_READ(PORT_HOTPLUG_EN);
+
+ /* Activate the CRT */
+ temp |= CRT_HOTPLUG_INT_EN;
+ }
+
+ if (IS_I9XX(dev)) {
+ /* SDVOB */
+ o = intel_sdvo_find(dev, 1);
+ if (o && intel_sdvo_supports_hotplug(o)) {
+ intel_sdvo_set_hotplug(o, 1);
+ temp |= SDVOB_HOTPLUG_INT_EN;
+ }
+
+ /* SDVOC */
+ o = intel_sdvo_find(dev, 0);
+ if (o && intel_sdvo_supports_hotplug(o)) {
+ intel_sdvo_set_hotplug(o, 1);
+ temp |= SDVOC_HOTPLUG_INT_EN;
+ }
+
+ I915_WRITE(SDVOB, I915_READ(SDVOB) | SDVO_INTERRUPT_ENABLE);
+ I915_WRITE(SDVOC, I915_READ(SDVOC) | SDVO_INTERRUPT_ENABLE);
+ } else {
+ /* DVO ???? */
+ }
+
+ if (IS_I9XX(dev) && !IS_I915G(dev) && !IS_I915GM(dev)) {
+ I915_WRITE(PORT_HOTPLUG_EN, temp);
+
+ DRM_DEBUG("HEN %08x\n",I915_READ(PORT_HOTPLUG_EN));
+ DRM_DEBUG("HST %08x\n",I915_READ(PORT_HOTPLUG_STAT));
+
+ I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
+ }
+ }
+
+ if (IS_I9XX(dev) && !IS_I915G(dev) && !IS_I915GM(dev))
+ I915_WRITE(I915REG_INT_ENABLE_R, dev_priv->irq_enable_reg);
+ else
+ I915_WRITE16(I915REG_INT_ENABLE_R, dev_priv->irq_enable_reg);
+
dev_priv->irq_enabled = 1;
}
return -EINVAL;
}
- flag = I915_READ(I915REG_INT_ENABLE_R);
+ if (IS_I9XX(dev) && !IS_I915G(dev) && !IS_I915GM(dev))
+ flag = I915_READ(I915REG_INT_ENABLE_R);
+ else
+ flag = I915_READ16(I915REG_INT_ENABLE_R);
+
pipe->pipe = 0;
- if (flag & VSYNC_PIPEA_FLAG)
+ if (flag & I915_DISPLAY_PIPE_A_EVENT_INTERRUPT)
pipe->pipe |= DRM_I915_VBLANK_PIPE_A;
- if (flag & VSYNC_PIPEB_FLAG)
+ if (flag & I915_DISPLAY_PIPE_B_EVENT_INTERRUPT)
pipe->pipe |= DRM_I915_VBLANK_PIPE_B;
return 0;
*/
void i915_driver_irq_preinstall(struct drm_device * dev)
{
- drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
+ struct drm_i915_private *dev_priv = (struct drm_i915_private *) dev->dev_private;
- I915_WRITE(I915REG_PIPEASTAT, 0xffff);
- I915_WRITE(I915REG_PIPEBSTAT, 0xffff);
I915_WRITE16(I915REG_HWSTAM, 0xeffe);
- I915_WRITE16(I915REG_INT_MASK_R, 0x0);
- I915_WRITE16(I915REG_INT_ENABLE_R, 0x0);
+ if (IS_I9XX(dev) && !IS_I915G(dev) && !IS_I915GM(dev)) {
+ I915_WRITE(I915REG_INT_MASK_R, 0x0);
+ I915_WRITE(I915REG_INT_ENABLE_R, 0x0);
+ } else {
+ I915_WRITE16(I915REG_INT_MASK_R, 0x0);
+ I915_WRITE16(I915REG_INT_ENABLE_R, 0x0);
+ }
+
}
int i915_driver_irq_postinstall(struct drm_device * dev)
return;
dev_priv->irq_enabled = 0;
- I915_WRITE(I915REG_HWSTAM, 0xffffffff);
- I915_WRITE(I915REG_INT_MASK_R, 0xffffffff);
- I915_WRITE(I915REG_INT_ENABLE_R, 0x0);
-
- I915_WRITE(I915REG_PIPEASTAT, 0xffff);
- I915_WRITE(I915REG_PIPEBSTAT, 0xffff);
+ temp = I915_READ(I915REG_PIPEASTAT);
+ I915_WRITE(I915REG_PIPEASTAT, temp);
+ temp = I915_READ(I915REG_PIPEBSTAT);
+ I915_WRITE(I915REG_PIPEBSTAT, temp);
- temp = I915_READ(I915REG_INT_IDENTITY_R);
- I915_WRITE(I915REG_INT_IDENTITY_R, temp);
+ if (IS_I9XX(dev) && !IS_I915G(dev) && !IS_I915GM(dev)) {
+ I915_WRITE(I915REG_HWSTAM, 0xffffffff);
+ I915_WRITE(I915REG_INT_MASK_R, 0xffffffff);
+ I915_WRITE(I915REG_INT_ENABLE_R, 0x0);
+
+ temp = I915_READ(I915REG_INT_IDENTITY_R);
+ I915_WRITE(I915REG_INT_IDENTITY_R, temp);
+ } else {
+ I915_WRITE16(I915REG_HWSTAM, 0xffff);
+ I915_WRITE16(I915REG_INT_MASK_R, 0xffff);
+ I915_WRITE16(I915REG_INT_ENABLE_R, 0x0);
+
+ temp = I915_READ16(I915REG_INT_IDENTITY_R);
+ I915_WRITE16(I915REG_INT_IDENTITY_R, temp);
+ }
}
projects / platform / upstream / libdrm.git / commitdiff