arm64: dts: nuvoton: Add initial ma35d1 device tree

Add initial device tree support for Nuvoton ma35d1 SoC, including
cpu, clock, reset, and serial controllers.
Add reference boards som-256m and iot-512m.

Signed-off-by: Jacky Huang <ychuang3@nuvoton.com>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>

diff --git a/arch/arm64/boot/dts/nuvoton/Makefile b/arch/arm64/boot/dts/nuvoton/Makefile
index a99dab9..3bc9787 100644 (file)
--- a/arch/arm64/boot/dts/nuvoton/Makefile
+++ b/arch/arm64/boot/dts/nuvoton/Makefile
@@ -1,2 +1,4 @@
 # SPDX-License-Identifier: GPL-2.0
+dtb-$(CONFIG_ARCH_MA35) += ma35d1-iot-512m.dtb
+dtb-$(CONFIG_ARCH_MA35) += ma35d1-som-256m.dtb
 dtb-$(CONFIG_ARCH_NPCM) += nuvoton-npcm845-evb.dtb

diff --git a/arch/arm64/boot/dts/nuvoton/ma35d1-iot-512m.dts b/arch/arm64/boot/dts/nuvoton/ma35d1-iot-512m.dts
new file mode 100644 (file)
index 0000000..b89e2be
--- /dev/null
+++ b/arch/arm64/boot/dts/nuvoton/ma35d1-iot-512m.dts
@@ -0,0 +1,56 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2023 Nuvoton Technology Corp.
+ * Author: Shan-Chun Hung <schung@nuvoton.com>
+ *         Jacky huang <ychuang3@nuvoton.com>
+ */
+
+/dts-v1/;
+#include "ma35d1.dtsi"
+
+/ {
+       model = "Nuvoton MA35D1-IoT";
+       compatible = "nuvoton,ma35d1-iot", "nuvoton,ma35d1";
+
+       aliases {
+               serial0 = &uart0;
+       };
+
+       chosen {
+               stdout-path = "serial0:115200n8";
+       };
+
+       mem: memory@80000000 {
+               device_type = "memory";
+               reg = <0x00000000 0x80000000 0 0x20000000>; /* 512M DRAM */
+       };
+
+       clk_hxt: clock-hxt {
+               compatible = "fixed-clock";
+               #clock-cells = <0>;
+               clock-frequency = <24000000>;
+               clock-output-names = "clk_hxt";
+       };
+};
+
+&uart0 {
+       status = "okay";
+};
+
+&clk {
+       assigned-clocks = <&clk CAPLL>,
+                         <&clk DDRPLL>,
+                         <&clk APLL>,
+                         <&clk EPLL>,
+                         <&clk VPLL>;
+       assigned-clock-rates = <800000000>,
+                              <266000000>,
+                              <180000000>,
+                              <500000000>,
+                              <102000000>;
+       nuvoton,pll-mode = "integer",
+                          "fractional",
+                          "integer",
+                          "integer",
+                          "integer";
+};

diff --git a/arch/arm64/boot/dts/nuvoton/ma35d1-som-256m.dts b/arch/arm64/boot/dts/nuvoton/ma35d1-som-256m.dts
new file mode 100644 (file)
index 0000000..a1ebdde
--- /dev/null
+++ b/arch/arm64/boot/dts/nuvoton/ma35d1-som-256m.dts
@@ -0,0 +1,56 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2023 Nuvoton Technology Corp.
+ * Author: Shan-Chun Hung <schung@nuvoton.com>
+ *         Jacky huang <ychuang3@nuvoton.com>
+ */
+
+/dts-v1/;
+#include "ma35d1.dtsi"
+
+/ {
+       model = "Nuvoton MA35D1-SOM";
+       compatible = "nuvoton,ma35d1-som", "nuvoton,ma35d1";
+
+       aliases {
+               serial0 = &uart0;
+       };
+
+       chosen {
+               stdout-path = "serial0:115200n8";
+       };
+
+       mem: memory@80000000 {
+               device_type = "memory";
+               reg = <0x00000000 0x80000000 0 0x10000000>; /* 256M DRAM */
+       };
+
+       clk_hxt: clock-hxt {
+               compatible = "fixed-clock";
+               #clock-cells = <0>;
+               clock-frequency = <24000000>;
+               clock-output-names = "clk_hxt";
+       };
+};
+
+&uart0 {
+       status = "okay";
+};
+
+&clk {
+       assigned-clocks = <&clk CAPLL>,
+                         <&clk DDRPLL>,
+                         <&clk APLL>,
+                         <&clk EPLL>,
+                         <&clk VPLL>;
+       assigned-clock-rates = <800000000>,
+                              <266000000>,
+                              <180000000>,
+                              <500000000>,
+                              <102000000>;
+       nuvoton,pll-mode = "integer",
+                          "fractional",
+                          "integer",
+                          "integer",
+                          "integer";
+};

diff --git a/arch/arm64/boot/dts/nuvoton/ma35d1.dtsi b/arch/arm64/boot/dts/nuvoton/ma35d1.dtsi
new file mode 100644 (file)
index 0000000..781cdae
--- /dev/null
+++ b/arch/arm64/boot/dts/nuvoton/ma35d1.dtsi
@@ -0,0 +1,234 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2023 Nuvoton Technology Corp.
+ * Author: Shan-Chun Hung <schung@nuvoton.com>
+ *         Jacky huang <ychuang3@nuvoton.com>
+ */
+
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/clock/nuvoton,ma35d1-clk.h>
+#include <dt-bindings/reset/nuvoton,ma35d1-reset.h>
+
+/ {
+       compatible = "nuvoton,ma35d1";
+       interrupt-parent = <&gic>;
+       #address-cells = <2>;
+       #size-cells = <2>;
+
+       cpus {
+               #address-cells = <2>;
+               #size-cells = <0>;
+
+               cpu0: cpu@0 {
+                       device_type = "cpu";
+                       compatible = "arm,cortex-a35";
+                       reg = <0x0 0x0>;
+                       enable-method = "psci";
+                       next-level-cache = <&L2_0>;
+               };
+
+               cpu1: cpu@1 {
+                       device_type = "cpu";
+                       compatible = "arm,cortex-a35";
+                       reg = <0x0 0x1>;
+                       enable-method = "psci";
+                       next-level-cache = <&L2_0>;
+               };
+
+               L2_0: l2-cache {
+                       compatible = "cache";
+                       cache-level = <2>;
+                       cache-unified;
+                       cache-size = <0x80000>;
+               };
+       };
+
+       psci {
+               compatible = "arm,psci-0.2";
+               method = "smc";
+       };
+
+       gic: interrupt-controller@50801000 {
+               compatible = "arm,gic-400";
+               reg = <0x0 0x50801000 0 0x1000>, /* GICD */
+                     <0x0 0x50802000 0 0x2000>, /* GICC */
+                     <0x0 0x50804000 0 0x2000>, /* GICH */
+                     <0x0 0x50806000 0 0x2000>; /* GICV */
+               #interrupt-cells = <3>;
+               interrupt-parent = <&gic>;
+               interrupt-controller;
+               interrupts = <GIC_PPI 9 (GIC_CPU_MASK_RAW(0x13) |
+                             IRQ_TYPE_LEVEL_HIGH)>;
+       };
+
+       timer {
+               compatible = "arm,armv8-timer";
+               interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) |
+                             IRQ_TYPE_LEVEL_LOW)>, /* Physical Secure */
+                            <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) |
+                             IRQ_TYPE_LEVEL_LOW)>, /* Physical Non-Secure */
+                            <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) |
+                             IRQ_TYPE_LEVEL_LOW)>, /* Virtual */
+                            <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) |
+                             IRQ_TYPE_LEVEL_LOW)>; /* Hypervisor */
+               interrupt-parent = <&gic>;
+       };
+
+       soc {
+               compatible = "simple-bus";
+               #address-cells = <2>;
+               #size-cells = <2>;
+               ranges;
+
+               sys: system-management@40460000 {
+                       compatible = "nuvoton,ma35d1-reset";
+                       reg = <0x0 0x40460000 0x0 0x200>;
+                       #reset-cells = <1>;
+               };
+
+               clk: clock-controller@40460200 {
+                       compatible = "nuvoton,ma35d1-clk";
+                       reg = <0x00000000 0x40460200 0x0 0x100>;
+                       #clock-cells = <1>;
+                       clocks = <&clk_hxt>;
+               };
+
+               uart0: serial@40700000 {
+                       compatible = "nuvoton,ma35d1-uart";
+                       reg = <0x0 0x40700000 0x0 0x100>;
+                       interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
+                       clocks = <&clk UART0_GATE>;
+                       status = "disabled";
+               };
+
+               uart1: serial@40710000 {
+                       compatible = "nuvoton,ma35d1-uart";
+                       reg = <0x0 0x40710000 0x0 0x100>;
+                       interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
+                       clocks = <&clk UART1_GATE>;
+                       status = "disabled";
+               };
+
+               uart2: serial@40720000 {
+                       compatible = "nuvoton,ma35d1-uart";
+                       reg = <0x0 0x40720000 0x0 0x100>;
+                       interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
+                       clocks = <&clk UART2_GATE>;
+                       status = "disabled";
+               };
+
+               uart3: serial@40730000 {
+                       compatible = "nuvoton,ma35d1-uart";
+                       reg = <0x0 0x40730000 0x0 0x100>;
+                       interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
+                       clocks = <&clk UART3_GATE>;
+                       status = "disabled";
+               };
+
+               uart4: serial@40740000 {
+                       compatible = "nuvoton,ma35d1-uart";
+                       reg = <0x0 0x40740000 0x0 0x100>;
+                       interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
+                       clocks = <&clk UART4_GATE>;
+                       status = "disabled";
+               };
+
+               uart5: serial@40750000 {
+                       compatible = "nuvoton,ma35d1-uart";
+                       reg = <0x0 0x40750000 0x0 0x100>;
+                       interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
+                       clocks = <&clk UART5_GATE>;
+                       status = "disabled";
+               };
+
+               uart6: serial@40760000 {
+                       compatible = "nuvoton,ma35d1-uart";
+                       reg = <0x0 0x40760000 0x0 0x100>;
+                       interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
+                       clocks = <&clk UART6_GATE>;
+                       status = "disabled";
+               };
+
+               uart7: serial@40770000 {
+                       compatible = "nuvoton,ma35d1-uart";
+                       reg = <0x0 0x40770000 0x0 0x100>;
+                       interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
+                       clocks = <&clk UART7_GATE>;
+                       status = "disabled";
+               };
+
+               uart8: serial@40780000 {
+                       compatible = "nuvoton,ma35d1-uart";
+                       reg = <0x0 0x40780000 0x0 0x100>;
+                       interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
+                       clocks = <&clk UART8_GATE>;
+                       status = "disabled";
+               };
+
+               uart9: serial@40790000 {
+                       compatible = "nuvoton,ma35d1-uart";
+                       reg = <0x0 0x40790000 0x0 0x100>;
+                       interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
+                       clocks = <&clk UART9_GATE>;
+                       status = "disabled";
+               };
+
+               uart10: serial@407a0000 {
+                       compatible = "nuvoton,ma35d1-uart";
+                       reg = <0x0 0x407a0000 0x0 0x100>;
+                       interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
+                       clocks = <&clk UART10_GATE>;
+                       status = "disabled";
+               };
+
+               uart11: serial@407b0000 {
+                       compatible = "nuvoton,ma35d1-uart";
+                       reg = <0x0 0x407b0000 0x0 0x100>;
+                       interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
+                       clocks = <&clk UART11_GATE>;
+                       status = "disabled";
+               };
+
+               uart12: serial@407c0000 {
+                       compatible = "nuvoton,ma35d1-uart";
+                       reg = <0x0 0x407c0000 0x0 0x100>;
+                       interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
+                       clocks = <&clk UART12_GATE>;
+                       status = "disabled";
+               };
+
+               uart13: serial@407d0000 {
+                       compatible = "nuvoton,ma35d1-uart";
+                       reg = <0x0 0x407d0000 0x0 0x100>;
+                       interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
+                       clocks = <&clk UART13_GATE>;
+                       status = "disabled";
+               };
+
+               uart14: serial@407e0000 {
+                       compatible = "nuvoton,ma35d1-uart";
+                       reg = <0x0 0x407e0000 0x0 0x100>;
+                       interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
+                       clocks = <&clk UART14_GATE>;
+                       status = "disabled";
+               };
+
+               uart15: serial@407f0000 {
+                       compatible = "nuvoton,ma35d1-uart";
+                       reg = <0x0 0x407f0000 0x0 0x100>;
+                       interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
+                       clocks = <&clk UART15_GATE>;
+                       status = "disabled";
+               };
+
+               uart16: serial@40880000 {
+                       compatible = "nuvoton,ma35d1-uart";
+                       reg = <0x0 0x40880000 0x0 0x100>;
+                       interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
+                       clocks = <&clk UART16_GATE>;
+                       status = "disabled";
+               };
+       };
+};