# Note that GCC does not numerically define an architecture version
# macro, but instead defines a whole series of macros which makes
# testing for a specific architecture or later rather impossible.
-arch-$(CONFIG_CPU_32v7) :=-D__LINUX_ARM_ARCH__=7 $(call cc-option,-march=armv7a,-march=armv5t -Wa$(comma)-march=armv7a)
+arch-$(CONFIG_CPU_32v7) :=-D__LINUX_ARM_ARCH__=7 $(call cc-option,-march=armv7-a,-march=armv5t -Wa$(comma)-march=armv7-a)
arch-$(CONFIG_CPU_32v6) :=-D__LINUX_ARM_ARCH__=6 $(call cc-option,-march=armv6,-march=armv5t -Wa$(comma)-march=armv6)
# Only override the compiler option if ARMv6. The ARMv6K extensions are
# always available in ARMv7
machine-$(CONFIG_ARCH_IXP23XX) := ixp23xx
machine-$(CONFIG_ARCH_OMAP1) := omap1
machine-$(CONFIG_ARCH_OMAP2) := omap2
+ machine-$(CONFIG_ARCH_OMAP3) := omap2
plat-$(CONFIG_ARCH_OMAP) := omap
machine-$(CONFIG_ARCH_S3C2410) := s3c2410 s3c2400 s3c2412 s3c2440 s3c2442 s3c2443
plat-$(CONFIG_PLAT_S3C24XX) := s3c24xx
#include <linux/errno.h>
#include <linux/err.h>
#include <linux/clk.h>
+#include <linux/io.h>
-#include <asm/io.h>
#include <asm/mach-types.h>
#include <mach/cpu.h>
return -EINVAL;
parent = clk->parent;
- if (unlikely(parent == 0))
+ if (unlikely(parent == NULL))
return -EIO;
realrate = parent->rate;
if (clk->flags & ALWAYS_ENABLED)
return 0;
- if (unlikely(clk->enable_reg == 0)) {
+ if (unlikely(clk->enable_reg == NULL)) {
printk(KERN_ERR "clock.c: Enable for %s without enable code\n",
clk->name);
return -EINVAL;
__u16 regval16;
__u32 regval32;
- if (clk->enable_reg == 0)
+ if (clk->enable_reg == NULL)
return;
if (clk->flags & ENABLE_REG_32BIT) {
return clk->parent->rate / (1 << dsor_exp);
}
- if(clk->round_rate != 0)
+ if (clk->round_rate != NULL)
return clk->round_rate(clk, rate);
return clk->rate;
/* Clocks in the DSP domain need api_ck. Just assume bootloader
* has not enabled any DSP clocks */
- if ((u32)clk->enable_reg == DSP_IDLECT2) {
+ if (clk->enable_reg == DSP_IDLECT2) {
printk(KERN_INFO "Skipping reset check for DSP domain "
"clock \"%s\"\n", clk->name);
return;
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/platform_device.h>
+#include <linux/io.h>
#include <mach/hardware.h>
-#include <asm/io.h>
#include <asm/mach/map.h>
#include <mach/tc.h>
#if defined(CONFIG_OMAP_STI)
- #define OMAP1_STI_BASE IO_ADDRESS(0xfffea000)
+ #define OMAP1_STI_BASE 0xfffea000
#define OMAP1_STI_CHANNEL_BASE (OMAP1_STI_BASE + 0x400)
static struct resource sti_resources[] = {
#include <linux/serial_8250.h>
#include <linux/serial_reg.h>
#include <linux/clk.h>
+#include <linux/io.h>
-#include <asm/io.h>
#include <asm/mach-types.h>
#include <mach/board.h>
static struct plat_serial8250_port serial_platform_data[] = {
{
- .membase = (char*)IO_ADDRESS(OMAP_UART1_BASE),
- .mapbase = (unsigned long)OMAP_UART1_BASE,
+ .membase = IO_ADDRESS(OMAP_UART1_BASE),
+ .mapbase = OMAP_UART1_BASE,
.irq = INT_UART1,
.flags = UPF_BOOT_AUTOCONF,
.iotype = UPIO_MEM,
.uartclk = OMAP16XX_BASE_BAUD * 16,
},
{
- .membase = (char*)IO_ADDRESS(OMAP_UART2_BASE),
- .mapbase = (unsigned long)OMAP_UART2_BASE,
+ .membase = IO_ADDRESS(OMAP_UART2_BASE),
+ .mapbase = OMAP_UART2_BASE,
.irq = INT_UART2,
.flags = UPF_BOOT_AUTOCONF,
.iotype = UPIO_MEM,
.uartclk = OMAP16XX_BASE_BAUD * 16,
},
{
- .membase = (char*)IO_ADDRESS(OMAP_UART3_BASE),
- .mapbase = (unsigned long)OMAP_UART3_BASE,
+ .membase = IO_ADDRESS(OMAP_UART3_BASE),
+ .mapbase = OMAP_UART3_BASE,
.irq = INT_UART3,
.flags = UPF_BOOT_AUTOCONF,
.iotype = UPIO_MEM,
#include <linux/errno.h>
#include <linux/delay.h>
#include <linux/clk.h>
-#include <asm/bitops.h>
-
-#include <asm/io.h>
+#include <linux/io.h>
+#include <linux/bitops.h>
#include <mach/clock.h>
+ #include <mach/clockdomain.h>
#include <mach/sram.h>
#include <mach/cpu.h>
#include <asm/div64.h>
u8 cpu_mask;
/*-------------------------------------------------------------------------
- * Omap2 specific clock functions
+ * OMAP2/3 specific clock functions
*-------------------------------------------------------------------------*/
/**
+ * omap2_init_clk_clkdm - look up a clockdomain name, store pointer in clk
+ * @clk: OMAP clock struct ptr to use
+ *
+ * Convert a clockdomain name stored in a struct clk 'clk' into a
+ * clockdomain pointer, and save it into the struct clk. Intended to be
+ * called during clk_register(). No return value.
+ */
+ void omap2_init_clk_clkdm(struct clk *clk)
+ {
+ struct clockdomain *clkdm;
+
+ if (!clk->clkdm_name)
+ return;
+
+ clkdm = clkdm_lookup(clk->clkdm_name);
+ if (clkdm) {
+ pr_debug("clock: associated clk %s to clkdm %s\n",
+ clk->name, clk->clkdm_name);
+ clk->clkdm = clkdm;
+ } else {
+ pr_debug("clock: could not associate clk %s to "
+ "clkdm %s\n", clk->name, clk->clkdm_name);
+ }
+ }
+
+ /**
* omap2_init_clksel_parent - set a clksel clk's parent field from the hardware
* @clk: OMAP clock struct ptr to use
*
if (clk->enable)
return clk->enable(clk);
- if (unlikely(clk->enable_reg == 0)) {
+ if (unlikely(clk->enable_reg == NULL)) {
printk(KERN_ERR "clock.c: Enable for %s without enable code\n",
clk->name);
return 0; /* REVISIT: -EINVAL */
return;
}
- if (clk->enable_reg == 0) {
+ if (clk->enable_reg == NULL) {
/*
* 'Independent' here refers to a clock which is not
* controlled by its parent.
_omap2_clk_disable(clk);
if (likely((u32)clk->parent))
omap2_clk_disable(clk->parent);
+ if (clk->clkdm)
+ omap2_clkdm_clk_disable(clk->clkdm, clk);
+
}
}
return ret;
}
+ if (clk->clkdm)
+ omap2_clkdm_clk_enable(clk->clkdm, clk);
+
ret = _omap2_clk_enable(clk);
- if (unlikely(ret != 0) && clk->parent) {
- omap2_clk_disable(clk->parent);
- clk->usecount--;
+ if (unlikely(ret != 0)) {
+ if (clk->clkdm)
+ omap2_clkdm_clk_disable(clk->clkdm, clk);
+
+ if (clk->parent) {
+ omap2_clk_disable(clk->parent);
+ clk->usecount--;
+ }
}
}
/* Given a clock and a rate apply a clock specific rounding function */
long omap2_clk_round_rate(struct clk *clk, unsigned long rate)
{
- if (clk->round_rate != 0)
+ if (clk->round_rate != NULL)
return clk->round_rate(clk, rate);
if (clk->flags & RATE_FIXED)
*/
void __iomem *omap2_get_clksel(struct clk *clk, u32 *field_mask)
{
- if (unlikely((clk->clksel_reg == 0) || (clk->clksel_mask == 0)))
+ if (unlikely((clk->clksel_reg == NULL) || (clk->clksel_mask == NULL)))
return NULL;
*field_mask = clk->clksel_mask;
void __iomem *div_addr;
div_addr = omap2_get_clksel(clk, &field_mask);
- if (div_addr == 0)
+ if (div_addr == NULL)
return 0;
field_val = __raw_readl(div_addr) & field_mask;
return -EINVAL;
div_addr = omap2_get_clksel(clk, &field_mask);
- if (div_addr == 0)
+ if (div_addr == NULL)
return -EINVAL;
field_val = omap2_divisor_to_clksel(clk, new_div);
return -EINVAL;
/* dpll_ck, core_ck, virt_prcm_set; plus all clksel clocks */
- if (clk->set_rate != 0)
+ if (clk->set_rate != NULL)
ret = clk->set_rate(clk, rate);
if (unlikely(ret == 0 && (clk->flags & RATE_PROPAGATES)))
const struct clksel_rate *clkr;
*parent_div = 0;
- *src_addr = 0;
+ *src_addr = NULL;
clks = omap2_get_clksel_by_parent(clk, src_clk);
if (clks == NULL)
field_val = omap2_clksel_get_src_field(&src_addr, new_parent,
&field_mask, clk, &parent_div);
- if (src_addr == 0)
+ if (src_addr == NULL)
return -EINVAL;
if (clk->usecount > 0)
#include <linux/clk.h>
#include <linux/io.h>
#include <linux/limits.h>
+#include <linux/bitops.h>
#include <mach/clock.h>
#include <mach/sram.h>
#include <asm/div64.h>
-#include <asm/bitops.h>
#include "memory.h"
#include "clock.h"
static void _omap3_dpll_write_clken(struct clk *clk, u8 clken_bits)
{
const struct dpll_data *dd;
+ u32 v;
dd = clk->dpll_data;
- cm_rmw_reg_bits(dd->enable_mask, clken_bits << __ffs(dd->enable_mask),
- dd->control_reg);
+ v = __raw_readl(dd->control_reg);
+ v &= ~dd->enable_mask;
+ v |= clken_bits << __ffs(dd->enable_mask);
+ __raw_writel(v, dd->control_reg);
}
/* _omap3_wait_dpll_status: wait for a DPLL to enter a specific state */
state <<= dd->idlest_bit;
idlest_mask = 1 << dd->idlest_bit;
- while (((cm_read_reg(dd->idlest_reg) & idlest_mask) != state) &&
+ while (((__raw_readl(dd->idlest_reg) & idlest_mask) != state) &&
i < MAX_DPLL_WAIT_TRIES) {
i++;
udelay(1);
dd = clk->dpll_data;
- v = cm_read_reg(dd->autoidle_reg);
+ v = __raw_readl(dd->autoidle_reg);
v &= dd->autoidle_mask;
v >>= __ffs(dd->autoidle_mask);
static void omap3_dpll_allow_idle(struct clk *clk)
{
const struct dpll_data *dd;
+ u32 v;
if (!clk || !clk->dpll_data)
return;
* by writing 0x5 instead of 0x1. Add some mechanism to
* optionally enter this mode.
*/
- cm_rmw_reg_bits(dd->autoidle_mask,
- DPLL_AUTOIDLE_LOW_POWER_STOP << __ffs(dd->autoidle_mask),
- dd->autoidle_reg);
+ v = __raw_readl(dd->autoidle_reg);
+ v &= ~dd->autoidle_mask;
+ v |= DPLL_AUTOIDLE_LOW_POWER_STOP << __ffs(dd->autoidle_mask);
+ __raw_writel(v, dd->autoidle_reg);
}
/**
static void omap3_dpll_deny_idle(struct clk *clk)
{
const struct dpll_data *dd;
+ u32 v;
if (!clk || !clk->dpll_data)
return;
dd = clk->dpll_data;
- cm_rmw_reg_bits(dd->autoidle_mask,
- DPLL_AUTOIDLE_DISABLE << __ffs(dd->autoidle_mask),
- dd->autoidle_reg);
+ v = __raw_readl(dd->autoidle_reg);
+ v &= ~dd->autoidle_mask;
+ v |= DPLL_AUTOIDLE_DISABLE << __ffs(dd->autoidle_mask);
+ __raw_writel(v, dd->autoidle_reg);
}
/* Clock control for DPLL outputs */
for (clkp = onchip_34xx_clks;
clkp < onchip_34xx_clks + ARRAY_SIZE(onchip_34xx_clks);
clkp++) {
- if ((*clkp)->flags & cpu_clkflg)
+ if ((*clkp)->flags & cpu_clkflg) {
clk_register(*clkp);
+ omap2_init_clk_clkdm(*clkp);
+ }
}
/* REVISIT: Not yet ready for OMAP3 */
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/platform_device.h>
+#include <linux/io.h>
#include <mach/hardware.h>
-#include <asm/io.h>
#include <asm/mach-types.h>
#include <asm/mach/map.h>
#include <mach/board.h>
#include <mach/mux.h>
#include <mach/gpio.h>
-
- #if defined(CONFIG_I2C_OMAP) || defined(CONFIG_I2C_OMAP_MODULE)
-
- #define OMAP2_I2C_BASE2 0x48072000
- #define OMAP2_I2C_INT2 57
-
- static struct resource i2c_resources2[] = {
- {
- .start = OMAP2_I2C_BASE2,
- .end = OMAP2_I2C_BASE2 + 0x3f,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = OMAP2_I2C_INT2,
- .flags = IORESOURCE_IRQ,
- },
- };
-
- static struct platform_device omap_i2c_device2 = {
- .name = "i2c_omap",
- .id = 2,
- .num_resources = ARRAY_SIZE(i2c_resources2),
- .resource = i2c_resources2,
- };
-
- /* See also arch/arm/plat-omap/devices.c for first I2C on 24xx */
- static void omap_init_i2c(void)
- {
- /* REVISIT: Second I2C not in use on H4? */
- if (machine_is_omap_h4())
- return;
-
- if (!cpu_is_omap2430()) {
- omap_cfg_reg(J15_24XX_I2C2_SCL);
- omap_cfg_reg(H19_24XX_I2C2_SDA);
- }
- (void) platform_device_register(&omap_i2c_device2);
- }
-
- #else
-
- static void omap_init_i2c(void) {}
-
- #endif
+ #include <mach/eac.h>
#if defined(CONFIG_OMAP_DSP) || defined(CONFIG_OMAP_DSP_MODULE)
#define OMAP2_MBOX_BASE IO_ADDRESS(OMAP24XX_MAILBOX_BASE)
#if defined(CONFIG_OMAP_STI)
- #define OMAP2_STI_BASE IO_ADDRESS(0x48068000)
+ #if defined(CONFIG_ARCH_OMAP2)
+
+ #define OMAP2_STI_BASE 0x48068000
#define OMAP2_STI_CHANNEL_BASE 0x54000000
#define OMAP2_STI_IRQ 4
.flags = IORESOURCE_IRQ,
}
};
+ #elif defined(CONFIG_ARCH_OMAP3)
+
+ #define OMAP3_SDTI_BASE 0x54500000
+ #define OMAP3_SDTI_CHANNEL_BASE 0x54600000
+
+ static struct resource sti_resources[] = {
+ {
+ .start = OMAP3_SDTI_BASE,
+ .end = OMAP3_SDTI_BASE + 0xFFF,
+ .flags = IORESOURCE_MEM,
+ },
+ {
+ .start = OMAP3_SDTI_CHANNEL_BASE,
+ .end = OMAP3_SDTI_CHANNEL_BASE + SZ_1M - 1,
+ .flags = IORESOURCE_MEM,
+ }
+ };
+
+ #endif
static struct platform_device sti_device = {
.name = "sti",
static inline void omap_init_sti(void) {}
#endif
- #if defined(CONFIG_SPI_OMAP24XX)
+ #if defined(CONFIG_SPI_OMAP24XX) || defined(CONFIG_SPI_OMAP24XX_MODULE)
#include <mach/mcspi.h>
#define OMAP2_MCSPI1_BASE 0x48098000
#define OMAP2_MCSPI2_BASE 0x4809a000
+ #define OMAP2_MCSPI3_BASE 0x480b8000
+ #define OMAP2_MCSPI4_BASE 0x480ba000
static struct omap2_mcspi_platform_config omap2_mcspi1_config = {
.num_cs = 4,
},
};
- struct platform_device omap2_mcspi1 = {
+ static struct platform_device omap2_mcspi1 = {
.name = "omap2_mcspi",
.id = 1,
.num_resources = ARRAY_SIZE(omap2_mcspi1_resources),
},
};
- struct platform_device omap2_mcspi2 = {
+ static struct platform_device omap2_mcspi2 = {
.name = "omap2_mcspi",
.id = 2,
.num_resources = ARRAY_SIZE(omap2_mcspi2_resources),
},
};
+ #if defined(CONFIG_ARCH_OMAP2430) || defined(CONFIG_ARCH_OMAP3)
+ static struct omap2_mcspi_platform_config omap2_mcspi3_config = {
+ .num_cs = 2,
+ };
+
+ static struct resource omap2_mcspi3_resources[] = {
+ {
+ .start = OMAP2_MCSPI3_BASE,
+ .end = OMAP2_MCSPI3_BASE + 0xff,
+ .flags = IORESOURCE_MEM,
+ },
+ };
+
+ static struct platform_device omap2_mcspi3 = {
+ .name = "omap2_mcspi",
+ .id = 3,
+ .num_resources = ARRAY_SIZE(omap2_mcspi3_resources),
+ .resource = omap2_mcspi3_resources,
+ .dev = {
+ .platform_data = &omap2_mcspi3_config,
+ },
+ };
+ #endif
+
+ #ifdef CONFIG_ARCH_OMAP3
+ static struct omap2_mcspi_platform_config omap2_mcspi4_config = {
+ .num_cs = 1,
+ };
+
+ static struct resource omap2_mcspi4_resources[] = {
+ {
+ .start = OMAP2_MCSPI4_BASE,
+ .end = OMAP2_MCSPI4_BASE + 0xff,
+ .flags = IORESOURCE_MEM,
+ },
+ };
+
+ static struct platform_device omap2_mcspi4 = {
+ .name = "omap2_mcspi",
+ .id = 4,
+ .num_resources = ARRAY_SIZE(omap2_mcspi4_resources),
+ .resource = omap2_mcspi4_resources,
+ .dev = {
+ .platform_data = &omap2_mcspi4_config,
+ },
+ };
+ #endif
+
static void omap_init_mcspi(void)
{
platform_device_register(&omap2_mcspi1);
platform_device_register(&omap2_mcspi2);
+ #if defined(CONFIG_ARCH_OMAP2430) || defined(CONFIG_ARCH_OMAP3)
+ platform_device_register(&omap2_mcspi3);
+ #endif
+ #ifdef CONFIG_ARCH_OMAP3
+ platform_device_register(&omap2_mcspi4);
+ #endif
}
#else
static inline void omap_init_mcspi(void) {}
#endif
+ #ifdef CONFIG_SND_OMAP24XX_EAC
+
+ #define OMAP2_EAC_BASE 0x48090000
+
+ static struct resource omap2_eac_resources[] = {
+ {
+ .start = OMAP2_EAC_BASE,
+ .end = OMAP2_EAC_BASE + 0x109,
+ .flags = IORESOURCE_MEM,
+ },
+ };
+
+ static struct platform_device omap2_eac_device = {
+ .name = "omap24xx-eac",
+ .id = -1,
+ .num_resources = ARRAY_SIZE(omap2_eac_resources),
+ .resource = omap2_eac_resources,
+ .dev = {
+ .platform_data = NULL,
+ },
+ };
+
+ void omap_init_eac(struct eac_platform_data *pdata)
+ {
+ omap2_eac_device.dev.platform_data = pdata;
+ platform_device_register(&omap2_eac_device);
+ }
+
+ #else
+ void omap_init_eac(struct eac_platform_data *pdata) {}
+ #endif
+
+ #ifdef CONFIG_OMAP_SHA1_MD5
+ static struct resource sha1_md5_resources[] = {
+ {
+ .start = OMAP24XX_SEC_SHA1MD5_BASE,
+ .end = OMAP24XX_SEC_SHA1MD5_BASE + 0x64,
+ .flags = IORESOURCE_MEM,
+ },
+ {
+ .start = INT_24XX_SHA1MD5,
+ .flags = IORESOURCE_IRQ,
+ }
+ };
+
+ static struct platform_device sha1_md5_device = {
+ .name = "OMAP SHA1/MD5",
+ .id = -1,
+ .num_resources = ARRAY_SIZE(sha1_md5_resources),
+ .resource = sha1_md5_resources,
+ };
+
+ static void omap_init_sha1_md5(void)
+ {
+ platform_device_register(&sha1_md5_device);
+ }
+ #else
+ static inline void omap_init_sha1_md5(void) { }
+ #endif
+
+ #if defined(CONFIG_HDQ_MASTER_OMAP) || defined(CONFIG_HDQ_MASTER_OMAP_MODULE)
+ #if defined(CONFIG_ARCH_OMAP2430) || defined(CONFIG_ARCH_OMAP3430)
+ #define OMAP_HDQ_BASE 0x480B2000
+ #endif
+ static struct resource omap_hdq_resources[] = {
+ {
+ .start = OMAP_HDQ_BASE,
+ .end = OMAP_HDQ_BASE + 0x1C,
+ .flags = IORESOURCE_MEM,
+ },
+ {
+ .start = INT_24XX_HDQ_IRQ,
+ .flags = IORESOURCE_IRQ,
+ },
+ };
+ static struct platform_device omap_hdq_dev = {
+ .name = "omap_hdq",
+ .id = 0,
+ .dev = {
+ .platform_data = NULL,
+ },
+ .num_resources = ARRAY_SIZE(omap_hdq_resources),
+ .resource = omap_hdq_resources,
+ };
+ static inline void omap_hdq_init(void)
+ {
+ (void) platform_device_register(&omap_hdq_dev);
+ }
+ #else
+ static inline void omap_hdq_init(void) {}
+ #endif
+
/*-------------------------------------------------------------------------*/
static int __init omap2_init_devices(void)
/* please keep these calls, and their implementations above,
* in alphabetical order so they're easier to sort through.
*/
- omap_init_i2c();
omap_init_mbox();
omap_init_mcspi();
+ omap_hdq_init();
omap_init_sti();
+ omap_init_sha1_md5();
return 0;
}
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
+ #undef DEBUG
+
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/err.h>
#include <linux/clk.h>
#include <linux/ioport.h>
#include <linux/spinlock.h>
+#include <linux/io.h>
+ #include <linux/module.h>
-#include <asm/io.h>
#include <asm/mach-types.h>
#include <mach/gpmc.h>
- #undef DEBUG
-
- #ifdef CONFIG_ARCH_OMAP2420
- #define GPMC_BASE 0x6800a000
- #endif
-
- #ifdef CONFIG_ARCH_OMAP2430
- #define GPMC_BASE 0x6E000000
- #endif
+ #include <mach/sdrc.h>
+ /* GPMC register offsets */
#define GPMC_REVISION 0x00
#define GPMC_SYSCONFIG 0x10
#define GPMC_SYSSTATUS 0x14
#define GPMC_CS0 0x60
#define GPMC_CS_SIZE 0x30
- #define GPMC_CS_NUM 8
#define GPMC_MEM_START 0x00000000
#define GPMC_MEM_END 0x3FFFFFFF
#define BOOT_ROM_SPACE 0x100000 /* 1MB */
static DEFINE_SPINLOCK(gpmc_mem_lock);
static unsigned gpmc_cs_map;
- static void __iomem *gpmc_base =
- (void __iomem *) IO_ADDRESS(GPMC_BASE);
- static void __iomem *gpmc_cs_base =
- (void __iomem *) IO_ADDRESS(GPMC_BASE) + GPMC_CS0;
+ static void __iomem *gpmc_base;
- static struct clk *gpmc_fck;
+ static struct clk *gpmc_l3_clk;
static void gpmc_write_reg(int idx, u32 val)
{
{
void __iomem *reg_addr;
- reg_addr = gpmc_cs_base + (cs * GPMC_CS_SIZE) + idx;
+ reg_addr = gpmc_base + GPMC_CS0 + (cs * GPMC_CS_SIZE) + idx;
__raw_writel(val, reg_addr);
}
u32 gpmc_cs_read_reg(int cs, int idx)
{
- return __raw_readl(gpmc_cs_base + (cs * GPMC_CS_SIZE) + idx);
+ void __iomem *reg_addr;
+
+ reg_addr = gpmc_base + GPMC_CS0 + (cs * GPMC_CS_SIZE) + idx;
+ return __raw_readl(reg_addr);
}
+ /* TODO: Add support for gpmc_fck to clock framework and use it */
unsigned long gpmc_get_fclk_period(void)
{
- /* In picoseconds */
- return 1000000000 / ((clk_get_rate(gpmc_fck)) / 1000);
+ unsigned long rate = clk_get_rate(gpmc_l3_clk);
+
+ if (rate == 0) {
+ printk(KERN_WARNING "gpmc_l3_clk not enabled\n");
+ return 0;
+ }
+
+ rate /= 1000;
+ rate = 1000000000 / rate; /* In picoseconds */
+
+ return rate;
}
unsigned int gpmc_ns_to_ticks(unsigned int time_ns)
return (time_ns * 1000 + tick_ps - 1) / tick_ps;
}
+ unsigned int gpmc_ticks_to_ns(unsigned int ticks)
+ {
+ return ticks * gpmc_get_fclk_period() / 1000;
+ }
+
unsigned int gpmc_round_ns_to_ticks(unsigned int time_ns)
{
unsigned long ticks = gpmc_ns_to_ticks(time_ns);
GPMC_SET_ONE(GPMC_CS_CONFIG5, 24, 27, page_burst_access);
+ if (cpu_is_omap34xx()) {
+ GPMC_SET_ONE(GPMC_CS_CONFIG6, 16, 19, wr_data_mux_bus);
+ GPMC_SET_ONE(GPMC_CS_CONFIG6, 24, 28, wr_access);
+ }
+
/* caller is expected to have initialized CONFIG1 to cover
* at least sync vs async
*/
spin_unlock(&gpmc_mem_lock);
return r;
}
+ EXPORT_SYMBOL(gpmc_cs_request);
void gpmc_cs_free(int cs)
{
gpmc_cs_set_reserved(cs, 0);
spin_unlock(&gpmc_mem_lock);
}
+ EXPORT_SYMBOL(gpmc_cs_free);
- void __init gpmc_mem_init(void)
+ static void __init gpmc_mem_init(void)
{
int cs;
unsigned long boot_rom_space = 0;
void __init gpmc_init(void)
{
u32 l;
+ char *ck;
+
+ if (cpu_is_omap24xx()) {
+ ck = "core_l3_ck";
+ if (cpu_is_omap2420())
+ l = OMAP2420_GPMC_BASE;
+ else
+ l = OMAP34XX_GPMC_BASE;
+ } else if (cpu_is_omap34xx()) {
+ ck = "gpmc_fck";
+ l = OMAP34XX_GPMC_BASE;
+ }
- gpmc_fck = clk_get(NULL, "gpmc_fck"); /* Always on ENABLE_ON_INIT */
- if (IS_ERR(gpmc_fck))
- WARN_ON(1);
- else
- clk_enable(gpmc_fck);
+ gpmc_l3_clk = clk_get(NULL, ck);
+ if (IS_ERR(gpmc_l3_clk)) {
+ printk(KERN_ERR "Could not get GPMC clock %s\n", ck);
+ return -ENODEV;
+ }
+
+ gpmc_base = ioremap(l, SZ_4K);
+ if (!gpmc_base) {
+ clk_put(gpmc_l3_clk);
+ printk(KERN_ERR "Could not get GPMC register memory\n");
+ return -ENOMEM;
+ }
+
+ BUG_ON(IS_ERR(gpmc_l3_clk));
l = gpmc_read_reg(GPMC_REVISION);
printk(KERN_INFO "GPMC revision %d.%d\n", (l >> 4) & 0x0f, l & 0x0f);
#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/init.h>
+#include <linux/io.h>
-#include <asm/io.h>
+#include <asm/cputype.h>
+ #include <mach/common.h>
#include <mach/control.h>
#include <mach/cpu.h>
- #if defined(CONFIG_ARCH_OMAP2420)
- #define TAP_BASE io_p2v(0x48014000)
- #elif defined(CONFIG_ARCH_OMAP2430)
- #define TAP_BASE io_p2v(0x4900A000)
- #elif defined(CONFIG_ARCH_OMAP34XX)
- #define TAP_BASE io_p2v(0x4830A000)
- #endif
+ static u32 class;
+ static void __iomem *tap_base;
+ static u16 tap_prod_id;
#define OMAP_TAP_IDCODE 0x0204
- #if defined(CONFIG_ARCH_OMAP34XX)
- #define OMAP_TAP_PROD_ID 0x0210
- #else
- #define OMAP_TAP_PROD_ID 0x0208
- #endif
-
#define OMAP_TAP_DIE_ID_0 0x0218
#define OMAP_TAP_DIE_ID_1 0x021C
#define OMAP_TAP_DIE_ID_2 0x0220
* it means its Cortex r0p0 which is 3430 ES1
*/
if ((((cpuid >> 4) & 0xFFF) == 0xC08) && ((cpuid & 0xF) == 0x0)) {
+
+ if (reg == tap_prod_id) {
+ regval = 0x000F00F0;
+ goto out;
+ }
+
switch (reg) {
case OMAP_TAP_IDCODE : regval = 0x0B7AE02F; break;
/* Making DevType as 0xF in ES1 to differ from ES2 */
- case OMAP_TAP_PROD_ID : regval = 0x000F00F0; break;
case OMAP_TAP_DIE_ID_0: regval = 0x01000000; break;
case OMAP_TAP_DIE_ID_1: regval = 0x1012d687; break;
case OMAP_TAP_DIE_ID_2: regval = 0x00000000; break;
case OMAP_TAP_DIE_ID_3: regval = 0x2d2c0000; break;
}
} else
- regval = __raw_readl(TAP_BASE + reg);
+ regval = __raw_readl(tap_base + reg);
+ out:
return regval;
}
u8 rev;
idcode = read_tap_reg(OMAP_TAP_IDCODE);
- prod_id = read_tap_reg(OMAP_TAP_PROD_ID);
+ prod_id = read_tap_reg(tap_prod_id);
hawkeye = (idcode >> 12) & 0xffff;
rev = (idcode >> 28) & 0x0f;
dev_type = (prod_id >> 16) & 0x0f;
}
+ void __init omap2_set_globals_tap(struct omap_globals *omap2_globals)
+ {
+ class = omap2_globals->class;
+ tap_base = omap2_globals->tap;
+
+ if (class == 0x3430)
+ tap_prod_id = 0x0210;
+ else
+ tap_prod_id = 0x0208;
+ }
* OMAP2 I/O mapping code
*
* Copyright (C) 2005 Nokia Corporation
- * Author: Juha Yrjölä <juha.yrjola@nokia.com>
- * Updated map desc to add 2430 support : <x0khasim@ti.com>
+ * Copyright (C) 2007 Texas Instruments
+ *
+ * Author:
+ * Juha Yrjola <juha.yrjola@nokia.com>
+ * Syed Khasim <x0khasim@ti.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/init.h>
+#include <linux/io.h>
#include <asm/tlb.h>
-#include <asm/io.h>
#include <asm/mach/map.h>
#include <mach/mux.h>
#include <mach/omapfb.h>
+ #include <mach/sram.h>
+
+ #include "memory.h"
+
+ #include "clock.h"
+
+ #include <mach/powerdomain.h>
+
+ #include "powerdomains.h"
- extern void omap_sram_init(void);
- extern int omap2_clk_init(void);
- extern void omap2_check_revision(void);
- extern void omap2_init_memory(void);
- extern void gpmc_init(void);
- extern void omapfb_reserve_sdram(void);
+ #include <mach/clockdomain.h>
+ #include "clockdomains.h"
/*
* The machine specific code may provide the extra mapping besides the
* default mapping provided here.
*/
- static struct map_desc omap2_io_desc[] __initdata = {
+
+ #ifdef CONFIG_ARCH_OMAP24XX
+ static struct map_desc omap24xx_io_desc[] __initdata = {
{
.virtual = L3_24XX_VIRT,
.pfn = __phys_to_pfn(L3_24XX_PHYS),
.type = MT_DEVICE
},
{
- .virtual = L4_24XX_VIRT,
- .pfn = __phys_to_pfn(L4_24XX_PHYS),
- .length = L4_24XX_SIZE,
- .type = MT_DEVICE
+ .virtual = L4_24XX_VIRT,
+ .pfn = __phys_to_pfn(L4_24XX_PHYS),
+ .length = L4_24XX_SIZE,
+ .type = MT_DEVICE
},
+ };
+
+ #ifdef CONFIG_ARCH_OMAP2420
+ static struct map_desc omap242x_io_desc[] __initdata = {
+ {
+ .virtual = DSP_MEM_24XX_VIRT,
+ .pfn = __phys_to_pfn(DSP_MEM_24XX_PHYS),
+ .length = DSP_MEM_24XX_SIZE,
+ .type = MT_DEVICE
+ },
+ {
+ .virtual = DSP_IPI_24XX_VIRT,
+ .pfn = __phys_to_pfn(DSP_IPI_24XX_PHYS),
+ .length = DSP_IPI_24XX_SIZE,
+ .type = MT_DEVICE
+ },
+ {
+ .virtual = DSP_MMU_24XX_VIRT,
+ .pfn = __phys_to_pfn(DSP_MMU_24XX_PHYS),
+ .length = DSP_MMU_24XX_SIZE,
+ .type = MT_DEVICE
+ },
+ };
+
+ #endif
+
#ifdef CONFIG_ARCH_OMAP2430
+ static struct map_desc omap243x_io_desc[] __initdata = {
{
.virtual = L4_WK_243X_VIRT,
.pfn = __phys_to_pfn(L4_WK_243X_PHYS),
.length = OMAP243X_GPMC_SIZE,
.type = MT_DEVICE
},
+ {
+ .virtual = OMAP243X_SDRC_VIRT,
+ .pfn = __phys_to_pfn(OMAP243X_SDRC_PHYS),
+ .length = OMAP243X_SDRC_SIZE,
+ .type = MT_DEVICE
+ },
+ {
+ .virtual = OMAP243X_SMS_VIRT,
+ .pfn = __phys_to_pfn(OMAP243X_SMS_PHYS),
+ .length = OMAP243X_SMS_SIZE,
+ .type = MT_DEVICE
+ },
+ };
+ #endif
#endif
+
+ #ifdef CONFIG_ARCH_OMAP34XX
+ static struct map_desc omap34xx_io_desc[] __initdata = {
{
- .virtual = DSP_MEM_24XX_VIRT,
- .pfn = __phys_to_pfn(DSP_MEM_24XX_PHYS),
- .length = DSP_MEM_24XX_SIZE,
+ .virtual = L3_34XX_VIRT,
+ .pfn = __phys_to_pfn(L3_34XX_PHYS),
+ .length = L3_34XX_SIZE,
.type = MT_DEVICE
},
{
- .virtual = DSP_IPI_24XX_VIRT,
- .pfn = __phys_to_pfn(DSP_IPI_24XX_PHYS),
- .length = DSP_IPI_24XX_SIZE,
+ .virtual = L4_34XX_VIRT,
+ .pfn = __phys_to_pfn(L4_34XX_PHYS),
+ .length = L4_34XX_SIZE,
.type = MT_DEVICE
},
{
- .virtual = DSP_MMU_24XX_VIRT,
- .pfn = __phys_to_pfn(DSP_MMU_24XX_PHYS),
- .length = DSP_MMU_24XX_SIZE,
+ .virtual = L4_WK_34XX_VIRT,
+ .pfn = __phys_to_pfn(L4_WK_34XX_PHYS),
+ .length = L4_WK_34XX_SIZE,
+ .type = MT_DEVICE
+ },
+ {
+ .virtual = OMAP34XX_GPMC_VIRT,
+ .pfn = __phys_to_pfn(OMAP34XX_GPMC_PHYS),
+ .length = OMAP34XX_GPMC_SIZE,
.type = MT_DEVICE
- }
+ },
+ {
+ .virtual = OMAP343X_SMS_VIRT,
+ .pfn = __phys_to_pfn(OMAP343X_SMS_PHYS),
+ .length = OMAP343X_SMS_SIZE,
+ .type = MT_DEVICE
+ },
+ {
+ .virtual = OMAP343X_SDRC_VIRT,
+ .pfn = __phys_to_pfn(OMAP343X_SDRC_PHYS),
+ .length = OMAP343X_SDRC_SIZE,
+ .type = MT_DEVICE
+ },
+ {
+ .virtual = L4_PER_34XX_VIRT,
+ .pfn = __phys_to_pfn(L4_PER_34XX_PHYS),
+ .length = L4_PER_34XX_SIZE,
+ .type = MT_DEVICE
+ },
+ {
+ .virtual = L4_EMU_34XX_VIRT,
+ .pfn = __phys_to_pfn(L4_EMU_34XX_PHYS),
+ .length = L4_EMU_34XX_SIZE,
+ .type = MT_DEVICE
+ },
};
+ #endif
void __init omap2_map_common_io(void)
{
- iotable_init(omap2_io_desc, ARRAY_SIZE(omap2_io_desc));
+ #if defined(CONFIG_ARCH_OMAP2420)
+ iotable_init(omap24xx_io_desc, ARRAY_SIZE(omap24xx_io_desc));
+ iotable_init(omap242x_io_desc, ARRAY_SIZE(omap242x_io_desc));
+ #endif
+
+ #if defined(CONFIG_ARCH_OMAP2430)
+ iotable_init(omap24xx_io_desc, ARRAY_SIZE(omap24xx_io_desc));
+ iotable_init(omap243x_io_desc, ARRAY_SIZE(omap243x_io_desc));
+ #endif
+
+ #if defined(CONFIG_ARCH_OMAP34XX)
+ iotable_init(omap34xx_io_desc, ARRAY_SIZE(omap34xx_io_desc));
+ #endif
/* Normally devicemaps_init() would flush caches and tlb after
* mdesc->map_io(), but we must also do it here because of the CPU
void __init omap2_init_common_hw(void)
{
omap2_mux_init();
+ pwrdm_init(powerdomains_omap);
+ clkdm_init(clockdomains_omap, clkdm_pwrdm_autodeps);
omap2_clk_init();
- /*
- * Need to Fix this for 2430
- */
- #ifndef CONFIG_ARCH_OMAP2430
omap2_init_memory();
- #endif
gpmc_init();
}
#include <linux/errno.h>
#include <linux/delay.h>
#include <linux/clk.h>
-
-#include <asm/io.h>
+#include <linux/io.h>
#include <mach/common.h>
#include <mach/clock.h>
return prev;
}
+ #if !defined(CONFIG_ARCH_OMAP2)
+ void omap2_sram_ddr_init(u32 *slow_dll_ctrl, u32 fast_dll_ctrl,
+ u32 base_cs, u32 force_unlock)
+ {
+ }
+ void omap2_sram_reprogram_sdrc(u32 perf_level, u32 dll_val,
+ u32 mem_type)
+ {
+ }
+ #endif
+
void omap2_init_memory_params(u32 force_lock_to_unlock_mode)
{
unsigned long dll_cnt;
{
u32 l;
+ if (!cpu_is_omap2420())
+ return;
+
l = sms_read_reg(SMS_SYSCONFIG);
l &= ~(0x3 << 3);
l |= (0x2 << 3);
/*
* linux/arch/arm/mach-omap2/mux.c
*
- * OMAP2 pin multiplexing configurations
+ * OMAP2 and OMAP3 pin multiplexing configurations
*
* Copyright (C) 2004 - 2008 Texas Instruments Inc.
* Copyright (C) 2003 - 2008 Nokia Corporation
*/
#include <linux/module.h>
#include <linux/init.h>
-#include <asm/system.h>
-#include <asm/io.h>
+#include <linux/io.h>
#include <linux/spinlock.h>
+#include <asm/system.h>
+
#include <mach/control.h>
#include <mach/mux.h>
#define OMAP24XX_PINS_SZ 0
#endif /* CONFIG_ARCH_OMAP24XX */
- #define OMAP24XX_PULL_ENA (1 << 3)
- #define OMAP24XX_PULL_UP (1 << 4)
+ #ifdef CONFIG_ARCH_OMAP34XX
+ static struct pin_config __initdata_or_module omap34xx_pins[] = {
+ /*
+ * Name, reg-offset,
+ * mux-mode | [active-mode | off-mode]
+ */
+
+ /* 34xx I2C */
+ MUX_CFG_34XX("K21_34XX_I2C1_SCL", 0x1ba,
+ OMAP34XX_MUX_MODE0 | OMAP34XX_PIN_INPUT_PULLUP)
+ MUX_CFG_34XX("J21_34XX_I2C1_SDA", 0x1bc,
+ OMAP34XX_MUX_MODE0 | OMAP34XX_PIN_INPUT_PULLUP)
+ MUX_CFG_34XX("AF15_34XX_I2C2_SCL", 0x1be,
+ OMAP34XX_MUX_MODE0 | OMAP34XX_PIN_INPUT_PULLUP)
+ MUX_CFG_34XX("AE15_34XX_I2C2_SDA", 0x1c0,
+ OMAP34XX_MUX_MODE0 | OMAP34XX_PIN_INPUT_PULLUP)
+ MUX_CFG_34XX("AF14_34XX_I2C3_SCL", 0x1c2,
+ OMAP34XX_MUX_MODE0 | OMAP34XX_PIN_INPUT_PULLUP)
+ MUX_CFG_34XX("AG14_34XX_I2C3_SDA", 0x1c4,
+ OMAP34XX_MUX_MODE0 | OMAP34XX_PIN_INPUT_PULLUP)
+ MUX_CFG_34XX("AD26_34XX_I2C4_SCL", 0xa00,
+ OMAP34XX_MUX_MODE0 | OMAP34XX_PIN_INPUT_PULLUP)
+ MUX_CFG_34XX("AE26_34XX_I2C4_SDA", 0xa02,
+ OMAP34XX_MUX_MODE0 | OMAP34XX_PIN_INPUT_PULLUP)
+
+ /* PHY - HSUSB: 12-pin ULPI PHY: Port 1*/
+ MUX_CFG_34XX("Y8_3430_USB1HS_PHY_CLK", 0x5da,
+ OMAP34XX_MUX_MODE3 | OMAP34XX_PIN_OUTPUT)
+ MUX_CFG_34XX("Y9_3430_USB1HS_PHY_STP", 0x5d8,
+ OMAP34XX_MUX_MODE3 | OMAP34XX_PIN_OUTPUT)
+ MUX_CFG_34XX("AA14_3430_USB1HS_PHY_DIR", 0x5ec,
+ OMAP34XX_MUX_MODE3 | OMAP34XX_PIN_INPUT_PULLDOWN)
+ MUX_CFG_34XX("AA11_3430_USB1HS_PHY_NXT", 0x5ee,
+ OMAP34XX_MUX_MODE3 | OMAP34XX_PIN_INPUT_PULLDOWN)
+ MUX_CFG_34XX("W13_3430_USB1HS_PHY_D0", 0x5dc,
+ OMAP34XX_MUX_MODE3 | OMAP34XX_PIN_INPUT_PULLDOWN)
+ MUX_CFG_34XX("W12_3430_USB1HS_PHY_D1", 0x5de,
+ OMAP34XX_MUX_MODE3 | OMAP34XX_PIN_INPUT_PULLDOWN)
+ MUX_CFG_34XX("W11_3430_USB1HS_PHY_D2", 0x5e0,
+ OMAP34XX_MUX_MODE3 | OMAP34XX_PIN_INPUT_PULLDOWN)
+ MUX_CFG_34XX("Y11_3430_USB1HS_PHY_D3", 0x5ea,
+ OMAP34XX_MUX_MODE3 | OMAP34XX_PIN_INPUT_PULLDOWN)
+ MUX_CFG_34XX("W9_3430_USB1HS_PHY_D4", 0x5e4,
+ OMAP34XX_MUX_MODE3 | OMAP34XX_PIN_INPUT_PULLDOWN)
+ MUX_CFG_34XX("Y12_3430_USB1HS_PHY_D5", 0x5e6,
+ OMAP34XX_MUX_MODE3 | OMAP34XX_PIN_INPUT_PULLDOWN)
+ MUX_CFG_34XX("W8_3430_USB1HS_PHY_D6", 0x5e8,
+ OMAP34XX_MUX_MODE3 | OMAP34XX_PIN_INPUT_PULLDOWN)
+ MUX_CFG_34XX("Y13_3430_USB1HS_PHY_D7", 0x5e2,
+ OMAP34XX_MUX_MODE3 | OMAP34XX_PIN_INPUT_PULLDOWN)
+
+ /* PHY - HSUSB: 12-pin ULPI PHY: Port 2*/
+ MUX_CFG_34XX("AA8_3430_USB2HS_PHY_CLK", 0x5f0,
+ OMAP34XX_MUX_MODE3 | OMAP34XX_PIN_OUTPUT)
+ MUX_CFG_34XX("AA10_3430_USB2HS_PHY_STP", 0x5f2,
+ OMAP34XX_MUX_MODE3 | OMAP34XX_PIN_OUTPUT)
+ MUX_CFG_34XX("AA9_3430_USB2HS_PHY_DIR", 0x5f4,
+ OMAP34XX_MUX_MODE3 | OMAP34XX_PIN_INPUT_PULLDOWN)
+ MUX_CFG_34XX("AB11_3430_USB2HS_PHY_NXT", 0x5f6,
+ OMAP34XX_MUX_MODE3 | OMAP34XX_PIN_INPUT_PULLDOWN)
+ MUX_CFG_34XX("AB10_3430_USB2HS_PHY_D0", 0x5f8,
+ OMAP34XX_MUX_MODE3 | OMAP34XX_PIN_INPUT_PULLDOWN)
+ MUX_CFG_34XX("AB9_3430_USB2HS_PHY_D1", 0x5fa,
+ OMAP34XX_MUX_MODE3 | OMAP34XX_PIN_INPUT_PULLDOWN)
+ MUX_CFG_34XX("W3_3430_USB2HS_PHY_D2", 0x1d4,
+ OMAP34XX_MUX_MODE3 | OMAP34XX_PIN_INPUT_PULLDOWN)
+ MUX_CFG_34XX("T4_3430_USB2HS_PHY_D3", 0x1de,
+ OMAP34XX_MUX_MODE3 | OMAP34XX_PIN_INPUT_PULLDOWN)
+ MUX_CFG_34XX("T3_3430_USB2HS_PHY_D4", 0x1d8,
+ OMAP34XX_MUX_MODE3 | OMAP34XX_PIN_INPUT_PULLDOWN)
+ MUX_CFG_34XX("R3_3430_USB2HS_PHY_D5", 0x1da,
+ OMAP34XX_MUX_MODE3 | OMAP34XX_PIN_INPUT_PULLDOWN)
+ MUX_CFG_34XX("R4_3430_USB2HS_PHY_D6", 0x1dc,
+ OMAP34XX_MUX_MODE3 | OMAP34XX_PIN_INPUT_PULLDOWN)
+ MUX_CFG_34XX("T2_3430_USB2HS_PHY_D7", 0x1d6,
+ OMAP34XX_MUX_MODE3 | OMAP34XX_PIN_INPUT_PULLDOWN)
+
+ /* TLL - HSUSB: 12-pin TLL Port 1*/
+ MUX_CFG_34XX("Y8_3430_USB1HS_TLL_CLK", 0x5da,
+ OMAP34XX_MUX_MODE6 | OMAP34XX_PIN_INPUT_PULLDOWN)
+ MUX_CFG_34XX("Y9_3430_USB1HS_TLL_STP", 0x5d8,
+ OMAP34XX_MUX_MODE6 | OMAP34XX_PIN_INPUT_PULLUP)
+ MUX_CFG_34XX("AA14_3430_USB1HS_TLL_DIR", 0x5ec,
+ OMAP34XX_MUX_MODE6 | OMAP34XX_PIN_INPUT_PULLDOWN)
+ MUX_CFG_34XX("AA11_3430_USB1HS_TLL_NXT", 0x5ee,
+ OMAP34XX_MUX_MODE6 | OMAP34XX_PIN_INPUT_PULLDOWN)
+ MUX_CFG_34XX("W13_3430_USB1HS_TLL_D0", 0x5dc,
+ OMAP34XX_MUX_MODE6 | OMAP34XX_PIN_INPUT_PULLDOWN)
+ MUX_CFG_34XX("W12_3430_USB1HS_TLL_D1", 0x5de,
+ OMAP34XX_MUX_MODE6 | OMAP34XX_PIN_INPUT_PULLDOWN)
+ MUX_CFG_34XX("W11_3430_USB1HS_TLL_D2", 0x5e0,
+ OMAP34XX_MUX_MODE6 | OMAP34XX_PIN_INPUT_PULLDOWN)
+ MUX_CFG_34XX("Y11_3430_USB1HS_TLL_D3", 0x5ea,
+ OMAP34XX_MUX_MODE6 | OMAP34XX_PIN_INPUT_PULLDOWN)
+ MUX_CFG_34XX("W9_3430_USB1HS_TLL_D4", 0x5e4,
+ OMAP34XX_MUX_MODE6 | OMAP34XX_PIN_INPUT_PULLDOWN)
+ MUX_CFG_34XX("Y12_3430_USB1HS_TLL_D5", 0x5e6,
+ OMAP34XX_MUX_MODE6 | OMAP34XX_PIN_INPUT_PULLDOWN)
+ MUX_CFG_34XX("W8_3430_USB1HS_TLL_D6", 0x5e8,
+ OMAP34XX_MUX_MODE6 | OMAP34XX_PIN_INPUT_PULLDOWN)
+ MUX_CFG_34XX("Y13_3430_USB1HS_TLL_D7", 0x5e2,
+ OMAP34XX_MUX_MODE6 | OMAP34XX_PIN_INPUT_PULLDOWN)
+
+ /* TLL - HSUSB: 12-pin TLL Port 2*/
+ MUX_CFG_34XX("AA8_3430_USB2HS_TLL_CLK", 0x5f0,
+ OMAP34XX_MUX_MODE6 | OMAP34XX_PIN_INPUT_PULLDOWN)
+ MUX_CFG_34XX("AA10_3430_USB2HS_TLL_STP", 0x5f2,
+ OMAP34XX_MUX_MODE6 | OMAP34XX_PIN_INPUT_PULLUP)
+ MUX_CFG_34XX("AA9_3430_USB2HS_TLL_DIR", 0x5f4,
+ OMAP34XX_MUX_MODE6 | OMAP34XX_PIN_INPUT_PULLDOWN)
+ MUX_CFG_34XX("AB11_3430_USB2HS_TLL_NXT", 0x5f6,
+ OMAP34XX_MUX_MODE6 | OMAP34XX_PIN_INPUT_PULLDOWN)
+ MUX_CFG_34XX("AB10_3430_USB2HS_TLL_D0", 0x5f8,
+ OMAP34XX_MUX_MODE6 | OMAP34XX_PIN_INPUT_PULLDOWN)
+ MUX_CFG_34XX("AB9_3430_USB2HS_TLL_D1", 0x5fa,
+ OMAP34XX_MUX_MODE6 | OMAP34XX_PIN_INPUT_PULLDOWN)
+ MUX_CFG_34XX("W3_3430_USB2HS_TLL_D2", 0x1d4,
+ OMAP34XX_MUX_MODE2 | OMAP34XX_PIN_INPUT_PULLDOWN)
+ MUX_CFG_34XX("T4_3430_USB2HS_TLL_D3", 0x1de,
+ OMAP34XX_MUX_MODE2 | OMAP34XX_PIN_INPUT_PULLDOWN)
+ MUX_CFG_34XX("T3_3430_USB2HS_TLL_D4", 0x1d8,
+ OMAP34XX_MUX_MODE2 | OMAP34XX_PIN_INPUT_PULLDOWN)
+ MUX_CFG_34XX("R3_3430_USB2HS_TLL_D5", 0x1da,
+ OMAP34XX_MUX_MODE2 | OMAP34XX_PIN_INPUT_PULLDOWN)
+ MUX_CFG_34XX("R4_3430_USB2HS_TLL_D6", 0x1dc,
+ OMAP34XX_MUX_MODE2 | OMAP34XX_PIN_INPUT_PULLDOWN)
+ MUX_CFG_34XX("T2_3430_USB2HS_TLL_D7", 0x1d6,
+ OMAP34XX_MUX_MODE2 | OMAP34XX_PIN_INPUT_PULLDOWN)
+
+ /* TLL - HSUSB: 12-pin TLL Port 3*/
+ MUX_CFG_34XX("AA6_3430_USB3HS_TLL_CLK", 0x180,
+ OMAP34XX_MUX_MODE5 | OMAP34XX_PIN_INPUT_PULLDOWN)
+ MUX_CFG_34XX("AB3_3430_USB3HS_TLL_STP", 0x166,
+ OMAP34XX_MUX_MODE5 | OMAP34XX_PIN_INPUT_PULLUP)
+ MUX_CFG_34XX("AA3_3430_USB3HS_TLL_DIR", 0x168,
+ OMAP34XX_MUX_MODE5 | OMAP34XX_PIN_INPUT_PULLDOWN)
+ MUX_CFG_34XX("Y3_3430_USB3HS_TLL_NXT", 0x16a,
+ OMAP34XX_MUX_MODE5 | OMAP34XX_PIN_INPUT_PULLDOWN)
+ MUX_CFG_34XX("AA5_3430_USB3HS_TLL_D0", 0x186,
+ OMAP34XX_MUX_MODE5 | OMAP34XX_PIN_INPUT_PULLDOWN)
+ MUX_CFG_34XX("Y4_3430_USB3HS_TLL_D1", 0x184,
+ OMAP34XX_MUX_MODE5 | OMAP34XX_PIN_INPUT_PULLDOWN)
+ MUX_CFG_34XX("Y5_3430_USB3HS_TLL_D2", 0x188,
+ OMAP34XX_MUX_MODE5 | OMAP34XX_PIN_INPUT_PULLDOWN)
+ MUX_CFG_34XX("W5_3430_USB3HS_TLL_D3", 0x18a,
+ OMAP34XX_MUX_MODE5 | OMAP34XX_PIN_INPUT_PULLDOWN)
+ MUX_CFG_34XX("AB12_3430_USB3HS_TLL_D4", 0x16c,
+ OMAP34XX_MUX_MODE5 | OMAP34XX_PIN_INPUT_PULLDOWN)
+ MUX_CFG_34XX("AB13_3430_USB3HS_TLL_D5", 0x16e,
+ OMAP34XX_MUX_MODE5 | OMAP34XX_PIN_INPUT_PULLDOWN)
+ MUX_CFG_34XX("AA13_3430_USB3HS_TLL_D6", 0x170,
+ OMAP34XX_MUX_MODE5 | OMAP34XX_PIN_INPUT_PULLDOWN)
+ MUX_CFG_34XX("AA12_3430_USB3HS_TLL_D7", 0x172,
+ OMAP34XX_MUX_MODE5 | OMAP34XX_PIN_INPUT_PULLDOWN)
+
+ /* PHY FSUSB: FS Serial for Port 1 (multiple PHY modes supported) */
+ MUX_CFG_34XX("AF10_3430_USB1FS_PHY_MM1_RXDP", 0x5d8,
+ OMAP34XX_MUX_MODE5 | OMAP34XX_PIN_INPUT_PULLDOWN)
+ MUX_CFG_34XX("AG9_3430_USB1FS_PHY_MM1_RXDM", 0x5ee,
+ OMAP34XX_MUX_MODE5 | OMAP34XX_PIN_INPUT_PULLDOWN)
+ MUX_CFG_34XX("W13_3430_USB1FS_PHY_MM1_RXRCV", 0x5dc,
+ OMAP34XX_MUX_MODE5 | OMAP34XX_PIN_INPUT_PULLDOWN)
+ MUX_CFG_34XX("W12_3430_USB1FS_PHY_MM1_TXSE0", 0x5de,
+ OMAP34XX_MUX_MODE5 | OMAP34XX_PIN_INPUT_PULLDOWN)
+ MUX_CFG_34XX("W11_3430_USB1FS_PHY_MM1_TXDAT", 0x5e0,
+ OMAP34XX_MUX_MODE5 | OMAP34XX_PIN_INPUT_PULLDOWN)
+ MUX_CFG_34XX("Y11_3430_USB1FS_PHY_MM1_TXEN_N", 0x5ea,
+ OMAP34XX_MUX_MODE5 | OMAP34XX_PIN_OUTPUT)
+
+ /* PHY FSUSB: FS Serial for Port 2 (multiple PHY modes supported) */
+ MUX_CFG_34XX("AF7_3430_USB2FS_PHY_MM2_RXDP", 0x5f2,
+ OMAP34XX_MUX_MODE5 | OMAP34XX_PIN_INPUT_PULLDOWN)
+ MUX_CFG_34XX("AH7_3430_USB2FS_PHY_MM2_RXDM", 0x5f6,
+ OMAP34XX_MUX_MODE5 | OMAP34XX_PIN_INPUT_PULLDOWN)
+ MUX_CFG_34XX("AB10_3430_USB2FS_PHY_MM2_RXRCV", 0x5f8,
+ OMAP34XX_MUX_MODE5 | OMAP34XX_PIN_INPUT_PULLDOWN)
+ MUX_CFG_34XX("AB9_3430_USB2FS_PHY_MM2_TXSE0", 0x5fa,
+ OMAP34XX_MUX_MODE5 | OMAP34XX_PIN_INPUT_PULLDOWN)
+ MUX_CFG_34XX("W3_3430_USB2FS_PHY_MM2_TXDAT", 0x1d4,
+ OMAP34XX_MUX_MODE5 | OMAP34XX_PIN_INPUT_PULLDOWN)
+ MUX_CFG_34XX("T4_3430_USB2FS_PHY_MM2_TXEN_N", 0x1de,
+ OMAP34XX_MUX_MODE5 | OMAP34XX_PIN_OUTPUT)
+
+ /* PHY FSUSB: FS Serial for Port 3 (multiple PHY modes supported) */
+ MUX_CFG_34XX("AH3_3430_USB3FS_PHY_MM3_RXDP", 0x166,
+ OMAP34XX_MUX_MODE6 | OMAP34XX_PIN_INPUT_PULLDOWN)
+ MUX_CFG_34XX("AE3_3430_USB3FS_PHY_MM3_RXDM", 0x16a,
+ OMAP34XX_MUX_MODE6 | OMAP34XX_PIN_INPUT_PULLDOWN)
+ MUX_CFG_34XX("AD1_3430_USB3FS_PHY_MM3_RXRCV", 0x186,
+ OMAP34XX_MUX_MODE6 | OMAP34XX_PIN_INPUT_PULLDOWN)
+ MUX_CFG_34XX("AE1_3430_USB3FS_PHY_MM3_TXSE0", 0x184,
+ OMAP34XX_MUX_MODE6 | OMAP34XX_PIN_INPUT_PULLDOWN)
+ MUX_CFG_34XX("AD2_3430_USB3FS_PHY_MM3_TXDAT", 0x188,
+ OMAP34XX_MUX_MODE6 | OMAP34XX_PIN_INPUT_PULLDOWN)
+ MUX_CFG_34XX("AC1_3430_USB3FS_PHY_MM3_TXEN_N", 0x18a,
+ OMAP34XX_MUX_MODE6 | OMAP34XX_PIN_OUTPUT)
+
+ };
+
+ #define OMAP34XX_PINS_SZ ARRAY_SIZE(omap34xx_pins)
+
+ #else
+ #define omap34xx_pins NULL
+ #define OMAP34XX_PINS_SZ 0
+ #endif /* CONFIG_ARCH_OMAP34XX */
#if defined(CONFIG_OMAP_MUX_DEBUG) || defined(CONFIG_OMAP_MUX_WARNINGS)
- void __init_or_module omap2_cfg_debug(const struct pin_config *cfg, u8 reg)
+ static void __init_or_module omap2_cfg_debug(const struct pin_config *cfg, u16 reg)
{
u16 orig;
u8 warn = 0, debug = 0;
- orig = omap_ctrl_readb(cfg->mux_reg);
+ if (cpu_is_omap24xx())
+ orig = omap_ctrl_readb(cfg->mux_reg);
+ else
+ orig = omap_ctrl_readw(cfg->mux_reg);
#ifdef CONFIG_OMAP_MUX_DEBUG
debug = cfg->debug;
spin_lock_irqsave(&mux_spin_lock, flags);
reg |= cfg->mask & 0x7;
if (cfg->pull_val)
- reg |= OMAP24XX_PULL_ENA;
+ reg |= OMAP2_PULL_ENA;
if (cfg->pu_pd_val)
- reg |= OMAP24XX_PULL_UP;
+ reg |= OMAP2_PULL_UP;
omap2_cfg_debug(cfg, reg);
omap_ctrl_writeb(reg, cfg->mux_reg);
spin_unlock_irqrestore(&mux_spin_lock, flags);
return 0;
}
#else
- #define omap24xx_cfg_reg 0
+ #define omap24xx_cfg_reg NULL
+ #endif
+
+ #ifdef CONFIG_ARCH_OMAP34XX
+ static int __init_or_module omap34xx_cfg_reg(const struct pin_config *cfg)
+ {
+ static DEFINE_SPINLOCK(mux_spin_lock);
+ unsigned long flags;
+ u16 reg = 0;
+
+ spin_lock_irqsave(&mux_spin_lock, flags);
+ reg |= cfg->mux_val;
+ omap2_cfg_debug(cfg, reg);
+ omap_ctrl_writew(reg, cfg->mux_reg);
+ spin_unlock_irqrestore(&mux_spin_lock, flags);
+
+ return 0;
+ }
+ #else
+ #define omap34xx_cfg_reg NULL
#endif
int __init omap2_mux_init(void)
arch_mux_cfg.pins = omap24xx_pins;
arch_mux_cfg.size = OMAP24XX_PINS_SZ;
arch_mux_cfg.cfg_reg = omap24xx_cfg_reg;
+ } else if (cpu_is_omap34xx()) {
+ arch_mux_cfg.pins = omap34xx_pins;
+ arch_mux_cfg.size = OMAP34XX_PINS_SZ;
+ arch_mux_cfg.cfg_reg = omap34xx_cfg_reg;
}
return omap_mux_register(&arch_mux_cfg);
*
* OMAP2 serial support.
*
- * Copyright (C) 2005 Nokia Corporation
+ * Copyright (C) 2005-2008 Nokia Corporation
* Author: Paul Mundt <paul.mundt@nokia.com>
*
* Based off of arch/arm/mach-omap/omap1/serial.c
#include <linux/serial_8250.h>
#include <linux/serial_reg.h>
#include <linux/clk.h>
-
-#include <asm/io.h>
+#include <linux/io.h>
#include <mach/common.h>
#include <mach/board.h>
- static struct clk * uart1_ick = NULL;
- static struct clk * uart1_fck = NULL;
- static struct clk * uart2_ick = NULL;
- static struct clk * uart2_fck = NULL;
- static struct clk * uart3_ick = NULL;
- static struct clk * uart3_fck = NULL;
+ static struct clk *uart_ick[OMAP_MAX_NR_PORTS];
+ static struct clk *uart_fck[OMAP_MAX_NR_PORTS];
static struct plat_serial8250_port serial_platform_data[] = {
{
- .membase = (char *)IO_ADDRESS(OMAP_UART1_BASE),
- .mapbase = (unsigned long)OMAP_UART1_BASE,
+ .membase = IO_ADDRESS(OMAP_UART1_BASE),
+ .mapbase = OMAP_UART1_BASE,
.irq = 72,
.flags = UPF_BOOT_AUTOCONF,
.iotype = UPIO_MEM,
.regshift = 2,
- .uartclk = OMAP16XX_BASE_BAUD * 16,
+ .uartclk = OMAP24XX_BASE_BAUD * 16,
}, {
- .membase = (char *)IO_ADDRESS(OMAP_UART2_BASE),
- .mapbase = (unsigned long)OMAP_UART2_BASE,
+ .membase = IO_ADDRESS(OMAP_UART2_BASE),
+ .mapbase = OMAP_UART2_BASE,
.irq = 73,
.flags = UPF_BOOT_AUTOCONF,
.iotype = UPIO_MEM,
.regshift = 2,
- .uartclk = OMAP16XX_BASE_BAUD * 16,
+ .uartclk = OMAP24XX_BASE_BAUD * 16,
}, {
- .membase = (char *)IO_ADDRESS(OMAP_UART3_BASE),
- .mapbase = (unsigned long)OMAP_UART3_BASE,
+ .membase = IO_ADDRESS(OMAP_UART3_BASE),
+ .mapbase = OMAP_UART3_BASE,
.irq = 74,
.flags = UPF_BOOT_AUTOCONF,
.iotype = UPIO_MEM,
.regshift = 2,
- .uartclk = OMAP16XX_BASE_BAUD * 16,
+ .uartclk = OMAP24XX_BASE_BAUD * 16,
}, {
.flags = 0
}
int value)
{
offset <<= p->regshift;
- __raw_writeb(value, (unsigned long)(p->membase + offset));
+ __raw_writeb(value, p->membase + offset);
}
/*
serial_write_reg(p, UART_OMAP_SYSC, (0x02 << 3) | (1 << 2) | (1 << 0));
}
- void __init omap_serial_init()
+ void omap_serial_enable_clocks(int enable)
+ {
+ int i;
+ for (i = 0; i < OMAP_MAX_NR_PORTS; i++) {
+ if (uart_ick[i] && uart_fck[i]) {
+ if (enable) {
+ clk_enable(uart_ick[i]);
+ clk_enable(uart_fck[i]);
+ } else {
+ clk_disable(uart_ick[i]);
+ clk_disable(uart_fck[i]);
+ }
+ }
+ }
+ }
+
+ void __init omap_serial_init(void)
{
int i;
const struct omap_uart_config *info;
+ char name[16];
/*
* Make sure the serial ports are muxed on at this point.
* if not needed.
*/
- info = omap_get_config(OMAP_TAG_UART,
- struct omap_uart_config);
+ info = omap_get_config(OMAP_TAG_UART, struct omap_uart_config);
if (info == NULL)
return;
struct plat_serial8250_port *p = serial_platform_data + i;
if (!(info->enabled_uarts & (1 << i))) {
- p->membase = 0;
+ p->membase = NULL;
p->mapbase = 0;
continue;
}
- switch (i) {
- case 0:
- uart1_ick = clk_get(NULL, "uart1_ick");
- if (IS_ERR(uart1_ick))
- printk("Could not get uart1_ick\n");
- else {
- clk_enable(uart1_ick);
- }
-
- uart1_fck = clk_get(NULL, "uart1_fck");
- if (IS_ERR(uart1_fck))
- printk("Could not get uart1_fck\n");
- else {
- clk_enable(uart1_fck);
- }
- break;
- case 1:
- uart2_ick = clk_get(NULL, "uart2_ick");
- if (IS_ERR(uart2_ick))
- printk("Could not get uart2_ick\n");
- else {
- clk_enable(uart2_ick);
- }
-
- uart2_fck = clk_get(NULL, "uart2_fck");
- if (IS_ERR(uart2_fck))
- printk("Could not get uart2_fck\n");
- else {
- clk_enable(uart2_fck);
- }
- break;
- case 2:
- uart3_ick = clk_get(NULL, "uart3_ick");
- if (IS_ERR(uart3_ick))
- printk("Could not get uart3_ick\n");
- else {
- clk_enable(uart3_ick);
- }
-
- uart3_fck = clk_get(NULL, "uart3_fck");
- if (IS_ERR(uart3_fck))
- printk("Could not get uart3_fck\n");
- else {
- clk_enable(uart3_fck);
- }
- break;
- }
+ sprintf(name, "uart%d_ick", i+1);
+ uart_ick[i] = clk_get(NULL, name);
+ if (IS_ERR(uart_ick[i])) {
+ printk(KERN_ERR "Could not get uart%d_ick\n", i+1);
+ uart_ick[i] = NULL;
+ } else
+ clk_enable(uart_ick[i]);
+
+ sprintf(name, "uart%d_fck", i+1);
+ uart_fck[i] = clk_get(NULL, name);
+ if (IS_ERR(uart_fck[i])) {
+ printk(KERN_ERR "Could not get uart%d_fck\n", i+1);
+ uart_fck[i] = NULL;
+ } else
+ clk_enable(uart_fck[i]);
omap_serial_reset(p);
}
# ARMv7
config CPU_V7
bool "Support ARM V7 processor"
- depends on ARCH_INTEGRATOR || MACH_REALVIEW_EB
+ depends on ARCH_INTEGRATOR || MACH_REALVIEW_EB || ARCH_OMAP3
select CPU_32v6K
select CPU_32v7
select CPU_ABRT_EV7
help
This option enables the Feroceon L2 cache controller.
+config CACHE_FEROCEON_L2_WRITETHROUGH
+ bool "Force Feroceon L2 cache write through"
+ depends on CACHE_FEROCEON_L2
+ default n
+ help
+ Say Y here to use the Feroceon L2 cache in writethrough mode.
+ Unless you specifically require this, say N for writeback mode.
+
config CACHE_L2X0
bool "Enable the L2x0 outer cache controller"
depends on REALVIEW_EB_ARM11MP || MACH_REALVIEW_PB11MP || MACH_REALVIEW_PB1176
#include <linux/serial_8250.h>
#include <linux/serial_reg.h>
#include <linux/clk.h>
+#include <linux/io.h>
#include <mach/hardware.h>
#include <asm/system.h>
#include <asm/pgtable.h>
#include <asm/mach/map.h>
-#include <asm/io.h>
#include <asm/setup.h>
#include <mach/common.h>
static void __init __omap2_set_globals(void)
{
+ omap2_set_globals_tap(omap2_globals);
omap2_set_globals_memory(omap2_globals);
omap2_set_globals_control(omap2_globals);
omap2_set_globals_prcm(omap2_globals);
#if defined(CONFIG_ARCH_OMAP2420)
static struct omap_globals omap242x_globals = {
- .tap = (__force void __iomem *)OMAP2_IO_ADDRESS(0x48014000),
- .sdrc = (__force void __iomem *)OMAP2_IO_ADDRESS(OMAP2420_SDRC_BASE),
- .sms = (__force void __iomem *)OMAP2_IO_ADDRESS(OMAP2420_SMS_BASE),
- .ctrl = (__force void __iomem *)OMAP2_IO_ADDRESS(OMAP2420_CTRL_BASE),
- .prm = (__force void __iomem *)OMAP2_IO_ADDRESS(OMAP2420_PRM_BASE),
- .cm = (__force void __iomem *)OMAP2_IO_ADDRESS(OMAP2420_CM_BASE),
+ .class = OMAP242X_CLASS,
+ .tap = OMAP2_IO_ADDRESS(0x48014000),
+ .sdrc = OMAP2_IO_ADDRESS(OMAP2420_SDRC_BASE),
+ .sms = OMAP2_IO_ADDRESS(OMAP2420_SMS_BASE),
+ .ctrl = OMAP2_IO_ADDRESS(OMAP2420_CTRL_BASE),
+ .prm = OMAP2_IO_ADDRESS(OMAP2420_PRM_BASE),
+ .cm = OMAP2_IO_ADDRESS(OMAP2420_CM_BASE),
};
void __init omap2_set_globals_242x(void)
#if defined(CONFIG_ARCH_OMAP2430)
static struct omap_globals omap243x_globals = {
- .tap = (__force void __iomem *)OMAP2_IO_ADDRESS(0x4900a000),
- .sdrc = (__force void __iomem *)OMAP2_IO_ADDRESS(OMAP243X_SDRC_BASE),
- .sms = (__force void __iomem *)OMAP2_IO_ADDRESS(OMAP243X_SMS_BASE),
- .ctrl = (__force void __iomem *)OMAP2_IO_ADDRESS(OMAP243X_CTRL_BASE),
- .prm = (__force void __iomem *)OMAP2_IO_ADDRESS(OMAP2430_PRM_BASE),
- .cm = (__force void __iomem *)OMAP2_IO_ADDRESS(OMAP2430_CM_BASE),
+ .class = OMAP243X_CLASS,
+ .tap = OMAP2_IO_ADDRESS(0x4900a000),
+ .sdrc = OMAP2_IO_ADDRESS(OMAP243X_SDRC_BASE),
+ .sms = OMAP2_IO_ADDRESS(OMAP243X_SMS_BASE),
+ .ctrl = OMAP2_IO_ADDRESS(OMAP243X_CTRL_BASE),
+ .prm = OMAP2_IO_ADDRESS(OMAP2430_PRM_BASE),
+ .cm = OMAP2_IO_ADDRESS(OMAP2430_CM_BASE),
};
void __init omap2_set_globals_243x(void)
#if defined(CONFIG_ARCH_OMAP3430)
static struct omap_globals omap343x_globals = {
- .tap = (__force void __iomem *)OMAP2_IO_ADDRESS(0x4830A000),
- .sdrc = (__force void __iomem *)OMAP2_IO_ADDRESS(OMAP343X_SDRC_BASE),
- .sms = (__force void __iomem *)OMAP2_IO_ADDRESS(OMAP343X_SMS_BASE),
- .ctrl = (__force void __iomem *)OMAP2_IO_ADDRESS(OMAP343X_CTRL_BASE),
- .prm = (__force void __iomem *)OMAP2_IO_ADDRESS(OMAP3430_PRM_BASE),
- .cm = (__force void __iomem *)OMAP2_IO_ADDRESS(OMAP3430_CM_BASE),
+ .class = OMAP343X_CLASS,
+ .tap = OMAP2_IO_ADDRESS(0x4830A000),
+ .sdrc = OMAP2_IO_ADDRESS(OMAP343X_SDRC_BASE),
+ .sms = OMAP2_IO_ADDRESS(OMAP343X_SMS_BASE),
+ .ctrl = OMAP2_IO_ADDRESS(OMAP343X_CTRL_BASE),
+ .prm = OMAP2_IO_ADDRESS(OMAP3430_PRM_BASE),
+ .cm = OMAP2_IO_ADDRESS(OMAP3430_CM_BASE),
};
void __init omap2_set_globals_343x(void)
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/platform_device.h>
+#include <linux/io.h>
#include <mach/hardware.h>
-#include <asm/io.h>
#include <asm/mach-types.h>
#include <asm/mach/map.h>
#include <mach/tc.h>
+ #include <mach/control.h>
#include <mach/board.h>
+#include <mach/mmc.h>
#include <mach/mux.h>
#include <mach/gpio.h>
#include <mach/menelaus.h>
#include <mach/mcbsp.h>
+ #include <mach/dsp_common.h>
#if defined(CONFIG_OMAP_DSP) || defined(CONFIG_OMAP_DSP_MODULE)
- #include "../plat-omap/dsp/dsp_common.h"
-
static struct dsp_platform_data dsp_pdata = {
.kdev_list = LIST_HEAD_INIT(dsp_pdata.kdev_list),
};
{
static DEFINE_MUTEX(dsp_pdata_lock);
- mutex_init(&kdev->lock);
+ spin_lock_init(&kdev->lock);
mutex_lock(&dsp_pdata_lock);
list_add_tail(&kdev->entry, &dsp_pdata.kdev_list);
static void omap_init_kp(void)
{
+ /* 2430 and 34xx keypad is on TWL4030 */
+ if (cpu_is_omap2430() || cpu_is_omap34xx())
+ return;
+
if (machine_is_omap_h2() || machine_is_omap_h3()) {
omap_cfg_reg(F18_1610_KBC0);
omap_cfg_reg(D20_1610_KBC1);
{
int i;
- if (size > OMAP_MAX_MCBSP_COUNT) {
- printk(KERN_WARNING "Registered too many McBSPs platform_data."
- " Using maximum (%d) available.\n",
- OMAP_MAX_MCBSP_COUNT);
- size = OMAP_MAX_MCBSP_COUNT;
- }
-
omap_mcbsp_devices = kzalloc(size * sizeof(struct platform_device *),
GFP_KERNEL);
if (!omap_mcbsp_devices) {
/*-------------------------------------------------------------------------*/
-#if defined(CONFIG_MMC_OMAP) || defined(CONFIG_MMC_OMAP_MODULE)
+#if defined(CONFIG_MMC_OMAP) || defined(CONFIG_MMC_OMAP_MODULE) || \
+ defined(CONFIG_MMC_OMAP_HS) || defined(CONFIG_MMC_OMAP_HS_MODULE)
-#ifdef CONFIG_ARCH_OMAP24XX
+#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
#define OMAP_MMC1_BASE 0x4809c000
-#define OMAP_MMC1_INT INT_24XX_MMC_IRQ
+#define OMAP_MMC1_END (OMAP_MMC1_BASE + 0x1fc)
+#define OMAP_MMC1_INT INT_24XX_MMC_IRQ
+
+#define OMAP_MMC2_BASE 0x480b4000
+#define OMAP_MMC2_END (OMAP_MMC2_BASE + 0x1fc)
+#define OMAP_MMC2_INT INT_24XX_MMC2_IRQ
+
#else
+
#define OMAP_MMC1_BASE 0xfffb7800
+#define OMAP_MMC1_END (OMAP_MMC1_BASE + 0x7f)
#define OMAP_MMC1_INT INT_MMC
-#endif
+
#define OMAP_MMC2_BASE 0xfffb7c00 /* omap16xx only */
+#define OMAP_MMC2_END (OMAP_MMC2_BASE + 0x7f)
+#define OMAP_MMC2_INT INT_1610_MMC2
-static struct omap_mmc_conf mmc1_conf;
+#endif
+
+static struct omap_mmc_platform_data mmc1_data;
static u64 mmc1_dmamask = 0xffffffff;
static struct resource mmc1_resources[] = {
{
.start = OMAP_MMC1_BASE,
- .end = OMAP_MMC1_BASE + 0x7f,
+ .end = OMAP_MMC1_END,
.flags = IORESOURCE_MEM,
},
{
.id = 1,
.dev = {
.dma_mask = &mmc1_dmamask,
- .platform_data = &mmc1_conf,
+ .platform_data = &mmc1_data,
},
.num_resources = ARRAY_SIZE(mmc1_resources),
.resource = mmc1_resources,
};
-#ifdef CONFIG_ARCH_OMAP16XX
+#if defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP2430) || \
+ defined(CONFIG_ARCH_OMAP34XX)
-static struct omap_mmc_conf mmc2_conf;
+static struct omap_mmc_platform_data mmc2_data;
static u64 mmc2_dmamask = 0xffffffff;
static struct resource mmc2_resources[] = {
{
.start = OMAP_MMC2_BASE,
- .end = OMAP_MMC2_BASE + 0x7f,
+ .end = OMAP_MMC2_END,
.flags = IORESOURCE_MEM,
},
{
- .start = INT_1610_MMC2,
+ .start = OMAP_MMC2_INT,
.flags = IORESOURCE_IRQ,
},
};
.id = 2,
.dev = {
.dma_mask = &mmc2_dmamask,
- .platform_data = &mmc2_conf,
+ .platform_data = &mmc2_data,
},
.num_resources = ARRAY_SIZE(mmc2_resources),
.resource = mmc2_resources,
};
#endif
-static void __init omap_init_mmc(void)
+static inline void omap_init_mmc_conf(const struct omap_mmc_config *mmc_conf)
{
- const struct omap_mmc_config *mmc_conf;
- const struct omap_mmc_conf *mmc;
-
- /* NOTE: assumes MMC was never (wrongly) enabled */
- mmc_conf = omap_get_config(OMAP_TAG_MMC, struct omap_mmc_config);
- if (!mmc_conf)
+ if (cpu_is_omap2430() || cpu_is_omap34xx())
return;
- /* block 1 is always available and has just one pinout option */
- mmc = &mmc_conf->mmc[0];
- if (mmc->enabled) {
+ if (mmc_conf->mmc[0].enabled) {
if (cpu_is_omap24xx()) {
omap_cfg_reg(H18_24XX_MMC_CMD);
omap_cfg_reg(H15_24XX_MMC_CLKI);
omap_cfg_reg(P20_1710_MMC_DATDIR0);
}
}
- if (mmc->wire4) {
+ if (mmc_conf->mmc[0].wire4) {
if (cpu_is_omap24xx()) {
omap_cfg_reg(H14_24XX_MMC_DAT1);
omap_cfg_reg(E19_24XX_MMC_DAT2);
} else {
omap_cfg_reg(MMC_DAT1);
/* NOTE: DAT2 can be on W10 (here) or M15 */
- if (!mmc->nomux)
+ if (!mmc_conf->mmc[0].nomux)
omap_cfg_reg(MMC_DAT2);
omap_cfg_reg(MMC_DAT3);
}
}
- mmc1_conf = *mmc;
- (void) platform_device_register(&mmc_omap_device1);
+#if defined(CONFIG_ARCH_OMAP2420)
+ if (mmc_conf->mmc[0].internal_clock) {
+ /*
+ * Use internal loop-back in MMC/SDIO
+ * Module Input Clock selection
+ */
+ if (cpu_is_omap24xx()) {
+ u32 v = omap_ctrl_readl(OMAP2_CONTROL_DEVCONF0);
+ v |= (1 << 24); /* not used in 243x */
+ omap_ctrl_writel(v, OMAP2_CONTROL_DEVCONF0);
+ }
+ }
+#endif
}
#ifdef CONFIG_ARCH_OMAP16XX
/* block 2 is on newer chips, and has many pinout options */
- mmc = &mmc_conf->mmc[1];
- if (mmc->enabled) {
- if (!mmc->nomux) {
+ if (mmc_conf->mmc[1].enabled) {
+ if (!mmc_conf->mmc[1].nomux) {
omap_cfg_reg(Y8_1610_MMC2_CMD);
omap_cfg_reg(Y10_1610_MMC2_CLK);
omap_cfg_reg(R18_1610_MMC2_CLKIN);
omap_cfg_reg(W8_1610_MMC2_DAT0);
- if (mmc->wire4) {
+ if (mmc_conf->mmc[1].wire4) {
omap_cfg_reg(V8_1610_MMC2_DAT1);
omap_cfg_reg(W15_1610_MMC2_DAT2);
omap_cfg_reg(R10_1610_MMC2_DAT3);
if (cpu_is_omap1710())
omap_writel(omap_readl(MOD_CONF_CTRL_1) | (1 << 24),
MOD_CONF_CTRL_1);
- mmc2_conf = *mmc;
+ }
+#endif
+}
+
+static void __init omap_init_mmc(void)
+{
+ const struct omap_mmc_config *mmc_conf;
+
+ /* NOTE: assumes MMC was never (wrongly) enabled */
+ mmc_conf = omap_get_config(OMAP_TAG_MMC, struct omap_mmc_config);
+ if (!mmc_conf)
+ return;
+
+ omap_init_mmc_conf(mmc_conf);
+
+ if (mmc_conf->mmc[0].enabled) {
+ mmc1_data.conf = mmc_conf->mmc[0];
+ (void) platform_device_register(&mmc_omap_device1);
+ }
+
+#if defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP2430) || \
+ defined(CONFIG_ARCH_OMAP34XX)
+ if (mmc_conf->mmc[1].enabled) {
+ mmc2_data.conf = mmc_conf->mmc[1];
(void) platform_device_register(&mmc_omap_device2);
}
#endif
- return;
}
+
+void omap_set_mmc_info(int host, const struct omap_mmc_platform_data *info)
+{
+ switch (host) {
+ case 1:
+ mmc1_data = *info;
+ break;
+#if defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP2430) || \
+ defined(CONFIG_ARCH_OMAP34XX)
+ case 2:
+ mmc2_data = *info;
+ break;
+#endif
+ default:
+ BUG();
+ }
+}
+
#else
static inline void omap_init_mmc(void) {}
+void omap_set_mmc_info(int host, const struct omap_mmc_platform_data *info) {}
#endif
/*-------------------------------------------------------------------------*/
*/
static int __init omap_init_devices(void)
{
- /*
- * Need to enable relevant once for 2430 SDP
- */
- #ifndef CONFIG_MACH_OMAP_2430SDP
/* please keep these calls, and their implementations above,
* in alphabetical order so they're easier to sort through.
*/
omap_init_uwire();
omap_init_wdt();
omap_init_rng();
- #endif
return 0;
}
arch_initcall(omap_init_devices);
#include <linux/list.h>
#include <linux/clk.h>
#include <linux/delay.h>
+#include <linux/io.h>
#include <mach/hardware.h>
#include <mach/dmtimer.h>
-#include <asm/io.h>
#include <mach/irqs.h>
/* register offsets */
for (i = 0; i < dm_timer_count; i++) {
timer = &dm_timers[i];
- timer->io_base = (void __iomem *)io_p2v(timer->phys_base);
+ timer->io_base = IO_ADDRESS(timer->phys_base);
#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
if (cpu_class_is_omap2()) {
char clk_name[16];
#include <linux/sysdev.h>
#include <linux/err.h>
#include <linux/clk.h>
+#include <linux/io.h>
#include <mach/hardware.h>
#include <asm/irq.h>
#include <mach/gpio.h>
#include <asm/mach/irq.h>
-#include <asm/io.h>
-
/*
* OMAP1510 GPIO registers
*/
- #define OMAP1510_GPIO_BASE (void __iomem *)0xfffce000
+ #define OMAP1510_GPIO_BASE IO_ADDRESS(0xfffce000)
#define OMAP1510_GPIO_DATA_INPUT 0x00
#define OMAP1510_GPIO_DATA_OUTPUT 0x04
#define OMAP1510_GPIO_DIR_CONTROL 0x08
/*
* OMAP1610 specific GPIO registers
*/
- #define OMAP1610_GPIO1_BASE (void __iomem *)0xfffbe400
- #define OMAP1610_GPIO2_BASE (void __iomem *)0xfffbec00
- #define OMAP1610_GPIO3_BASE (void __iomem *)0xfffbb400
- #define OMAP1610_GPIO4_BASE (void __iomem *)0xfffbbc00
+ #define OMAP1610_GPIO1_BASE IO_ADDRESS(0xfffbe400)
+ #define OMAP1610_GPIO2_BASE IO_ADDRESS(0xfffbec00)
+ #define OMAP1610_GPIO3_BASE IO_ADDRESS(0xfffbb400)
+ #define OMAP1610_GPIO4_BASE IO_ADDRESS(0xfffbbc00)
#define OMAP1610_GPIO_REVISION 0x0000
#define OMAP1610_GPIO_SYSCONFIG 0x0010
#define OMAP1610_GPIO_SYSSTATUS 0x0014
/*
* OMAP730 specific GPIO registers
*/
- #define OMAP730_GPIO1_BASE (void __iomem *)0xfffbc000
- #define OMAP730_GPIO2_BASE (void __iomem *)0xfffbc800
- #define OMAP730_GPIO3_BASE (void __iomem *)0xfffbd000
- #define OMAP730_GPIO4_BASE (void __iomem *)0xfffbd800
- #define OMAP730_GPIO5_BASE (void __iomem *)0xfffbe000
- #define OMAP730_GPIO6_BASE (void __iomem *)0xfffbe800
+ #define OMAP730_GPIO1_BASE IO_ADDRESS(0xfffbc000)
+ #define OMAP730_GPIO2_BASE IO_ADDRESS(0xfffbc800)
+ #define OMAP730_GPIO3_BASE IO_ADDRESS(0xfffbd000)
+ #define OMAP730_GPIO4_BASE IO_ADDRESS(0xfffbd800)
+ #define OMAP730_GPIO5_BASE IO_ADDRESS(0xfffbe000)
+ #define OMAP730_GPIO6_BASE IO_ADDRESS(0xfffbe800)
#define OMAP730_GPIO_DATA_INPUT 0x00
#define OMAP730_GPIO_DATA_OUTPUT 0x04
#define OMAP730_GPIO_DIR_CONTROL 0x08
/*
* omap24xx specific GPIO registers
*/
- #define OMAP242X_GPIO1_BASE (void __iomem *)0x48018000
- #define OMAP242X_GPIO2_BASE (void __iomem *)0x4801a000
- #define OMAP242X_GPIO3_BASE (void __iomem *)0x4801c000
- #define OMAP242X_GPIO4_BASE (void __iomem *)0x4801e000
+ #define OMAP242X_GPIO1_BASE IO_ADDRESS(0x48018000)
+ #define OMAP242X_GPIO2_BASE IO_ADDRESS(0x4801a000)
+ #define OMAP242X_GPIO3_BASE IO_ADDRESS(0x4801c000)
+ #define OMAP242X_GPIO4_BASE IO_ADDRESS(0x4801e000)
- #define OMAP243X_GPIO1_BASE (void __iomem *)0x4900C000
- #define OMAP243X_GPIO2_BASE (void __iomem *)0x4900E000
- #define OMAP243X_GPIO3_BASE (void __iomem *)0x49010000
- #define OMAP243X_GPIO4_BASE (void __iomem *)0x49012000
- #define OMAP243X_GPIO5_BASE (void __iomem *)0x480B6000
+ #define OMAP243X_GPIO1_BASE IO_ADDRESS(0x4900C000)
+ #define OMAP243X_GPIO2_BASE IO_ADDRESS(0x4900E000)
+ #define OMAP243X_GPIO3_BASE IO_ADDRESS(0x49010000)
+ #define OMAP243X_GPIO4_BASE IO_ADDRESS(0x49012000)
+ #define OMAP243X_GPIO5_BASE IO_ADDRESS(0x480B6000)
#define OMAP24XX_GPIO_REVISION 0x0000
#define OMAP24XX_GPIO_SYSCONFIG 0x0010
* omap34xx specific GPIO registers
*/
- #define OMAP34XX_GPIO1_BASE (void __iomem *)0x48310000
- #define OMAP34XX_GPIO2_BASE (void __iomem *)0x49050000
- #define OMAP34XX_GPIO3_BASE (void __iomem *)0x49052000
- #define OMAP34XX_GPIO4_BASE (void __iomem *)0x49054000
- #define OMAP34XX_GPIO5_BASE (void __iomem *)0x49056000
- #define OMAP34XX_GPIO6_BASE (void __iomem *)0x49058000
+ #define OMAP34XX_GPIO1_BASE IO_ADDRESS(0x48310000)
+ #define OMAP34XX_GPIO2_BASE IO_ADDRESS(0x49050000)
+ #define OMAP34XX_GPIO3_BASE IO_ADDRESS(0x49052000)
+ #define OMAP34XX_GPIO4_BASE IO_ADDRESS(0x49054000)
+ #define OMAP34XX_GPIO5_BASE IO_ADDRESS(0x49056000)
+ #define OMAP34XX_GPIO6_BASE IO_ADDRESS(0x49058000)
+ #define OMAP_MPUIO_VBASE IO_ADDRESS(OMAP_MPUIO_BASE)
struct gpio_bank {
void __iomem *base;
#ifdef CONFIG_ARCH_OMAP16XX
static struct gpio_bank gpio_bank_1610[5] = {
- { OMAP_MPUIO_BASE, INT_MPUIO, IH_MPUIO_BASE, METHOD_MPUIO},
+ { OMAP_MPUIO_VBASE, INT_MPUIO, IH_MPUIO_BASE, METHOD_MPUIO},
{ OMAP1610_GPIO1_BASE, INT_GPIO_BANK1, IH_GPIO_BASE, METHOD_GPIO_1610 },
{ OMAP1610_GPIO2_BASE, INT_1610_GPIO_BANK2, IH_GPIO_BASE + 16, METHOD_GPIO_1610 },
{ OMAP1610_GPIO3_BASE, INT_1610_GPIO_BANK3, IH_GPIO_BASE + 32, METHOD_GPIO_1610 },
#ifdef CONFIG_ARCH_OMAP15XX
static struct gpio_bank gpio_bank_1510[2] = {
- { OMAP_MPUIO_BASE, INT_MPUIO, IH_MPUIO_BASE, METHOD_MPUIO },
+ { OMAP_MPUIO_VBASE, INT_MPUIO, IH_MPUIO_BASE, METHOD_MPUIO },
{ OMAP1510_GPIO_BASE, INT_GPIO_BANK1, IH_GPIO_BASE, METHOD_GPIO_1510 }
};
#endif
#ifdef CONFIG_ARCH_OMAP730
static struct gpio_bank gpio_bank_730[7] = {
- { OMAP_MPUIO_BASE, INT_730_MPUIO, IH_MPUIO_BASE, METHOD_MPUIO },
+ { OMAP_MPUIO_VBASE, INT_730_MPUIO, IH_MPUIO_BASE, METHOD_MPUIO },
{ OMAP730_GPIO1_BASE, INT_730_GPIO_BANK1, IH_GPIO_BASE, METHOD_GPIO_730 },
{ OMAP730_GPIO2_BASE, INT_730_GPIO_BANK2, IH_GPIO_BASE + 32, METHOD_GPIO_730 },
{ OMAP730_GPIO3_BASE, INT_730_GPIO_BANK3, IH_GPIO_BASE + 64, METHOD_GPIO_730 },
gpio_irq = bank->virtual_irq_start;
for (; isr != 0; isr >>= 1, gpio_irq++) {
- struct irq_desc *d;
-
if (!(isr & 1))
continue;
- d = irq_desc + gpio_irq;
- desc_handle_irq(gpio_irq, d);
+ generic_handle_irq(gpio_irq);
}
}
/* if bank has any level sensitive GPIO pin interrupt
gpio_bank_count = 5;
gpio_bank = gpio_bank_1610;
- rev = omap_readw(gpio_bank[1].base + OMAP1610_GPIO_REVISION);
+ rev = __raw_readw(gpio_bank[1].base + OMAP1610_GPIO_REVISION);
printk(KERN_INFO "OMAP GPIO hardware version %d.%d\n",
(rev >> 4) & 0x0f, rev & 0x0f);
}
gpio_bank_count = 4;
gpio_bank = gpio_bank_242x;
- rev = omap_readl(gpio_bank[0].base + OMAP24XX_GPIO_REVISION);
+ rev = __raw_readl(gpio_bank[0].base + OMAP24XX_GPIO_REVISION);
printk(KERN_INFO "OMAP242x GPIO hardware version %d.%d\n",
(rev >> 4) & 0x0f, rev & 0x0f);
}
gpio_bank_count = 5;
gpio_bank = gpio_bank_243x;
- rev = omap_readl(gpio_bank[0].base + OMAP24XX_GPIO_REVISION);
+ rev = __raw_readl(gpio_bank[0].base + OMAP24XX_GPIO_REVISION);
printk(KERN_INFO "OMAP243x GPIO hardware version %d.%d\n",
(rev >> 4) & 0x0f, rev & 0x0f);
}
gpio_bank_count = OMAP34XX_NR_GPIOS;
gpio_bank = gpio_bank_34xx;
- rev = omap_readl(gpio_bank[0].base + OMAP24XX_GPIO_REVISION);
+ rev = __raw_readl(gpio_bank[0].base + OMAP24XX_GPIO_REVISION);
printk(KERN_INFO "OMAP34xx GPIO hardware version %d.%d\n",
(rev >> 4) & 0x0f, rev & 0x0f);
}
int j, gpio_count = 16;
bank = &gpio_bank[i];
- bank->base = IO_ADDRESS(bank->base);
spin_lock_init(&bank->lock);
if (bank_is_mpuio(bank))
- omap_writew(0xFFFF, OMAP_MPUIO_BASE + OMAP_MPUIO_GPIO_MASKIT);
+ __raw_writew(0xffff, bank->base + OMAP_MPUIO_GPIO_MASKIT);
if (cpu_is_omap15xx() && bank->method == METHOD_GPIO_1510) {
__raw_writew(0xffff, bank->base + OMAP1510_GPIO_INT_MASK);
__raw_writew(0x0000, bank->base + OMAP1510_GPIO_INT_STATUS);
#ifndef __ASM_ARCH_OMAP_GPIO_H
#define __ASM_ARCH_OMAP_GPIO_H
+#include <linux/io.h>
#include <mach/irqs.h>
-#include <asm/io.h>
- #define OMAP_MPUIO_BASE (void __iomem *)0xfffb5000
+ #define OMAP_MPUIO_BASE 0xfffb5000
#ifdef CONFIG_ARCH_OMAP730
#define OMAP_MPUIO_INPUT_LATCH 0x00
extern void omap_set_gpio_direction(int gpio, int is_input);
extern void omap_set_gpio_dataout(int gpio, int enable);
extern int omap_get_gpio_datain(int gpio);
+ extern void omap2_gpio_prepare_for_retention(void);
+ extern void omap2_gpio_resume_after_retention(void);
extern void omap_set_gpio_debounce(int gpio, int enable);
extern void omap_set_gpio_debounce_time(int gpio, int enable);
#define INT_UART2 (15 + IH2_BASE)
#define INT_BT_MCSI1TX (16 + IH2_BASE)
#define INT_BT_MCSI1RX (17 + IH2_BASE)
+ #define INT_SOSSI_MATCH (19 + IH2_BASE)
#define INT_USB_W2FC (20 + IH2_BASE)
#define INT_1WIRE (21 + IH2_BASE)
#define INT_OS_TIMER (22 + IH2_BASE)
#define INT_1610_DMA_CH14 (61 + IH2_BASE)
#define INT_1610_DMA_CH15 (62 + IH2_BASE)
#define INT_1610_NAND (63 + IH2_BASE)
+ #define INT_1610_SHA1MD5 (91 + IH2_BASE)
/*
* OMAP-730 specific IRQ numbers for interrupt handler 2
#define INT_24XX_GPTIMER10 46
#define INT_24XX_GPTIMER11 47
#define INT_24XX_GPTIMER12 48
+ #define INT_24XX_SHA1MD5 51
+ #define INT_24XX_MCBSP4_IRQ_TX 54
+ #define INT_24XX_MCBSP4_IRQ_RX 55
#define INT_24XX_I2C1_IRQ 56
#define INT_24XX_I2C2_IRQ 57
+ #define INT_24XX_HDQ_IRQ 58
#define INT_24XX_MCBSP1_IRQ_TX 59
#define INT_24XX_MCBSP1_IRQ_RX 60
#define INT_24XX_MCBSP2_IRQ_TX 62
#define INT_24XX_MCBSP2_IRQ_RX 63
+ #define INT_24XX_SPI1_IRQ 65
+ #define INT_24XX_SPI2_IRQ 66
#define INT_24XX_UART1_IRQ 72
#define INT_24XX_UART2_IRQ 73
#define INT_24XX_UART3_IRQ 74
#define INT_24XX_USB_IRQ_HGEN 78
#define INT_24XX_USB_IRQ_HSOF 79
#define INT_24XX_USB_IRQ_OTG 80
+ #define INT_24XX_MCBSP5_IRQ_TX 81
+ #define INT_24XX_MCBSP5_IRQ_RX 82
#define INT_24XX_MMC_IRQ 83
+ #define INT_24XX_MMC2_IRQ 86
+ #define INT_24XX_MCBSP3_IRQ_TX 89
+ #define INT_24XX_MCBSP3_IRQ_RX 90
+ #define INT_24XX_SPI3_IRQ 91
+
+ #define INT_243X_MCBSP2_IRQ 16
+ #define INT_243X_MCBSP3_IRQ 17
+ #define INT_243X_MCBSP4_IRQ 18
+ #define INT_243X_MCBSP5_IRQ 19
+ #define INT_243X_MCBSP1_IRQ 64
+ #define INT_243X_HS_USB_MC 92
+ #define INT_243X_HS_USB_DMA 93
+ #define INT_243X_CARKIT_IRQ 94
+
+ #define INT_34XX_BENCH_MPU_EMUL 3
+ #define INT_34XX_ST_MCBSP2_IRQ 4
+ #define INT_34XX_ST_MCBSP3_IRQ 5
+ #define INT_34XX_SSM_ABORT_IRQ 6
+ #define INT_34XX_SYS_NIRQ 7
+ #define INT_34XX_D2D_FW_IRQ 8
+ #define INT_34XX_PRCM_MPU_IRQ 11
+ #define INT_34XX_MCBSP1_IRQ 16
+ #define INT_34XX_MCBSP2_IRQ 17
+ #define INT_34XX_MCBSP3_IRQ 22
+ #define INT_34XX_MCBSP4_IRQ 23
+ #define INT_34XX_CAM_IRQ 24
+ #define INT_34XX_MCBSP5_IRQ 27
+ #define INT_34XX_GPIO_BANK1 29
+ #define INT_34XX_GPIO_BANK2 30
+ #define INT_34XX_GPIO_BANK3 31
+ #define INT_34XX_GPIO_BANK4 32
+ #define INT_34XX_GPIO_BANK5 33
+ #define INT_34XX_GPIO_BANK6 34
+ #define INT_34XX_USIM_IRQ 35
+ #define INT_34XX_WDT3_IRQ 36
+ #define INT_34XX_SPI4_IRQ 48
+ #define INT_34XX_SHA1MD52_IRQ 49
+ #define INT_34XX_FPKA_READY_IRQ 50
+ #define INT_34XX_SHA1MD51_IRQ 51
+ #define INT_34XX_RNG_IRQ 52
+ #define INT_34XX_I2C3_IRQ 61
+ #define INT_34XX_FPKA_ERROR_IRQ 64
+ #define INT_34XX_PBIAS_IRQ 75
+ #define INT_34XX_OHCI_IRQ 76
+ #define INT_34XX_EHCI_IRQ 77
+ #define INT_34XX_TLL_IRQ 78
+ #define INT_34XX_PARTHASH_IRQ 79
+ #define INT_34XX_MMC3_IRQ 94
+ #define INT_34XX_GPT12_IRQ 95
+#define INT_34XX_BENCH_MPU_EMUL 3
+
/* Max. 128 level 2 IRQs (OMAP1610), 192 GPIOs (OMAP730) and
* 16 MPUIO lines */
#define OMAP_MAX_GPIO_LINES 192
#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/init.h>
+#include <linux/io.h>
#include <asm/tlb.h>
-#include <asm/io.h>
#include <asm/cacheflush.h>
#include <asm/mach/map.h>
#define omap1_sram_init() do {} while (0)
#endif
- #if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
+ #if defined(CONFIG_ARCH_OMAP2)
static void (*_omap2_sram_ddr_init)(u32 *slow_dll_ctrl, u32 fast_dll_ctrl,
u32 base_cs, u32 force_unlock);
#ifdef CONFIG_ARCH_OMAP3
- static u32 (*_omap2_sram_reprogram_gpmc)(u32 perf_level);
- u32 omap2_sram_reprogram_gpmc(u32 perf_level)
- {
- if (!_omap2_sram_reprogram_gpmc)
- omap_sram_error();
-
- return _omap2_sram_reprogram_gpmc(perf_level);
- }
-
- static u32 (*_omap2_sram_configure_core_dpll)(u32 m, u32 n,
- u32 freqsel, u32 m2);
- u32 omap2_sram_configure_core_dpll(u32 m, u32 n, u32 freqsel, u32 m2)
+ static u32 (*_omap3_sram_configure_core_dpll)(u32 sdrc_rfr_ctrl,
+ u32 sdrc_actim_ctrla,
+ u32 sdrc_actim_ctrlb,
+ u32 m2);
+ u32 omap3_configure_core_dpll(u32 sdrc_rfr_ctrl, u32 sdrc_actim_ctrla,
+ u32 sdrc_actim_ctrlb, u32 m2)
{
- if (!_omap2_sram_configure_core_dpll)
+ if (!_omap3_sram_configure_core_dpll)
omap_sram_error();
- return _omap2_sram_configure_core_dpll(m, n, freqsel, m2);
+ return _omap3_sram_configure_core_dpll(sdrc_rfr_ctrl,
+ sdrc_actim_ctrla,
+ sdrc_actim_ctrlb, m2);
}
/* REVISIT: Should this be same as omap34xx_sram_init() after off-idle? */
{
omap_sram_ceil = omap_sram_base + omap_sram_size;
- _omap2_sram_reprogram_gpmc = omap_sram_push(omap34xx_sram_reprogram_gpmc,
- omap34xx_sram_reprogram_gpmc_sz);
-
- _omap2_sram_configure_core_dpll =
- omap_sram_push(omap34xx_sram_configure_core_dpll,
- omap34xx_sram_configure_core_dpll_sz);
+ _omap3_sram_configure_core_dpll =
+ omap_sram_push(omap3_sram_configure_core_dpll,
+ omap3_sram_configure_core_dpll_sz);
}
int __init omap34xx_sram_init(void)
{
- _omap2_sram_ddr_init = omap_sram_push(omap34xx_sram_ddr_init,
- omap34xx_sram_ddr_init_sz);
-
- _omap2_sram_reprogram_sdrc = omap_sram_push(omap34xx_sram_reprogram_sdrc,
- omap34xx_sram_reprogram_sdrc_sz);
-
- _omap2_set_prcm = omap_sram_push(omap34xx_sram_set_prcm,
- omap34xx_sram_set_prcm_sz);
-
- _omap2_sram_reprogram_gpmc = omap_sram_push(omap34xx_sram_reprogram_gpmc,
- omap34xx_sram_reprogram_gpmc_sz);
-
- _omap2_sram_configure_core_dpll =
- omap_sram_push(omap34xx_sram_configure_core_dpll,
- omap34xx_sram_configure_core_dpll_sz);
+ _omap3_sram_configure_core_dpll =
+ omap_sram_push(omap3_sram_configure_core_dpll,
+ omap3_sram_configure_core_dpll_sz);
return 0;
}
projects / profile / ivi / kernel-x86-ivi.git / commitdiff