XWAY SoCs for booting from NOR flash. The U-Boot image needs to
be swapped if a flash programmer is used.
+- ARM options:
+ CONFIG_SYS_EXCEPTION_VECTORS_HIGH
+
+ Select high exception vectors of the ARM core, e.g., do not
+ clear the V bit of the c1 register of CP15.
+
- Linux Kernel Interface:
CONFIG_CLOCKS_IN_MHZ
* disable MMU and D cache, and enable I cache
*/
mrc p15, 0, r0, c1, c0, 0
- bic r0, r0, #0x00002300 /* clear bits 13, 9:8 (--V- --RS) */
+ bic r0, r0, #0x00000300 /* clear bits 9:8 (---- --RS) */
bic r0, r0, #0x00000087 /* clear bits 7, 2:0 (B--- -CAM) */
+#ifdef CONFIG_SYS_EXCEPTION_VECTORS_HIGH
+ orr r0, r0, #0x00002000 /* set bit 13 (--V- ----) */
+#else
+ bic r0, r0, #0x00002000 /* clear bit 13 (--V- ----) */
+#endif
orr r0, r0, #0x00000002 /* set bit 2 (A) Align */
orr r0, r0, #0x00001000 /* set bit 12 (I) I-Cache */
mcr p15, 0, r0, c1, c0, 0
#define CONFIG_ARM926EJS /* arm926ejs CPU core */
#define CONFIG_SOC_DA8XX /* TI DA8xx SoC */
#define CONFIG_SOC_DA850 /* TI DA850 SoC */
+#define CONFIG_SYS_EXCEPTION_VECTORS_HIGH
#define CONFIG_SYS_CLK_FREQ clk_get(DAVINCI_ARM_CLKID)
#define CONFIG_SYS_OSCIN_FREQ 24000000
#define CONFIG_SYS_TIMERBASE DAVINCI_TIMER0_BASE
#define CONFIG_ARM926EJS /* arm926ejs CPU core */
#define CONFIG_SOC_DA8XX /* TI DA8xx SoC */
#define CONFIG_SOC_DA850 /* TI DA850 SoC */
+#define CONFIG_SYS_EXCEPTION_VECTORS_HIGH
#define CONFIG_SYS_CLK_FREQ clk_get(DAVINCI_ARM_CLKID)
#define CONFIG_SYS_OSCIN_FREQ 24000000
#define CONFIG_SYS_TIMERBASE DAVINCI_TIMER0_BASE
#define CONFIG_ARM926EJS /* arm926ejs CPU core */
#define CONFIG_SOC_DA8XX /* TI DA8xx SoC */
#define CONFIG_SOC_DA850 /* TI DA850 SoC */
+#define CONFIG_SYS_EXCEPTION_VECTORS_HIGH
#define CONFIG_SYS_CLK_FREQ clk_get(DAVINCI_ARM_CLKID)
#define CONFIG_SYS_OSCIN_FREQ 24000000
#define CONFIG_SYS_TIMERBASE DAVINCI_TIMER0_BASE