typedef cl_buffer (cl_buffer_get_buffer_from_libva_cb)(cl_context ctx, unsigned int bo_name, size_t *sz);
extern cl_buffer_get_buffer_from_libva_cb *cl_buffer_get_buffer_from_libva;
-typedef cl_buffer (cl_buffer_get_image_from_libva_cb)(cl_context ctx, unsigned int bo_name, struct _cl_mem_image *image, unsigned int offset);
+typedef cl_buffer (cl_buffer_get_image_from_libva_cb)(cl_context ctx, unsigned int bo_name, struct _cl_mem_image *image);
extern cl_buffer_get_image_from_libva_cb *cl_buffer_get_image_from_libva;
/* Unref a buffer and destroy it if no more ref */
image = cl_mem_image(mem);
- mem->bo = cl_buffer_get_image_from_libva(ctx, bo_name, image, offset);
+ mem->bo = cl_buffer_get_image_from_libva(ctx, bo_name, image);
image->w = width;
image->h = height;
cl_buffer intel_share_image_from_libva(cl_context ctx,
unsigned int bo_name,
- struct _cl_mem_image *image,
- unsigned int offset)
+ struct _cl_mem_image *image)
{
drm_intel_bo *intel_bo;
uint32_t intel_tiling, intel_swizzle_mode;
intel_bo = intel_driver_share_buffer((intel_driver_t *)ctx->drv, "shared from libva", bo_name);
- intel_bo->offset += offset;
drm_intel_bo_get_tiling(intel_bo, &intel_tiling, &intel_swizzle_mode);
image->tiling = get_cl_tiling(intel_tiling);
ss->ss0.surface_array_spacing = 1;
}
ss->ss0.surface_format = format;
- ss->ss1.base_addr = obj_bo->offset;
+ ss->ss1.base_addr = obj_bo->offset + obj_bo_offset;
ss->ss2.width = w - 1;
ss->ss2.height = h - 1;
ss->ss0.tile_walk = I965_TILEWALK_YMAJOR;
}
ss->ss0.render_cache_rw_mode = 1; /* XXX do we need to set it? */
- intel_gpgpu_set_buf_reloc_gen7(gpgpu, index, obj_bo, obj_bo_offset);
+ intel_gpgpu_set_buf_reloc_gen7(gpgpu, index, obj_bo, obj_bo->offset + obj_bo_offset);
assert(index < GEN_MAX_SURFACES);
}
ss->ss0.surface_array_spacing = 1;
}
ss->ss0.surface_format = format;
- ss->ss1.base_addr = obj_bo->offset;
+ ss->ss1.base_addr = obj_bo->offset + obj_bo_offset;
ss->ss2.width = w - 1;
ss->ss2.height = h - 1;
ss->ss3.depth = depth - 1;
ss->ss0.tile_walk = I965_TILEWALK_YMAJOR;
}
ss->ss0.render_cache_rw_mode = 1; /* XXX do we need to set it? */
- intel_gpgpu_set_buf_reloc_gen7(gpgpu, index, obj_bo, obj_bo_offset);
+ intel_gpgpu_set_buf_reloc_gen7(gpgpu, index, obj_bo, obj_bo->offset + obj_bo_offset);
assert(index < GEN_MAX_SURFACES);
}