arm64: dts: ti: k3-j7200-som-p0: main_i2c0 have an ioexpander on the SOM

The J7200 SOM have additional io expander which is used to control several
SOM level muxes to make sure that the correct signals are routed to the
correct pin on the SOM <-> CPB connectors.

Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
Reviewed-by: Vignesh Raghavendra <vigneshr@ti.com>
Reviewed-by: Grygorii Strashko <grygorii.strashko@ti.com>
Link: https://lore.kernel.org/r/20201120073533.24486-2-peter.ujfalusi@ti.com

diff --git a/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts b/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts
index 96fa263..1a8dd23 100644 (file)
--- a/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts
+++ b/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts
@@ -43,13 +43,6 @@
 };
 
 &main_pmx0 {
-       main_i2c0_pins_default: main-i2c0-pins-default {
-               pinctrl-single,pins = <
-                       J721E_IOPAD(0xd4, PIN_INPUT_PULLUP, 0) /* (V3) I2C0_SCL */
-                       J721E_IOPAD(0xd8, PIN_INPUT_PULLUP, 0) /* (W2) I2C0_SDA */
-               >;
-       };
-
        main_i2c1_pins_default: main-i2c1-pins-default {
                pinctrl-single,pins = <
                        J721E_IOPAD(0xdc, PIN_INPUT_PULLUP, 3) /* (U3) ECAP0_IN_APWM_OUT.I2C1_SCL */
@@ -146,10 +139,6 @@
 };
 
 &main_i2c0 {
-       pinctrl-names = "default";
-       pinctrl-0 = <&main_i2c0_pins_default>;
-       clock-frequency = <400000>;
-
        exp1: gpio@20 {
                compatible = "ti,tca6416";
                reg = <0x20>;

diff --git a/arch/arm64/boot/dts/ti/k3-j7200-som-p0.dtsi b/arch/arm64/boot/dts/ti/k3-j7200-som-p0.dtsi
index fbd17d3..7b5e9aa 100644 (file)
--- a/arch/arm64/boot/dts/ti/k3-j7200-som-p0.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-j7200-som-p0.dtsi
@@ -48,6 +48,15 @@
        };
 };
 
+&main_pmx0 {
+       main_i2c0_pins_default: main-i2c0-pins-default {
+               pinctrl-single,pins = <
+                       J721E_IOPAD(0xd4, PIN_INPUT_PULLUP, 0) /* (V3) I2C0_SCL */
+                       J721E_IOPAD(0xd8, PIN_INPUT_PULLUP, 0) /* (W2) I2C0_SDA */
+               >;
+       };
+};
+
 &hbmc {
        /* OSPI and HBMC are muxed inside FSS, Bootloader will enable
         * appropriate node based on board detection
@@ -131,3 +140,20 @@
 &mailbox0_cluster11 {
        status = "disabled";
 };
+
+&main_i2c0 {
+       pinctrl-names = "default";
+       pinctrl-0 = <&main_i2c0_pins_default>;
+       clock-frequency = <400000>;
+
+       exp_som: gpio@21 {
+               compatible = "ti,tca6408";
+               reg = <0x21>;
+               gpio-controller;
+               #gpio-cells = <2>;
+               gpio-line-names = "USB2.0_MUX_SEL", "CANUART_MUX1_SEL0",
+                                 "CANUART_MUX2_SEL0", "CANUART_MUX_SEL1",
+                                 "UART/LIN_MUX_SEL", "TRC_D17/AUDIO_REFCLK_SEL",
+                                 "GPIO_LIN_EN", "CAN_STB";
+       };
+};