ret i8 %c1
}
-
define i16 @shuf16i1_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0(i16 %a) {
; AVX512F-LABEL: shuf16i1_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0:
; AVX512F: # %bb.0:
%d = bitcast <64 x i1> %c to i64
ret i64 %d
}
+
+define void @PR32547(<8 x float> %a, <8 x float> %b, <8 x float> %c, <8 x float> %d, float* %p) {
+; AVX512F-LABEL: PR32547:
+; AVX512F: # %bb.0: # %entry
+; AVX512F-NEXT: # kill: def $ymm3 killed $ymm3 def $zmm3
+; AVX512F-NEXT: # kill: def $ymm2 killed $ymm2 def $zmm2
+; AVX512F-NEXT: # kill: def $ymm1 killed $ymm1 def $zmm1
+; AVX512F-NEXT: # kill: def $ymm0 killed $ymm0 def $zmm0
+; AVX512F-NEXT: vcmpltps %zmm1, %zmm0, %k0
+; AVX512F-NEXT: vcmpltps %zmm3, %zmm2, %k1
+; AVX512F-NEXT: kmovw %k1, %eax
+; AVX512F-NEXT: kmovw %k0, %ecx
+; AVX512F-NEXT: movzbl %al, %eax
+; AVX512F-NEXT: shll $8, %ecx
+; AVX512F-NEXT: orl %eax, %ecx
+; AVX512F-NEXT: kmovw %ecx, %k1
+; AVX512F-NEXT: vxorps %xmm0, %xmm0, %xmm0
+; AVX512F-NEXT: vmovaps %zmm0, (%rdi) {%k1}
+; AVX512F-NEXT: vzeroupper
+; AVX512F-NEXT: retq
+;
+; AVX512VL-LABEL: PR32547:
+; AVX512VL: # %bb.0: # %entry
+; AVX512VL-NEXT: vcmpltps %ymm1, %ymm0, %k0
+; AVX512VL-NEXT: vcmpltps %ymm3, %ymm2, %k1
+; AVX512VL-NEXT: kmovw %k1, %eax
+; AVX512VL-NEXT: kmovw %k0, %ecx
+; AVX512VL-NEXT: movzbl %al, %eax
+; AVX512VL-NEXT: shll $8, %ecx
+; AVX512VL-NEXT: orl %eax, %ecx
+; AVX512VL-NEXT: kmovw %ecx, %k1
+; AVX512VL-NEXT: vxorps %xmm0, %xmm0, %xmm0
+; AVX512VL-NEXT: vmovaps %zmm0, (%rdi) {%k1}
+; AVX512VL-NEXT: vzeroupper
+; AVX512VL-NEXT: retq
+;
+; VL_BW_DQ-LABEL: PR32547:
+; VL_BW_DQ: # %bb.0: # %entry
+; VL_BW_DQ-NEXT: vcmpltps %ymm1, %ymm0, %k0
+; VL_BW_DQ-NEXT: vcmpltps %ymm3, %ymm2, %k1
+; VL_BW_DQ-NEXT: kmovd %k0, %eax
+; VL_BW_DQ-NEXT: kmovb %k1, %ecx
+; VL_BW_DQ-NEXT: shll $8, %eax
+; VL_BW_DQ-NEXT: orl %ecx, %eax
+; VL_BW_DQ-NEXT: kmovd %eax, %k1
+; VL_BW_DQ-NEXT: vxorps %xmm0, %xmm0, %xmm0
+; VL_BW_DQ-NEXT: vmovaps %zmm0, (%rdi) {%k1}
+; VL_BW_DQ-NEXT: vzeroupper
+; VL_BW_DQ-NEXT: retq
+ entry:
+ %0 = tail call i8 @llvm.x86.avx512.mask.cmp.ps.256(<8 x float> %a, <8 x float> %b, i32 1, i8 -1)
+ %1 = tail call i8 @llvm.x86.avx512.mask.cmp.ps.256(<8 x float> %c, <8 x float> %d, i32 1, i8 -1)
+ %conv.i = zext i8 %0 to i16
+ %conv.i18 = zext i8 %1 to i16
+ %shl = shl nuw i16 %conv.i, 8
+ %or = or i16 %shl, %conv.i18
+ %2 = bitcast float* %p to <16 x float>*
+ %3 = bitcast i16 %or to <16 x i1>
+ tail call void @llvm.masked.store.v16f32.p0v16f32(<16 x float> zeroinitializer, <16 x float>* %2, i32 64, <16 x i1> %3) #4
+ ret void
+}
+declare i8 @llvm.x86.avx512.mask.cmp.ps.256(<8 x float>, <8 x float>, i32, i8)
+declare void @llvm.masked.store.v16f32.p0v16f32(<16 x float>, <16 x float>*, i32, <16 x i1>)