intel: honor depthMode

Set up 3DSTATE_CLIP according to depthMode.

diff --git a/icd/intel/cmd_pipeline.c b/icd/intel/cmd_pipeline.c
index 17f63e6..de2adfd 100644 (file)
--- a/icd/intel/cmd_pipeline.c
+++ b/icd/intel/cmd_pipeline.c
@@ -498,12 +498,16 @@ static void gen6_3DSTATE_CLIP(struct intel_cmd *cmd)
 
     dw2 = GEN6_CLIP_DW2_CLIP_ENABLE |
           GEN6_CLIP_DW2_XY_TEST_ENABLE |
-          GEN6_CLIP_DW2_APIMODE_OGL |
           (vs->enable_user_clip ? 1 : 0) << GEN6_CLIP_DW2_UCP_CLIP_ENABLES__SHIFT |
           pipeline->provoking_vertex_tri << GEN6_CLIP_DW2_TRI_PROVOKE__SHIFT |
           pipeline->provoking_vertex_line << GEN6_CLIP_DW2_LINE_PROVOKE__SHIFT |
           pipeline->provoking_vertex_trifan << GEN6_CLIP_DW2_TRIFAN_PROVOKE__SHIFT;
 
+    if (pipeline->depth_zero_to_one)
+        dw2 |= GEN6_CLIP_DW2_APIMODE_D3D;
+    else
+        dw2 |= GEN6_CLIP_DW2_APIMODE_OGL;
+
     if (pipeline->rasterizerDiscardEnable)
         dw2 |= GEN6_CLIP_DW2_CLIPMODE_REJECT_ALL;
     else

diff --git a/icd/intel/pipeline.c b/icd/intel/pipeline.c
index 5cc4295..73dfbc4 100644 (file)
--- a/icd/intel/pipeline.c
+++ b/icd/intel/pipeline.c
@@ -806,6 +806,20 @@ static void pipeline_build_vertex_elements(struct intel_pipeline *pipeline,
     }
 }
 
+static void pipeline_build_viewport(struct intel_pipeline *pipeline,
+                                    const struct intel_pipeline_create_info *info)
+{
+    switch (info->vp.depthMode) {
+    case XGL_DEPTH_MODE_ZERO_TO_ONE:
+        pipeline->depth_zero_to_one = true;
+        break;
+    case XGL_DEPTH_MODE_NEGATIVE_ONE_TO_ONE:
+    default:
+        pipeline->depth_zero_to_one = false;
+        break;
+    }
+}
+
 static void pipeline_build_fragment_SBE(struct intel_pipeline *pipeline,
                                         const struct intel_pipeline_create_info *info)
 {
@@ -1167,6 +1181,7 @@ static XGL_RESULT pipeline_build_all(struct intel_pipeline *pipeline,
             sizeof(pipeline->vb[0]) * pipeline->vb_count);
 
     pipeline_build_vertex_elements(pipeline, info);
+    pipeline_build_viewport(pipeline, info);
     pipeline_build_fragment_SBE(pipeline, info);
     pipeline_build_msaa(pipeline, info);
     pipeline_build_depth_stencil(pipeline, info);

diff --git a/icd/intel/pipeline.h b/icd/intel/pipeline.h
index c340301..04a8a3e 100644 (file)
--- a/icd/intel/pipeline.h
+++ b/icd/intel/pipeline.h
@@ -190,6 +190,8 @@ struct intel_pipeline {
     /* Depth Buffer format */
     XGL_FORMAT db_format;
 
+    bool depth_zero_to_one;
+
     XGL_PIPELINE_CB_STATE_CREATE_INFO cb_state;
 
     // XGL_PIPELINE_RS_STATE_CREATE_INFO rs_state;