ARM: dts: meson: Add the Ethernet "timing-adjustment" clock

Add the "timing-adjusment" clock now that we now that this is connected
to the PRG_ETHERNET registers. It is used internally to generate the
RGMII RX delay no the MAC side (if needed).

Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Signed-off-by: Kevin Hilman <khilman@baylibre.com>
Link: https://lore.kernel.org/r/20200512215148.540322-2-martin.blumenstingl@googlemail.com

diff --git a/arch/arm/boot/dts/meson8b.dtsi b/arch/arm/boot/dts/meson8b.dtsi
index e34b039..ba36168 100644 (file)
--- a/arch/arm/boot/dts/meson8b.dtsi
+++ b/arch/arm/boot/dts/meson8b.dtsi
@@ -425,8 +425,9 @@
 
        clocks = <&clkc CLKID_ETH>,
                 <&clkc CLKID_MPLL2>,
-                <&clkc CLKID_MPLL2>;
-       clock-names = "stmmaceth", "clkin0", "clkin1";
+                <&clkc CLKID_MPLL2>,
+                <&clkc CLKID_FCLK_DIV2>;
+       clock-names = "stmmaceth", "clkin0", "clkin1", "timing-adjustment";
        rx-fifo-depth = <4096>;
        tx-fifo-depth = <2048>;
 

diff --git a/arch/arm/boot/dts/meson8m2.dtsi b/arch/arm/boot/dts/meson8m2.dtsi
index ca749cc..2397ba0 100644 (file)
--- a/arch/arm/boot/dts/meson8m2.dtsi
+++ b/arch/arm/boot/dts/meson8m2.dtsi
@@ -30,8 +30,9 @@
                0xc1108140 0x8>;
        clocks = <&clkc CLKID_ETH>,
                 <&clkc CLKID_MPLL2>,
-                <&clkc CLKID_MPLL2>;
-       clock-names = "stmmaceth", "clkin0", "clkin1";
+                <&clkc CLKID_MPLL2>,
+                <&clkc CLKID_FCLK_DIV2>;
+       clock-names = "stmmaceth", "clkin0", "clkin1", "timing-adjustment";
        resets = <&reset RESET_ETHERNET>;
        reset-names = "stmmaceth";
 };