tvin: add vdin and viu support for tl1 [1/1]
authorxuhua zhang <xuhua.zhang@amlogic.com>
Sat, 29 Sep 2018 11:03:25 +0000 (19:03 +0800)
committerJianxin Pan <jianxin.pan@amlogic.com>
Mon, 29 Oct 2018 11:20:54 +0000 (04:20 -0700)
PD#172587

Problem:
do not suppoert for tl1

Solution:
add vdin and viu support for fl1

Verify:
verified on PTM

Change-Id: If4e267356fa666541853cfc7b49008795f9ec301
Signed-off-by: xuhua zhang <xuhua.zhang@amlogic.com>
arch/arm/boot/dts/amlogic/tl1_pxp.dts
drivers/amlogic/media/vin/tvin/vdin/vdin_ctl.c
drivers/amlogic/media/vin/tvin/vdin/vdin_ctl.h
drivers/amlogic/media/vin/tvin/vdin/vdin_drv.c
drivers/amlogic/media/vin/tvin/vdin/vdin_drv.h
drivers/amlogic/media/vin/tvin/vdin/vdin_regs.h
drivers/amlogic/media/vin/tvin/viu/viuin.c

index fa75d5e..7068dfb 100644 (file)
                        alignment = <0x400000>;
                };
 
-
-       };
+               /*  vdin0 CMA pool */
+               //vdin0_cma_reserved:linux,vdin0_cma {
+               //      compatible = "shared-dma-pool";
+               //      reusable;
+                       /* 3840x2160x4x4 ~=128 M */
+               //      size = <0x8000000>;
+               //      alignment = <0x400000>;
+               //};
+
+               /*  vdin1 CMA pool */
+               vdin1_cma_reserved:linux,vdin1_cma {
+                       compatible = "shared-dma-pool";
+                       reusable;
+                       /* 1920x1080x2x4  =16 M */
+                       size = <0x1400000>;
+                       alignment = <0x400000>;
+               };
+       }; /* end of reserved-memory */
 
        codec_mm {
                compatible = "amlogic, codec, mm";
                interrupts = <0 12 1>,
                                <0 13 1>;
        };
+
+       vdin@0 {
+               compatible = "amlogic, vdin";
+               /*memory-region = <&vdin0_cma_reserved>;*/
+               status = "okay";
+               /*bit0:(1:share with codec_mm;0:cma alone)
+                *bit8:(1:alloc in discontinus way;0:alone in continuous way)
+                */
+               flag_cma = <0x101>;
+               /*MByte, if 10bit disable: 64M(YUV422),
+                *if 10bit enable: 64*1.5 = 96M(YUV422)
+                *if support 4K2K-YUV444-10bit-WR:3840*2160*4*4 ~= 128M
+                *if support 4K2K-YUV422-10bit-wr:3840*2160*3*4 ~= 96M
+                *if support 4K2K-YUV422-8BIT-WR:3840*2160*2*4 ~= 64M
+                *if support 1080p-YUV422-8BIT-WR:1920*1080*2*4 ~= 16M
+                */
+               cma_size = <190>;
+               interrupts = <0 83 1>;
+               rdma-irq = <2>;
+               clocks = <&clkc CLKID_FCLK_DIV5>,
+                       <&clkc CLKID_VDIN_MEAS_COMP>;
+               clock-names = "fclk_div5", "cts_vdin_meas_clk";
+               vdin_id = <0>;
+               /*vdin write mem color depth support:
+                * bit0:support 8bit
+                * bit1:support 9bit
+                * bit2:support 10bit
+                * bit3:support 12bit
+                * bit4:support yuv422 10bit full pack mode (from txl new add)
+                * bit8:use 8bit  at 4k_50/60hz_10bit
+                * bit9:use 10bit at 4k_50/60hz_10bit
+                */
+               tv_bit_mode = <0x215>;
+       };
+
+       vdin@1 {
+               compatible = "amlogic, vdin";
+               memory-region = <&vdin1_cma_reserved>;
+               status = "okay";
+               /*bit0:(1:share with codec_mm;0:cma alone)
+                *bit8:(1:alloc in discontinus way;0:alone in continuous way)
+                */
+               flag_cma = <0>;
+               interrupts = <0 85 1>;
+               rdma-irq = <4>;
+               clocks = <&clkc CLKID_FCLK_DIV5>,
+                       <&clkc CLKID_VDIN_MEAS_COMP>;
+               clock-names = "fclk_div5", "cts_vdin_meas_clk";
+               vdin_id = <1>;
+               /*vdin write mem color depth support:
+                *bit0:support 8bit
+                *bit1:support 9bit
+                *bit2:support 10bit
+                *bit3:support 12bit
+                */
+               tv_bit_mode = <0x15>;
+       };
 }; /* end of / */
 
 &audiobus {
index 421d3d9..da16b14 100644 (file)
@@ -585,8 +585,8 @@ static void vdin_set_meas_mux(unsigned int offset, enum tvin_port_e port_,
                        (bt_path == BT_PATH_GPIO_B))
                        meas_mux = MEAS_MUX_656_B;
                else if ((is_meson_gxl_cpu() || is_meson_gxm_cpu() ||
-                       is_meson_g12a_cpu() || is_meson_g12b_cpu()) &&
-                       (bt_path == BT_PATH_GPIO))
+                       is_meson_g12a_cpu() || is_meson_g12b_cpu() ||
+                       is_meson_tl1_cpu()) && (bt_path == BT_PATH_GPIO))
                        meas_mux = MEAS_MUX_656;
                else
                        pr_info("cpu not define or do not support  bt656");
@@ -696,8 +696,8 @@ void vdin_set_top(unsigned int offset,
                        wr_bits(offset, VDIN_ASFIFO_CTRL3, 0xe4,
                                VDI9_ASFIFO_CTRL_BIT, VDI9_ASFIFO_CTRL_WID);
                } else if ((is_meson_gxm_cpu() || is_meson_gxl_cpu() ||
-                       is_meson_g12a_cpu() || is_meson_g12b_cpu()) &&
-                       (bt_path == BT_PATH_GPIO)) {
+                       is_meson_g12a_cpu() || is_meson_g12b_cpu() ||
+                       is_meson_tl1_cpu()) && (bt_path == BT_PATH_GPIO)) {
                        vdin_mux = VDIN_MUX_656;
                        wr_bits(offset, VDIN_ASFIFO_CTRL0, 0xe4,
                                VDI1_ASFIFO_CTRL_BIT, VDI1_ASFIFO_CTRL_WID);
@@ -2614,7 +2614,7 @@ void vdin_set_default_regmap(unsigned int offset)
        /* [11: 0]       write.lfifo_buf_size   = 0x100 */
        if (is_meson_m8b_cpu() ||
                is_meson_gxtvbb_cpu() || is_meson_txl_cpu() ||
-               is_meson_txlx_cpu())
+               is_meson_txlx_cpu() || is_meson_tl1_cpu())
                wr(offset, VDIN_LFIFO_CTRL,     0x00000f00);
        else
                wr(offset, VDIN_LFIFO_CTRL,     0x00000780);
@@ -4326,3 +4326,34 @@ void vdin_clk_onoff(struct vdin_dev_s *devp, bool onoff)
                wr(offset, VDIN_COM_GCLK_CTRL2, 0x55555555);
        }
 }
+
+void vdin_write_mif_or_afbce(struct vdin_dev_s *devp,
+       enum vdin_output_mif_e sel)
+{
+       unsigned int offset = devp->addr_offset;
+
+       if (offset == 0) {
+               if (sel == VDIN_OUTPUT_TO_MIF) {
+                       W_VCBUS_BIT(VDIN_MISC_CTRL, 1, VDIN0_MIF_ENABLE_BIT, 1);
+                       W_VCBUS_BIT(VDIN_MISC_CTRL, 1, VDIN0_OUT_MIF_BIT, 1);
+                       W_VCBUS_BIT(VDIN_MISC_CTRL, 0, VDIN0_OUT_AFBCE_BIT, 1);
+               } else if (sel == VDIN_OUTPUT_TO_AFBCE) {
+                       W_VCBUS_BIT(VDIN_MISC_CTRL, 1, VDIN0_MIF_ENABLE_BIT, 1);
+                       W_VCBUS_BIT(VDIN_MISC_CTRL, 0, VDIN0_OUT_MIF_BIT, 1);
+                       W_VCBUS_BIT(VDIN_MISC_CTRL, 1, VDIN0_OUT_AFBCE_BIT, 1);
+               }
+       } else {
+               if (sel == VDIN_OUTPUT_TO_MIF) {
+                       W_VCBUS_BIT(VDIN_MISC_CTRL, 1, VDIN1_MIF_ENABLE_BIT, 1);
+                       W_VCBUS_BIT(VDIN_MISC_CTRL, 1, VDIN1_OUT_MIF_BIT, 1);
+                       W_VCBUS_BIT(VDIN_MISC_CTRL, 0, VDIN1_OUT_AFBCE_BIT, 1);
+               } else if (sel == VDIN_OUTPUT_TO_AFBCE) {
+                       /*sel vdin1 afbce: not support in sw now,
+                        *just reserved interface
+                        */
+                       W_VCBUS_BIT(VDIN_MISC_CTRL, 1, VDIN1_MIF_ENABLE_BIT, 1);
+                       W_VCBUS_BIT(VDIN_MISC_CTRL, 0, VDIN1_OUT_MIF_BIT, 1);
+                       W_VCBUS_BIT(VDIN_MISC_CTRL, 1, VDIN1_OUT_AFBCE_BIT, 1);
+               }
+       }
+}
index 4d127ae..0d8199b 100644 (file)
 #define DV_READ_MODE_AXI       (1 << 6)
 #define DV_CRC_CHECK   (1 << 7)
 
+enum vdin_output_mif_e {
+       VDIN_OUTPUT_TO_MIF = 0,
+       VDIN_OUTPUT_TO_AFBCE = 1,
+};
+
 /* *********************************************************************** */
 /* *** enum definitions ********************************************* */
 /* *********************************************************************** */
@@ -202,5 +207,8 @@ extern enum tvin_force_color_range_e color_range_force;
 
 extern void vdin_vlock_input_sel(unsigned int type,
        enum vframe_source_type_e source_type);
+extern void vdin_write_mif_or_afbce(struct vdin_dev_s *devp,
+       enum vdin_output_mif_e sel);
+
 #endif
 
index 70f4ab3..8d1394e 100644 (file)
@@ -523,6 +523,8 @@ void vdin_start_dec(struct vdin_dev_s *devp)
 
        vdin_hw_enable(devp->addr_offset);
        vdin_set_all_regs(devp);
+       if (is_meson_tl1_cpu() && (devp->index == 0))
+               vdin_write_mif_or_afbce(devp, VDIN_OUTPUT_TO_MIF);
        if (!(devp->parm.flag & TVIN_PARM_FLAG_CAP) &&
                (devp->frontend) &&
                devp->frontend->dec_ops &&
@@ -2487,12 +2489,13 @@ static int vdin_drv_probe(struct platform_device *pdev)
        /* @todo vdin_addr_offset */
        if (is_meson_gxbb_cpu() && vdevp->index)
                vdin_addr_offset[vdevp->index] = 0x70;
-       else if ((is_meson_g12a_cpu() || is_meson_g12b_cpu()) && vdevp->index)
+       else if ((is_meson_g12a_cpu() || is_meson_g12b_cpu() ||
+               is_meson_tl1_cpu()) && vdevp->index)
                vdin_addr_offset[vdevp->index] = 0x100;
        vdevp->addr_offset = vdin_addr_offset[vdevp->index];
        vdevp->flags = 0;
        /*canvas align number*/
-       if (is_meson_g12a_cpu() || is_meson_g12b_cpu())
+       if (is_meson_g12a_cpu() || is_meson_g12b_cpu() || is_meson_tl1_cpu())
                vdevp->canvas_align = 64;
        else
                vdevp->canvas_align = 32;
index 4438f8d..1ee8eb9 100644 (file)
@@ -45,7 +45,7 @@
 #include "vdin_vf.h"
 #include "vdin_regs.h"
 
-#define VDIN_VER "Ref.2018/04/28"
+#define VDIN_VER "Ref.2018/09/29"
 
 /*the counter of vdin*/
 #define VDIN_MAX_DEVS                  2
index ac49237..eaf40b0 100644 (file)
 #define VDIN0_REQ_EN_BIT 0
 #define VDIN1_REQ_EN_BIT 1
 #define VDIN_MISC_CTRL 0x2782
+#define VDIN0_OUT_AFBCE_BIT 21
+#define VDIN0_OUT_MIF_BIT 20
+#define VDIN0_MIF_ENABLE_BIT 19
+#define VDIN1_OUT_AFBCE_BIT 18
+#define VDIN1_OUT_MIF_BIT 17
+#define VDIN1_MIF_ENABLE_BIT 16
 #define VDIN0_MIF_RST_BIT 3
 #define VDIN1_MIF_RST_BIT 4
 #define VDIN_MIF_RST_W 1
index 8a7922b..3fe16a6 100644 (file)
@@ -178,7 +178,8 @@ static int viuin_open(struct tvin_frontend_s *fe, enum tvin_port_e port)
        /*open the venc to vdin path*/
        switch (rd_bits_viu(VPU_VIU_VENC_MUX_CTRL, 0, 2)) {
        case 0:
-               if (is_meson_g12a_cpu() || is_meson_g12b_cpu())
+               if (is_meson_g12a_cpu() || is_meson_g12b_cpu()
+                       || is_meson_tl1_cpu())
                        viu_mux = 0x4;
                else
                        viu_mux = 0x8;
@@ -212,7 +213,7 @@ static int viuin_open(struct tvin_frontend_s *fe, enum tvin_port_e port)
                        wr_viu(VPU_VIU2VDIN_HDN_CTRL, 0x40f00);
        } else
                wr_bits_viu(VPU_VIU2VDIN_HDN_CTRL, devp->parm.h_active, 0, 14);
-       if (is_meson_g12a_cpu() || is_meson_g12b_cpu()) {
+       if (is_meson_g12a_cpu() || is_meson_g12b_cpu() || is_meson_tl1_cpu()) {
                if (((port >= TVIN_PORT_VIU1_WB0_VD1) &&
                        (port <= TVIN_PORT_VIU1_WB0_POST_BLEND)) ||
                        ((port >= TVIN_PORT_VIU2_WB0_VD1) &&
@@ -307,7 +308,8 @@ static void viuin_close(struct tvin_frontend_s *fe)
        if (open_cnt)
                open_cnt--;
        if (open_cnt == 0) {
-               if (is_meson_g12a_cpu() || is_meson_g12b_cpu()) {
+               if (is_meson_g12a_cpu() || is_meson_g12b_cpu()
+                       || is_meson_tl1_cpu()) {
                        wr_viu(VPU_VIU_VDIN_IF_MUX_CTRL, 0);
                        wr_viu(VPP_WRBAK_CTRL, 0);