drm/i915/dg1: Update DMC_DEBUG3 register

Current DMC_DEBUG3(_MMIO(0x101090)) address is for TGL,
it is wrong for DG1. Just like commit 5bcc95ca382e
("drm/i915/dg1: Update DMC_DEBUG register"), correct
this issue for DG1 platform to avoid wrong register
being read.

BSpec: 49788

v2: fix "not wrong" typo. (Jani)

Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
Cc: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Chuansheng Liu <chuansheng.liu@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20220211002933.84240-1-chuansheng.liu@intel.com

diff --git a/drivers/gpu/drm/i915/display/intel_display_debugfs.c b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
index f4de004..f6c4ad8 100644 (file)
--- a/drivers/gpu/drm/i915/display/intel_display_debugfs.c
+++ b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
@@ -474,8 +474,8 @@ static int i915_dmc_info(struct seq_file *m, void *unused)
                 * reg for DC3CO debugging and validation,
                 * but TGL DMC f/w is using DMC_DEBUG3 reg for DC3CO counter.
                 */
-               seq_printf(m, "DC3CO count: %d\n",
-                          intel_de_read(dev_priv, DMC_DEBUG3));
+               seq_printf(m, "DC3CO count: %d\n", intel_de_read(dev_priv, IS_DGFX(dev_priv) ?
+                                       DG1_DMC_DEBUG3 : TGL_DMC_DEBUG3));
        } else {
                dc5_reg = IS_BROXTON(dev_priv) ? BXT_DMC_DC3_DC5_COUNT :
                                                 SKL_DMC_DC3_DC5_COUNT;

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 87c9231..9c215a6 100644 (file)
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -5632,7 +5632,8 @@
 #define TGL_DMC_DEBUG_DC6_COUNT        _MMIO(0x101088)
 #define DG1_DMC_DEBUG_DC5_COUNT        _MMIO(0x134154)
 
-#define DMC_DEBUG3             _MMIO(0x101090)
+#define TGL_DMC_DEBUG3         _MMIO(0x101090)
+#define DG1_DMC_DEBUG3         _MMIO(0x13415c)
 
 /* Display Internal Timeout Register */
 #define RM_TIMEOUT             _MMIO(0x42060)