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clk: qcom: dispcc-sm8250: Disable EDP_GTC for sm8350
author
Robert Foss
<robert.foss@linaro.org>
Wed, 2 Nov 2022 09:01:36 +0000
(10:01 +0100)
committer
Bjorn Andersson
<andersson@kernel.org>
Sun, 6 Nov 2022 04:38:18 +0000
(23:38 -0500)
SM8350 does not have the EDP_GTC clock, so let's disable it
for this SoC.
Signed-off-by: Robert Foss <robert.foss@linaro.org>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link:
https://lore.kernel.org/r/20221102090140.965450-2-robert.foss@linaro.org
drivers/clk/qcom/dispcc-sm8250.c
patch
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diff --git
a/drivers/clk/qcom/dispcc-sm8250.c
b/drivers/clk/qcom/dispcc-sm8250.c
index
709076f
..
180ac27
100644
(file)
--- a/
drivers/clk/qcom/dispcc-sm8250.c
+++ b/
drivers/clk/qcom/dispcc-sm8250.c
@@
-1330,6
+1330,9
@@
static int disp_cc_sm8250_probe(struct platform_device *pdev)
disp_cc_pll1_config.test_ctl_hi1_val = 0x01800000;
disp_cc_pll1_init.ops = &clk_alpha_pll_lucid_5lpe_ops;
disp_cc_pll1.vco_table = lucid_5lpe_vco;
+
+ disp_cc_sm8250_clocks[DISP_CC_MDSS_EDP_GTC_CLK] = NULL;
+ disp_cc_sm8250_clocks[DISP_CC_MDSS_EDP_GTC_CLK_SRC] = NULL;
}
clk_lucid_pll_configure(&disp_cc_pll0, regmap, &disp_cc_pll0_config);