[TableGen] Pass result of std::unique to vector::erase instead of calculating a size...

llvm-svn: 328031

diff --git a/llvm/docs/AMDGPUUsage.rst b/llvm/docs/AMDGPUUsage.rst
index d0671b0a74e0c0998dcaea2eb0e4855fe7ee7180..6d70cfa9c45d50da14594c1f03812bd998ba07ec 100644 (file)
--- a/llvm/docs/AMDGPUUsage.rst
+++ b/llvm/docs/AMDGPUUsage.rst
@@ -1,4 +1,4 @@
-=============================
+============================
 User Guide for AMDGPU Backend
 =============================
 

diff --git a/llvm/docs/CodeGenerator.rst b/llvm/docs/CodeGenerator.rst
index 7329f3d1fe6131a9288cd265f6cb5130df167135..a9e50707382102a7c83d2a641987b5bbbada4a2d 100644 (file)
--- a/llvm/docs/CodeGenerator.rst
+++ b/llvm/docs/CodeGenerator.rst
@@ -2656,3 +2656,9 @@ The AMDGPU backend
 The AMDGPU code generator lives in the ``lib/Target/AMDGPU``
 directory. This code generator is capable of targeting a variety of
 AMD GPU processors. Refer to :doc:`AMDGPUUsage` for more information.
+
+The X86 backend
+------------------
+
+The X86 code generator lives in the ``lib/Target/X86``
+directory. Refer to :doc:`X86Usage` for more information.

diff --git a/llvm/docs/CompilerWriterInfo.rst b/llvm/docs/CompilerWriterInfo.rst
index 60f102472c6368083ac6a18102154b6e64da1748..9148ff0aa894c8b80eccb2c1fb875334328e639c 100644 (file)
--- a/llvm/docs/CompilerWriterInfo.rst
+++ b/llvm/docs/CompilerWriterInfo.rst
@@ -99,6 +99,8 @@ X86
 * `X86 and X86-64 SysV psABI <https://github.com/hjl-tools/x86-psABI/wiki/X86-psABI>`_
 * `Calling conventions for different C++ compilers and operating systems  <http://www.agner.org/optimize/calling_conventions.pdf>`_
 
+Refer to :doc:`X86Usage` for additional documentation.
+
 XCore
 -----
 

diff --git a/llvm/docs/X86Usage.rst b/llvm/docs/X86Usage.rst
new file mode 100644 (file)
index 0000000..a8197d5
--- /dev/null
+++ b/llvm/docs/X86Usage.rst
@@ -0,0 +1,85 @@
+=============================
+User Guide for X86 Backend
+=============================
+
+.. contents::
+   :local:
+
+Introduction
+============
+
+The X86 backend provides ISA code generation for X86 CPUs. It lives in the
+``lib/Target/X86`` directory.
+
+LLVM
+====
+
+.. _x86-processors
+
+Processors
+----------
+
+Use the ``clang -march=<Processor>`` option to specify the X86 processor.
+
+  .. table:: X86 processors
+     :name: x86-processor-table
+
+     ================== ===================
+     Processor          Alternative
+                        Name
+     ``i386``
+     ``i486``
+     ``i586``
+     ``pentium``
+     ``pentium-mmx``
+     ``i686``
+     ``pentiumpro``
+     ``pentium2``
+     ``pentium3``       - ``pentium3m``
+     ``pentium-m``
+     ``pentium4``       - ``pentium4m``
+     ``lakemont``
+     ``yonah``
+     ``prescott``
+     ``nocona``
+     ``core2``
+     ``penryn``
+     ``bonnell``        - ``atom``
+     ``silvermont``     - ``slm``
+     ``goldmont``
+     ``nehalem``        - ``corei7``
+     ``westmere``
+     ``sandybridge``    - ``corei7-avx``
+     ``ivybridge``      - ``core-avx-i``
+     ``haswell``        - ``core-avx2``
+     ``broadwell``      - ``skylake``
+     ``knl``
+     ``knm``
+     ``skylake-avx512`` - ``skx``
+     ``cannonlake``
+     ``icelake``
+     ``k6``
+     ``k6-2``
+     ``k6-3``
+     ``athlon``         - ``athlon-tbird``
+     ``athlon-4``       - ``athlon-xp``
+                        - ``athlon-mp``
+     ``k8``             - ``opteron``
+                        - ``athlon64``
+                        - ``athlon-fx``
+     ``k8-sse3``        - ``opteron-sse3``
+                        - ``athlon64-sse3``
+     ``amdfam10h``      - ``barcelona``
+     ``btver1``
+     ``btver2``
+     ``bdver1``
+     ``bdver2``
+     ``bdver3``
+     ``bdver4``
+     ``znver1``
+     ``geode``
+     ``winchip-c6``
+     ``winchip2``
+     ``c3``
+     ``c3-2``
+     ================== ===================

diff --git a/llvm/docs/index.rst b/llvm/docs/index.rst
index 2173f94459dd4b8ee7ab0302b2bb37633c0d443e..84c7ccb1021aac4c61d9a9dd997a28d1d3763569 100644 (file)
--- a/llvm/docs/index.rst
+++ b/llvm/docs/index.rst
@@ -276,6 +276,7 @@ For API clients and LLVM developers.
    HowToUseAttributes
    NVPTXUsage
    AMDGPUUsage
+   X86Usage
    StackMaps
    InAlloca
    BigEndianNEON
@@ -380,6 +381,9 @@ For API clients and LLVM developers.
 :doc:`AMDGPUUsage`
    This document describes using the AMDGPU backend to compile GPU kernels.
 
+:doc:`X86Usage`
+   This document describes using the X86 backend.
+
 :doc:`StackMaps`
   LLVM support for mapping instruction addresses to the location of
   values and allowing code to be patched.

diff --git a/llvm/utils/TableGen/CodeGenSchedule.cpp b/llvm/utils/TableGen/CodeGenSchedule.cpp
index c4ec4933cb838102bfcce4dd2f175c4632d9fb24..71d957beaa1598f2798e94f0a95d27a8d47b92c1 100644 (file)
--- a/llvm/utils/TableGen/CodeGenSchedule.cpp
+++ b/llvm/utils/TableGen/CodeGenSchedule.cpp
@@ -1398,8 +1398,7 @@ static void inferFromTransitions(ArrayRef<PredTransition> LastTransitions,
            PI = I->PredTerm.begin(), PE = I->PredTerm.end(); PI != PE; ++PI) {
       Preds.push_back(PI->Predicate);
     }
-    RecIter PredsEnd = std::unique(Preds.begin(), Preds.end());
-    Preds.resize(PredsEnd - Preds.begin());
+    Preds.erase(std::unique(Preds.begin(), Preds.end()), Preds.end());
     SCTrans.PredTerm = Preds;
     SchedModels.getSchedClass(FromClassIdx).Transitions.push_back(SCTrans);
   }