powerpc/85xx: Add ucc uart support for p1025rdb

Add device tree nodes to enable ucc uart support on P1025RDB.

Signed-off-by: Zhicheng Fan <B32736@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>

diff --git a/arch/powerpc/boot/dts/fsl/p1021si-post.dtsi b/arch/powerpc/boot/dts/fsl/p1021si-post.dtsi
index 4252ef8..adb82fd 100644 (file)
--- a/arch/powerpc/boot/dts/fsl/p1021si-post.dtsi
+++ b/arch/powerpc/boot/dts/fsl/p1021si-post.dtsi
@@ -1,7 +1,7 @@
 /*
  * P1021/P1012 Silicon/SoC Device Tree Source (post include)
  *
- * Copyright 2011 Freescale Semiconductor Inc.
+ * Copyright 2011-2012 Freescale Semiconductor Inc.
  *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions are met:
@@ -213,6 +213,20 @@
                interrupt-parent = <&qeic>;
        };
 
+       ucc@2600 {
+               cell-index = <7>;
+               reg = <0x2600 0x200>;
+               interrupts = <42>;
+               interrupt-parent = <&qeic>;
+       };
+
+       ucc@2200 {
+               cell-index = <3>;
+               reg = <0x2200 0x200>;
+               interrupts = <34>;
+               interrupt-parent = <&qeic>;
+       };
+
        muram@10000 {
                #address-cells = <1>;
                #size-cells = <1>;

diff --git a/arch/powerpc/boot/dts/p1025rdb.dtsi b/arch/powerpc/boot/dts/p1025rdb.dtsi
index cf3676f..f502564 100644 (file)
--- a/arch/powerpc/boot/dts/p1025rdb.dtsi
+++ b/arch/powerpc/boot/dts/p1025rdb.dtsi
@@ -282,5 +282,45 @@
                                0x1  0x4  0x2  0x0  0x2  0x0    /* ENET5_RX_DV_SER5_CTS_B */
                                0x1  0x8  0x2  0x0  0x2  0x0>;    /* ENET5_RX_ER_SER5_CD_B */
                };
+
+               pio3: ucc_pin@03 {
+                       pio-map = <
+               /* port  pin  dir  open_drain  assignment  has_irq */
+                               0x0  0x16 0x2  0x0  0x2  0x0    /* SER7_CD_B*/
+                               0x0  0x12 0x2  0x0  0x2  0x0    /* SER7_CTS_B*/
+                               0x0  0x13 0x1  0x0  0x2  0x0    /* SER7_RTS_B*/
+                               0x0  0x14 0x2  0x0  0x2  0x0    /* SER7_RXD0*/
+                               0x0  0x15 0x1  0x0  0x2  0x0>;    /* SER7_TXD0*/
+               };
+
+               pio4: ucc_pin@04 {
+                       pio-map = <
+               /* port  pin  dir  open_drain  assignment  has_irq */
+                               0x1  0x0  0x2  0x0  0x2  0x0    /* SER3_CD_B*/
+                               0x0  0x1c 0x2  0x0  0x2  0x0    /* SER3_CTS_B*/
+                               0x0  0x1d 0x1  0x0  0x2  0x0    /* SER3_RTS_B*/
+                               0x0  0x1e 0x2  0x0  0x2  0x0    /* SER3_RXD0*/
+                               0x0  0x1f 0x1  0x0  0x2  0x0>;    /* SER3_TXD0*/
+               };
+       };
+};
+
+&qe {
+       serial2: ucc@2600 {
+               device_type = "serial";
+               compatible = "ucc_uart";
+               port-number = <0>;
+               rx-clock-name = "brg6";
+               tx-clock-name = "brg6";
+               pio-handle = <&pio3>;
+       };
+
+       serial3: ucc@2200 {
+               device_type = "serial";
+               compatible = "ucc_uart";
+               port-number = <1>;
+               rx-clock-name = "brg2";
+               tx-clock-name = "brg2";
+               pio-handle = <&pio4>;
        };
 };