const Instruction *getInstruction() const { return Data.second; }
/// Returns true if this references a valid instruction.
- bool isValid() const { return Data.second; }
+ operator bool() const { return Data.second != nullptr; }
/// Invalidate this reference.
void invalidate() { Data.second = nullptr; }
void RetireControlUnit::consumeCurrentToken() {
const RetireControlUnit::RUToken &Current = peekCurrentToken();
assert(Current.NumSlots && "Reserved zero slots?");
- assert(Current.IR.isValid() && "Invalid RUToken in the RCU queue.");
+ assert(Current.IR && "Invalid RUToken in the RCU queue.");
// Update the slot index to be the next item in the circular queue.
CurrentInstructionSlotIdx += Current.NumSlots;
void RetireControlUnit::onInstructionExecuted(unsigned TokenID) {
assert(Queue.size() > TokenID);
- assert(Queue[TokenID].Executed == false && Queue[TokenID].IR.isValid());
+ assert(Queue[TokenID].Executed == false && Queue[TokenID].IR);
Queue[TokenID].Executed = true;
}
unsigned RemovedElements = 0;
for (auto I = WaitSet.begin(), E = WaitSet.end(); I != E;) {
InstRef &IR = *I;
- if (!IR.isValid())
+ if (!IR)
break;
// Check if this instruction is now ready. In case, force
unsigned RemovedElements = 0;
for (auto I = IssuedSet.begin(), E = IssuedSet.end(); I != E;) {
InstRef &IR = *I;
- if (!IR.isValid())
+ if (!IR)
break;
Instruction &IS = *IR.getInstruction();
if (!IS.isExecuted()) {
AvailableEntries = CarryOver >= DispatchWidth ? 0 : DispatchWidth - CarryOver;
unsigned DispatchedOpcodes = DispatchWidth - AvailableEntries;
CarryOver -= DispatchedOpcodes;
- assert(CarriedOver.isValid() && "Invalid dispatched instruction");
+ assert(CarriedOver && "Invalid dispatched instruction");
SmallVector<unsigned, 8> RegisterFiles(PRF.getNumRegisterFiles(), 0U);
notifyInstructionDispatched(CarriedOver, RegisterFiles, DispatchedOpcodes);
Error ExecuteStage::issueReadyInstructions() {
InstRef IR = HWS.select();
- while (IR.isValid()) {
+ while (IR) {
if (Error Err = issueInstruction(IR))
return Err;
return issueReadyInstructions();
}
-
#ifndef NDEBUG
static void verifyInstructionEliminated(const InstRef &IR) {
const Instruction &Inst = *IR.getInstruction();
}
#endif
-
Error ExecuteStage::handleInstructionEliminated(InstRef &IR) {
#ifndef NDEBUG
verifyInstructionEliminated(IR);
namespace mca {
-bool FetchStage::hasWorkToComplete() const {
- return CurrentInstruction.isValid();
-}
+bool FetchStage::hasWorkToComplete() const { return CurrentInstruction; }
bool FetchStage::isAvailable(const InstRef & /* unused */) const {
- if (CurrentInstruction.isValid())
+ if (CurrentInstruction)
return checkNextStage(CurrentInstruction);
return false;
}
llvm::Error FetchStage::getNextInstruction() {
- assert(!CurrentInstruction.isValid() &&
- "There is already an instruction to process!");
+ assert(!CurrentInstruction && "There is already an instruction to process!");
if (!SM.hasNext())
return llvm::ErrorSuccess();
const SourceRef SR = SM.peekNext();
}
llvm::Error FetchStage::execute(InstRef & /*unused */) {
- assert(CurrentInstruction.isValid() && "There is no instruction to process!");
+ assert(CurrentInstruction && "There is no instruction to process!");
if (llvm::Error Val = moveToTheNextStage(CurrentInstruction))
return Val;
}
llvm::Error FetchStage::cycleStart() {
- if (!CurrentInstruction.isValid())
+ if (!CurrentInstruction)
return getNextInstruction();
return llvm::ErrorSuccess();
}