rs6000: Fix invalid address passed to __builtin_mma_disassemble_acc [PR104923]

The mma_disassemble_output_operand predicate is too lenient on the types
of addresses it will accept, leading to combine creating invalid address
that eventually lead to ICEs in LRA.  The solution is to restrict the
addresses to indirect, indexed or those valid for quad memory accesses.

2022-03-15  Peter Bergner  <bergner@linux.ibm.com>

gcc/
	PR target/104923
	* config/rs6000/predicates.md (mma_disassemble_output_operand): Restrict
	acceptable MEM addresses.

gcc/testsuite/
	PR target/104923
	* gcc.target/powerpc/pr104923.c: New test.

diff --git a/gcc/config/rs6000/predicates.md b/gcc/config/rs6000/predicates.md
index 566b85b..b1fcc69 100644 (file)
--- a/gcc/config/rs6000/predicates.md
+++ b/gcc/config/rs6000/predicates.md
@@ -1277,10 +1277,15 @@
 (define_predicate "mma_disassemble_output_operand"
   (match_code "reg,subreg,mem")
 {
+  if (MEM_P (op))
+    {
+      rtx  addr = XEXP (op, 0);
+      return indexed_or_indirect_address (addr, mode)
+            || quad_address_p (addr, mode, false);
+    }
+
   if (SUBREG_P (op))
     op = SUBREG_REG (op);
-  if (!REG_P (op))
-    return true;
 
   return vsx_register_operand (op, mode);
 })

diff --git a/gcc/testsuite/gcc.target/powerpc/pr104923.c b/gcc/testsuite/gcc.target/powerpc/pr104923.c
new file mode 100644 (file)
index 0000000..f119824
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/pr104923.c
@@ -0,0 +1,21 @@
+/* PR target/104923 */
+/* { dg-require-effective-target power10_ok } */
+/* { dg-options "-O2 -mdejagnu-cpu=power10" } */
+
+/* Make sure we do not ICE on the following test cases.  */
+
+void
+foo (__vector char *dst, __vector_quad *acc, unsigned int n)
+{
+  __vector char a[4];
+  __builtin_mma_disassemble_acc(a, acc);
+  dst[2 * n] = a[0];
+}
+
+void
+bar (__vector char *dst, __vector_quad *acc, unsigned int n)
+{
+  __vector char a[4];
+  __builtin_mma_disassemble_acc(a, acc);
+  dst[3 * n] = a[0];
+}