ASoC: SOF: amd: Enable cache for AMD Rembrandt platform
authorV sujith kumar Reddy <Vsujithkumar.Reddy@amd.com>
Tue, 13 Dec 2022 07:16:37 +0000 (12:46 +0530)
committerMark Brown <broonie@kernel.org>
Sun, 25 Dec 2022 23:33:27 +0000 (23:33 +0000)
Enable DSP cache for ACP memory

Signed-off-by: V sujith kumar Reddy <Vsujithkumar.Reddy@amd.com>
Link: https://lore.kernel.org/r/20221213071640.3038853-1-Vsujithkumar.Reddy@amd.com
Signed-off-by: Mark Brown <broonie@kernel.org>
sound/soc/sof/amd/acp-dsp-offset.h
sound/soc/sof/amd/acp-loader.c
sound/soc/sof/amd/acp.h

index de57262..920155d 100644 (file)
@@ -85,4 +85,8 @@
 
 #define ACP_SCRATCH_REG_0                      0x10000
 #define ACP6X_DSP_FUSION_RUNSTALL              0x0644
+
+/* Cache window registers */
+#define ACP_DSP0_CACHE_OFFSET0                 0x0420
+#define ACP_DSP0_CACHE_SIZE0                   0x0424
 #endif
index 090c8b1..a4bce5a 100644 (file)
@@ -151,6 +151,7 @@ static void configure_pte_for_fw_loading(int type, int num_pages, struct acp_dev
 int acp_dsp_pre_fw_run(struct snd_sof_dev *sdev)
 {
        struct pci_dev *pci = to_pci_dev(sdev->dev);
+       const struct sof_amd_acp_desc *desc = get_chip_info(sdev->pdata);
        struct acp_dev_data *adata;
        unsigned int src_addr, size_fw;
        u32 page_count, dma_size;
@@ -183,6 +184,12 @@ int acp_dsp_pre_fw_run(struct snd_sof_dev *sdev)
        if (ret < 0)
                dev_err(sdev->dev, "acp dma transfer status: %d\n", ret);
 
+       if (desc->rev > 3) {
+               /* Cache Window enable */
+               snd_sof_dsp_write(sdev, ACP_DSP_BAR, ACP_DSP0_CACHE_OFFSET0, desc->sram_pte_offset);
+               snd_sof_dsp_write(sdev, ACP_DSP_BAR, ACP_DSP0_CACHE_SIZE0, SRAM1_SIZE | BIT(31));
+       }
+
        /* Free memory once DMA is complete */
        dma_size =  (PAGE_ALIGN(sdev->basefw.fw->size) >> PAGE_SHIFT) * ACP_PAGE_SIZE;
        dma_free_coherent(&pci->dev, dma_size, adata->bin_buf, adata->sha_dma_addr);
index 09e16ef..4314094 100644 (file)
@@ -72,6 +72,8 @@
 #define EXCEPT_MAX_HDR_SIZE                    0x400
 #define AMD_STACK_DUMP_SIZE                    32
 
+#define SRAM1_SIZE                             0x13A000
+
 enum clock_source {
        ACP_CLOCK_96M = 0,
        ACP_CLOCK_48M,