AArch64: bail instead of asserting on unexpected type in G_CONSTANT 0.

llvm-svn: 368031

diff --git a/llvm/lib/Target/AArch64/AArch64InstructionSelector.cpp b/llvm/lib/Target/AArch64/AArch64InstructionSelector.cpp
index 59cfcca..c3c1825 100644 (file)
--- a/llvm/lib/Target/AArch64/AArch64InstructionSelector.cpp
+++ b/llvm/lib/Target/AArch64/AArch64InstructionSelector.cpp
@@ -1296,8 +1296,8 @@ bool AArch64InstructionSelector::earlySelect(MachineInstr &I) const {
 
     Register DefReg = I.getOperand(0).getReg();
     LLT Ty = MRI.getType(DefReg);
-    assert((Ty == LLT::scalar(64) || Ty == LLT::scalar(32)) &&
-           "Unexpected legal constant type");
+    if (Ty != LLT::scalar(64) && Ty != LLT::scalar(32))
+      return false;
 
     if (Ty == LLT::scalar(64)) {
       I.getOperand(1).ChangeToRegister(AArch64::XZR, false);

diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/const-0.ll b/llvm/test/CodeGen/AArch64/GlobalISel/const-0.ll
new file mode 100644 (file)
index 0000000..89d1ee2
--- /dev/null
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/const-0.ll
@@ -0,0 +1,25 @@
+; RUN: llc -mtriple=aarch64-linux-gnu -global-isel -O0 -o - %s | FileCheck %s
+
+%struct.comp = type { i8*, i32, i8*, [3 x i8], i32 }
+
+define void @regbranch() {
+; CHECK-LABEL: regbranch:
+; CHECK: mov {{w[0-9]+}}, #0
+cond_next240.i:
+  br i1 false, label %cond_true251.i, label %cond_next272.i
+
+cond_true251.i:
+  switch i8 0, label %cond_next272.i [
+      i8 42, label %bb268.i
+      i8 43, label %bb268.i
+      i8 63, label %bb268.i
+  ]
+
+bb268.i:
+  br label %cond_next272.i
+
+cond_next272.i:
+  %len.2.i = phi i32 [ 0, %bb268.i ], [ 0, %cond_next240.i ], [ 0, %cond_true251.i ]
+  %tmp278.i = icmp eq i32 %len.2.i, 1
+  ret void
+}