usb: dwc3: add P3 in U2 SS inactive quirk
authorHuang Rui <ray.huang@amd.com>
Tue, 28 Oct 2014 11:54:28 +0000 (19:54 +0800)
committerFelipe Balbi <balbi@ti.com>
Mon, 3 Nov 2014 16:03:36 +0000 (10:03 -0600)
This patch adds P3 in U2 SS inactive quirk, and some special platforms can
configure that if it is needed.

[ balbi@ti.com : added DeviceTree binding documentation ]

Signed-off-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Felipe Balbi <balbi@ti.com>
Documentation/devicetree/bindings/usb/dwc3.txt
drivers/usb/dwc3/core.c
drivers/usb/dwc3/core.h
drivers/usb/dwc3/platform_data.h

index 5fcd680..36e4287 100644 (file)
@@ -19,6 +19,7 @@ Optional properties:
  - snps,has-lpm-erratum: true when DWC3 was configured with LPM Erratum enabled
  - snps,lpm-nyet-threshold: LPM NYET threshold
  - snps,u2exit_lfps_quirk: set if we want to enable u2exit lfps quirk
+ - snps,u2ss_inp3_quirk: set if we enable P3 OK for U2/SS Inactive quirk
 
 This is usually a subnode to DWC3 glue to which it is connected.
 
index 33cbea5..7c54da1 100644 (file)
@@ -365,6 +365,24 @@ static void dwc3_cache_hwparams(struct dwc3 *dwc)
 }
 
 /**
+ * dwc3_phy_setup - Configure USB PHY Interface of DWC3 Core
+ * @dwc: Pointer to our controller context structure
+ */
+static void dwc3_phy_setup(struct dwc3 *dwc)
+{
+       u32 reg;
+
+       reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(0));
+
+       if (dwc->u2ss_inp3_quirk)
+               reg |= DWC3_GUSB3PIPECTL_U2SSINP3OK;
+
+       dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), reg);
+
+       mdelay(100);
+}
+
+/**
  * dwc3_core_init - Low-level initialization of DWC3 Core
  * @dwc: Pointer to our controller context structure
  *
@@ -489,6 +507,8 @@ static int dwc3_core_init(struct dwc3 *dwc)
 
        dwc3_writel(dwc->regs, DWC3_GCTL, reg);
 
+       dwc3_phy_setup(dwc);
+
        ret = dwc3_alloc_scratch_buffers(dwc);
        if (ret)
                goto err1;
@@ -734,6 +754,8 @@ static int dwc3_probe(struct platform_device *pdev)
                                "snps,disable_scramble_quirk");
                dwc->u2exit_lfps_quirk = of_property_read_bool(node,
                                "snps,u2exit_lfps_quirk");
+               dwc->u2ss_inp3_quirk = of_property_read_bool(node,
+                               "snps,u2ss_inp3_quirk");
        } else if (pdata) {
                dwc->maximum_speed = pdata->maximum_speed;
                dwc->has_lpm_erratum = pdata->has_lpm_erratum;
@@ -745,6 +767,7 @@ static int dwc3_probe(struct platform_device *pdev)
 
                dwc->disable_scramble_quirk = pdata->disable_scramble_quirk;
                dwc->u2exit_lfps_quirk = pdata->u2exit_lfps_quirk;
+               dwc->u2ss_inp3_quirk = pdata->u2ss_inp3_quirk;
        }
 
        /* default to superspeed if no maximum_speed passed */
index f93145c..66fd26b 100644 (file)
 
 /* Global USB3 PIPE Control Register */
 #define DWC3_GUSB3PIPECTL_PHYSOFTRST   (1 << 31)
+#define DWC3_GUSB3PIPECTL_U2SSINP3OK   (1 << 29)
 #define DWC3_GUSB3PIPECTL_SUSPHY       (1 << 17)
 
 /* Global TX Fifo Size Register */
@@ -681,6 +682,7 @@ struct dwc3_scratchpad_array {
  * @three_stage_setup: set if we perform a three phase setup
  * @disable_scramble_quirk: set if we enable the disable scramble quirk
  * @u2exit_lfps_quirk: set if we enable u2exit lfps quirk
+ * @u2ss_inp3_quirk: set if we enable P3 OK for U2/SS Inactive quirk
  */
 struct dwc3 {
        struct usb_ctrlrequest  *ctrl_req;
@@ -790,6 +792,7 @@ struct dwc3 {
 
        unsigned                disable_scramble_quirk:1;
        unsigned                u2exit_lfps_quirk:1;
+       unsigned                u2ss_inp3_quirk:1;
 };
 
 /* -------------------------------------------------------------------------- */
index 3f21591..cf92c81 100644 (file)
@@ -30,4 +30,5 @@ struct dwc3_platform_data {
        unsigned disable_scramble_quirk:1;
        unsigned has_lpm_erratum:1;
        unsigned u2exit_lfps_quirk:1;
+       unsigned u2ss_inp3_quirk:1;
 };