* sim/m32r/uread16.ms: New testcase.

	* sim/m32r/uread32.ms: New testcase.
	* sim/m32r/uwrite16.ms: New testcase.
	* sim/m32r/uwrite32.ms: New testcase.

diff --git a/sim/testsuite/ChangeLog b/sim/testsuite/ChangeLog
index 2a1adf2..29dc237 100644 (file)
--- a/sim/testsuite/ChangeLog
+++ b/sim/testsuite/ChangeLog
@@ -10,6 +10,11 @@
 
        * sim/m32r/trap.cgs: Properly align trap2_handler.
 
+       * sim/m32r/uread16.ms: New testcase.
+       * sim/m32r/uread32.ms: New testcase.
+       * sim/m32r/uwrite16.ms: New testcase.
+       * sim/m32r/uwrite32.ms: New testcase.
+
 1998-12-14  Dave Brolley  <brolley@cygnus.com>
 
        * sim/fr30/call.cgs: Test ret here as well.

diff --git a/sim/testsuite/sim/m32r/.Sanitize b/sim/testsuite/sim/m32r/.Sanitize
index 79687a2..6c2bde7 100644 (file)
--- a/sim/testsuite/sim/m32r/.Sanitize
+++ b/sim/testsuite/sim/m32r/.Sanitize
@@ -168,6 +168,10 @@ xor3.cgs
 
 hello.ms
 hw-trap.ms
+uread16.ms
+uread32.ms
+uwrite16.ms
+uwrite32.ms
 
 Things-to-lose:
 

diff --git a/sim/testsuite/sim/m32r/uread16.ms b/sim/testsuite/sim/m32r/uread16.ms
new file mode 100644 (file)
index 0000000..550e99a
--- /dev/null
+++ b/sim/testsuite/sim/m32r/uread16.ms
@@ -0,0 +1,18 @@
+# mach: m32r m32rx
+# xerror:
+# output: *misaligned read*
+
+       .include "testutils.inc"
+
+       start
+
+; construct bra trap2_handler in trap 2 slot
+       ld24 r0,#foo+1
+       ldh r0,@r0
+       fail
+       exit 0
+
+.data
+       .p2align 2
+foo:
+       .short 42

diff --git a/sim/testsuite/sim/m32r/uread32.ms b/sim/testsuite/sim/m32r/uread32.ms
new file mode 100644 (file)
index 0000000..935c716
--- /dev/null
+++ b/sim/testsuite/sim/m32r/uread32.ms
@@ -0,0 +1,18 @@
+# mach: m32r m32rx
+# xerror:
+# output: *misaligned read*
+
+       .include "testutils.inc"
+
+       start
+
+; construct bra trap2_handler in trap 2 slot
+       ld24 r0,#foo+1
+       ld r0,@r0
+       fail
+       exit 0
+
+.data
+       .p2align 2
+foo:
+       .word 42

diff --git a/sim/testsuite/sim/m32r/uwrite16.ms b/sim/testsuite/sim/m32r/uwrite16.ms
new file mode 100644 (file)
index 0000000..11bfd6e
--- /dev/null
+++ b/sim/testsuite/sim/m32r/uwrite16.ms
@@ -0,0 +1,18 @@
+# mach: m32r m32rx
+# xerror:
+# output: *misaligned write*
+
+       .include "testutils.inc"
+
+       start
+
+; construct bra trap2_handler in trap 2 slot
+       ld24 r0,#foo+1
+       sth r0,@r0
+       fail
+       exit 0
+
+.data
+       .p2align 2
+foo:
+       .short 42

diff --git a/sim/testsuite/sim/m32r/uwrite32.ms b/sim/testsuite/sim/m32r/uwrite32.ms
new file mode 100644 (file)
index 0000000..495a123
--- /dev/null
+++ b/sim/testsuite/sim/m32r/uwrite32.ms
@@ -0,0 +1,18 @@
+# mach: m32r m32rx
+# xerror:
+# output: *misaligned write*
+
+       .include "testutils.inc"
+
+       start
+
+; construct bra trap2_handler in trap 2 slot
+       ld24 r0,#foo+1
+       st r0,@r0
+       fail
+       exit 0
+
+.data
+       .p2align 2
+foo:
+       .word 42