drm/amdgpu: Support setting EEPROM table version
authorStanley.Yang <Stanley.Yang@amd.com>
Tue, 30 May 2023 14:48:34 +0000 (22:48 +0800)
committerAlex Deucher <alexander.deucher@amd.com>
Fri, 9 Jun 2023 16:44:31 +0000 (12:44 -0400)
Add setting EEPROM table version interface for umcv8.10,
Add EEPROM table v2.1 to UMC v8.10.

Signed-off-by: Stanley.Yang <Stanley.Yang@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drivers/gpu/drm/amd/amdgpu/amdgpu_umc.h
drivers/gpu/drm/amd/amdgpu/umc_v8_10.c

index 86133f7..43321f5 100644 (file)
@@ -59,6 +59,8 @@ struct amdgpu_umc_ras {
                                      void *ras_error_status);
        void (*ecc_info_query_ras_error_address)(struct amdgpu_device *adev,
                                        void *ras_error_status);
+       /* support different eeprom table version for different asic */
+       void (*set_eeprom_table_version)(struct amdgpu_ras_eeprom_table_header *hdr);
 };
 
 struct amdgpu_umc_funcs {
index d51ae0b..46bfdee 100644 (file)
@@ -444,6 +444,11 @@ static void umc_v8_10_ecc_info_query_ras_error_address(struct amdgpu_device *ade
                umc_v8_10_ecc_info_query_error_address, ras_error_status);
 }
 
+static void umc_v8_10_set_eeprom_table_version(struct amdgpu_ras_eeprom_table_header *hdr)
+{
+       hdr->version = RAS_TABLE_VER_V2_1;
+}
+
 const struct amdgpu_ras_block_hw_ops umc_v8_10_ras_hw_ops = {
        .query_ras_error_count = umc_v8_10_query_ras_error_count,
        .query_ras_error_address = umc_v8_10_query_ras_error_address,
@@ -457,4 +462,5 @@ struct amdgpu_umc_ras umc_v8_10_ras = {
        .query_ras_poison_mode = umc_v8_10_query_ras_poison_mode,
        .ecc_info_query_ras_error_count = umc_v8_10_ecc_info_query_ras_error_count,
        .ecc_info_query_ras_error_address = umc_v8_10_ecc_info_query_ras_error_address,
+       .set_eeprom_table_version = umc_v8_10_set_eeprom_table_version,
 };