PPC4xx_IBM_DDR2_DUMP_REGISTER(SDTR3);
PPC4xx_IBM_DDR2_DUMP_REGISTER(MMODE);
PPC4xx_IBM_DDR2_DUMP_REGISTER(MEMODE);
- PPC4xx_IBM_DDR2_DUMP_REGISTER(ECCCR);
+ PPC4xx_IBM_DDR2_DUMP_REGISTER(ECCES);
#if (defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \
defined(CONFIG_460EX) || defined(CONFIG_460GT))
PPC4xx_IBM_DDR2_DUMP_REGISTER(CID);
The recv function should process packets as long as the hardware has them
readily available before returning. i.e. you should drain the hardware fifo.
-The common code sets up packet buffers for you already (NetRxPackets), so there
-is no need to allocate your own. For each packet you receive, you should call
-the NetReceive() function on it with the packet length. So the pseudo code
-here would look something like:
+For each packet you receive, you should call the NetReceive() function on it
+along with the packet length. The common code sets up packet buffers for you
+already in the .bss (NetRxPackets), so there should be no need to allocate your
+own. This doesn't mean you must use the NetRxPackets array however; you're
+free to call the NetReceive() function with any buffer you wish. So the pseudo
+code here would look something like:
int ape_recv(struct eth_device *dev)
{
int length, i = 0;
}
The halt function should turn off / disable the hardware and place it back in
-its reset state.
+its reset state. It can be called at any time (before any call to the related
+init function), so make sure it can handle this sort of thing.
So the call graph at this stage would look something like:
some net operation (ping / tftp / whatever...)
#define REG_READ(a) readl((a))
/* we don't need 16 bit initialisation on 32 bit bus */
-#define get_reg_init_bus(x) get_reg((x))
+#define get_reg_init_bus(r,d) get_reg((r),(d))
#else
memset(priv, 0, sizeof(*priv));
priv->regs = (struct cs8900_regs *)base_addr;
- /* Load MAC address from EEPROM */
- cs8900_get_enetaddr(dev);
-
dev->iobase = base_addr;
dev->priv = priv;
dev->init = cs8900_init;
dev->halt = cs8900_halt;
dev->send = cs8900_send;
dev->recv = cs8900_recv;
+
+ /* Load MAC address from EEPROM */
+ cs8900_get_enetaddr(dev);
+
sprintf(dev->name, "%s-%hu", CS8900_DRIVERNAME, dev_num);
eth_register(dev);
int i, oft, lnk;
u8 io_mode;
struct board_info *db = &dm9000_info;
- uchar enetaddr[6];
DM9000_DBG("%s\n", __func__);
/* Clear interrupt status */
DM9000_iow(DM9000_ISR, ISR_ROOS | ISR_ROS | ISR_PTS | ISR_PRS);
- /* Set Node address */
- if (!eth_getenv_enetaddr("ethaddr", enetaddr)) {
-#if !defined(CONFIG_DM9000_NO_SROM)
- for (i = 0; i < 3; i++)
- dm9000_read_srom_word(i, enetaddr + 2 * i);
- eth_setenv_enetaddr("ethaddr", enetaddr);
-#endif
- }
-
- printf("MAC: %pM\n", enetaddr);
+ printf("MAC: %pM\n", dev->enetaddr);
/* fill device MAC address registers */
for (i = 0, oft = DM9000_PAR; i < 6; i++, oft++)
- DM9000_iow(oft, enetaddr[i]);
+ DM9000_iow(oft, dev->enetaddr[i]);
for (i = 0, oft = 0x16; i < 8; i++, oft++)
DM9000_iow(oft, 0xff);
}
#endif
+static void dm9000_get_enetaddr(struct eth_device *dev)
+{
+#if !defined(CONFIG_DM9000_NO_SROM)
+ int i;
+ for (i = 0; i < 3; i++)
+ dm9000_read_srom_word(i, dev->enetaddr + (2 * i));
+#endif
+}
+
/*
Read a byte from I/O port
*/
{
struct eth_device *dev = &(dm9000_info.netdev);
+ /* Load MAC address from EEPROM */
+ dm9000_get_enetaddr(dev);
+
dev->init = dm9000_init;
dev->halt = dm9000_halt;
dev->send = dm9000_send;
.tbd_base = NULL,
.tbd_index = 0,
.bd = NULL,
+ .rdb_ptr = NULL,
+ .base_ptr = NULL,
};
/*
/*
* Set the auto-negotiation advertisement register bits
*/
- miiphy_write(dev->name, CONFIG_FEC_MXC_PHYADDR, PHY_ANAR, 0x1e0);
+ miiphy_write(dev->name, CONFIG_FEC_MXC_PHYADDR, PHY_ANAR,
+ PHY_ANLPAR_TXFD | PHY_ANLPAR_TX | PHY_ANLPAR_10FD |
+ PHY_ANLPAR_10 | PHY_ANLPAR_PSB_802_3);
miiphy_write(dev->name, CONFIG_FEC_MXC_PHYADDR, PHY_BMCR,
PHY_BMCR_AUTON | PHY_BMCR_RST_NEG);
uint32_t p = 0;
/* reserve data memory and consider alignment */
- fec->rdb_ptr = malloc(size * count + DB_DATA_ALIGNMENT);
+ if (fec->rdb_ptr == NULL)
+ fec->rdb_ptr = malloc(size * count + DB_DATA_ALIGNMENT);
p = (uint32_t)fec->rdb_ptr;
if (!p) {
puts("fec_imx27: not enough malloc memory!\n");
writel(FEC_ECNTRL_ETHER_EN, &fec->eth->ecntrl);
miiphy_wait_aneg(edev);
- miiphy_speed(edev->name, 0);
- miiphy_duplex(edev->name, 0);
+ miiphy_speed(edev->name, CONFIG_FEC_MXC_PHYADDR);
+ miiphy_duplex(edev->name, CONFIG_FEC_MXC_PHYADDR);
/*
* Enable SmartDMA receive task
* Datasheet forces the startaddress of each chain is 16 byte
* aligned
*/
- fec->base_ptr = malloc((2 + FEC_RBD_NUM) *
- sizeof(struct fec_bd) + DB_ALIGNMENT);
+ if (fec->base_ptr == NULL)
+ fec->base_ptr = malloc((2 + FEC_RBD_NUM) *
+ sizeof(struct fec_bd) + DB_ALIGNMENT);
base = (uint32_t)fec->base_ptr;
if (!base) {
puts("fec_imx27: not enough malloc memory!\n");
writel(0, &fec->eth->ecntrl);
fec->rbd_index = 0;
fec->tbd_index = 0;
- free(fec->rdb_ptr);
- free(fec->base_ptr);
debug("eth_halt: done\n");
}
#ifdef CONFIG_PXA250
#ifdef CONFIG_XSENGINE
-#define SMC_inl(a,r) (*((volatile dword *)((a)->iobase+(r<<1))))
-#define SMC_inw(a,r) (*((volatile word *)((a)->iobase+(r<<1))))
+#define SMC_inl(a,r) (*((volatile dword *)((a)->iobase+((r)<<1))))
+#define SMC_inw(a,r) (*((volatile word *)((a)->iobase+((r)<<1))))
#define SMC_inb(a,p) ({ \
- unsigned int __p = (unsigned int)((a)->iobase + (p<<1)); \
+ unsigned int __p = (unsigned int)((a)->iobase + ((p)<<1)); \
unsigned int __v = *(volatile unsigned short *)((__p) & ~2); \
if (__p & 2) __v >>= 8; \
else __v &= 0xff; \
__v; })
#define SMC_inb(a,p) ({ \
unsigned int ___v = SMC_inw((a),(p) & ~1); \
- if (p & 1) ___v >>= 8; \
+ if ((p) & 1) ___v >>= 8; \
else ___v &= 0xff; \
___v; })
#else
#define CONFIG_SYS_EBC_PB1CR (CONFIG_SYS_FPGA_BASE | 0x3a000) /* BAS=FPGA,BS=2MB,BU=R/W,BW=16bit*/
#endif /* !defined(CONFIG_ARCHES) */
-#define CONFIG_SYS_EBC_CFG 0xB8400000 /* EBC0_CFG */
+#define CONFIG_SYS_EBC_CFG 0xbfc00000
/*
* Arches doesn't use PerCS3 but GPIO43, so let's configure the GPIO
#define CONFIG_SMC91111
#define CONFIG_SMC91111_BASE (0x70000000)
#undef CONFIG_SMC_USE_32_BIT
-#define CONFIG_SMC_USE_IOFUNCS
#endif /* __LPD7A400_10_H */
#define CONFIG_SMC91111
#define CONFIG_SMC91111_BASE (0x70000000)
#undef CONFIG_SMC_USE_32_BIT
-#define CONFIG_SMC_USE_IOFUNCS
#endif /* __LPD7A404_10_H */
#include <config_cmd_default.h>
#ifndef USE_920T_MMU
- #define CONFIG_CMD_PING)
+ #define CONFIG_CMD_PING
#undef CONFIG_CMD_CACHE
#else
#define CONFIG_CMD_DATE