drm/amd/display: Update ASIC header files

Also separate register address initialization between ASICs for the
registers that were removed in scaled-down variation of the ASIC.

Signed-off-by: Nikola Cornij <nikola.cornij@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c
index 81b81e6..4ca9b6e 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c
@@ -535,11 +535,13 @@ void hubp1_program_deadline(
        REG_SET(VBLANK_PARAMETERS_3, 0,
                REFCYC_PER_META_CHUNK_VBLANK_L, dlg_attr->refcyc_per_meta_chunk_vblank_l);
 
-       REG_SET(NOM_PARAMETERS_0, 0,
-               DST_Y_PER_PTE_ROW_NOM_L, dlg_attr->dst_y_per_pte_row_nom_l);
+       if (REG(NOM_PARAMETERS_0))
+               REG_SET(NOM_PARAMETERS_0, 0,
+                       DST_Y_PER_PTE_ROW_NOM_L, dlg_attr->dst_y_per_pte_row_nom_l);
 
-       REG_SET(NOM_PARAMETERS_1, 0,
-               REFCYC_PER_PTE_GROUP_NOM_L, dlg_attr->refcyc_per_pte_group_nom_l);
+       if (REG(NOM_PARAMETERS_1))
+               REG_SET(NOM_PARAMETERS_1, 0,
+                       REFCYC_PER_PTE_GROUP_NOM_L, dlg_attr->refcyc_per_pte_group_nom_l);
 
        REG_SET(NOM_PARAMETERS_4, 0,
                DST_Y_PER_META_ROW_NOM_L, dlg_attr->dst_y_per_meta_row_nom_l);
@@ -568,11 +570,13 @@ void hubp1_program_deadline(
        REG_SET(VBLANK_PARAMETERS_4, 0,
                REFCYC_PER_META_CHUNK_VBLANK_C, dlg_attr->refcyc_per_meta_chunk_vblank_c);
 
-       REG_SET(NOM_PARAMETERS_2, 0,
-               DST_Y_PER_PTE_ROW_NOM_C, dlg_attr->dst_y_per_pte_row_nom_c);
+       if (REG(NOM_PARAMETERS_2))
+               REG_SET(NOM_PARAMETERS_2, 0,
+                       DST_Y_PER_PTE_ROW_NOM_C, dlg_attr->dst_y_per_pte_row_nom_c);
 
-       REG_SET(NOM_PARAMETERS_3, 0,
-               REFCYC_PER_PTE_GROUP_NOM_C, dlg_attr->refcyc_per_pte_group_nom_c);
+       if (REG(NOM_PARAMETERS_3))
+               REG_SET(NOM_PARAMETERS_3, 0,
+                       REFCYC_PER_PTE_GROUP_NOM_C, dlg_attr->refcyc_per_pte_group_nom_c);
 
        REG_SET(NOM_PARAMETERS_6, 0,
                DST_Y_PER_META_ROW_NOM_C, dlg_attr->dst_y_per_meta_row_nom_c);

diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h
index 4a3703e..c794ce4 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h
@@ -30,6 +30,7 @@
 #define TO_DCN10_HUBP(hubp)\
        container_of(hubp, struct dcn10_hubp, base)
 
+/* Register address initialization macro for all ASICs (including those with reduced functionality) */
 #define HUBP_REG_LIST_DCN(id)\
        SRI(DCHUBP_CNTL, HUBP, id),\
        SRI(HUBPREQ_DEBUG_DB, HUBP, id),\
@@ -78,16 +79,12 @@
        SRI(REF_FREQ_TO_PIX_FREQ, HUBPREQ, id),\
        SRI(VBLANK_PARAMETERS_1, HUBPREQ, id),\
        SRI(VBLANK_PARAMETERS_3, HUBPREQ, id),\
-       SRI(NOM_PARAMETERS_0, HUBPREQ, id),\
-       SRI(NOM_PARAMETERS_1, HUBPREQ, id),\
        SRI(NOM_PARAMETERS_4, HUBPREQ, id),\
        SRI(NOM_PARAMETERS_5, HUBPREQ, id),\
        SRI(PER_LINE_DELIVERY_PRE, HUBPREQ, id),\
        SRI(PER_LINE_DELIVERY, HUBPREQ, id),\
        SRI(VBLANK_PARAMETERS_2, HUBPREQ, id),\
        SRI(VBLANK_PARAMETERS_4, HUBPREQ, id),\
-       SRI(NOM_PARAMETERS_2, HUBPREQ, id),\
-       SRI(NOM_PARAMETERS_3, HUBPREQ, id),\
        SRI(NOM_PARAMETERS_6, HUBPREQ, id),\
        SRI(NOM_PARAMETERS_7, HUBPREQ, id),\
        SRI(DCN_TTU_QOS_WM, HUBPREQ, id),\
@@ -96,11 +93,19 @@
        SRI(DCN_SURF0_TTU_CNTL1, HUBPREQ, id),\
        SRI(DCN_SURF1_TTU_CNTL0, HUBPREQ, id),\
        SRI(DCN_SURF1_TTU_CNTL1, HUBPREQ, id),\
-       SRI(DCN_VM_MX_L1_TLB_CNTL, HUBPREQ, id),\
        SRI(HUBP_CLK_CNTL, HUBP, id)
 
+/* Register address initialization macro for "generic" ASICs with full functionality */
+#define HUBP_REG_LIST_DCN_GEN(id)\
+       SRI(NOM_PARAMETERS_0, HUBPREQ, id),\
+       SRI(NOM_PARAMETERS_1, HUBPREQ, id),\
+       SRI(NOM_PARAMETERS_2, HUBPREQ, id),\
+       SRI(NOM_PARAMETERS_3, HUBPREQ, id),\
+       SRI(DCN_VM_MX_L1_TLB_CNTL, HUBPREQ, id)
+
 #define HUBP_REG_LIST_DCN10(id)\
        HUBP_REG_LIST_DCN(id),\
+       HUBP_REG_LIST_DCN_GEN(id),\
        SRI(PREFETCH_SETTINS, HUBPREQ, id),\
        SRI(PREFETCH_SETTINS_C, HUBPREQ, id),\
        SRI(DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_MSB, HUBPREQ, id),\
@@ -237,6 +242,7 @@
 #define HUBP_SF(reg_name, field_name, post_fix)\
        .field_name = reg_name ## __ ## field_name ## post_fix
 
+/* Mask/shift struct generation macro for all ASICs (including those with reduced functionality) */
 #define HUBP_MASK_SH_LIST_DCN(mask_sh)\
        HUBP_SF(HUBP0_DCHUBP_CNTL, HUBP_BLANK_EN, mask_sh),\
        HUBP_SF(HUBP0_DCHUBP_CNTL, HUBP_TTU_DISABLE, mask_sh),\
@@ -335,8 +341,6 @@
        HUBP_SF(HUBPREQ0_REF_FREQ_TO_PIX_FREQ, REF_FREQ_TO_PIX_FREQ, mask_sh),\
        HUBP_SF(HUBPREQ0_VBLANK_PARAMETERS_1, REFCYC_PER_PTE_GROUP_VBLANK_L, mask_sh),\
        HUBP_SF(HUBPREQ0_VBLANK_PARAMETERS_3, REFCYC_PER_META_CHUNK_VBLANK_L, mask_sh),\
-       HUBP_SF(HUBPREQ0_NOM_PARAMETERS_0, DST_Y_PER_PTE_ROW_NOM_L, mask_sh),\
-       HUBP_SF(HUBPREQ0_NOM_PARAMETERS_1, REFCYC_PER_PTE_GROUP_NOM_L, mask_sh),\
        HUBP_SF(HUBPREQ0_NOM_PARAMETERS_4, DST_Y_PER_META_ROW_NOM_L, mask_sh),\
        HUBP_SF(HUBPREQ0_NOM_PARAMETERS_5, REFCYC_PER_META_CHUNK_NOM_L, mask_sh),\
        HUBP_SF(HUBPREQ0_PER_LINE_DELIVERY_PRE, REFCYC_PER_LINE_DELIVERY_PRE_L, mask_sh),\
@@ -345,8 +349,6 @@
        HUBP_SF(HUBPREQ0_PER_LINE_DELIVERY, REFCYC_PER_LINE_DELIVERY_C, mask_sh),\
        HUBP_SF(HUBPREQ0_VBLANK_PARAMETERS_2, REFCYC_PER_PTE_GROUP_VBLANK_C, mask_sh),\
        HUBP_SF(HUBPREQ0_VBLANK_PARAMETERS_4, REFCYC_PER_META_CHUNK_VBLANK_C, mask_sh),\
-       HUBP_SF(HUBPREQ0_NOM_PARAMETERS_2, DST_Y_PER_PTE_ROW_NOM_C, mask_sh),\
-       HUBP_SF(HUBPREQ0_NOM_PARAMETERS_3, REFCYC_PER_PTE_GROUP_NOM_C, mask_sh),\
        HUBP_SF(HUBPREQ0_NOM_PARAMETERS_6, DST_Y_PER_META_ROW_NOM_C, mask_sh),\
        HUBP_SF(HUBPREQ0_NOM_PARAMETERS_7, REFCYC_PER_META_CHUNK_NOM_C, mask_sh),\
        HUBP_SF(HUBPREQ0_DCN_TTU_QOS_WM, QoS_LEVEL_LOW_WM, mask_sh),\
@@ -357,12 +359,20 @@
        HUBP_SF(HUBPREQ0_DCN_SURF0_TTU_CNTL0, QoS_LEVEL_FIXED, mask_sh),\
        HUBP_SF(HUBPREQ0_DCN_SURF0_TTU_CNTL0, QoS_RAMP_DISABLE, mask_sh),\
        HUBP_SF(HUBPREQ0_DCN_SURF0_TTU_CNTL1, REFCYC_PER_REQ_DELIVERY_PRE, mask_sh),\
-       HUBP_SF(HUBPREQ0_DCN_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, mask_sh),\
-       HUBP_SF(HUBPREQ0_DCN_VM_MX_L1_TLB_CNTL, SYSTEM_ACCESS_MODE, mask_sh),\
        HUBP_SF(HUBP0_HUBP_CLK_CNTL, HUBP_CLOCK_ENABLE, mask_sh)
 
+/* Mask/shift struct generation macro for "generic" ASICs with full functionality */
+#define HUBP_MASK_SH_LIST_DCN_GEN(mask_sh)\
+       HUBP_SF(HUBPREQ0_NOM_PARAMETERS_0, DST_Y_PER_PTE_ROW_NOM_L, mask_sh),\
+       HUBP_SF(HUBPREQ0_NOM_PARAMETERS_1, REFCYC_PER_PTE_GROUP_NOM_L, mask_sh),\
+       HUBP_SF(HUBPREQ0_NOM_PARAMETERS_2, DST_Y_PER_PTE_ROW_NOM_C, mask_sh),\
+       HUBP_SF(HUBPREQ0_NOM_PARAMETERS_3, REFCYC_PER_PTE_GROUP_NOM_C, mask_sh),\
+       HUBP_SF(HUBPREQ0_DCN_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, mask_sh),\
+       HUBP_SF(HUBPREQ0_DCN_VM_MX_L1_TLB_CNTL, SYSTEM_ACCESS_MODE, mask_sh)
+
 #define HUBP_MASK_SH_LIST_DCN10(mask_sh)\
        HUBP_MASK_SH_LIST_DCN(mask_sh),\
+       HUBP_MASK_SH_LIST_DCN_GEN(mask_sh),\
        HUBP_SF(HUBPREQ0_PREFETCH_SETTINS, DST_Y_PREFETCH, mask_sh),\
        HUBP_SF(HUBPREQ0_PREFETCH_SETTINS, VRATIO_PREFETCH, mask_sh),\
        HUBP_SF(HUBPREQ0_PREFETCH_SETTINS_C, VRATIO_PREFETCH_C, mask_sh),\