Incorrect test for zero-r0 code gen.

diff --git a/sim/igen/ChangeLog b/sim/igen/ChangeLog
index a9f790a..5ca4d0e 100644 (file)
--- a/sim/igen/ChangeLog
+++ b/sim/igen/ChangeLog
@@ -1,3 +1,13 @@
+Fri May 23 12:01:08 1997  Andrew Cagney  <cagney@b1.cygnus.com>
+
+       * gen-semantics.c (print_semantic_body): Incorrect test for
+       zero-r0 code.
+
+Fri May 16 14:32:31 1997  Andrew Cagney  <cagney@b1.cygnus.com>
+
+       * gen-semantics.c (print_semantic_body): Use common sim-engine
+       interface.
+
 Fri May 16 11:48:30 1997  Andrew Cagney  <cagney@b1.cygnus.com>
 
        * gen-semantics.c (print_semantic_body): Add code to clear r0.

diff --git a/sim/igen/gen-semantics.c b/sim/igen/gen-semantics.c
index 35b247f..b249e38 100644 (file)
--- a/sim/igen/gen-semantics.c
+++ b/sim/igen/gen-semantics.c
@@ -176,7 +176,7 @@ print_semantic_body(lf *file,
   /* Architecture expects r0 to be zero.  Instead of having to check
      every read to see if it is refering to r0 just zap the r0
      register */
-  if ((code & generate_with_semantic_delayed_branch))
+  if ((code & generate_with_zero_r0))
     {
       lf_printf (file, "\n");
       lf_printf (file, "GPR(0) = 0;\n");
@@ -201,7 +201,7 @@ print_semantic_body(lf *file,
   else {
     /* abort so it is implemented now */
     table_entry_print_cpp_line_nr(file, instruction->file_entry);
-    lf_printf(file, "engine_error (SD, CPU, cia, \"%s:%d:0x%%08lx:%%s unimplemented\\n\",\n",
+    lf_printf(file, "sim_engine_abort (SD, CPU, cia, \"%s:%d:0x%%08lx:%%s unimplemented\\n\",\n",
              filter_filename(instruction->file_entry->file_name),
              instruction->file_entry->line_nr);
     if ((code & generate_with_semantic_delayed_branch))