drm/amd/display: Only blank DCN when we have set_blank implementation

Also rename timing_generator to optc

Signed-off-by: Yue Hin Lau <Yuehin.Lau@amd.com>
Reviewed-by: Eric Bernstein <Eric.Bernstein@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/Makefile b/drivers/gpu/drm/amd/display/dc/dcn10/Makefile
index 9eac228..5469bdf 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dcn10/Makefile
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/Makefile
@@ -23,7 +23,7 @@
 # Makefile for DCN.
 
 DCN10 = dcn10_resource.o dcn10_ipp.o dcn10_hw_sequencer.o \
-               dcn10_dpp.o dcn10_opp.o dcn10_timing_generator.o \
+               dcn10_dpp.o dcn10_opp.o dcn10_optc.o \
                dcn10_hubp.o dcn10_mpc.o \
                dcn10_dpp_dscl.o dcn10_dpp_cm.o dcn10_cm_common.o \
                dcn10_hubbub.o

diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
index 824de36..c9d717c 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
@@ -32,7 +32,7 @@
 #include "dce/dce_hwseq.h"
 #include "abm.h"
 #include "dmcu.h"
-#include "dcn10/dcn10_timing_generator.h"
+#include "dcn10_optc.h"
 #include "dcn10/dcn10_dpp.h"
 #include "dcn10/dcn10_mpc.h"
 #include "timing_generator.h"
@@ -465,6 +465,8 @@ static enum dc_status dcn10_prog_pixclk_crtc_otg(
        bool enableStereo    = stream->timing.timing_3d_format == TIMING_3D_FORMAT_NONE ?
                        false:true;
        bool rightEyePolarity = stream->timing.flags.RIGHT_EYE_3D_POLARITY;
+       int width = stream->timing.h_addressable + stream->timing.h_border_left + stream->timing.h_border_right;
+       int height = stream->timing.v_addressable + stream->timing.v_border_bottom + stream->timing.v_border_top;
 
        /* by upper caller loop, pipe0 is parent pipe and be called first.
         * back end is set up by for pipe0. Other children pipe share back end
@@ -518,11 +520,14 @@ static enum dc_status dcn10_prog_pixclk_crtc_otg(
        /* program otg blank color */
        color_space = stream->output_color_space;
        color_space_to_black_color(dc, color_space, &black_color);
-       pipe_ctx->stream_res.tg->funcs->set_blank_color(
-                       pipe_ctx->stream_res.tg,
-                       &black_color);
 
-       if (!pipe_ctx->stream_res.tg->funcs->is_blanked(pipe_ctx->stream_res.tg)) {
+       if (pipe_ctx->stream_res.tg->funcs->set_blank_color)
+               pipe_ctx->stream_res.tg->funcs->set_blank_color(
+                               pipe_ctx->stream_res.tg,
+                               &black_color);
+
+       if (pipe_ctx->stream_res.tg->funcs->is_blanked &&
+                       !pipe_ctx->stream_res.tg->funcs->is_blanked(pipe_ctx->stream_res.tg)) {
                pipe_ctx->stream_res.tg->funcs->set_blank(pipe_ctx->stream_res.tg, true);
                hwss_wait_for_blank_complete(pipe_ctx->stream_res.tg);
                false_optc_underflow_wa(dc, pipe_ctx->stream, pipe_ctx->stream_res.tg);
@@ -1808,6 +1813,10 @@ static void program_all_pipe_in_tree(
                struct pipe_ctx *pipe_ctx,
                struct dc_state *context)
 {
+       struct dc_stream_state *stream = pipe_ctx->stream;
+       int width = stream->timing.h_addressable + stream->timing.h_border_left + stream->timing.h_border_right;
+       int height = stream->timing.v_addressable + stream->timing.v_border_bottom + stream->timing.v_border_top;
+
        if (pipe_ctx->top_pipe == NULL) {
 
                pipe_ctx->stream_res.tg->dlg_otg_param.vready_offset = pipe_ctx->pipe_dlg_param.vready_offset;
@@ -1818,7 +1827,11 @@ static void program_all_pipe_in_tree(
 
                pipe_ctx->stream_res.tg->funcs->program_global_sync(
                                pipe_ctx->stream_res.tg);
-               pipe_ctx->stream_res.tg->funcs->set_blank(pipe_ctx->stream_res.tg, !is_pipe_tree_visible(pipe_ctx));
+
+               if (pipe_ctx->stream_res.tg->funcs->set_blank)
+                       pipe_ctx->stream_res.tg->funcs->set_blank(
+                                       pipe_ctx->stream_res.tg,
+                                       !is_pipe_tree_visible(pipe_ctx));
        }
 
        if (pipe_ctx->plane_state != NULL) {
@@ -1925,9 +1938,12 @@ static void dcn10_apply_ctx_for_surface(
 {
        int i;
        struct timing_generator *tg;
+       struct output_pixel_processor *opp;
        bool removed_pipe[4] = { false };
        unsigned int ref_clk_mhz = dc->res_pool->ref_clock_inKhz/1000;
        bool program_water_mark = false;
+       int width = stream->timing.h_addressable + stream->timing.h_border_left + stream->timing.h_border_right;
+       int height = stream->timing.v_addressable + stream->timing.v_border_bottom + stream->timing.v_border_top;
 
        struct pipe_ctx *top_pipe_to_program =
                        find_top_pipe_for_stream(dc, context, stream);
@@ -1935,6 +1951,8 @@ static void dcn10_apply_ctx_for_surface(
        if (!top_pipe_to_program)
                return;
 
+       opp = top_pipe_to_program->stream_res.opp;
+
        tg = top_pipe_to_program->stream_res.tg;
 
        tg->funcs->lock(tg);
@@ -1942,7 +1960,8 @@ static void dcn10_apply_ctx_for_surface(
        if (num_planes == 0) {
 
                /* OTG blank before remove all front end */
-               tg->funcs->set_blank(tg, true);
+               if (tg->funcs->set_blank)
+                       tg->funcs->set_blank(tg, true);
        }
 
        /* Disconnect unused mpcc */

diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_timing_generator.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c
similarity index 99%
rename from drivers/gpu/drm/amd/display/dc/dcn10/dcn10_timing_generator.c
rename to drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c
index f73752c..827dd14 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_timing_generator.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c
@@ -23,8 +23,9 @@
  *
  */
 
+
 #include "reg_helper.h"
-#include "dcn10_timing_generator.h"
+#include "dcn10_optc.h"
 #include "dc.h"
 
 #define REG(reg)\
@@ -251,8 +252,7 @@ void optc1_program_timing(
                v_init = v_init / 2;
                if ((optc->dlg_otg_param.vstartup_start/2)*2 > asic_blank_end)
                        v_fp2 = v_fp2 / 2;
-       }
-       else
+       } else
                REG_UPDATE(OTG_INTERLACE_CONTROL,
                                OTG_INTERLACE_ENABLE, 0);
 

diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_timing_generator.h b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h
similarity index 100%
rename from drivers/gpu/drm/amd/display/dc/dcn10/dcn10_timing_generator.h
rename to drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h

diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c
index 65ce96b..44825e2 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c
@@ -34,7 +34,7 @@
 #include "dcn10/dcn10_mpc.h"
 #include "irq/dcn10/irq_service_dcn10.h"
 #include "dcn10/dcn10_dpp.h"
-#include "dcn10/dcn10_timing_generator.h"
+#include "dcn10_optc.h"
 #include "dcn10/dcn10_hw_sequencer.h"
 #include "dce110/dce110_hw_sequencer.h"
 #include "dcn10/dcn10_opp.h"

diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/opp.h b/drivers/gpu/drm/amd/display/dc/inc/hw/opp.h
index 6da125d..17e143e 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/inc/hw/opp.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/hw/opp.h
@@ -282,25 +282,6 @@ struct opp_funcs {
                        bool enable,
                        bool rightEyePolarity);
 
-       void (*opp_set_test_pattern)(
-                       struct output_pixel_processor *opp,
-                       enum controller_dp_test_pattern test_pattern,
-                       enum dc_color_depth color_depth,
-                       int width,
-                       int height);
-
-       void (*opp_dpg_blank_enable)(
-                       struct output_pixel_processor *opp,
-                       bool enable,
-                       const struct tg_color *color,
-                       int width,
-                       int height);
-
-       void (*opp_convert_pti)(
-               struct output_pixel_processor *opp,
-               bool enable,
-               bool polarity);
-
 };
 
 #endif

diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h b/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h
index a32c745..4c0aa56 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h
@@ -28,6 +28,7 @@
 #include "dc_types.h"
 #include "clock_source.h"
 #include "inc/hw/timing_generator.h"
+#include "inc/hw/opp.h"
 #include "inc/hw/link_encoder.h"
 #include "core_status.h"