while (SM.hasNext()) {
InstRef IR = SM.peekNext();
std::unique_ptr<Instruction> NewIS =
- IB->createInstruction(IR.first, *IR.second);
+ IB.createInstruction(IR.first, *IR.second);
const InstrDesc &Desc = NewIS->getDesc();
if (!DU->isAvailable(Desc.NumMicroOps) ||
!DU->canDispatch(IR.first, *NewIS))
class Backend {
const llvm::MCSubtargetInfo &STI;
- std::unique_ptr<InstrBuilder> IB;
+ InstrBuilder &IB;
std::unique_ptr<Scheduler> HWS;
std::unique_ptr<DispatchUnit> DU;
SourceMgr &SM;
void runCycle(unsigned Cycle);
public:
- Backend(const llvm::MCSubtargetInfo &Subtarget, const llvm::MCInstrInfo &MCII,
- const llvm::MCRegisterInfo &MRI, SourceMgr &Source,
+ Backend(const llvm::MCSubtargetInfo &Subtarget,
+ const llvm::MCRegisterInfo &MRI, InstrBuilder &B, SourceMgr &Source,
unsigned DispatchWidth = 0, unsigned RegisterFileSize = 0,
unsigned MaxRetirePerCycle = 0, unsigned LoadQueueSize = 0,
unsigned StoreQueueSize = 0, bool AssumeNoAlias = false)
- : STI(Subtarget),
+ : STI(Subtarget), IB(B),
HWS(llvm::make_unique<Scheduler>(this, Subtarget.getSchedModel(),
LoadQueueSize, StoreQueueSize,
AssumeNoAlias)),
this, MRI, Subtarget.getSchedModel().MicroOpBufferSize,
RegisterFileSize, MaxRetirePerCycle, DispatchWidth, HWS.get())),
SM(Source), Cycles(0) {
- IB = llvm::make_unique<InstrBuilder>(Subtarget, MCII);
HWS->setDispatchUnit(DU.get());
}
void notifyReleasedBuffers(llvm::ArrayRef<unsigned> Buffers);
void notifyCycleEnd(unsigned Cycle);
};
-
} // namespace mca
#endif
if (DispatchWidth)
Width = DispatchWidth;
+ // Create an instruction builder.
+ std::unique_ptr<mca::InstrBuilder> IB =
+ llvm::make_unique<mca::InstrBuilder>(*STI, *MCII);
+
std::unique_ptr<mca::Backend> B = llvm::make_unique<mca::Backend>(
- *STI, *MCII, *MRI, *S, Width, RegisterFileSize, MaxRetirePerCycle,
+ *STI, *MRI, *IB, *S, Width, RegisterFileSize, MaxRetirePerCycle,
LoadQueueSize, StoreQueueSize, AssumeNoAlias);
std::unique_ptr<mca::BackendPrinter> Printer =