[llvm-mca] Pass the InstrBuilder to the constructor of Backend.
authorAndrea Di Biagio <Andrea_DiBiagio@sn.scee.net>
Fri, 23 Mar 2018 11:50:43 +0000 (11:50 +0000)
committerAndrea Di Biagio <Andrea_DiBiagio@sn.scee.net>
Fri, 23 Mar 2018 11:50:43 +0000 (11:50 +0000)
This is done in preparation for the fix for PR36784.
No functional change.

llvm-svn: 328306

llvm/tools/llvm-mca/Backend.cpp
llvm/tools/llvm-mca/Backend.h
llvm/tools/llvm-mca/llvm-mca.cpp

index 94edf873ed4dc18bdcfe7f464cdf675ec7eaac83..d0afa45461cd4c8728bd30553be45f152d77aede 100644 (file)
@@ -34,7 +34,7 @@ void Backend::runCycle(unsigned Cycle) {
   while (SM.hasNext()) {
     InstRef IR = SM.peekNext();
     std::unique_ptr<Instruction> NewIS =
-        IB->createInstruction(IR.first, *IR.second);
+        IB.createInstruction(IR.first, *IR.second);
     const InstrDesc &Desc = NewIS->getDesc();
     if (!DU->isAvailable(Desc.NumMicroOps) ||
         !DU->canDispatch(IR.first, *NewIS))
index 027850ecba5406e1517dab3d0c7888a31fc631f7..902327ac625eb97508ad73e9c9f48d1488f262db 100644 (file)
@@ -47,7 +47,7 @@ class HWStallEvent;
 class Backend {
   const llvm::MCSubtargetInfo &STI;
 
-  std::unique_ptr<InstrBuilder> IB;
+  InstrBuilder &IB;
   std::unique_ptr<Scheduler> HWS;
   std::unique_ptr<DispatchUnit> DU;
   SourceMgr &SM;
@@ -59,12 +59,12 @@ class Backend {
   void runCycle(unsigned Cycle);
 
 public:
-  Backend(const llvm::MCSubtargetInfo &Subtarget, const llvm::MCInstrInfo &MCII,
-          const llvm::MCRegisterInfo &MRI, SourceMgr &Source,
+  Backend(const llvm::MCSubtargetInfo &Subtarget,
+          const llvm::MCRegisterInfo &MRI, InstrBuilder &B, SourceMgr &Source,
           unsigned DispatchWidth = 0, unsigned RegisterFileSize = 0,
           unsigned MaxRetirePerCycle = 0, unsigned LoadQueueSize = 0,
           unsigned StoreQueueSize = 0, bool AssumeNoAlias = false)
-      : STI(Subtarget),
+      : STI(Subtarget), IB(B),
         HWS(llvm::make_unique<Scheduler>(this, Subtarget.getSchedModel(),
                                          LoadQueueSize, StoreQueueSize,
                                          AssumeNoAlias)),
@@ -72,7 +72,6 @@ public:
             this, MRI, Subtarget.getSchedModel().MicroOpBufferSize,
             RegisterFileSize, MaxRetirePerCycle, DispatchWidth, HWS.get())),
         SM(Source), Cycles(0) {
-    IB = llvm::make_unique<InstrBuilder>(Subtarget, MCII);
     HWS->setDispatchUnit(DU.get());
   }
 
@@ -98,7 +97,6 @@ public:
   void notifyReleasedBuffers(llvm::ArrayRef<unsigned> Buffers);
   void notifyCycleEnd(unsigned Cycle);
 };
-
 } // namespace mca
 
 #endif
index 0ae9c8849bbba0258f1324925a316c6afd4a1052..5c085af9685810c17018e70ae53a6f5dad20e790 100644 (file)
@@ -321,8 +321,12 @@ int main(int argc, char **argv) {
   if (DispatchWidth)
     Width = DispatchWidth;
 
+  // Create an instruction builder.
+  std::unique_ptr<mca::InstrBuilder> IB =
+      llvm::make_unique<mca::InstrBuilder>(*STI, *MCII);
+
   std::unique_ptr<mca::Backend> B = llvm::make_unique<mca::Backend>(
-      *STI, *MCII, *MRI, *S, Width, RegisterFileSize, MaxRetirePerCycle,
+      *STI, *MRI, *IB, *S, Width, RegisterFileSize, MaxRetirePerCycle,
       LoadQueueSize, StoreQueueSize, AssumeNoAlias);
 
   std::unique_ptr<mca::BackendPrinter> Printer =